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TTS / Local Trigger
GOL / GBT from detector DAQ optical fibers
12 AMC Slots
Power
AMC13 AMC13
AMC
AMC
AMC
Clocks
Fast controls
Power
DAQ
MCH1
Commercial MCH
Management
Ethernet
Fiber links to trigger
Ethernet
One specific geometry shown, others possible...
26 Sept 2013 E. Hazen - TWEPP 2013 3 / 40
“MTCA.CMS” Crate Requirements
● Dual-star backplane with redundant clocks
– Fabrics A, B routed star-wise to both MCH sites
– MCH2 CLK1 routed star-wise to AMC FCLKA
● Full-height, double width slots (pref. 12)
● Vertical cooling
Spartan-6
FPGA
Kintex-7 FPGA
With heatsink
DDR3 SDRAM
Tongue 2 PCB
Clocks T3 connector board removed
Tongue 1 PCB to show internal detail
GbE, Fabric A
Serial # SFP0
(DAQ Loop-back test)
USB 3x SFP+
(MMC console) 10Gb/s capable
SFP1
(DAQ Output)
Functions listed
for initial HCAL
JTAG firmware
(MMC AVR-32) SFP2
(Spare)
SFP3
JTAG (TTC/TTS)
(AMC13 FPGAs)
DAQ
SFP+ GTX GTX
10 Gb/s Fabric A
GTX
Kintex 7 12 ports
DAQ Gb/s
SFP+ GTX
10 Gb/s GTX (10 Gb possible)
GTX
Spare
SFP+ 512 Mbyte
10 G b/s
GTX DDR3
1600MT/s (6.4 GB/s)
GTP
IO
Fabric B
GbE GTP Spartan 6 80 Mb/s (TTC)
MCH1
IPMI MMC May upgrade to
uC ~ 320 Mb/s
Front JTAG
Panel
LEDs Flash
via T3
26 Sept 2013 E. Hazen - TWEPP 2013 22 / 40
AMC13 Clock Paths
Tongue 1 LVDS
Tongue 2
160MHz x 4 SY89872 SY89832
Divide by 40MHz Future Fanout
2/4 Option
For ext clock T2 U23
Div DS91M125
Recovered
Reset 1:4
Clock SY89832 40MHz
Fanout
SFP 160MHz Fanout Clock
To uTCA
T1 U3 backplane
1300nm receiver
IO_L10
(ATM type)
Compatible with M-LVDS
TTC fiber data MGT CLK
ADN2814
Clock/data MGT CLK
Recovery IO_L9
IC
T1 U2 Virtex 6
GCLK
Recovered Data
80 Mb/s LVDS
80Mb/sec
TTC data
Spartan 6 To uTCA
LX130T
● Low-jitter clock path Backplane
(Fabric B)
Measured jitter << 10ps (measurement limit)
8k event
SDRAM
L1A
TTC
FIFO
TP[0:7] Level 1
Trigger 5 Gb/s
BC0
8b/10b
Fabric A
MUX MGT MGT
CLK
16
Data
Level 2
Framing
DAQ
Buffer
Status
AMC13 FEROL
Data from 4 blocks (4Kbytes each)
-Receive block
FED -Ack. block
-DATA (64 bit) SFP itf
-Order blocks
Main
-WEN Logic
-UCTRL
-CLOCK
-Backpressure Block is sent until it is
-link down acknowledged
Send commands
Internal
Receive CMD
+ ACk (one at the time)
DDR3 power
DDR3
Kintex-7
LS to T2
7 GP4 GND
5 mil dielectric
8 GBL Impedance control (TTC)
Fabric B (TTC)
AVR 32 (MMC)
Connector to T3
Connector from T1
Jumper
GTX Board
~5 cm 20 cm (est)
AMC13XG PCB (Nelco) backplane PCB
(Kintex-7 FPGA)
Total length: 50 cm (3.3ns) NOTE: Preliminary!
still tweaking parameters
NOTE: Preliminary!
still tweaking parameters
10.0 Gb/s
Backplane
Coax Fiber AMC
Clock TTC
AMC13XG Test
Source Encoder
Rx
TTCex (904)
TTT (BU)
1
Oscilloscope
Coax
2
Goal: Measure phase shift between TTC input and clock on uTCA backplane
300 ps
700 s
● Measure TTC to custom AMC rx card ● Measure TTT to 3.5GHz diff probe
● 6 power cycles of whole uTCA crate on AMC card clock inputs w/ 100Ω
● Converges in O(200s) ● 6 power cycles of whole uTCA crate
● Slow drift seen but very low level, ● Vary from 10 min to 8h off time
● nearly unmeasurable with this setup
T1 U2 Virtex 6
GCLK
Recovered Data
80 Mb/s LVDS
140
120
100
Delay 80
Delay (ps)
(ps) Fitted
60
40
Slope: 25.8 ps/°C
20
0
24 25 26 27 28 29 30 31
-20
Temperature (°C)
T3 board
Provides JTAG / LEDs on front panel
T1 base board
Can be removed after initial programming MMC functions (Wisconsin firmware)
TTC optical rx
Crosspoint switch or other custom board 3x SFP+ cage
can be installed here (but see notes!) Cross-over GbE from MCH1
for controls and local DAQ