Assignment-1, 2018

DD-HDL, IV-A, B,C,D

Ref:

1.Digital Systems Design Using Verilog by Charles Roth (Author), Lizy K. John (Author),
Byeong Kil Lee (Author)- chapter 3

2. Application-Specific Integrated Circuits-Michael John Sebastian Smith

Date of completion: 27/01/2018

One word answer:

1. Write the difference between the CBIC and Channelled Mask Gate Array.
2. Define the following terms i. Standard Parts ii. Glue Logic iii. ASSPs
3. What is Y-Chart?
4. What is the main advantage of antifuse FPGAs?
5. What are the major programmable elements in an FPGA?
6. What are the disadvantages of SRAM FPGAs?
7. What are the disadvantages of antifuse FPGAs?
8. How many transistors are typically required to make an SRAM cell?
9. What is an MPGA?
10. What is an advantage of a CPLD over an FPGA?
11. What is the advantage of an FPGA over a CPLD?
12. Name three vendors of CPLDs.
13. Name three vendors of FPGAs.
14. In which applications should a designer use a CPLD rather than an FPGA?
15. In which applications should a designer use an MPGA rather than an FPGA?
16. In which applications should a designer use an FPGA rather than an MPGA?
17. A company is designing an experimental product that is in version 1 now. It is
expected that the product will undergo several revisions. The company’s plan
is to use an FPGA for the actual design. What type of FPGA (SRAM or antifuse)
should be used?
18. A company is designing a product. It expects to sell 1000 copies of the
product. Should the company use an MPGA or an FPGA for this product?
19. A company is designing a product. It expects to sell 100 million copies of the
product. Should the company use an MPGA or an FPGA for this product?

Design Problems:

1. A Cell Based ASIC is using AND gate as standard Cells and two 2 to 4 decoder
as fixed block. Implement a 4 to 16 decoder.
2. Implement the sum of full–adder using Cell Based ASICs. Consider the base cell
of 2:1 MUX and in one base array only 3 base cells are fabricated. Show the
customization steps before and after defining the Mask
3. Implement MOD-16 counter with Xilinx 3000 FPGA.
 4. One input one-output sequence detector that produces an output value 1
every time the sequence 0101 is detected and an output value 0 at all other
times. For example, if the input sequence is 010101 then the corresponding
output sequence is 000101. Implement using ACT-2 FPGA.
5. Show the fusible link connection of PLA for the implementation of multiple
output function of Full-adder.
6. ACT-1 LM can handle 4 no. of inputs. How many LM do you need to implement
a 32-bit wide address decoder?
7. Give the implementation of BCD-to-7 segment decoder using (i) PAL (ii)
XC3000. Assume common cathode display.
8. Altera MAX using PAL in its macrocell cell. Consider the function given below.

(i) Implement the function using ALTERA MAX by considering 3-wide OR

plane. Use expander term.
(ii) Is it active low or active high programming?
(iii) How EPROM transistor is working as switching element?

9. Show how the Actel ACT 2 and ACT 3 sequential element (used in the S-Module)
can be wired to implement:

(i) positive-edge–triggered flip-flop with clear,

(ii) a negative-edge–triggered flip-flop with clear,

(iii) a transparent-high latch,

(iv) a transparent-low latch,

10. Consider a four-input LUT (used in the CLB in the Xilinx XC2000, the first generation
of Xilinx FPGAs). This CLB can implement any Boolean function of four variables.
Consider the function

Z = (A · (B + C)) + (B · D) + (E · F · G · H · I)

We can use four CLBs to implement Z as follows:

CLB1: Z = Z1 + (B · D) + Z3 ,
CLB2: Z1 = A · (B + C) ,
CLB3: Z3 = E · F · G · Z5 ,
CLB4: Z5 = H · I

Show the implementation considering the chip layout. It should contain

interconnection between logic blocks and I/O pads.

11. Consider the logic block of shift registers given below. Implement the same using
LUT based FPGA.
12.Consider the structure shown below of FPGA.

Fig.11a.
(a) Implement an 8-to-1 multiplexer using a minimum number of logic blocks of
the type shown in Fig. 11a. Give the X and Y functions for each block and
show the connections between blocks.
(b) Repeat (a) using the logic blocks of Figure 11b. Give X, Y, and Z for each block.
(c) What are the LUT contents for the design in part (a)?
(d) What are the LUT contents for the design in part (b)?

Fig.11b.