2015 Fifth International Conference on Advanced Computing & Communication Technologies
Reduction of Leakage Power & Noise for DRAM Design using Sleep
Transistor Technique
Priyanka Kushwah Nikhil Saxena
M.tech Student, ITM Assistant prof., Dept.
Gwalior, M.P., India of ECE, ITM
priyankakushwah03 Gwalior, M.P., India
@gmail.com saxena.nikhil9@gma
il.com
Abstract-In this paper the analysis of DRAM logic
compatible 3T cell has been shown. Due to its high
density and low cost of memory, it is universally used
by the advanced processor for on chip data and
program memory. DRAM has transistor-capacitor
cell structure, where capacitor is charged to produce
1 or 0. Memory array, which is arranged in row and
column, is word line and bit line respectively. Here I
have proposed sleep transistor technique at 3T dram
with semantic design, for improvement of leakage and
also calculated stability by calculating noise, slew rate
and settling time. This circuit proposed two voltage
source are connected to bit line and bit line bar
respectively. switching of main transistor is
performed by word line, which is at low for write
operation and high for read operation. The
simulation result shows that when a wide range of
operating voltage is taken, which is from 0.7 to 1.3v
then it is observed that low voltage operation is
suitable for low slew rate or low read access time and
the leakage current reduced as increase in the range
of operating voltage. At 0.7v the leakage current is
595.4×10-12 amp, slew rate is 6.96×103 dB, noise
measurement is 5.995×10-14, settling time is 46.63×10-
9
. The design has been carried out at the 45
nanometre scale technology on cadence virtuoso
simulating tool.
Keywords: DRAM, Leakage current, Leakage power,
Slew Rate, Noise measurement, Settling time.
I. INTRODUCTION
Dynamic random access memory are mostly used
as a primary storage in personal computers and
engineering workstation due to its high density as
compared to static random access memory and fast
access especially if compared with hard disk [1]. In
modern electronics industry generally use the word
"memory" is refer to RAM. Read/Write memory or
random access memory hold instructions
temporarily, which is required for CPU (central
processing unit) to process the task and permit
modification of data bits which is stored in the
memory arrays i.e. volatile memory. It is further
classified into two major sub categories: Static
2327-0659/15 $31.00 © 2015 IEEE
DOI 10.1109/ACCT.2015.81
Shyam Akashe Saurabh
Prof., Dept.of ECE, Khandelwal
ITMUniversity Assistant Prof., Dept.
Gwalior, M.P., India of ECE, ITM
shyam.akashe@itmu Gwalior, M.P., India
niversity.ac.in
RAM (SRAM) and Dynamic RAM (DRAM) . The
SRAM cell consist of a latch, it does not need to be
refreshed as the cell transistor holds the data as
long as the power supply is not cut-off. The DRAM
cell comprise of a capacitor to store binary
information and a transistor to access the capacitor,
hence the information degraded constantly so the
DRAM cell need to be refreshed periodically.
According to the structure of SRAM, it needs more
transistor in order to store certain amount of data,
but a DRAM modules needs a transistor and a
capacitor for every bit of data whereas SRAM
needs 6 transistor i.e. DRAM has the 6 time larger
capacity with a similar number of transistors to an
SRAM module, this ultimately reduces the price of
the memory. Due to its low price DRAM has
become main memory in personal computers and
engineering workstations. SRAM is mainly used
for the high speed and low power consumption, so
it is mainly used for cache memory in
microprocessor [2]-[3]. We proposed conventional
dynamic random access memory using 3 transistor
cells with structural support to enable high
performance designs, which is tolerant to process
variations for future generation of high
performance microprocessors. This paper describes
the parameters' variation in accordance with the
operating voltage in nanotechnology [3].
The reminder of this paper is as follows: section II
discusses about the conventional 1T-1C DRAM
cell. The proposed 3T DRAM cell with sleep
transistor technique will be presented in section III.
In section IV Sleep transistor technique discussed.
The proposed scheme will be simulated for 45nm
CMOS technology with the simulation result
presented in section V. Finally, the conclusion of
this paper will be presented in section VI.
II. Conventional 1T-1C DRAM Cell
Dynamic random access memory is the most cost
effective and higher density random access
memory, which is used as main memory in
personal computers and workstations. The term
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dynamic stands for its leakage phenomenon which used as a sleep transistor to reduce the leakage of
degrades the charge stored in the memory cell with the proposed circuit.
the time i.e. it need periodic refreshment in order to
retain the data. The first 1kb DRAM was proposed
in 1970, now DRAMs have became the main
leading edge of force behind the VLSI technology
development. The DRAM technology has increased
six times in last three decades up to 4GB [4]-[5].
Although a number of DRAM cell circuit design
have been proposed over the years. A particular
1T-1C DRAM cell shown in Fig. 1, has become the
standard cell design in semiconductor industries
which consist of single access transistor, N, and
capacitor, C, for storing the data bit, and called as
1T-1C DRAM Cell.

Figure.2 3T DRAM cell with Sleep transistor technique

IV. SLEEP TRANSISTOR

Sleep transistor are generally high Vt. When idle

condition occurs, they are switched off and help to
consume about 40% leakage power because they
help to create virtual power & virtual ground
networks. The virtual power network drives to
minimize the size can be estimated gate delay time
of a CMOS Cell is defined as

 (Vdd) = CVdd/[ (Vdd  VtL)] (1)

Figure.1 Standard 1T-1C DRAM cell
III. PROPOSED 3T DRAM CELL
Dynamic Random access memory has a large array
of cell, a particular cell contain a transistor and a
capacitor for a single bit of data according to chip
configuration. In this section we have described
proposed 3T DRAM circuit with sleep transistor
technique to reduce a leakage of the circuit and for
reaching improved performance.[6] Fig. 2 shows
schematic of 3T DRAM Cell with sleep transistor.
Here we have chosen 4- NMOS devices due to its
inbuilt high-speed over PMOS devices and an
further advantage of NMOS is it can be
supplementary complex even having the equivalent
dies area as PMOS device i.e. higher density. There
are 4 transistor NM1, NM2, NM3, NM4 are
connected. Where NM2 used as a access transistor
to store a information data. The other two transistor
NM1 & NM3 are used as a switches, each transistor
is turn on or off according to write and read
operation respectively [7]. transistor NM4 has been
The voltage swing is calculated by
V = Isleep × Rsleep (2)
If Wsleep is additionally great then the current
resonators suppress large ground forces and will
not switch. If it is too small the ground bounce is
up to 0.5 vdd. so usually the sleep transistor is 3%
of DRAM Cell area. In Figure 2, there is our
DRAM cell with sized up Sleep transistor.
V. PERFORMANCE ANALYSIS &
SIMULATION RESULT
A. Leakage Current
Gate length is scaled down continuously, which
increases the device leakage exponentially across
the generation of technology. For DRAM Cell,
source of standby power is leakage current. At
nanoscale technology, the most important
components of leakage current are the gate

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tunnelling leakage , sub-threshold leakage and rate capability (in volts / second) at all points in an
reverse bias band to band tunnelling junction amplifier which have to satisfy the condition

Slew rate = max (dvout (t)/dt) (12)

Leakage current (pA)
800 Slew rate (v/μS)
L
600 14
e
s 12
a 400
l 10
k 8
200 leakage current e
a 6
0 w
g 4 slew rate
e 0.7 0.9 1.1 1.3 2
r 0
voltage (volts) a 0.7 0.8 0.9 1 1.1 1.2 1.3
t
voltage (volts)
Figure.3 shows improving result of leakage current in 3T e
DRAM cell during Read operation

Figure.5 shows improving result of Slew rate in 3T DRAM cell

B. Leakage power
PMOS and NMOS transistor is in OFF state when
the CMOS inverter is in ideal mode. There is no
current flowing through the power supply to the
ground in ideal mode. There is small current
flowing through the off state transistor which gives
rise to leakage power consumption which is shown
by equation 2.
during Read operation
D. Settling time
It is commonly defined as the time required for the
response curve to reach and stay within a range of
certain percentage (usually 5% or 2%) of the final
value. it is mostly depends on the system response
& time constant.

Ptot = Il × Vdd (2) Settling time (nS)

46.68
Leakage power (pW) 46.66
450
settling time

L 400 46.64
e p 350 46.62
300
a o 46.6
250
k w 200 46.58
leakage power
a e 150 0.7 0.8 0.9 1 1.1 1.2 1.3
g r 100 Voltage (volts)
e 50
0
0.7 0.9 1.1 1.3 Figure.6 shows improving result of settling time in 3T DRAM
voltage (volts) cell during Read operation

Figure.4 shows improving result of leakage Power in 3T DRAM E. Noise measurement

cell during Read operation
It is calculated by cadence virtuoso tool on 45
nanometer CMOS technology.
C. Slew Rate

It is defined as the highest rate of change of output

voltage per unit time & it is represented by volt /
second. Limitations of the slew rate capability
which can give rise to the non linear effects in
electronic amplifier. For a sinusoidal waveform not
to be subjected to the slew rate limitation, the slew

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 VI. CONCLUSION
Noise measurement (E-14)
We have proposed a 3T DRAM cell with sleep
transistor technique in which we present read/write
6 operation at a range of operating supply voltage. In
5.995 this paper it is observed that by adding up
5.99
Noise meas.

additional NMOS transistor in the circuit leakage

5.985
current and power have been reduced and slew rate
5.98
5.975 Noise are increased with increase in voltage, whereas,
5.97
measurement settling time and noise is decreased with increase in
5.965 voltage. It can be considered that high performance
5.96 and a lesser amount of power consumption as
increase in working voltage at 45 nanometer
0.7 0.9 1.1 1.3
technology in Cadence virtuoso tool.
Voltage (volts)
Acknowledgement

The authors would like to be thankful for the

Figure.7 shows improving result of Noise measurement in 3T
DRAM cell during Read operation
support by ITM Gwalior for their best guidance,
technical advice and support. This work has been
TABLE- I done with the collaboration of cadence design
system Bangalore.

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