Cadence Training Learning Maps

Cadence Training Services learning maps provide a comprehensive visual overview of the learning
opportunities for Cadence customers. They provide recommended course flows as well as tool
experience and knowledge levels to guide students through a complete learning plan. Learning Maps
cover all Cadence® Technologies and reference courses available worldwide. For course names,
descriptions, and schedules, please select the Browse Catalog button at
https://www.cadence.com/training.

Contents
• PCB Design and Analysis
• Custom IC, Analog, and RF Design
• Digital Design and Signoff
• System Design and Analysis
• IC Package Design and Analysis
• Tensilica® Processor IP
 Learning Mapand
PCB Design Digital Design
Analysis and Signoff
Learning Map
Logic Design PCB Design SI/PI Analysis Library Development

Beginner
Beginner

Allegro® Design Entry Allegro Design Entry Allegro PCB Editor Basic Essential High-Speed PCB Allegro PCB Librarian
HDL Front-to-Back Using OrCAD® Techniques Design for Signal Integrity
Flow Capture

Allegro Design Entry Allegro PCB Editor PCB Design at RF – Multi- Allegro Design Workbench for
HDL Intermediate Techniques Gigabit Transmission, EMI Librarians
OrCAD CIS
Basics Control, and PCB Materials

Allegro System Allegro PCB Router Basics Allegro Design Workbench for
Design Authoring Allegro Sigrity™ SI Foundations Administrators

Allegro System Allegro Team Design Allegro PCB Editor Advanced Allegro Design Entry HDL SKILL®
Methodologies Allegro Sigrity PI Programming
Architect Authoring

Allegro Design Reuse Allegro Design Allegro High-Speed Constraint Allegro PCB Editor SKILL
Workbench for Management Sigrity PowerDC™ and
Programming Language
Engineers and OptimizePI™
Designers
Allegro Tool Setup and
Allegro AMS Analog Simulation Allegro Update Training Sigrity SystemSI™ for Configuration
Simulator with PSpice® Parallel Bus and Serial Link
Analysis
Advanced

Advanced
Allegro AMS Analog Simulation Advanced Design Verification Sigrity PowerSI® for Model
Simulator with PSpice with the RAVEL Programming Generation and Analysis
Advanced Advanced Language
Analysis Analysis
New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available © 2017 Cadence Design Systems, Inc.
 Learning Design
IC Package Map Digital Design and
and Analysis SignoffMap
Learning

Beginner
Beginner

IC Package Design SI/PI Analysis

SiP Layout Allegro Sigrity™ SI Foundations

Allegro® Package Designer Allegro Sigrity PI

Allegro FPGA System Planner Sigrity PowerDC™ and OptimizePI™

Allegro Sigrity Package Assessment and Model Extraction Sigrity SystemSI™ for Parallel Bus and Serial Link Analysis

OrbitIO™ System Planner Sigrity PowerSI® for Model Generation and Analysis

Advanced Design Verification with the RAVEL Programming

Language
Advanced

Advanced
New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available © 2017 Cadence Design Systems, Inc.
 Learning
Custom Map Digital
IC, Analog and RFDesign
Designand Signoff Map
Learning 1 of 2 – see next page

Circuit Design, Simulation, Modeling and RF Design Library

Beginner
Beginner

Characterization
Virtuoso® Analog Design Virtuoso Schematic Editor Spectre Simulator
Environment Fundamentals Series Cadence® Library
Virtuoso® ADE Explorer Series S1: Spectre Basics Characterization and
Virtuoso Analog Simulation Series S1: Set Up and Run Analog Simulations Validation
S2: Large-Signal
T1: Introduction to the Virtuoso Using the Spectre® Simulator
ADE XL Environment S3: Small-Signal
S2: Analyzing Simulations Using ViVA XL Virtuoso
S4: Spectre MDL Liberate™ MX for
T2: Creating Sweeps and
Memory
Running Corners S3: Corner Analysis and Monte Carlo High-Performance Sim.
Characterization
Simulation using Spectre Simulators
T3: Monte Carlo Simulation Using
ADE XL Spectre Accelerated
S4: Real-Time Tuning, Checks/Asserts, Parallel Simulator (APS) Cadence Variety™
T4: Sensitivity Analysis and Circuit and Reliability Analysis
Spectre XPS for Mixed- Statistical Library
Optimization Using ADE GXL Characterization
Virtuoso ADE Assembler Series Signal Designs

S1: Introducing the Assembler Virtuoso EAD with LDE

Mixed-Signal Simulations Using
Environment
AMS Designer Virtuoso Spectre Pro Series
Analog Modeling with Verilog-A S2: Sweeping Variables, Simulating S1: DC Algorithm
Corners and Creating Run Plans
S2: AC, XF, STB, Noise
Behavioral Modeling with /
S3: Circuit Checks, Device Asserts and S3: Transient Algorithm
Verilog-AMS / VHDL-AMS
Reliability Analysis
S4: Fourier Transform
Real Modeling with / SystemVerilog
Advanced

Advanced
/ Verilog-AMS Virtuoso ADE Verifier S5: Transient Noise

Transistor-Level Power Signoff Variation Analysis Using the Virtuoso Spectre® RF/ Shooting Newton
with Voltus™-Fi Variation Option / Harmonic Balance

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available © 2017 Cadence Design Systems, Inc.
 Learning
Custom Map Digital
IC, Analog and RFDesign
Designand Signoff Map
Learning 2 of 2 – see prior page

IC CAD Layout Design and Advanced Nodes Layout Verification

Beginner
Beginner

SKILL® Language Virtuoso® Layout Design Virtuoso® Layout Pro Series Physical Quantus™ QRC Assura®
Programming Basics T1: Env. and Basic Commands Verification Transistor-Level Verification
Introduction System (PVS) Series DRC/LVS
Virtuoso Connectivity- T2: Create and Edit Commands
SKILL Language Driven Layout Transition T1: Overview
Programming and Technology Assura
T3: Basic Commands Physical Setup
Fundamentals Rules-
Virtuoso Abstract Verification
T4: Advanced Commands Writer
Language
Generator
SKILL Language Rules-
T2: Parasitic
T5: Interactive Routing Writer
Programming Extraction
Virtuoso Floorplanner
T6: Constraint-Driven Flow and
Power Routing T3: Extracted
SKILL Development
of Parameterized Virtuoso Space-Based View Flows
Router T7: Module Generator and and
Cells
Floorplanner Advanced
Features
Virtuoso Space- T8: Debugging Layout Issues
SKILL Based Router
Programming for IC Express
Layout Design
Virtuoso® Advanced-Node Series – ICADV
Virtuoso Layout for Advanced Nodes
Advanced SKILL
Language
Advanced

Advanced
T1: Place and Route
Programming
T2: Electromigration

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available © 2017 Cadence Design Systems, Inc.
 Learning Map Digital
Digital Design Design
and Signoff and Signoff
Learning Map
Synthesis Implementation Silicon Signoff Equivalence Checking

Beginner
Beginner

Cadence® RTL-to-GDS Flow

Genus™ Synthesis Solution Virtuoso® Digital Implementation Basic Static Timing Analysis Logic Equivalence Checking with
Conformal® EC

Low-Power Synthesis Flow Innovus™ Implementation System

Tempus™ Signoff Timing Analysis
with Genus Synthesis Solution Conformal Low-Power
and Closure
Verification
Innovus Implementation System
Test Synthesis Using Genus (Hierarchical)
Synthesis Solution Voltus™ Power-Grid Analysis and Conformal ECO
Signoff
Low-Power Flow with Innovus
Advanced Synthesis with Genus Implementation System
Conformal Constraint
Synthesis Solution
Designer
Innovus Clock Concurrent
Fundamentals of IEEE 1801 Low- Optimization Technology for
Power Specification Flow Clock Tree Synthesis

Modus DFT Software Solution Analog-on-Top Mixed-Signal

Implementation
Advanced

Advanced
Joules™ Power Calculator

New Course Number of days for instructor-led course Online Course Available © 2017 Cadence Design Systems, Inc.
 System Design and Verification Learning Map
Simulation, Acceleration, Emulation, Coverage and Debug

Beginner
Beginner
Beginnr

Incisive® SystemC®, VHDL, and The Xcelium™ Simulator Specman® In-Circuit Emulation with Protium™ Rapid
Verilog Simulation Fundamentals for Block- Palladium® XP Prototyping
level Environment Platform
Developers
Incisive Comprehensive Cadence® RTL-To-GDSII
Coverage with IMC Flow

Incisive Simulation Foundations of Metric-Driven Specman Advanced Power-Aware Emulation

Performance Optimization Verification Verification with DPA and CPF

Perspec™ System Verifier Xcelium Integrated Acceleration and

Coverage Emulation Using
Palladium XP
Indago™ Analyzer App (15.2)
Indago Analyzer
App (17.10)
Low-Power Simulation with
CPF
Metric-Driven Verification Using
vManager™
Low-Power Simulation with
IEEE1801 UPF
Advanced
Advanced

Advanced
vManager Tool Usage in Batch
Incisive Functional Safety Mode
Simulator

New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available © 2017 Cadence Design Systems, Inc.
 Learning
System Mapand
Design Digital Design and
Verification SignoffMap
Learning
Design and Verification Languages

Beginner
Beginner

VHDL Language and Application Verilog Language and Application C++ Language Fundamentals
for Design and Verification

Verilog for VHDL Users Master VHDL For Verilog

SystemC® Language
Engineers
Fundamentals

Real Modeling with Verilog AMS SystemVerilog for Design and

SystemC Synthesis with
Verification
Stratus HLS

Real Modeling with SystemVerilog Advanced / SystemVerilog Verification with PSL SystemC Transaction-Level
SystemVerilog AMS Accelerated Verification Using Assertions Modeling TLM2.0
UVM

SystemVerilog Advanced JasperGold® Formal Perl for EDA Engineering

Register Verification Using Fundamentals
UVM

Tcl Scripting for EDA + Intro to

Tk
Advanced

Advanced
New Course Number of days for instructor-led course Tiers of Cadence products used in course Online Course Available © 2017 Cadence Design Systems, Inc.
 Learning Map
Tensilica Digital Design
Processor and Signoff
IP Learning Map
Tensilica Processors ConnX DSP Fusion DSP HiFi Audio DSP Vision DSP
Tensilica® Processor
Fundamentals

Tensilica Xtensa® Tensilica ConnX Tensilica Fusion F1 DSP Tensilica Audio Codec API Tensilica Vision P5 DSP
Processor Interfaces BBE16EP Baseband
Engine

Tensilica Xtensa Tensilica ConnX Tensilica Fusion G3 DSP Tensilica HiFi 2/EP/Mini Tensilica Vision P6 DSP
Hardware Verification and BBE32EP Baseband Audio Engine ISA
EDA Engine

Tensilica Instruction Tensilica ConnX Tensilica Fusion G6 DSP Tensilica HiFi 3 Audio Tensilica Vision C5 DSP
Extension Language and BBE64EP Baseband Engine ISA
Design Engine

Introduction to System Tensilica HiFi 4 DSP

Modeling with Tensilica
Processor Cores

New Course Number of days for instructor-led course Online Course Available Online Course Available © 2017 Cadence Design Systems, Inc.
© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks
of Cadence Design Systems, Inc. SystemC is a trademark of Accellera Systems Initiative Inc. All other trademarks are the property of their respective owners.