The floating-gate MOSFET (FGMOS) is a field-effect transistor, whose structure is similar to a

conventional MOSFET. The gate of the FGMOS is electrically isolated, creating a floating node in DC, and
a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically
isolated from it. These inputs are only capacitively connected to the FG. Since the FG is completely
surrounded by highly resistive material, the charge contained in it remains unchanged for long periods
of time. Usually Fowler-Nordheim tunneling and hot-carrier injection mechanisms are used to modify
the amount of charge stored in the FG.

Some applications of the FGMOS are digital storage element in EPROM, EEPROM and flash memories,
neuronal computational element in neural networks, analog storage element, digital potentiometers
and single-transistor DACs.

The first report of a floating-gate MOSFET was made by Kahng and Sze,[1] and dates from 1967. The first
application of the FGMOS was to store digital data in EEPROM, EPROM and flash memories.

In 1989 Intel employed the FGMOS as an analog nonvolatile memory element in its ETANN chip,[2]
demonstrating the potential of using FGMOS devices for applications other than digital memory.

Three research accomplishments laid the groundwork for much of the current FGMOS circuit
development:

Thomsen and Brooke's demonstration and use of electron tunneling in a standard CMOS double-poly
process[3] allowed many researchers to investigate FGMOS circuits concepts without requiring access to
specialized fabrication processes.

The νMOS, or neuron-MOS, circuit approach by Shibata and Ohmi[4] provided the initial inspiration and
framework to use capacitors for linear computations. These researchers concentrated on the FG circuit
properties instead of the device properties, and used either UV light to equalize charge, or simulated FG
elements by opening and closing MOSFET switches.

Carver Mead's adaptive retina[5] gave the first example of using continuously-operating FG
programming/erasing techniques, in this case UV light, as the backbone of an adaptive circuit
technology.An FGMOS can be fabricated by electrically isolating the gate of a standard MOS transistor,
so that there are no resistive connections to its gate. A number of secondary gates or inputs are then
deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only
capacitively connected to the FG, since the FG is completely surrounded by highly resistive material. So,
in terms of its DC operating point, the FG is a floating node.

For applications where the charge of the FG needs to be modified, a pair of small extra transistors are
added to each FGMOS transistor to conduct the injection and tunneling operations. The gates of every
transistor are connected together; the tunneling transistor has its source, drain and bulk terminals
interconnected to create a capacitive tunneling structure. The injection transistor is connected normally
and specific voltages are applied to create hot carriers that are then injected via an electric field into the
floating gate.

FGMOS transistor for purely capacitive use can be fabricated on N or P versions. [6] For charge
modification applications, the tunneling transistor (and therefore the operating FGMOS) needs to be
embedded into a well, hence the technology dictates the type of FGMOS that can be fabricated.