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bq24650
SLUSA75A – JULY 2010 – REVISED APRIL 2016

bq24650 Synchronous Switch-Mode Battery Charge Controller for Solar Power


With Maximum Power Point Tracking
1

1 Features
• Maximum Power Point Tracking (MPPT) • Small 3.5 × 3.5 mm2 16-Pin QFN Package
Capability by Input Voltage Regulation
• Programmable MPPT Setting 2 Applications
• 5-V to 28-V Input Solar Panel • Solar-Powered Applications
• 600-kHz NMOS-NMOS Synchronous Buck • Remote Monitoring Stations
Controller • Portable Handheld Instruments
• Resistor Programmable Float Voltage • 12-V to 24-V Automotive Systems
• Accommodates Li-Ion/Polymer, LiFePO4, Lead • Current-Limited Power Source
Acid Chemistries
• Accuracy 3 Description
– ±0.5% Charge Voltage Regulation The bq24650 device is a highly integrated switch-
mode battery charge controller. It provides input
– ±3% Charge Current Regulation
voltage regulation, which reduces charge current
– ±0.6% Input Voltage Regulation when input voltage falls below a programmed level.
• High Integration When the input is powered by a solar panel, the input
– Internal Loop Compensation regulation loop lowers the charge current so that the
solar panel can provide maximum power output.
– Internal Digital Soft Start
• Safety The bq24650 offers a constant-frequency
synchronous PWM controller with high accuracy
– Input Overvoltage Protection current and voltage regulation, charge
– Battery Temperature-Sensing preconditioning, charge termination, and charge
– Battery Absent Detection status monitoring.
– Thermal Shutdown Device Information(1)
• Charge Status Outputs for LED or Host Processor PART NUMBER PACKAGE BODY SIZE (NOM)
• Charge Enable on MPPSET Pin bq24650 VQFN (16) 3.50 mm × 3.50 mm
• Automatic Sleep Mode for Low Power (1) For all available packages, see the orderable addendum at
Consumption the end of the data sheet.
– < 15-μA OFF-State Battery Discharge Current
Typical Application
Solar Cell
D1
Half Panel
VIN R6: 10Ω
R5
2Ω
C1
VCC C2
2.2µF
bq24650 1uF

VREF
C3 C4:1µF
R9 R3 1µF
5.23kΩ 499kΩ REGN
D2
MPPSET BTST C6
Pack Q1 10uF
Thermistor RSR
HIDRV C5
TS L: 10µH 20mΩ Battery Pack
R10 100nF
CE Q3 R4 PH
30.1kΩ 36kΩ TERM_EN
Q2 C9
LODRV C8 4.7µF
GND 10µF
C10
VIN D3 R2
SRP 22pF
R7:10kΩ STAT1 C7 499kΩ
0.1µF R1
R8:10k Ω STAT2 Thermal SRN
100kΩ
Pad VFB
D4

Copyright © 2016, Texas Instruments Incorporated

Solar Panel 21 V, MPPT = 18 V, 2-cell, ICHARGE = 2 A, IPRECHARGE = ITERM = 0.2 A, TS = 0 - 45°C


1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24650
SLUSA75A – JULY 2010 – REVISED APRIL 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 11
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 20
3 Description ............................................................. 1 9 Application and Implementation ........................ 22
4 Revision History..................................................... 2 9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 28
7 Specifications......................................................... 4 11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
7.1 Absolute Maximum Ratings ...................................... 4
11.2 Layout Example .................................................... 29
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 30
7.4 Thermal Information .................................................. 5 12.1 Device Support...................................................... 30
7.5 Electrical Characteristics........................................... 5 12.2 Community Resources.......................................... 30
7.6 Typical Characteristics .............................................. 9 12.3 Trademarks ........................................................... 30
12.4 Electrostatic Discharge Caution ............................ 30
8 Detailed Description ............................................ 11
12.5 Glossary ................................................................ 30
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11 13 Mechanical, Packaging, and Orderable
Information ........................................................... 30

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (July 2010) to Revision A Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Removed Ordering Information table .................................................................................................................................... 1

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5 Description (continued)
The bq24650 charges the battery in three phases: pre-conditioning, constant current, and constant voltage.
Charge is terminated when the current reaches 1/10 of the fast charge rate. The pre-charge timer is fixed at 30
minutes. The bq24650 automatically restarts the charge cycle if the battery voltage falls below an internal
threshold and enters a low quiescent current sleep mode when the input voltage falls below the battery voltage.
The bq24650 supports a battery from 2.1 V to 26 V with VFB set to a 2.1-V feedback reference. The charge
current is programmed by selecting an appropriate sense resistor. The bq24650 is available in a 16 -pin, 3.5 mm
× 3.5 mm2 thin QFN package.

6 Pin Configuration and Functions

RVA Package
16-Pin VQFN
Top View

LODRV
HIDRV
BTST

PH
16

15

14

13
VCC 1 12 REGN

MPPSET 2 11 GND
ThermalPad
STAT1 3 10 SRP

TS 4 9 SRN
5

8
STAT2

VREF

TERM_EN

VFB

Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
IC power positive supply. Place a 1-μF ceramic capacitor from VCC to GND and place it as close as
1 VCC P
possible to IC. Place a 10-Ω resistor from input side to VCC pin to filter the noise.
Input voltage set point. Use a voltage divider from input source to GND to set voltage on MPPSET to 1.2
2 MPPSET I
V. To disable charge, pull MPPSET below 75 mV.
Open-drain charge status output to indicate various charger operation. Connect to the cathode of LED
3 STAT1 O with 10 kΩ to the pullup rail. LOW or LED light up indicates charge in progress. Otherwise stays HI or
LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off.
Temperature qualification voltage input. Connect to a negative temperature coefficient thermistor.
4 TS I Program the hot and cold temperature window with a resistor divider from VREF to TS to GND. A 103AT-
2 thermister is recommended.
Open-drain charge status output to indicate various charger operation. Connect to the cathode of LED
5 STAT2 O with 10 kΩ to the pullup rail. LOW or LED light up indicates charge is complete. Otherwise, stays HI or
LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off.
3.3-V reference voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC.
6 VREF P
This voltage could be used for programming voltage on TS and the pullup rail of STAT1 and STAT2.
Charge termination enable. Pull TERM_EN to GND to disable charge termination. Pull TERM_EN to
7 TERM_EN I
VREF to allow charge termination. TERM_EN must be terminated and cannot be left floating.
Charge voltage analog feedback adjustment. Connect the output of a resistor divider powered from the
8 VFB I
battery terminals to this node to adjust the output battery voltage regulation.

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Pin Functions (continued)


PIN
TYPE DESCRIPTION
NO. NAME
Charge current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to
9 SRN I provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from SRN to GND for
common-mode filtering.
Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to
10 SRP P/I provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP to GND for common-
mode filtering.
Power ground. Ground connection for high-current power converter node. On PCB layout, connect
11 GND P directly to source of low-side power MOSFET, to ground connection of input and output capacitors of the
charger. Only connect to GND through the thermal pad underneath the IC.
PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to GND,
12 REGN P close to the IC. Use to drive low-side driver and high-side driver bootstrap Schottky diode from REGN to
BTST.
PWM low-side driver output. Connect to the gate of the low-side N-channel power MOSFET with a short
13 LODRV O
trace.
Switching node, charge current output inductor connection. Connect the 0.1-μF bootstrap capacitor from
14 PH P
PH to BTST.
PWM high-side driver output. Connect to the gate of the high-side N-channel power MOSFET with a short
15 HIDRV O
trace.
16 BTST P PWM high-side driver positive supply. Connect the 0.1-µF bootstrap capacitor from PH to BTST.
Exposed pad beneath the IC. The thermal pad must always be soldered to the board and have the vias
Thermal
— — on the thermal pad plane star-connecting to GND and ground plane for high-current power converter. It
Pad
also serves as a thermal pad to dissipate heat.

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN MAX UNIT
VCC, STAT1, STAT2, SRP, SRN –0.3 33
PH –2 36
VFB –0.3 16
Voltage (with respect to GND) V
REGN, LODRV, TS, MPPSET, TERM_EN –0.3 7
BTST, HIDRV with respect to GND –0.3 39
VREF –0.3 3.6
Maximum difference voltage SRP–SRN –0.5 0.5 V
Junction temperature, TJ –40 155 °C
Storage temperature, Tstg –55 155 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
(3) Must have a series resistor between battery pack to VFB if battery pack voltage is expected to be greater than 16 V. Usually the resistor
divider top resistor takes care of this.

7.2 ESD Ratings


VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions


MIN MAX UNIT
VCC, STAT1, STAT2, SRP, SRN –0.3 28
PH –2 30
Voltage range (with respect to VFB –0.3 14
V
GND) REGN, LODRV, TS, MPPSET, TERM_EN –0.3 6.5
BTST, HIDRV with respect to GND –0.3 34
VREF 3.3
Maximum difference voltage SRP–SRN –0.2 0.2 V
Junction temperature, TJ –40 125 °C

7.4 Thermal Information


bq24650
THERMAL METRIC (1) RVA (VQFN) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance (2) 43.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 81 °C/W
RθJB Junction-to-board thermal resistance 16 °C/W
(3)
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter (4) 15.77 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a
(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

7.5 Electrical Characteristics


5 V ≤ VVCC ≤ 28 V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CONDITIONS
VVCC_OP VCC input voltage operating range 5 28 V
QUIESCENT CURRENTS
Total battery discharge current (sum of
currents into VCC, BTST, PH, SRP, VCC < VBAT, VCC > VUVLO (SLEEP) 15 µA
SRN, VFB), VFB ≤ 2.1V
IBAT
Battery discharge current (sum of VCC > VBAT, VCC > VUVLO, CE = LOW 5 µA
currents into BTST, PH, SRP, SRN, VCC > VBAT, VCC > VVCCLOWV,
VFB), VFB ≤ 2.1V 5 µA
CE = HIGH, Charge done
VCC > VBAT, VCC > VUVLO, CE = LOW 0.7 1 mA
VCC > VBAT, VCC > VVCCLOWV,
2 3 mA
Adapter supply current (sum of current CE = HIGH, charge done
IAC
into VCC pin)
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charging, Qg_total = 10 nC 25 mA
[1]
CHARGE VOLTAGE REGULATION
VREG Feedback regulation voltage 2.1 V
TJ = 0°C to 85°C –0.5% 0.5%
Charge voltage regulation accuracy
TJ = –40°C to 125°C –0.7% 0.7%
IVFB Leakage current into VFB pin VFB = 2.1 V 100 nA

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Electrical Characteristics (continued)


5 V ≤ VVCC ≤ 28 V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT REGULATION – FAST CHARGE
VIREG_CHG SRP-SRN current sense voltage range VIREG_CHG = VSRP – VSRN 40 mV
Charge current regulation accuracy VIREG_CHG = 40 mV –3% 3%
CURRENT REGULATION – PRE-CHARGE
Precharge current sense voltage
VPRECHG VIREG_PRCHG = VSRP – VSRN 4 mV
range
Precharge current regulation accuracy VIREG_PRECH = 4 mV –25% 25%
CHARGE TERMINATION
Termination current sense voltage
VTERMCHG VITERM = VSRP – VSRN 4 mV
range
Termination current accuracy VITERM = 4 mV –25% 25%
Deglitch time for termination (both
100 ms
edges)
tQUAL Termination qualification time VBAT > VRECH and ICHG < ITERM 250 ms
Discharge current once termination is
IQUAL Termination qualification current 2 mA
detected
INPUT VOLTAGE REGULATION
VMPPSET MPPSET regulation voltage 1.2 V
Input voltage regulation accuracy –0.6% 0.6%
IMPPSET Leakage current into MPPSET pin VMPPSET = 7 V, TA = 0 – 85°C 1 µA
VMPPSET_CD MPPSET shorted to disable charge 75 mV
VMPPSET_CE MPPSET released to enable charge 175 mV
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
VUVLO AC undervoltage rising threshold Measure on VCC 3.65 3.85 4 V
VUVLO_HYS AC undervoltage hysteresis, falling 350 mV
VCC LOWV COMPARATOR
VVCC LOWV_fall Falling threshold, disable charge Measure on VCC 4.1 V
VVCC LOWV_rise Rising threshold, resume charge 4.35 V
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP _FALL SLEEP falling threshold VVCC – VSRN to enter SLEEP 40 100 150 mV
VSLEEP_HYS SLEEP hysteresis 500 mV
SLEEP rising shutdown deglitch VCC falling below SRN 100 ms
VCC rising above SRN, Delay to exit
SLEEP falling powerup deglitch 30 ms
SLEEP mode
BAT LOWV COMPARATOR
Precharge to fast charge transition
VLOWV Measure on VFB pin 1.54 1.55 1.56 V
(LOWV threshold)
VLOWV_HYS LOWV hysteresis 100 mV
LOWV rising deglitch VFB falling below VLOWV 25 ms
LOWV falling deglitch VFB rising above VLOWV + VLOWV_HYS 25 ms
RECHARGE COMPARATOR
Recharge threshold (with respect to
VRECHG Measure on VFB pin 35 50 65 mV
VREG)
Recharge rising deglitch VFB decreasing below VRECHG 10 ms
Recharge falling deglitch VFB increasing above VRECHG 10 ms
BAT OVERVOLTAGE COMPARATOR
VOV_RISE Overvoltage rising threshold As percentage of VFB 104%
VOV_FALL Overvoltage falling threshold As percentage of VFB 102%

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Electrical Characteristics (continued)


5 V ≤ VVCC ≤ 28 V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT OVERVOLTAGE COMPARATOR (ACOV)
AC overvoltage rising threshold on
VACOV 31 32 33 V
VCC
VACOV_HYS AC overvoltage falling hysteresis 1 V
AC overvoltage deglitch (both edges) Delay to changing the STAT pins 1 ms
AC overvoltage rising deglitch Delay to disable charge 1 ms
AC overvoltage falling deglitch Delay to resume charge 20 ms
THERMAL SHUTDOWN COMPARATOR
TSHUT Thermal shutdown rising temperature Temperature increasing 145 °C
TSHUT_HYS Thermal shutdown hysteresis 15 °C
Thermal shutdown rising deglitch Temperature increasing 100 µs
Thermal shutdown falling deglitch Temperature decreasing 10 ms
THERMISTOR COMPARATOR
VLTF Cold temperature rising threshold 72.5% 73.5% 74.5%
VLTF_HYS Rising hysteresis 0.2% 0.4% 0.6%
As percentage to VVREF
VHTF Hot temperature rising threshold 46.7% 47.5% 48.3%
VTCO Cut-off temperature rising threshold 44.3% 45% 45.7%
Deglitch time for temperature out of VTS < VLTF, or VTS < VTCO, or
400 ms
range detection VTS < VHTF
Deglitch time for temperature in valid VTS > VLTF – VLTF_HYS or VTS >VTCO, or
20 ms
range detection VTS > VHTF
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
Current rising, in synchronous mode
VOC Charge overcurrent rising threshold 80 mV
measure (VSRP – VSRN)
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
VISYNSET Charge undercurrent falling threshold Switch from CCM to DCM, VSRP > 2.2V 1 5 9 mV
BATTERY-SHORTED COMPARATOR (BATSHORT)
BAT short falling threshold, forced
VBATSHT VSRP falling 2 V
non-synchronous mode
VBATSHT_HYS BAT short rising hysteresis 200 mV
tBATSHT_DEG Deglitch on both edges 1 µs
LOW CHARGE CURRENT COMPARATOR
VLC Low charge current falling threshold Measure V(SRP-SRN) 1.25 mV
VLC_HYS Low charge current rising hysteresis 1.25 mV
tLC_DEG Deglitch on both edges 1 µs
VREF REGULATOR
VVREF_REG VREF regulator voltage VVCC > VUVLO, 0 – 35 mA load 3.267 3.3 3.333 V
IVREF_LIM VREF current limit VVREF = 0 V, VVCC > VUVLO 35 mA

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Electrical Characteristics (continued)


5 V ≤ VVCC ≤ 28 V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REGN REGULATOR
VREGN_REG REGN regulator voltage VVCC > 10 V, MPPSET > 175 mV 5.7 6.0 6.3 V
VREGN = 0 V, VVCC > VUVLO, MPPSET <
IREGN_LIM REGN current limit 40 mA
75 mV
BATTERY DETECTION
tWAKE Wake timer Max time charge is enabled 500 ms
IWAKE Wake current RSENSE = 10 mΩ 50 125 200 mA
tDISCHARGE Discharge timer Max time discharge current is applied 1 sec
IDISCHARGE Discharge current 6 mA
IFAULT Fault current after a timeout fault 2 mA
IQUAL Termination qualification current 2 mA
tQUAL Termination qualification time 250 ms
Voltage on VFB to detect battery absent
VWAKE Wake threshold (with respect to VREG) 50 mV
during wake
Voltage on VFB to detect battery absent
VDISCH Discharge threshold 1.55 V
during discharge
PWM HIGH-SIDE DRIVER (HIDRV)
High-side driver (HSD) turnon
RDS_HI_ON VBTST – VPH = 5.5 V 3.3 6 Ω
resistance
RDS_HI_OFF High-side driver turnoff resistance 1 1.4 Ω
Bootstrap refresh comparator VBTST – VPH when low side refresh pulse
VBTST_REFRESH 4.0 4.2 V
threshold Voltage is requested
PWM LOW-SIDE DRIVER (LODRV)
Low-side driver (LSD) turn-on
RDS_LO_ON 4.1 7 Ω
resistance
RDS_LO_OFF Low-side driver turn-off resistance 1 1.4 Ω
PWM DRIVERS TIMING
Dead time when switching between LSD
Driver dead-time 30 ns
and HSD, No load at LSD and HSD
PWM OSCILLATOR
VRAMP_HEIGHT PWM ramp height As percentage of VCC 7%
PWM switching frequency 510 600 690 kHz
INTERNAL SOFT START (8 STEPS TO REGULATION CURRENT ICHG)
Soft-start steps 8 step
Soft-start step time 1.6 ms
CHARGER SECTION POWER-UP SEQUENCING
Delay from MPPSET > 175 mV to charger
Charge-enable delay after power-up 1.5 s
is allowed to turn on
LOGIC IO PIN CHARACTERISTICS (STAT1, STAT2, TERM_EN)
STAT1, STAT2 output low saturation
VOUT_LOW Sink current = 5 mA 0.5 V
voltage
IOUT_HI Leakage current V = 32 V 1.2 µA
VIN_LOW TERM_EN input low threshold voltage 0.4 V
TERM_EN input high threshold
VIN_HI 1.6 V
voltage
IIN_BIAS TERM_EN bias current VTERM_EN = 0.5 V 60 µA

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7.6 Typical Characteristics


VCC = 25 V, bq24650 application circuit, TA = 25°C unless otherwise noted

MPPSET
VCC 1V/div
10V/div
LODRV
5V/div
VREF
2V/div PH
20V/div
REGN
5V/div

STAT1
20V/div IBAT
1A/div

800 ms/div 400 ms/div

Figure 1. Power Up on VCC Figure 2. Charge Start on MPPSET

MPPSET
MPPSET 1V/div
1V/div

LODRV LODRV
5V/div 5V/div
PH
20V/div
PH
20V/div

IBAT
IBAT 1A/div
1A/div

4 ms/div 10 ms/div

Figure 3. Charge Soft Start on MPPSET Figure 4. Charge Stop on MPPSET

HIDRV
HIDRV 20V/div
20V/div
PH
PH 20V/div
20V/div

LODRV
LODRV
5V/div
5V/div

IL
1A/div IL
1A/div

100 ns/div 200 ns/div

Figure 5. Switching in Continuous Conduction Mode Figure 6. Switching in Discontinuous Conduction Mode

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Typical Characteristics (continued)


VCC = 25 V, bq24650 application circuit, TA = 25°C unless otherwise noted

HIDRV
20V/div HIDRV
20V/div
PH PH
20V/div 20V/div

LODRV LODRV
5V/div 5V/div

IL IL
1A/div 1A/div

400 ms/div 100 ns/div

Figure 7. Switching at 100% Duty Cycle Figure 8. Recharge the BTST-PH Capacitor

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8 Detailed Description

8.1 Overview
The bq24650 is a highly integrated solar input Li-ion or Li-polymer battery charge controller.

8.2 Functional Block Diagram

VREF bq24650

VOLTAGE
REFERENCE
VCC -
SLEEP
SRN+100 mV +

VCC -
SLEEP UVLO
VUVLO +
3.3V UVLO
VREF LDO VCC
VCC

175 mV -
+

FBO

MPPSET - COMP
1.2 V + ERROR BTST
AMPLIFIER
EAO CE
EAI - +
+ PWM
1V -
VFB + LEVEL HIDRV
SHIFTER
2.1 V -
BAT_OVP

20uA +
SRP-SRN
SRP SYNCH PH
-
+ PWM
+ 5 mV - VCC
V(SRP-SRN) + CONTROL
20X
- LOGIC
0.8V -
SRN BTST - REFRESH 6V LDO REGN
_+ +
20 uA PH
CE
4V
FAULT
LODRV
V(SRP-SRN) -
2 mA CHG_OCP
200% X IBAT_REG +
GND
8 mA
FAULT
30 Minute STAT 1
IC Tj + TSHUT
Precharge CHARGE
CHARGE
Timer 145°C -
DISCHARGE STAT1
TERM_EN VFB - BAT_OVP
STATE
104% X 2.1V +
MACHINE
0.8V IBAT_ REG LOGIC
STAT2
0.8V
10 STAT 2

LOWV BATTERY
DETECTION
VFB - LOWV LOGIC DISCHARGE VREF
+
1.5V +-
+ LTF -
VCC ACOV
- +
+
32V - TS
VFB - SUSPEND
RCHRG HTF +
+ -
2.05V +-

RCHRG TCO +
V(SRP - SRN) + -
TERM TERM
0.8V -
10 TERMINATE CHARGE

Copyright © 2016, Texas Instruments Incorporated

8.3 Feature Description


8.3.1 Battery Voltage Regulation
The bq24650 uses a high accuracy voltage regulator for the charging voltage. The charge voltage is
programmed through a resistor divider from the battery to ground, with the midpoint tied to the VFB pin. The
voltage at the VFB pin is regulated to 2.1 V, giving Equation 1 for the regulation voltage:
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Feature Description (continued)


é R2 ù
VBAT = 2.1 V ´ ê1+
ë R1 úû
where
• R2 is connected from VFB to the battery
• and R1 is connected from VFB to GND. (1)
Li-Ion, LiFePO4, and sealed lead acid are widely used battery chemistries. Most commercial Li-ion cells can now
be charged to 4.2 V/cell. A LiFePO4 battery allows a much higher charge and discharge rate, but the energy
density is lower. The typical cell voltage is 3.6 V. The charge profile of both Li-Ion and LiFePO4 is
preconditioning, constant current, and constant voltage. For maximum cycle life, the end-of-charge voltage
threshold could be lowered to 4.1 V/cell.
Although the energy density is much lower than Li-based chemistry, lead acid is still popular due to its low
manufacturing cost and high discharge rates. The typical voltage limit is from 2.3 V to 2.45 V. After the battery
has been fully charged, a float charge is required to compensate for the self-discharge. The float charge limit is
100 mV to 200 mV below the constant voltage limit.
Precharge Fastcharge Current Fastcharge Voltage
Current Regulation Phase Regulation Phase Termination
Regulation
Regulation Voltage Phase
VRECH
Regulation Current

Charge
Current

Charge
Voltage

VLOWV

IPRECH & ITERM

Figure 9. Typical Charging Profile

8.3.2 Input Voltage Regulation


A solar panel has a unique point on the V-I or V-P curve, called the Maximum Power Point (MPP), at which the
entire photovoltaic (PV) system operates with maximum efficiency and produces its maximum output power. The
constant voltage algorithm is the simplest Maximum Power Point Tracking (MPPT) method. The bq24650
automatically reduces charge current so the maximum power point is maintained for maximum efficiency.
If the solar panel or other input source cannot provide the total power of the system and bq24650 charger, the
input voltage drops. When the voltage sensed on the MPPSET pin drops below 1.2 V, the charger maintains the
input voltage by reducing the charge current. If the MPPSET pin voltage is forced below 1.2 V, the bq24650
stays in the input voltage regulation loop while the output current is zero. The STAT1 pin is LOW and STAT2 pin
is HIGH.

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Feature Description (continued)


The voltage at the MPPSET pin is regulated to 1.2 V, giving Equation 2 for the regulation voltage:
é R3 ù
VMPPSET = 1.2 V ´ ê1+ ú
ë R4 û (2)
The MPPSET pin is also used as charge enable control. If the voltage on MPPSET is pulled down below 75 mV,
charge is disabled. Charge resumes if the voltage on MPPSET goes back above 175 mV.

8.3.3 Battery Current Regulation


Battery current is sensed by resistor RSR connected between SRP and SRN. The full-scale differential voltage
between SRP and SRN is fixed at 40 mV. Thus, for a 20-mΩ sense resistor, the charging current is 2 A. For
charging current, refer to Equation 3:
40 mV
ICHARGE =
RSR (3)

8.3.4 Battery Precharge


On power-up, if the battery voltage is below the VLOWV threshold, the bq24650 applies the precharge current to
the battery. This feature is intended to revive deeply discharged cells. If the VLOWV threshold is not reached within
30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.
The precharge current is determined as 1/10 of the fast charge current according to Equation 4:
4 mV
IPRECHARGE =
RSR (4)

8.3.5 Charge Termination and Recharge


The bq24650 monitors the charging current during the voltage regulation phase. Termination is detected while
the voltage on the VFB pin is higher than the VRECH threshold and the charge current is less than the ITERM
threshold (1/10 of fast charge current), as calculated in Equation 5:
4 mV
ITERM =
RSR (5)
A new charge cycle is initiated when one of the following conditions occurs:
• The battery voltage falls below the recharge threshold
• A power-on-reset (POR) event occurs
• MPPSET falls below 75 mV to reset charge enable
The TERM_EN pin may be taken LOW to disable termination. If TERM_EN is pulled above 1.6 V, the bq24650
allows termination.

8.3.6 Power Up
The bq24650 uses a SLEEP comparator to determine the source of power on the VCC pin, because VCC can be
supplied either from a battery or an adapter. If the VCC voltage is greater than the SRN voltage, and all other
conditions are met for charging, the bq24650 then attempts to charge a battery (see Enable and Disable
Charging). If SRN voltage is greater than VCC, indicating that a battery is the power source, the bq24650 enters
low quiescent current (< 15 µA) SLEEP mode to minimize current drain from the battery.
If VCC is below the UVLO threshold, the device is disabled, and VREF LDO turns off.

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Feature Description (continued)


8.3.7 Enable and Disable Charging
The following conditions have to be valid before charging is enabled:
• Charge is allowed (MPPSET > 175 mV)
• Device is not in undervoltage lockout (UVLO) mode and VCC is above the VCCLOWV threshold
• Device is not in SLEEP mode (that is, VCC > SRN)
• VCC voltage is lower than AC overvoltage threshold (VCC < VACOV)
• 30-ms delay is complete after initial power-up
• REGN LDO and VREF LDO voltages are at correct levels
• Thermal Shut (TSHUT) is not valid
• TS fault is not detected
One of the following conditions stops on-going charging:
• Charge is disabled (MPPSET < 75 mV)
• Adapter is removed, causing the device to enter VCCLOWV or SLEEP mode
• Adapter voltage is less than 100 mV above battery
• Adapter is over voltage
• REGN or VREF LDO voltage is not valid
• TSHUT IC temperature threshold is reached
• TS voltage goes out of range indicating the battery temperature is too hot or too cold

8.3.8 Automatic Internal Soft-Start Charger Current


The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists
of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.
Each step lasts approximately 1.6 ms, for a typical rise time of 13 ms. No external components are needed for
this function.

8.3.9 Converter Operation


The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A
type III compensation network allows using ceramic capacitors at the output of the converter. The compensation
input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The
feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output
(EAO). The LC output filter must be selected to give a resonant frequency of 12 kHz – 17 kHz for the bq24650,
where resonant frequency, fo, is given by:
1
fo =
2p L o Co (6)
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage and simplifies the loop
compensation. The ramp is offset by 300 mV to allow zero percent duty-cycle when the EAO signal is below the
ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100% duty-cycle
PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the N-channel upper
device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2 V for more
than 3 cycles, then the high-side N-channel power MOSFET is turned off and the low-side N-channel power
MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver
returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again due to leakage
current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region.

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Feature Description (continued)


8.3.10 Synchronous and Non-Synchronous Operation
The charger operates in synchronous mode when the SRP-SRN voltage is above 5 mV (0.5-A inductor current
for a 10-mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is break-
before-make complimentary switching to prevent shoot-through currents. During the 30-ns dead time where both
FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the low-side
FET turn on keeps power dissipation low, and allows safe charging at high currents. During synchronous mode
the inductor current is always flowing and the converter operates in continuous conduction mode (CCM), creating
a fixed two-pole system.
The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5 mV (0.5-A inductor
current for a 10-mΩ sense resistor). In addition, the charger is forced into non-synchronous mode when battery
voltage is lower than 2 V or when the average SRP-SRN voltage is lower than 1.25 mV.
During non-synchronous operation, the body-diode of the low-side MOSFET can conduct the positive inductor
current after the low-side N-channel power MOSFET turns off. When the load current decreases and the inductor
current drops to zero, the body diode is naturally turned off and the inductor current becomes discontinuous. This
mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side N-channel power MOSFET
turns on when the bootstrap capacitor voltage drops below 4.2 V, then the low-side power MOSFET turns off and
stays off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. The low-
side MOSFET on time is required to ensure the bootstrap capacitor is always recharged and able to keep the
high-side power MOSFET on during the next cycle. This is important for battery chargers, where unlike regular
DC-DC converters, there is a battery load that maintains a voltage and can both source and sink current. The
low-side pulse pulls the PH node (connection between high and low-side MOSFETs) down, allowing the
bootstrap capacitor to recharge up to the REGN LDO value. After the refresh pulse, the low-side MOSFET is
kept off to prevent negative inductor current from occurring.
At very low currents during non-synchronous operation, there may be a small amount of negative inductor
current during the recharge pulse. The charge must be low enough to be absorbed by the input capacitance.
Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the low-
side MOSFET does not turn on (except for recharge pulse) either, and there is almost no discharge from the
battery.
During DCM mode the loop response automatically changes and has a single pole system at which the pole is
proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.

8.3.11 Cycle-by-Cycle Charge Undercurrent


In the bq24650, if the SRP-SRN voltage decreases below 5 mV, the low-side FET is turned off for the remainder
of the switching cycle to prevent negative inductor current. During DCM, the low-side FET only turns on when the
bootstrap capacitor voltage drops below 4.2 V to provide refresh charge for the bootstrap capacitor. This is
important to prevent negative inductor current from causing a boost effect in which the input voltage increases as
power is transferred from the battery to the input capacitors and lead to an overvoltage stress on the VCC node
and potentially cause damage to the system.

8.3.12 Input Overvoltage Protection (ACOV)


ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage
reaches the ACOV threshold, charge is disabled.

8.3.13 Input Undervoltage Lockout (UVLO)


The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from
either input adapter or battery, since a conduction path exists from the battery to VCC through the high-side
NMOS body diode. When VCC is below the UVLO threshold, all circuits on the IC, including VREF LDO, are
disabled.

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Feature Description (continued)


8.3.14 Battery Overvoltage Protection
The converter does not allow the high-side FET to turn on until the BAT voltage goes below 102% of the
regulation voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load
is removed or the battery is disconnected. A current sink from SRP to GND is on to discharge the stored energy
on the output capacitors.

8.3.15 Cycle-by-Cycle Charge Overcurrent Protection


The charger has a secondary cycle-to-cycle over-current protection. It monitors the charge current and prevents
the current from exceeding 200% of the programmed charge current. The high-side gate drive turns off when
overcurrent is detected and automatically resumes when the current falls below the overcurrent threshold.

8.3.16 Thermal Shutdown Protection


The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junction temperatures low. As an added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C.

8.3.17 Temperature Qualification


The controller continuously monitors battery temperature by measuring the voltage between the TS pin and
GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this
voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.
To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. If battery
temperature is outside of this range, the controller suspends charge and waits until the battery temperature is
within the VLTF to VHTF range. During the charge cycle the battery temperature must be within the VLTF to VTCO
thresholds. If battery temperature is outside of this range, the controller suspends charge and waits until the
battery temperature is within the VLTF to VHTF range. The controller suspends charge by turning off the PWM
charge FETs. Figure 10 summarizes the operation.
VREF VREF

CHARGE SUSPENDED CHARGE SUSPENDED

VLTF VLTF
VLTFH VLTFH

TEMPERATURE RANGE TEMPERATURE RANGE


TO INITIATE CHARGE DURING A CHARGE
CYCLE

VHTF
VTCO
CHARGE SUSPENDED CHARGE SUSPENDED
GND GND

Figure 10. TS Pin, Thermistor Sense Thresholds

Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 15, the values of RT1 and RT2 can
be determined by using Equation 7 and Equation 8:
æ 1 1 ö
VVREF ´ RTHCOLD ´ RTHHOT ´ ç - ÷
è VLTF VTCO ø
RT2 =
æV ö æV ö
RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷
V
è TCO ø V
è LTF ø (7)

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Feature Description (continued)


VVREF
-1
VLTF
RT1 =
1 1
+
RT2 RTHCO LD (8)

VREF

bq24650 RT1

TS

RT2 RTH
103AT

Copyright © 2016, Texas Instruments Incorporated

Figure 11. TS Resistor Network

8.3.18 Charge Enable


MPPSET is used to disable or enable the charge process. A voltage above 175 mV on this pin enables charge,
provided all other conditions for charge are met (see Enable and Disable Charging). A voltage below 75 mV on
this pin also resets all timers and fault conditions.

8.3.19 Inductor, Capacitor, and Sense Resistor Selection Guidelines


The bq24650 provides internal loop compensation. With this scheme, the best stability occurs when the LC
resonant frequency, fo, is approximately 12 kHz – 17 kHz for the bq24650.
Table 1 provides a summary of typical LC components for various charge currents.

Table 1. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current
CHARGE CURRENT 0.5 A 1A 2A 4A 8A 10 A
Output inductor low 22 µH 15 µH 10 µH 6.8 µH 3.3 µH 3.3 µH
Output capacitor CO 7 µF 10 µF 15 µF 20 µF 40 µF 40 µF
Sense resistor 80 mΩ 40 mΩ 20 mΩ 10 mΩ 5 mΩ 4 mΩ

8.3.20 Charge Status Outputs


The open-drain STAT1 and STAT2 outputs indicate various charger operations as listed in Table 2. These status
pins can be used to drive LEDs or communicate with the host processor.

NOTE
OFF indicates that the open-drain transistor is turned off.

Table 2. STAT Pin Definition for bq24650


CHARGE STATE STAT1 STAT2
Charge in progress ON OFF
Charge complete OFF ON
Charge suspend, overvoltage, sleep mode, battery absent OFF OFF

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8.3.21 Battery Detection


For applications with removable battery packs, the bq24650 provides a battery absent detection scheme to
reliably detect insertion or removal of battery packs.

POR or RECHARGE The battery detection routine runs on


power up, or if VFB falls below VRECH
due to removing a battery or
discharging a battery
Apply 8mA discharge
current, start 1s timer

1s timer
VFB < VLOWV No No
expired

Yes Yes

Disable 6mA Battery Present,


discharge current Begin Charge

Enable 125mA Charge,


Start 0.5s timer

0.5s timer
VFB > VRECH No No
expired

Yes
Yes

Battery Present,
Disable 125mA Begin Charge
Charge

Battery Absent

Figure 12. Battery Detection Flowchart

When the device has powered up, a 6-mA discharge current is applied to the SRN terminal. If the battery voltage
falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is turned on
at low charge current (125 mA). If the battery voltage gets up above the recharge threshold within 500 ms, there
is no battery present and the cycle restarts. If either the 500 ms or 1 second timer time out before the respective
thresholds are hit, a battery is detected and a charge cycle is initiated.

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Battery not detected

VREG
VRECH
(VWAKE)
Battery
inserted

VLOWV
(VDISCH) Battery detected

tWAKE
tLOWV_DEG tRECH_DEG

Figure 13. Battery Detect Timing Diagram

Take care that the total output capacitance at the battery node is not so large that the discharge current source
cannot pull the VFB voltage below the LOWV threshold during the 1 second discharge time. The maximum output
capacitance can be calculated according to Equation 9:
I ´ tDISCH
CMAX = DISCH
é R ù
0.5 ´ ê1+ 2 ú
ë R1 û
where
• CMAX is the maximum output capacitance,
• IDISCH is the discharge current,
• tDISCH is the discharge time,
• and R2 and R1 are the voltage feedback resistors from the battery to the VFB pin. (9)
The 0.5 factor is the difference between the RECHARGE and the LOWV thresholds at the VFB pin.

8.3.21.1 Example
For a 3-cell Li+ charger, with R2 = 500 kΩ, R1 = 100 kΩ (giving 12.6 V for voltage regulation), IDISCH = 6 mA,
tDISCH = 1 second.
6 mA ´ 1 sec
CMAX = = 2000 μF
é 500 kW ù
0.5 ´ ê1+ ú
ë 100 kW û (10)
Based on these calculations, no more than 2000 µF must be allowed on the battery node for proper operation of
the battery detection circuit.

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8.4 Device Functional Modes


8.4.1 Converter Operation
The synchronous buck PWM converter uses a fixed-frequency voltage mode with a feed-forward control scheme.
A type-III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 17 kHz to 25 kHz for the
bq24650, where the resonant frequency, fo, is given by Equation 11:
1
fo =
2p Lo Co (11)
An internal sawtooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is 7% of the input adapter voltage, making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop
compensation. The ramp is offset by 300 mV to allow zero-percent duty cycle when the EAO signal is below the
ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100% duty-cycle
PWM request. Internal gate-drive logic allows achieving 99.5% duty cycle while ensuring the N-channel upper
device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2 V for more
than 3 cycles, then the high-side N-channel power MOSFET is turned off and the low-side N-channel power
MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver
returns to 100% duty-cycle operation until the (BTST–PH) voltage is detected to fall low again due to leakage
current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region.

8.4.2 Synchronous and Non-Synchronous Operation


The charger operates in synchronous mode when the SRP-SRN voltage is above 5 mV (0.5-A inductor current
for a 10-mΩ sense resistor). During synchronous mode, the internal gate-drive logic ensures there is break-
before-make complementary switching to prevent shoot-through currents. During the 30-ns dead time where both
FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the low-side
FET turn on keeps the power dissipation low, and allows safely charging at high currents. During synchronous
mode, the inductor current is always flowing and the converter operates in continuous-conduction mode (CCM),
creating a fixed two-pole system.
The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5 mV (0.5-A inductor
current for a 10-mΩ sense resistor). The charger is forced into non-synchronous mode when battery voltage is
lower than 2 V or when the average SRP-SRN voltage is lower than 1.25 mV.
During non-synchronous operation, the body diode of the low-side MOSFET can conduct the positive inductor
current after the high-side N-channel power MOSFET turns off. When the load current decreases and the
inductor current drops to zero, the body diode is naturally turned off and the inductor current becomes
discontinuous. This mode is called discontinuous-conduction mode (DCM). During DCM, the low-side N-channel
power MOSFET turns on for around 80 ns when the bootstrap capacitor voltage drops below 4.2 V; then the low-
side power MOSFET turns off and stays off until the beginning of the next cycle, where the high-side power
MOSFET is turned on again. The 80-ns low-side MOSFET ON-time is required to ensure the bootstrap capacitor
is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important
for battery chargers, where unlike regular DC-DC converters, there is a battery load that maintains a voltage and
can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high and
low-side MOSFETs) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80
ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring.
At very low currents during non-synchronous operation, there may be a small amount of negative inductor
current during the 80-ns recharge pulse. The charge must be low enough to be absorbed by the input
capacitance. Whenever the converter goes into zero-percent duty cycle, the high-side MOSFET does not turn on,
and the low-side MOSFET does not turn on (only 80-ns recharge pulse) either, and there is almost no discharge
from the battery.

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Device Functional Modes (continued)


During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.

POR

SLEEP MODE

VCC > SRN No


Indicate SLEEP

Yes

Enable VREF LDO &


Chip Bias

Indicate battery Battery Initiate battery


No
absent present? detect algorithm

Yes
See Enabling and Disabling
Charge Section
Indicate NOT
Conditions met Conditions met
No CHARGING, No No
for charge? for charge?
Suspend timers

Yes Yes

Regulate
precharge current
Start 30 minute Precharge
VFB < VLOWV Yes VFB < VLOWV Yes
precharge timer Indicate Charge- timer expired?
In-Progress

Start Fastcharge
No No
timer

Regulate
fastcharge current Yes
Indicate NOT
Conditions met
CHARGING, No Yes
for charge? Indicate Charge-
Suspend timers
In-Progress

No

Turn off charge,


FAULT
Enable IDISCHG for 1
Enable IFAULT
second VFB > VRECH
Fastcharge
Yes & No Yes
Timer Expired?
Indicate Charge In ICHG < ITERM Indicate FAULT
Progress

No

Charge Complete
VFB > VRECH Yes
VFB < VRECH No
Indicate DONE

Battery Removed

Yes Indicate BATTERY


ABSENT

Figure 14. Operational Flowchart for bq24650

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information


The evaluation module (bq24650EVM-639) is a complete charger module for evaluating a stand-alone multi-cell
Li-ion solar power charger using the bq24650 device.

9.2 Typical Application


Solar Cell
D1
Half Panel
VIN R6: 10Ω
R5
2Ω
C1
VCC C2
2.2µF
bq24650 1uF

VREF
C3 C4:1µF
R9 R3 1µF
5.23kΩ 499kΩ REGN
D2
MPPSET BTST C6
Pack Q1 10uF
Thermistor RSR
HIDRV C5
TS L: 10µH 20mΩ Battery Pack
R10 100nF
CE Q3 R4 PH
30.1kΩ 36kΩ TERM_EN
Q2 C9
LODRV C8 4.7µF
GND 10µF
C10
VIN D3 R2
SRP 22pF
R7:10kΩ STAT1 C7 499kΩ
0.1µF R1
R8:10k Ω STAT2 Thermal SRN
100kΩ
Pad VFB
D4

Copyright © 2016, Texas Instruments Incorporated

Solar Panel 21 V, MPPT = 18 V, 2-cell, ICHARGE = 2 A, IPRECHARGE = ITERM = 0.2 A, TS = 0 – 45°C

Figure 15. Typical System Schematic

9.2.1 Design Requirements


This design requires a 21-V solar panel charger for 2_cell and 2A Li-ion battery charger.

9.2.2 Detailed Design Procedure

9.2.2.1 Inductor Selection


The bq24650 has a 600-kHz switching frequency to allow the use of small inductor and capacitor values.
Inductor saturation current must be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG +(1/2)IRIPPLE (12)
Inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs), and
inductance (L):

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Typical Application (continued)


VIN ´ D ´ (1 - D)
IRIPPLE =
fs × L (13)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in
the range of 20% to 40% of the maximum charging current as a trade-off between inductor size and efficiency for
a practical design.

9.2.2.2 Input Capacitor


The input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst-
case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate
at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50%
and can be estimated by Equation 14:
ICIN = ICHG ´ D ´ (1 - D) (14)
A low ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and must be
placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The
voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V rating or higher
capacitor is preferred for a 20-V input voltage. A 20-μF capacitance is suggested for a typical 3-A to 4-A charging
current.

9.2.2.3 Output Capacitor


The output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given as:
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2 ´ 3 (15)
The output capacitor voltage ripple can be calculated in Equation 16:
VOUT æ V ö
DVO = ç 1 - OUT
2 ç
÷
8LCfs è VIN ÷
ø (16)
At certain input/output voltages and switching frequencies, the voltage ripple can be reduced by increasing the
output filter inductor and capacitor values.
The bq24650 has an internal loop compensator. To achieve good loop stability, the resonant frequency of the
output inductor and output capacitor must be designed between 12 kHz and 17 kHz. The preferred ceramic
capacitor has a 35 V or higher rating, X7R or X5R.
Ceramic capacitors show a de-bias effect. This effect reduces the effective capacitance when a DC-bias voltage
is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a
significant capacitance drop, especially for high voltages and small capacitor packages. See the manufacturer’s
datasheet about performance with a DC bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value to achieve the required value at the operating point.

9.2.2.4 Power MOSFETs Selection


Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6 V of gate drive voltage. 30 V or higher voltage rating MOSFETs are
preferred for 20-V input voltage, and 40 V or higher rating MOSFETs are preferred for 20-V to 28-V input voltage.
Figure-of-merit (FOM) is usually used for selecting a proper MOSFET based on a tradeoff between conduction
loss and switching loss. For a top-side MOSFET, FOM is defined as the product of the MOSFET's on-resistance,
RDS(on), and the gate-to-drain charge, QGD. For a bottom-side MOSFET, FOM is defined as the product of the
MOSFET's on-resistance, RDS(on), and the total gate charge, QG.
FOMtop = RDS(on) ´ QGD ; FOMbottom = RDS(ON) ´ QG
(17)
The lower the FOM value, the lower the total power loss. Usually a lower RDS(on) has a higher cost with the same
package size.
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Typical Application (continued)


Top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D = VOUT/VIN),
charging current (ICHG), the MOSFET's on-resistance RDS(on), input voltage (VIN), switching frequency (F), turnon
time (ton) and turnoff time (toff):
1
Ptop = D ´ ICHG2 ´ RDS(ON) + ´ VIN ´ ICHG ´ (t on + t off ) ´ F
2 (18)
The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100°C junction
temperature rise. The second term represents switching loss. The MOSFET turnon and turnoff times are given
by:
Q Q
t on = SW ; t off = SW
Ion Ioff

where
• QSW is the switching charge,
• Ion is the turnon gate driving current,
• and Ioff is the turnoff gate driving current. (19)
If the switching charge is not given in the MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD)
and gate-to-source charge (QGS):
1
QSW = QGD + ´ QGS
2 (20)
The gate driving current total can be estimated by the REGN voltage (VREGN), MOSFET plateau voltage (VPLT),
total turnon gate resistance (Ron), and turnoff gate resistance (Roff) of the gate driver:
VREGN - Vplt Vplt
Ion = ; Ioff =
Ron Roff (21)
The conduction loss of the bottom-side MOSFET is calculated in Equation 22 when it operates in synchronous
continuous conduction mode:
Pbottom = (1 - D) ´ ICHG2 ´ RDS(ON)
(22)
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result, all of the freewheeling current goes through the body diode of the bottom-side MOSFET. The
maximum charging current in non-synchronous mode can be up to 0.9 A (0.5 A typical) for a 10-mΩ charging
current sensing resistor, considering the IC tolerance. Choose a bottom-side MOSFET with either an internal
Schottky or body diode capable of carrying the maximum non-synchronous mode charging current.
MOSFET gate driver power loss contributes to dominant losses on the controller IC, when the buck converter is
switching. Choosing a MOSFET with a small Qg_total reduces power loss to avoid thermal shutdown.
PICLOSS_Driver = VIN ´ Qg_total ´ fs

where
• Qg_total is the total gate charge for both the upper and lower MOSFETs at 6V VREGN. (23)

9.2.2.5 Input Filter Design


During adapter hot plug-in, the parasitic inductance and the input capacitor from the adapter cable form a second
order system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage the
IC. The input filter must be carefully designed and tested to prevent an overvoltage event on the VCC pin.
There are several methods to damping or limiting the over-voltage spike during adapter hot plug-in. An
electrolytic capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC
maximum pin voltage rating. A high current capability TVS Zener diode can also limit the over-voltage level to an
IC safe level. However, these two solutions may not be lowest cost or smallest size.

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Typical Application (continued)


A cost-effective and small size solution is shown in Figure 16. R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used
for reverse voltage protection for the VCC pin. C2 is the VCC pin decoupling capacitor and it must be placed as
close as possible to the VCC pin. R2 and C2 form a damping RC network to further protect the IC from high dv/dt
and high voltage spike. The C2 value must be less than the C1 value so R1 can dominant the equivalent ESR
value to get enough damping effect for hot plug-in. R1 and R2 must be sized enough to handle in-rush current
power loss according to the resistor manufacturer’s datasheet. The filter component values always need to be
verified with a real application. Table 3 lists the components for the typical application.
D1
R2(1206)
R1(2010) 4.7 - 30 W
Adapter 2W
VCC pin
Connector C1
2.2 mF C2
0.1 - 1 mF

Copyright © 2016, Texas Instruments Incorporated

Figure 16. Input Filter

Table 3. Component List for the Typical System Circuit in Figure 15


PART DESIGNATOR QTY DESCRIPTION
Q1, Q2 2 N-channel MOSFET, 40-V, 10-A, PowerPAK SO-8, Vishay-Siliconix, Si7288
D2 1 Diode, Dual Schottky, 30-V, 200-mA, SOT-23, Fairchild, BAT54C
D3, D4 2 LED Diode, Green, 2.1-V, 20-mA, LTST-C190GKT
RSR 1 Sense Resistor, 20-mΩ, Vishay-Dale, WSL1206R0200DEA
L1 1 Inductor, 10-µH, 7-A, Vishay-Dale IHLP-2525CZ
C6, C8 2 Capacitor, Ceramic, 10-μF, 35-V, 20%, X7R, 1210, Panasonic
C9 1 Capacitor, Ceramic, 4.7-μF, 35-V, 20%, X7R, 1210, Panasonic
C2, C3, C4 3 Capacitor, Ceramic, 1-μF, 35-V, 10%, X7R, 0805, Kemet
C5, C7 2 Capacitor, Ceramic, 0.1-μF, 35-V, 10%, X7R, 0805, Kemet
C1 1 Capacitor, Ceramic, 2.2-μF, 35-V, 10%, X7R, 1210, Kemet
C10 1 Capacitor, Ceramic, 22-pF, 35-V, 10%, X7R, 0603 Kemet
R1 1 Resistor, Chip, 100-kΩ, 1/16-W, 0.5%, 0402
R2, R3 2 Resistor, Chip, 499-kΩ, 1/16-W, 0.5%, 0402
R4 1 Resistor, Chip, 36-kΩ, 1/16-W, 0.5%, 0402
R9 1 Resistor, Chip, 5.23-kΩ, 1/16-W, 1%, 0402
R10 1 Resistor, Chip, 30.1-kΩ, 1/16-W, 1%, 0402
R7, R8 2 Resistor, Chip, 10-kΩ, 1/16-W, 5%, 0402
R6 1 Resistor, Chip, 10-Ω, 1/4-W, 5%, 1206
R5 1 Resistor, Chip, 2-Ω, 1-W, 5%, 2012
D1 1 Diode, Schottky Rectifier, 40-V, 10-A, PDS1040
Q3 1 N-Channel MOSFET, 60-V, 115-mA, SOT-23, 2N7002DICT

9.2.2.6 MPPT Temperature Compensation


A typical solar panel comprises of a lot of cells in a series connection, and each cell is a forward-biased p-n
junction. So, the open-circuit voltage (VOC) of a solar cell has a temperature coefficient that is similar to a
common p-n diode, or about –2 mV/°C. A crystalline solar panel specification always provides both open-circuit
voltage VOC and peak power point voltage VMP. The difference between VOC and VMP can be approximated as
fixed and temperature-independent, so the temperature coefficient for the peak power point is similar to that of
VOC. Normally, panel manufacturers specify the 25°C values for VOC and VMP, and the temperature coefficient for
VOC, as shown in Figure 17.

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VOC

Panel Voltage - V
VMP

5 15 25 35 45 55
TA - Free-Air Temperature - °C

Figure 17. Solar Panel Output Voltage Temperature Characteristics

The bq24650 employs a feedback network to the MPPSET pin to program the input regulation voltage. Because
the temperature characteristic for a typical solar panel VMP voltage is almost linear, a simple solution for tracking
this characteristic can be implemented by using an LM234 3-terminal current source, which can create an easily
programmable, linear temperature dependent current to compensate the negative temperature coefficient of the
solar panel output voltage.
R21: 20W

VIN

Solar R20 C21


Panel 2Ω 0.47mF
LM234
C21
VCC
2.2mF R3 I1

RSET ISET
VREG
MPPSET

R4 I2
bq24650

Copyright © 2016, Texas Instruments Incorporated

Figure 18. Feedback Network

In the circuit shown in Figure 18, for the LM234 temperature sensor,
227 μV/ °K
ISET = ´ Temp
RSET (24)
Thus,
0.0677V
ISET (25°C) =
RSET (25)
The current node equation is Equation 26:
V V - VREG
I2 = REG = I1 + ISET = IN + ISET
R4 R3 (26)
To have a zero temperature coefficient on VREG,

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dI2 d(VIN - VREG ) 1 dI


= × + SET = 0
dT dT R3 dT (27)
æ -dVIN /dT ö 2mV × number of solar cells in series
R3 = ç ÷ = RSET ×
dI
è SET /dT ø 227μV (28)
VREG × R3 VMPPSET × R3
R4 = =
(VIN + R3 × ISET ) - VREG æ 0.0677V ö
ç VMP (25°C) + R3 × ÷ - VMPPSET
è RSET ø (29)
For example, given a common 18-cell solar panel that has the following specified characteristics:
Open-circuit voltage (VOC) = 10.3 V
Maximum power voltage (VMP) = 9V
Open-circuit voltage temperature coefficient (VOC) = –38 mV/°C
Applying the following parameters into the equations of R3 and R4:
1. Temperature coefficient for VMP (same as that of VOC) of –38 mV/°C
2. Peak power voltage of 9 V
3. MPPSET regulation voltage of 1.2 V
And choosing RSET = 1000 Ω.
The resistor values are RSET = 1 kΩ, R3 = 167.4 kΩ, and R4=10.6 kΩ. Selecting standard 1% accuracy resistors
and RSET = 1 kΩ, R3 = 169 kΩ, and R4=10.7 kΩ.

9.2.3 Application Curves

VIN
MPPT Regulation Point 20V/div
VIN VBAT
5V/div 5V/div

PH
20V/div

IBAT
0.5A/div IL
1A/div

10 ms/div 1 s/div

Figure 19. MPPT Regulation During Soft Start Figure 20. Battery Insertion and Removal

VIN VIN
20V/div 20V/div

VBAT VBAT
5V/div 5V/div

PH PH
20V/div 20V/div

IL IL
1A/div 1A/div

400 ms/div 10 ms/div

Figure 21. Short Battery Response Figure 22. Charge Reset During Battery Short

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100

95
ICHG 2A

ICHG 1A

Efficiency - %
90

85

80
0 5 10 15 20
VO - Output Voltage - V

VCC = 25 V

Figure 23. Efficiency vs Output Voltage

10 Power Supply Recommendations


The bq24650 requires a voltage source between 5 V and 28 V connected to VCC. and VCC can be supplied
either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, bq24650 exits the
SLEEP mode. If the SRN voltage is greater than VCC, bq24650 enters a low-quiescent current (< 15 μA) SLEEP
mode to minimize current drain from the battery.

11 Layout

11.1 Layout Guidelines


The switching node rise and fall times must be minimized for minimum switching loss. Proper layout of the
components to minimize the high frequency current path loop (see Figure 24) is important to prevent electrical
and magnetic field radiation and high frequency resonant problems. The following is a PCB layout priority list for
proper layout. Layout of the PCB according to this specific order is essential.
1. Place input capacitor as close as possible to the switching MOSFET supply and ground connections and use
the shortest copper trace connection. These parts must be placed on the same layer of the PCB instead of
on different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET gate terminals, and the gate drive signal traces
kept short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of the switching
MOSFETs.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging current sensing resistor must be placed right next to the inductor output. Route the sense leads
connected across the sensing resistor back to the IC in the same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 25 for Kelvin connection for
best current accuracy). Place decoupling capacitor on these traces next to the IC.
5. Place output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route analog ground separately from power ground and use a single ground connection to tie charger power
ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins
to reduce inductive and capacitive noise coupling. Connect analog ground to the GND pin. Use the thermal
pad as a single ground connection point to connect analog ground and power ground together, or use a 0-Ω
resistor to tie analog ground to power ground (thermal pad should tie to analog ground in this case). A star-
connection under the thermal pad is highly recommended.
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Layout Guidelines (continued)


8. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
9. Decoupling capacitors must be placed next to the IC pins and make trace connection as short as possible.
10. The number and physical size of the vias must be enough for a given current path.
L1 R1 VBAT
SW

High
Frequency
VIN BAT
Current
C1 Path C2 C3
PGND

Copyright © 2016, Texas Instruments Incorporated

Figure 24. High Frequency Current Path

11.2 Layout Example


Charge Current Direction
R SNS

To Inductor To Battery

Current Sensing Direction

To SRP and SRN pin


Copyright © 2016, Texas Instruments Incorporated

Figure 25. Sensing Resistor PCB Layout

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12 Device and Documentation Support

12.1 Device Support


12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Community Resources


The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

30 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated

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PACKAGE OPTION ADDENDUM

www.ti.com 10-Feb-2016

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

BQ24650RVAR ACTIVE VQFN RVA 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PAS
& no Sb/Br)
BQ24650RVAT ACTIVE VQFN RVA 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PAS
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 10-Feb-2016

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 10-Feb-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24650RVAR VQFN RVA 16 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
BQ24650RVAT VQFN RVA 16 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 10-Feb-2016

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ24650RVAR VQFN RVA 16 3000 367.0 367.0 35.0
BQ24650RVAT VQFN RVA 16 250 210.0 185.0 35.0

Pack Materials-Page 2
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requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
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Interface interface.ti.com Medical www.ti.com/medical
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Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity

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