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bq24650
SLUSA75A – JULY 2010 – REVISED APRIL 2016
1 Features
• Maximum Power Point Tracking (MPPT) • Small 3.5 × 3.5 mm2 16-Pin QFN Package
Capability by Input Voltage Regulation
• Programmable MPPT Setting 2 Applications
• 5-V to 28-V Input Solar Panel • Solar-Powered Applications
• 600-kHz NMOS-NMOS Synchronous Buck • Remote Monitoring Stations
Controller • Portable Handheld Instruments
• Resistor Programmable Float Voltage • 12-V to 24-V Automotive Systems
• Accommodates Li-Ion/Polymer, LiFePO4, Lead • Current-Limited Power Source
Acid Chemistries
• Accuracy 3 Description
– ±0.5% Charge Voltage Regulation The bq24650 device is a highly integrated switch-
mode battery charge controller. It provides input
– ±3% Charge Current Regulation
voltage regulation, which reduces charge current
– ±0.6% Input Voltage Regulation when input voltage falls below a programmed level.
• High Integration When the input is powered by a solar panel, the input
– Internal Loop Compensation regulation loop lowers the charge current so that the
solar panel can provide maximum power output.
– Internal Digital Soft Start
• Safety The bq24650 offers a constant-frequency
synchronous PWM controller with high accuracy
– Input Overvoltage Protection current and voltage regulation, charge
– Battery Temperature-Sensing preconditioning, charge termination, and charge
– Battery Absent Detection status monitoring.
– Thermal Shutdown Device Information(1)
• Charge Status Outputs for LED or Host Processor PART NUMBER PACKAGE BODY SIZE (NOM)
• Charge Enable on MPPSET Pin bq24650 VQFN (16) 3.50 mm × 3.50 mm
• Automatic Sleep Mode for Low Power (1) For all available packages, see the orderable addendum at
Consumption the end of the data sheet.
– < 15-μA OFF-State Battery Discharge Current
Typical Application
Solar Cell
D1
Half Panel
VIN R6: 10Ω
R5
2Ω
C1
VCC C2
2.2µF
bq24650 1uF
VREF
C3 C4:1µF
R9 R3 1µF
5.23kΩ 499kΩ REGN
D2
MPPSET BTST C6
Pack Q1 10uF
Thermistor RSR
HIDRV C5
TS L: 10µH 20mΩ Battery Pack
R10 100nF
CE Q3 R4 PH
30.1kΩ 36kΩ TERM_EN
Q2 C9
LODRV C8 4.7µF
GND 10µF
C10
VIN D3 R2
SRP 22pF
R7:10kΩ STAT1 C7 499kΩ
0.1µF R1
R8:10k Ω STAT2 Thermal SRN
100kΩ
Pad VFB
D4
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24650
SLUSA75A – JULY 2010 – REVISED APRIL 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 11
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 20
3 Description ............................................................. 1 9 Application and Implementation ........................ 22
4 Revision History..................................................... 2 9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 28
7 Specifications......................................................... 4 11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
7.1 Absolute Maximum Ratings ...................................... 4
11.2 Layout Example .................................................... 29
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 30
7.4 Thermal Information .................................................. 5 12.1 Device Support...................................................... 30
7.5 Electrical Characteristics........................................... 5 12.2 Community Resources.......................................... 30
7.6 Typical Characteristics .............................................. 9 12.3 Trademarks ........................................................... 30
12.4 Electrostatic Discharge Caution ............................ 30
8 Detailed Description ............................................ 11
12.5 Glossary ................................................................ 30
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11 13 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Removed Ordering Information table .................................................................................................................................... 1
5 Description (continued)
The bq24650 charges the battery in three phases: pre-conditioning, constant current, and constant voltage.
Charge is terminated when the current reaches 1/10 of the fast charge rate. The pre-charge timer is fixed at 30
minutes. The bq24650 automatically restarts the charge cycle if the battery voltage falls below an internal
threshold and enters a low quiescent current sleep mode when the input voltage falls below the battery voltage.
The bq24650 supports a battery from 2.1 V to 26 V with VFB set to a 2.1-V feedback reference. The charge
current is programmed by selecting an appropriate sense resistor. The bq24650 is available in a 16 -pin, 3.5 mm
× 3.5 mm2 thin QFN package.
RVA Package
16-Pin VQFN
Top View
LODRV
HIDRV
BTST
PH
16
15
14
13
VCC 1 12 REGN
MPPSET 2 11 GND
ThermalPad
STAT1 3 10 SRP
TS 4 9 SRN
5
8
STAT2
VREF
TERM_EN
VFB
Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
IC power positive supply. Place a 1-μF ceramic capacitor from VCC to GND and place it as close as
1 VCC P
possible to IC. Place a 10-Ω resistor from input side to VCC pin to filter the noise.
Input voltage set point. Use a voltage divider from input source to GND to set voltage on MPPSET to 1.2
2 MPPSET I
V. To disable charge, pull MPPSET below 75 mV.
Open-drain charge status output to indicate various charger operation. Connect to the cathode of LED
3 STAT1 O with 10 kΩ to the pullup rail. LOW or LED light up indicates charge in progress. Otherwise stays HI or
LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off.
Temperature qualification voltage input. Connect to a negative temperature coefficient thermistor.
4 TS I Program the hot and cold temperature window with a resistor divider from VREF to TS to GND. A 103AT-
2 thermister is recommended.
Open-drain charge status output to indicate various charger operation. Connect to the cathode of LED
5 STAT2 O with 10 kΩ to the pullup rail. LOW or LED light up indicates charge is complete. Otherwise, stays HI or
LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off.
3.3-V reference voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC.
6 VREF P
This voltage could be used for programming voltage on TS and the pullup rail of STAT1 and STAT2.
Charge termination enable. Pull TERM_EN to GND to disable charge termination. Pull TERM_EN to
7 TERM_EN I
VREF to allow charge termination. TERM_EN must be terminated and cannot be left floating.
Charge voltage analog feedback adjustment. Connect the output of a resistor divider powered from the
8 VFB I
battery terminals to this node to adjust the output battery voltage regulation.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN MAX UNIT
VCC, STAT1, STAT2, SRP, SRN –0.3 33
PH –2 36
VFB –0.3 16
Voltage (with respect to GND) V
REGN, LODRV, TS, MPPSET, TERM_EN –0.3 7
BTST, HIDRV with respect to GND –0.3 39
VREF –0.3 3.6
Maximum difference voltage SRP–SRN –0.5 0.5 V
Junction temperature, TJ –40 155 °C
Storage temperature, Tstg –55 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
(3) Must have a series resistor between battery pack to VFB if battery pack voltage is expected to be greater than 16 V. Usually the resistor
divider top resistor takes care of this.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a
(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
MPPSET
VCC 1V/div
10V/div
LODRV
5V/div
VREF
2V/div PH
20V/div
REGN
5V/div
STAT1
20V/div IBAT
1A/div
MPPSET
MPPSET 1V/div
1V/div
LODRV LODRV
5V/div 5V/div
PH
20V/div
PH
20V/div
IBAT
IBAT 1A/div
1A/div
4 ms/div 10 ms/div
HIDRV
HIDRV 20V/div
20V/div
PH
PH 20V/div
20V/div
LODRV
LODRV
5V/div
5V/div
IL
1A/div IL
1A/div
Figure 5. Switching in Continuous Conduction Mode Figure 6. Switching in Discontinuous Conduction Mode
HIDRV
20V/div HIDRV
20V/div
PH PH
20V/div 20V/div
LODRV LODRV
5V/div 5V/div
IL IL
1A/div 1A/div
Figure 7. Switching at 100% Duty Cycle Figure 8. Recharge the BTST-PH Capacitor
8 Detailed Description
8.1 Overview
The bq24650 is a highly integrated solar input Li-ion or Li-polymer battery charge controller.
VREF bq24650
VOLTAGE
REFERENCE
VCC -
SLEEP
SRN+100 mV +
VCC -
SLEEP UVLO
VUVLO +
3.3V UVLO
VREF LDO VCC
VCC
175 mV -
+
FBO
MPPSET - COMP
1.2 V + ERROR BTST
AMPLIFIER
EAO CE
EAI - +
+ PWM
1V -
VFB + LEVEL HIDRV
SHIFTER
2.1 V -
BAT_OVP
20uA +
SRP-SRN
SRP SYNCH PH
-
+ PWM
+ 5 mV - VCC
V(SRP-SRN) + CONTROL
20X
- LOGIC
0.8V -
SRN BTST - REFRESH 6V LDO REGN
_+ +
20 uA PH
CE
4V
FAULT
LODRV
V(SRP-SRN) -
2 mA CHG_OCP
200% X IBAT_REG +
GND
8 mA
FAULT
30 Minute STAT 1
IC Tj + TSHUT
Precharge CHARGE
CHARGE
Timer 145°C -
DISCHARGE STAT1
TERM_EN VFB - BAT_OVP
STATE
104% X 2.1V +
MACHINE
0.8V IBAT_ REG LOGIC
STAT2
0.8V
10 STAT 2
LOWV BATTERY
DETECTION
VFB - LOWV LOGIC DISCHARGE VREF
+
1.5V +-
+ LTF -
VCC ACOV
- +
+
32V - TS
VFB - SUSPEND
RCHRG HTF +
+ -
2.05V +-
RCHRG TCO +
V(SRP - SRN) + -
TERM TERM
0.8V -
10 TERMINATE CHARGE
Charge
Current
Charge
Voltage
VLOWV
8.3.6 Power Up
The bq24650 uses a SLEEP comparator to determine the source of power on the VCC pin, because VCC can be
supplied either from a battery or an adapter. If the VCC voltage is greater than the SRN voltage, and all other
conditions are met for charging, the bq24650 then attempts to charge a battery (see Enable and Disable
Charging). If SRN voltage is greater than VCC, indicating that a battery is the power source, the bq24650 enters
low quiescent current (< 15 µA) SLEEP mode to minimize current drain from the battery.
If VCC is below the UVLO threshold, the device is disabled, and VREF LDO turns off.
VLTF VLTF
VLTFH VLTFH
VHTF
VTCO
CHARGE SUSPENDED CHARGE SUSPENDED
GND GND
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 15, the values of RT1 and RT2 can
be determined by using Equation 7 and Equation 8:
æ 1 1 ö
VVREF ´ RTHCOLD ´ RTHHOT ´ ç - ÷
è VLTF VTCO ø
RT2 =
æV ö æV ö
RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷
V
è TCO ø V
è LTF ø (7)
VREF
bq24650 RT1
TS
RT2 RTH
103AT
Table 1. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current
CHARGE CURRENT 0.5 A 1A 2A 4A 8A 10 A
Output inductor low 22 µH 15 µH 10 µH 6.8 µH 3.3 µH 3.3 µH
Output capacitor CO 7 µF 10 µF 15 µF 20 µF 40 µF 40 µF
Sense resistor 80 mΩ 40 mΩ 20 mΩ 10 mΩ 5 mΩ 4 mΩ
NOTE
OFF indicates that the open-drain transistor is turned off.
1s timer
VFB < VLOWV No No
expired
Yes Yes
0.5s timer
VFB > VRECH No No
expired
Yes
Yes
Battery Present,
Disable 125mA Begin Charge
Charge
Battery Absent
When the device has powered up, a 6-mA discharge current is applied to the SRN terminal. If the battery voltage
falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is turned on
at low charge current (125 mA). If the battery voltage gets up above the recharge threshold within 500 ms, there
is no battery present and the cycle restarts. If either the 500 ms or 1 second timer time out before the respective
thresholds are hit, a battery is detected and a charge cycle is initiated.
VREG
VRECH
(VWAKE)
Battery
inserted
VLOWV
(VDISCH) Battery detected
tWAKE
tLOWV_DEG tRECH_DEG
Take care that the total output capacitance at the battery node is not so large that the discharge current source
cannot pull the VFB voltage below the LOWV threshold during the 1 second discharge time. The maximum output
capacitance can be calculated according to Equation 9:
I ´ tDISCH
CMAX = DISCH
é R ù
0.5 ´ ê1+ 2 ú
ë R1 û
where
• CMAX is the maximum output capacitance,
• IDISCH is the discharge current,
• tDISCH is the discharge time,
• and R2 and R1 are the voltage feedback resistors from the battery to the VFB pin. (9)
The 0.5 factor is the difference between the RECHARGE and the LOWV thresholds at the VFB pin.
8.3.21.1 Example
For a 3-cell Li+ charger, with R2 = 500 kΩ, R1 = 100 kΩ (giving 12.6 V for voltage regulation), IDISCH = 6 mA,
tDISCH = 1 second.
6 mA ´ 1 sec
CMAX = = 2000 μF
é 500 kW ù
0.5 ´ ê1+ ú
ë 100 kW û (10)
Based on these calculations, no more than 2000 µF must be allowed on the battery node for proper operation of
the battery detection circuit.
POR
SLEEP MODE
Yes
Yes
See Enabling and Disabling
Charge Section
Indicate NOT
Conditions met Conditions met
No CHARGING, No No
for charge? for charge?
Suspend timers
Yes Yes
Regulate
precharge current
Start 30 minute Precharge
VFB < VLOWV Yes VFB < VLOWV Yes
precharge timer Indicate Charge- timer expired?
In-Progress
Start Fastcharge
No No
timer
Regulate
fastcharge current Yes
Indicate NOT
Conditions met
CHARGING, No Yes
for charge? Indicate Charge-
Suspend timers
In-Progress
No
No
Charge Complete
VFB > VRECH Yes
VFB < VRECH No
Indicate DONE
Battery Removed
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
VREF
C3 C4:1µF
R9 R3 1µF
5.23kΩ 499kΩ REGN
D2
MPPSET BTST C6
Pack Q1 10uF
Thermistor RSR
HIDRV C5
TS L: 10µH 20mΩ Battery Pack
R10 100nF
CE Q3 R4 PH
30.1kΩ 36kΩ TERM_EN
Q2 C9
LODRV C8 4.7µF
GND 10µF
C10
VIN D3 R2
SRP 22pF
R7:10kΩ STAT1 C7 499kΩ
0.1µF R1
R8:10k Ω STAT2 Thermal SRN
100kΩ
Pad VFB
D4
where
• QSW is the switching charge,
• Ion is the turnon gate driving current,
• and Ioff is the turnoff gate driving current. (19)
If the switching charge is not given in the MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD)
and gate-to-source charge (QGS):
1
QSW = QGD + ´ QGS
2 (20)
The gate driving current total can be estimated by the REGN voltage (VREGN), MOSFET plateau voltage (VPLT),
total turnon gate resistance (Ron), and turnoff gate resistance (Roff) of the gate driver:
VREGN - Vplt Vplt
Ion = ; Ioff =
Ron Roff (21)
The conduction loss of the bottom-side MOSFET is calculated in Equation 22 when it operates in synchronous
continuous conduction mode:
Pbottom = (1 - D) ´ ICHG2 ´ RDS(ON)
(22)
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result, all of the freewheeling current goes through the body diode of the bottom-side MOSFET. The
maximum charging current in non-synchronous mode can be up to 0.9 A (0.5 A typical) for a 10-mΩ charging
current sensing resistor, considering the IC tolerance. Choose a bottom-side MOSFET with either an internal
Schottky or body diode capable of carrying the maximum non-synchronous mode charging current.
MOSFET gate driver power loss contributes to dominant losses on the controller IC, when the buck converter is
switching. Choosing a MOSFET with a small Qg_total reduces power loss to avoid thermal shutdown.
PICLOSS_Driver = VIN ´ Qg_total ´ fs
where
• Qg_total is the total gate charge for both the upper and lower MOSFETs at 6V VREGN. (23)
VOC
Panel Voltage - V
VMP
5 15 25 35 45 55
TA - Free-Air Temperature - °C
The bq24650 employs a feedback network to the MPPSET pin to program the input regulation voltage. Because
the temperature characteristic for a typical solar panel VMP voltage is almost linear, a simple solution for tracking
this characteristic can be implemented by using an LM234 3-terminal current source, which can create an easily
programmable, linear temperature dependent current to compensate the negative temperature coefficient of the
solar panel output voltage.
R21: 20W
VIN
RSET ISET
VREG
MPPSET
R4 I2
bq24650
In the circuit shown in Figure 18, for the LM234 temperature sensor,
227 μV/ °K
ISET = ´ Temp
RSET (24)
Thus,
0.0677V
ISET (25°C) =
RSET (25)
The current node equation is Equation 26:
V V - VREG
I2 = REG = I1 + ISET = IN + ISET
R4 R3 (26)
To have a zero temperature coefficient on VREG,
VIN
MPPT Regulation Point 20V/div
VIN VBAT
5V/div 5V/div
PH
20V/div
IBAT
0.5A/div IL
1A/div
10 ms/div 1 s/div
Figure 19. MPPT Regulation During Soft Start Figure 20. Battery Insertion and Removal
VIN VIN
20V/div 20V/div
VBAT VBAT
5V/div 5V/div
PH PH
20V/div 20V/div
IL IL
1A/div 1A/div
Figure 21. Short Battery Response Figure 22. Charge Reset During Battery Short
100
95
ICHG 2A
ICHG 1A
Efficiency - %
90
85
80
0 5 10 15 20
VO - Output Voltage - V
VCC = 25 V
11 Layout
High
Frequency
VIN BAT
Current
C1 Path C2 C3
PGND
To Inductor To Battery
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Feb-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
BQ24650RVAR ACTIVE VQFN RVA 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PAS
& no Sb/Br)
BQ24650RVAT ACTIVE VQFN RVA 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PAS
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Feb-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Feb-2016
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Feb-2016
Pack Materials-Page 2
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