74 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO.

1, JANUARY 2018

Time-to-Digital Converter With Sample-and-Hold

and Quantization Noise Scrambling Using
Harmonics in Ring Oscillators
Juan Pablo Caram, Member, IEEE, Jeff Galloway, Member, IEEE, and J. Stevenson Kenney, Fellow, IEEE

Abstract— A high-resolution, high-bandwidth, and noise-
scrambling, time-to-digital converter (TDC) is presented. Its
architecture, which exploits harmonics in ring oscillators, pro-
vides a sample-and-hold mechanism in the form of relative phase.
This storage mechanism is highly insensitive to noise and allows
for oversampling between input events, therefore, can be designed
for very high bandwidth. It can achieve lower quantization noise
with fewer measurements than noise-shaping TDCs. This paper
presents the architecture in detail, an in-depth analysis of noise
sensitivity of the time storage mechanism, and the results from
a prototype implemented in a 28-nm CMOS process.
Index Terms— Time-to-digital converter, digital phase-locked
loop, sample-and-hold, oversampling, ring oscillator, harmonics.
I. I NTRODUCTION
T IME-to-Digital Converters (TDCs) have had an increas-
ingly important role as CMOS technology continues to
scale down in feature size. This trend has resulted in the
degradation of analog performance and also in an increase
in speed and in time-domain resolution. This combination has
presented new design challenges and opportunities.
TDCs have found applications in multiple fields, but histori-
cally, particle physics has been the field that has most strongly
driven the research on accurate electronic time-interval mea-
surements. In principle, the use of time (and distance) to
determine the speed of a particle under the influence of a
magnetic field, plays an fundamental role in characterizing
and identifying the kind of particle being studied [2].
The focus on TDCs has recently shifted with the increased
interest in implementing most sub-circuits of a frequency syn-
thesizer in digital form. In phase-locked loops (PLLs) a digital
loop filter provides ease of reconfigurability, excellent out-of-
band rejection, lower silicon area, adaptive spur cancellation,
and noise immunity. PLLs that use a digital loop filter are
commonly refered to as digital PLLs (DPLLs), even though
they require some form of analog-to-digital conversion at the
Manuscript received January 24, 2017; revised April 11, 2017 and
May 24, 2017; accepted May 29, 2017. Date of publication June 20, 2017;
date of current version January 5, 2018. This paper was recommended by
Associate Editor A. Nagari. (Corresponding author: Juan Pablo Caram.)
J. P. Caram is with the Department of Electrical and Computer Engineering,
Georgia Institute of Technology, Atlanta, GA 30332 USA, and also with Sili-
con Creations LLC, Suwanee, GA 30024 USA (e-mail: jpcaram@gatech.edu).
J. Galloway is with Silicon Creations LLC, Suwanee, GA 30024 USA.
J. S. Kenney is with the Department of Electrical and Computer Engineer-
ing, Georgia Institute of Technology, Atlanta, GA 30332 USA.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2017.2712518
1549-8328 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
phase detector and digital-to-analog conversion at the oscilla-
tor. Both of these converters present several complexities and
great challenges in DPLL design.
The most important performance metrics in a PLL are
typically phase noise, or jitter, and power consumption. If a
TDC is used as a phase detector in a DPLL, its impact on these
parameters is the primary concern. The TDC will impact phase
noise in several ways. It will introduce quantization noise,
establishing an in-band phase noise floor given by
 2
(2πσtdc f vco )2 rad
PN = (1)
f ref Hz
where f vco and f ref are the frequencies of the VCO and the
reference respectively, and σtdc is the RMS quantization error
in the TDC.
It can also limit the bandwidth, which reduces the PLL’s
ability to suppress the VCO noise. Nonlinearity, also, can
create mixing products that result in spurs at low frequency
offsets, which are not attenuated by the loop filter.
TDC techniques have suffered from low resolution, low
linearity, high power consumption, device and power supply
sensitivity, and low bandwidth. Recent developments using
ring oscillators have allowed for 1st [8], [9], 2nd [10], and even
3rd order [12] noise shaping. Quantization noise shaping shifts
the quantization noise to higher frequencies, thus allowing
for improvement by low-pass filtering. This enables a tradeoff
between bandwidth and precision.
The proposed TDC architecture stores the input time quan-
tity in a ring oscillator carrying multiple edges, or phases, and
encodes the input quantity as the angle between these phases.
Noise that affects the frequency of the ring is “common-mode”
and is therefore rejected. Furthermore, this storage or sample-
and-hold mechanism allows for oversampling of the stored
quantity between input events, circumventing the bandwidth
penalty paid by Sigma-Delta () noise-shaping TDCs.
In Section II we study relevant TDC techniques, highlight-
ing how they achieve their performance and the tradeoffs they
incur, leading to the proposed TDC described in Section III.
Section IV provides an in-depth analysis of noise in the
HRO. The implementation of our prototype is described in
Section V. Section VI describes the measurement techniques
used to characterize the HRO TDC and measurement results.
The conclusion in Section VII summarizes the properties
of the HRO TDC and how it improves upon the current
state-of-the-art.
CARAM et al.: TDC WITH SAMPLE-AND-HOLD AND QUANTIZATION NOISE SCRAMBLING USING HROs
Fig. 1. Delay-Line-based TDCs. (a) Flash TDC, (b) Vernier TDC.
II. OVERVIEW OF TDC T ECHNIQUES
A time interval can be described by two events respectively
defining the start and the stop times of the interval. Alter-
natively, it can be described by a single event happening at
time te with duration Te . The TDC’s function is to measure Te .
Contrary to other data converters, it has no control over
when (te ) and how often the sampling occurs ( f e ). This is
instead determined by the input signal.
The most straightforward approach to digitally quantifying
a time interval is by counting clock cycles between the events
that define it. The resolution of such measurement is the period
of the clock, Tclk . Under the right circumstances (asynchronous
event frequency, event duration, and clock frequency), such
TDC can be very linear, and the quantization error becomes
scrambled across measurements (white and uniformly distrib-
uted between −Tclk /2 and Tclk /2). The resolution is limited by
the technology, which is only predicted to continue to improve,
but a counter running at extremely large frequencies will
consume significant power, making this approach unattractive
for high resolution applications. Nonetheless, it is still found
in hybrid techniques, where the high resolution is achieved by
other means and a counter is used to increase the dynamic
range [2], [11].
For small time intervals and higher resolution, the Flash
(or Delay-Line) TDC was introduced. Its operation and design
are relatively simple. This is probably why this topology
was quickly adopted in the first DPLL used in a commercial
product for wireless communications [3].
The Flash TDC, shown in Fig. 1(a), consists of a delay-line
of logic gates (typically inverters) into which the start signal
is injected, and the stop signal is used as the clock to the flip-
flops sampling every node in the line. The delay of each gate,
τgate , provides a mapping between the interval’s duration and
distance of propagation in number of gates.
This technique largely improves resolution which promises
to only get better with the continuous scaling of CMOS
devices, but introduces a new set of challenges. The delay
of an inverter (or any logic gate) is a very unreliable quan-
tity [25], not only over PVT, but also across neighboring
devices (matching) in the same die [6]. This results in large
nonlinearity. Flash TDCs also require a very large number of
75
gates in the delay line to support large time intervals. It is also
important to note that this architecture cannot resolve negative
time intervals, this is, when the start signal arrives after the
stop signal.
The Vernier Delay-Line TDC, shown in Fig. 1(b), improves
further on resolution. It uses instead two delay lines, with
different nominal gate delays, τfast and τslow , one for each
of the input signals. The start signal is launched into the
slower line and the stop signal into the faster one. Eventually,
both signals will have traveled through the same number of
inverters, N, i.e. the stop signal will “catch up” with the start
signal, where
Nτfast + Tin = Nτslow ⇒ Tin = N(τslow − τfast ) (2)
Since N is captured in the flip-flops, the input interval
Tin = tstop − tstart can be computed with a resolution of
τ = τslow − τfast . This improvement in resolution does not
help with the inherent linearity problem in delay-line based
TDCs. Furthermore, this technique exacerbates the problem
of requiring a large number of gates, proportionally with
the increase in resolution. The Vernier technique can also be
implemented using two counters driven by clocks with slightly
different frequencies [7] and actually precedes the Vernier
delay-line TDC.
An intuitive approach to improving the resolution of any
data converter is to amplify the input signal before quan-
tization. This has led to the concept of time amplification.
Attempts to design an analog “Time Amplifier” have been
reported in the literature [13], but since they rely heavily on
analog performance, they are of little practical use in modern
CMOS.
Major improvement in performance was achieved when
noise shaping was first adopted into TDC architectures. This
technique has long been used in voltage-domain data con-
verters.  modulation is the most common mechanism to
achieve quantization noise shaping. In its most simple form it
consists in integrating the sampled input X (z) and subtracting
the quantized output Y (z) from the next input. This results in
a differentiation of the quantization error, Q(z), shifting it to
higher frequency:
Y (z) = X (z)z −1 + Q(z)(1 − z −1 ) (3)
The integrator is most commonly implemented using a
capacitor to integrate from current to voltage. The frequency-
to-phase integration nature of oscillators has also been
exploited for such application. This is how ring oscillators
become essential in noise shaping TDCs.
The Gated Ring Oscillator (GRO) TDC [8], shown in
Fig. 2(a), operates by switching (gating) a ring oscillator on
and off, specifically by disconnecting the inverters from their
supply rails. The on and off states respond to the logic state
of a periodic input signal, therefore, the total phase change
during one period is directly proportional to its duty cycle.
The GRO achieves first-order noise shaping because the
quantization error propagates from one cycle to the next as
partial charge in the parasitic gate capacitance when the ring
is gated. If the charge at a given node is not high enough to be
registered as a logic high when the ring stops, the next cycle
76 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 1, JANUARY 2018
Fig. 2. Ring-oscillator-based noise-shaping TDCs. (a) Gated Ring Oscilla-
tor (GRO) TDC, (b) Switched Ring Oscillator (SRO) TDC.
starts with this partial charge and is taken into account in the
total phase in the next cycle.
This TDC is particularly affected by leakage, another dif-
ficulty that continues to exacerbate with CMOS scaling.1
When the ring is stopped, the parasitic capacitance holding the
quantization error loses charge. This introduces an additional
source of error, resulting in a performance below that of first-
order noise shaping.
The Switched Ring Oscillator (SRO) TDC [9], shown
in Fig. 2(b), significantly mitigates the leakage problem of the
GRO with a slight modification. Instead of switching between
f ring and f = 0, it never fully stops the ring and switches
between f fast and f slow .
In both the GRO and SRO TDCs, even though the imple-
mentations between [8] and [9] vary, the phase change per
switching or gating cycle is computed and is proportional
to the input time-interval. The intrinsic resolution of the
quantized phase is the delay of the ring elements, but low pass
filtering eliminates most of the quantization noise which has
been shifted to higher frequencies. It’s important to note that
both architectures require a time-difference generator (TDG)
to provide a single line that controls the gating or switching.
This block generates a control signal with a variable duty
cycle depending on the relative arrival times of the rising
and falling edges at the inputs. These TDCs therefore, as
presented in [8] and [9], require periodic input signals with
known duty cycles. Alternative configurations such as in [11]
are not subject to this limitation.
The TDC that we propose in the following section is an
attempt to improve upon some of these limitations.
III. H ARMONIC R ING O SCILLATOR TDC
A. Harmonics in Ring Oscillators
The fundamental frequency of a ring oscillator is
f ring = (2Nτgate )−1 . By setting specific initial conditions,
1 Except for some improvement with the introduction of FinFET devices.
Fig. 3. Ring oscillator operating in its second harmonic.
it can be set to oscillate in a harmonic mode, where the
frequency is an integer multiple of f ring .
Consider the ideal circuit in Fig. 3 consisting of six invert-
ers, two of which can be held in a reset state, forcing their
outputs to logic high. When reset is released, the ring is
placed in an unstable state causing logic transitions (edges)
to propagate. This ring oscillator is operating in its second
harmonic.
Harmonics in ring oscillators have been seldom studied, and
usually with the intention of avoiding them [14]–[17]. The
only two exceptions that we were able to find reported the
use of second-harmonic ring oscillators for a carrier-and-data-
recovery (CDR) circuit [18], and for a physically unclonable
function (PUF) for chip authentication [19].
B. Principle of Operation
The HRO TDC exploits the possibility of releasing the reset
condition of the inverters in Fig. 3 at different times. This
changes the relative phase of the two edges propagating in
the ring. The relationship between the arrival times of both
signals, A and B, their absolute and relative phases in the ring,
and the ring’s fundamental frequency are illustrated in Fig. 4.
As phase is the integral of frequency, and both edges propagate
in the same ring with a given f ring , their relative phase should
ideally remain constant. This circuit behaves as a differential
sample-and-hold in the phase domain.
Unfortunately, in a real ring oscillator with an even number
of stages, the two edges propagate at two different frequencies.
Note in Fig. 3 that, at any given node, if one of the edges is
a rising edge, then it will always be a rising edge when going
through that same node again. The other edge will always be
a falling edge when passing through that node. We can write
the period of both edges around the ring as

N/2−1
Tedge1 = τ f [2i ] + τr [2i + 1], (4)
i=0

N/2−1
Tedge2 = τ f [2i + 1] + τr [2i ], (5)
i=0
where τr [i ] and τ f [i ] are the propagation delays of each gate
when its output at node i is respectively a rising or a falling
edge. The rise and fall times of a gate can be designed to
match, but in practice, they will never be equal. Therefore,
in terms of frequency of oscillation, it is as if the edges were
propagating on different rings. The angle between both edges
CARAM et al.: TDC WITH SAMPLE-AND-HOLD AND QUANTIZATION NOISE SCRAMBLING USING HROs
Fig. 4. Sample-and-hold in the phase domain.
Fig. 5. Basic concepts of the HRO TDC.
quickly grows or shrinks. Eventually, the two edges collapse
and oscillation ceases. This places severe limitations for the
implementation of the proposed TDC using an even-stage ring
oscillator.
In an odd-stage ring carrying any number of edges, if an
edge is a rising edge at a given stage at a given time, then the
next time around (after propagating through an odd number
of stages) it will become a falling edge. Therefore, each edge
is affected by both the rise and fall times of every gate in the
ring and their periods (average after two cycles) are equal and
given by
1
N−1
Todd = τr [i ] + τ f [i ] (6)
2
i=0
Since an odd-stage ring overcomes the aforemetioned prob-
lem in even-stage rings, it provides a better platform for the
analog storage mechanism of the TDC.
Only two edges are required to encode the time information,
while at least three are required in an odd-stage ring. The third
can aid in identifying which edge, in any given sample of the
ring, came from which input signal. As illustrated in Fig. 5,
A is injected into the ring at two locations simultaneously,
close to each other, k gates apart. Signal B is injected at
the maximum possible distance from the two A inputs. Then,
it will be known at any time, that the two edges that are
closer together belong to signal A, while the third belongs to
signal B. This is true as long the B edge maintains a distance
greater than k gates from any of the two A edges. At any
time, if the A edges are at gates i and i + k, then the B edge
may not occupy any gates between i − k and i + 2k, totaling
77
Fig. 6. Model of the HRO TDC for noise analysis.
3k+1 gates. This determines the maximum measurement range
of (N − 3k − 1) × τgate .
Fig. 5 shows a conceptual third-harmonic HRO. The delay
elements are drawn intentionally with unequal sizes in the
disc to represent the unequal propagation times. It shows
the ring in three different states: (a) Neither A nor B have
arrived, (b) A has arrived and the two corresponding edges
start to propagate, and (c) B has arrived and now the angle
φtdc = φ0 − φin stores the desired quantity.
The objective at this point is to recover φtdc with a resolution
better than the average gate delay τgate and scramble the
nonlinearity that would result from the variation of individual
gate delays. As long as the ring oscillation and the ring
sampling remain asynchronous (which is highly likely unless
the free-running ring becomes injection-locked to the sampling
clock), every time the ring is sampled, each edge will be
located at a different delay stage. This means each sample
is subject to the mismatch of a different set of delay elements.
The nonlinearity introduced by the mismatch is then spread
or scrambled throughout multiple samples, resembling a zero-
mean noise-like signal. This is known as Dynamic Element
Matching (DEM). By averaging the samples, the effective gate
delay approaches the average gate delay and the uncertainty
in the measurement due to nonlinearity decays towards zero.
Furthermore, the position of each phase relative to the quanti-
zation thresholds at the time of sampling will be different for
each sample, thus the quantization noise becomes scrambled
as well.
IV. N OISE A NALYSIS
The diagram in Fig. 6 illustrates the signal flow for dif-
ferent types of noise and their sources. It also represents the
common-mode and differential effects by separating the signal
path of the two phases/edges that jointly store the time sample.
The sources can be grouped into quantization, and device and
circuit noise.
A. Quantization Noise
The input to a general uniform quantizer, normalized to its
resolution τ , can be written in the form tin = n + v, where
n and v ∈ [0, 1) are respectively the integer and fractional
parts of tin . If the quantized output is Q{tin } = n, then the
quantization error is v. If this error is properly randomized
such that v ∼ U (0, 1) [4], [5], the RMS error is then
78 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 1, JANUARY 2018

√
στ = 1/ 12. Moreover, the error in a measurement consisting
of the average of m samples is then
√
σm = στ / m. (7)
In an HRO TDC, tin stored in the ring is a constant during all
m samples, therefore v is not randomized. However, the quan-
tization errors are inherently scrambled throughout samples as
a “random” dither is introduced by the accumulation of phase.
As long as the ring’s frequency and the sampling frequency
remain asynchronous, this random dither can be considered
∼ U (0, 1), and (7) still holds.
In the absence of delay mismatch, the quantized samples
are a random variable given by
 Fig. 7. Quantization noise versus oversampling ratio of  noise-shaping
n, pn = 1 − v TDCs of different orders, L = 0, 1 and 2, and of the HRO TDC when
Q{tin } = (8) averaging m = 8 and m = 32 ring-samples per measurement.
n + 1, pn+1 = v
where pk is the probability of obtaining the value k.
The RMS quantization√ noise is, therefore, a function of v
and given by σ√τ = v(1 − v). On average throughout v,
στ = π/8 ≈ 1/ 6. Delay mismatch in the inverters introduce
further scrambling on στ , reducing its dependence on v.
Yet another source of scrambling can come from phase noise
in the sampling clock. Additional or intentional phase noise in
the clock may also lower the chances for the ring to become
injection locked. Contrary to most other TDC architectures,
the time computation is not referenced to the circuit’s clock.
The quantization noise is not only scrambled across ring
samples but throughout measurements as well as long as
the input signals are not synchronous to the sampling clock.
This occurs because the ring samples from one measurement
happen at different locations (phases) in the ring from those
in other measurements.
The HRO TDC is a special case of  noise-shaping
converter, carrying out zeroth-order (L = 0) noise shaping.
In this case the quantization noise is not shifted to higher fre-
quencies, but simply spread out across the entire measurement
bandwidth.
The in-band quantization noise power in  converters is Fig. 8. Impact of noise in the sample-and-hold process. (a) Fully correlated
given by [28] noise and (b) Uncorrelated noise.

π 2L σq2
σtdc
2
= (9)
(2L + 1)(OSR)2L+1
where L is the modulation order, σq is the RMS quantization
noise, and OSR is the oversampling ratio. The OSR is the
sampling frequency in multiples of the Nyquist frequency
for the given input signal. Conversely, it is the fraction of
the sampling frequency to which the converter’s bandwidth is
limited.
It is evident from (9) that any converter with L = 1 or
higher outperforms an L = 0 converter as OSR√increases,
except that the HRO TDC has σq = σm = στ / m, while
converters without sample-and-hold have σq = στ . This is
show in Fig. 7.
The overall impact of this property is that, for the same
raw resolution or unit delay, τ = τgate , and event rate, fe ,
the precision of the measurements taken with the HRO TDC
depends on the value of m which depends on the available time
between events, 1/ f e , and on the frequency of the sampling
clock, f s , which can be designed for. Other converters, for a
given precision, have to wait for a minimum number of input
events, which, more often than not, happen at a frequency
outside the control of the designer.
B. Device and Circuit Noise
Figs. 8(a) and 8(b) are modified versions of Fig. 4 with
additional information to aid in the understanding of noise
in the HRO TDC. In both, the dotted lines represent the
phase trajectory the stored edges would follow for an input
time interval Tin if there was no noise. In (a), a noise
source e f (t) affecting the overall f ring (t) = f ring + e f (t) is
introduced which deflects the ideal phase curves. At time t B
we can see that φin already contains an error, and remains
unaltered thereafter. A noise source with these characteristics
CARAM et al.: TDC WITH SAMPLE-AND-HOLD AND QUANTIZATION NOISE SCRAMBLING USING HROs 79

can introduce a permanent error during the sampling period

but does not affect the stored quantity φin after time t B .
In Fig. 8(b) a noise source only affecting the phase of the
edge originating from signal B has been added. It represents
fully uncorrelated noise. Such noise, as opposed to that in 8(a),
can affect the stored value of φin after time t B and the initial
value of φin .
To quantitatively understand the effect of noise, we need
to isolate the nature, source, and sensitivity to the different
types of noise. It is well understood that the two main
sources of noise in CMOS device are thermal and flicker Fig. 9. RMS jitter in a ring oscillator from uncorrelated and correlated
sources as function of observation time.
(1/ f ) noise. Thermal noise is white, while flicker noise has a
1/ f profile, which, below some frequency f 1/ f (also know as
the 1/ f corner), dominates over thermal noise. In oscillators,
these voltage and current domain noise sources translate into
the phase domain and accumulate indefinitely, resulting in an
upconversion around the frequency of oscillation. The phase
noise spectral density has a profile of 1/ f 3 and 1/ f 2 for
the upconverted flicker and thermal noises [20] respectively,
resulting in very high phase noise at low frequency offsets
around the carrier.
A time-domain parallel is illustrated in Fig. 9, describ- Fig. 10. Simulation setup to compute the ISF of a ring oscillator at the
ing how noise accumulates in a ring oscillator [21], [23]. supply voltage.
Two slope segments, with slopes of 0.5 and 1, for uncorrelated
and fully correlated noise sources respectively, are identified.
The transition time tc is tightly related to f 1/ f [24]. The designer can use (7) and (13) to estimate the maximum
1) Thermal Noise: Noise originating at different inverters in practical number of ring-samples per measurement taken at
a ring oscillator is uncorrelated. In addition, the autocorrelation a given sampling rate by observing when the accumulated
of thermal (white) noise is zero at any time offset other than thermal noise overcomes the quantization noise.
zero. Therefore, the effect of thermal noise from the inverters 2) Flicker Noise: There is no clear concensus about how
on different edges propagating in the ring is fully uncorrelated. Flicker noise should be modeled. We know, though, that most
It corresponds to sources e A and e B in Fig. 6 and is represented of its power concentrates at low frequencies and becomes
in Fig. 8(b). apparent, i.e. dominates over thermal noise, below f 1/ f .
An approximation of the timing uncertainty of a single Flicker noise is still uncorrelated between inverters, but since
inverter during its transition due to thermal noise is given flicker noise is “colored”, its autocorrelation R(t) has non-
by [25]: zero values away from zero time offset, t = 0 [26]. The
4kT γ τgate kT Cgate consequence is that on the same inverter, flicker noise will
στ2gate = + (10)
I N (Vdd − Vt N ) I N2 affect the phase similarly, in direction and magnitude, for
small values of t. This will occur in a general oscillator
The two terms in the expression above are for the the respec-
when the period is very small, i.e. the ring has few delay
tive contributions of the NMOS and PMOS transistors in the
elements. For the HRO specifically, the effect on the phase of
logic high to low transition of the single-ended CMOS inverter.
two propagating edges has a higher correlation when the two
I N is the saturation current of the NMOS and Vt N is its
edges have a small phase offset, this is, when both edges cross
threshold voltage.
the same inverter in a very short time. If the ring has many
A quick calculation with typical values for nanometer
delay stages, and the two edges storing the time quantity are far
CMOS (μCox = 50 × 10−6 A/V2 [29], V D D = 1.0 V,
apart, then the impact of flicker noise becomes less correlated.
Vt N = 0.2 V, W/L = 10, γ = 1, Cgate = 15 fF) yields:
We can conclude that flicker noise is partially correlated and
Cgate VDD will affect φtdc depending on its value and the size of the ring.
τgate = ≈ 47 ps (11) 3) Power Supply Noise: For noise originating at the power
2IN
στgate ≈ 93 f s (12) supply of the ring, we can hypothesize that phase noise will be
fully correlated throughout all the inverters, therefore affecting
Since the power of the sum of uncorrelated signals is the just the frequency of the ring and not the relative angle
sum of their powers, the timing uncertainty of a signal, after of multiple edges. We can show this is only partially true
propagating through N gates, is then using simulation and an impulse-sensitivity-function (ISF) [22]
√ approach.
σ N = N στgate (13)
To construct the ISF, (φ), of a ring oscillator at the power
This corresponds to the section of the curve with 0.5 slope supply we use the setup in Fig. 10. We then inject a narrow
in Fig. 9. current pulse into Cring at uniform time offsets covering one
80 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 1, JANUARY 2018

Fig. 11. Simulation results from the setup in Fig. 10: Phase error as function
of the angle at which the charge was injected (top) and voltage at each node
in the ring (bottom).

oscillation period. For each offset, we measure the phase

deviation (from nominal) several periods later. The top graph
in Fig. 11 shows the observed time deviation for a current
pulse injected at the specified time. This is the ISF.2 The
exact values used in this simplified simulation setup are not
important and in practical designs will vary. What is most
relevant here is that the ISF has a large DC component plus
a small variation across one period: (φ) = DC + γ (φ).
In a ring carrying edges A and B, each have their
own ISF. They are offset versions of one another, i.e.
B (φ) = A (φ +φtdc). With this information we can construct
a differential ISF for φtdc (the stored angle):
φtdc (φ) = B (φ) − A (φ)
= γ B (φ) − γ A (φ)
Since DC vanishes in φtdc we can define a noise common-
mode rejection ratio (CMRR) or power supply rejection
ratio (PSRR) for φtdc as
γRMS
PSRRφtdc = (15)
DC
Most of the noise originating at the supply is fully correlated
and common-mode, quantified by DC , and represented by e f
in Fig. 6. Still, some is uncorrelated between edges and is also
dependent on φtdc . It is quantified by γ (φ) and represented
by eA and eB in Fig. 6.
V. I MPLEMENTATION
The HRO TDC concept is general enough that it can be
implemented in several different forms and optimized for
different conditions of operation.
The implementation chosen in this work was intended to
resemble the theory accurately and to be as straight forward
as possible. For this reason, we chose to implement the HRO
TDC using only standard-cell logic gates.
A simplified schematic, first presented in [1], is shown in
Fig. 12. The inverting stages have been chosen to be NAND
gates such that we could accommodate external inputs on three
of them. The rest have their second input tied to logic high,
2 The ISF, as defined in [22], is dimensionless.
Fig. 12. Schematics of the prototype HRO TDC.
(14)
Fig. 13. Chip photograph, layout and dimensions.
thus operating as inverters. This maintains the uniformity
across gates in terms of propagation delay.
Each node is sampled by D-type flip-flops (FF), and the
samples of contiguous nodes are compared with XNOR gates.
At the stages where transitions have not fully completed, the
values at the input and the output of those stages are registered
as the same, therefore yielding a logic high at the XNOR’s
output. A logic low is observed everywhere else.
After sampling, the objective is to determine the number of
stages between the edges corresponding to inputs A and B.
This is the quantized version of φtdc . Even though there are
many ways to implement this logic function, our implemen-
tation focused on maximizing the ring-sampling frequency.
This requires the logic complexity per clock cycle to be
minimized. The decoder had a pipeline structure where a com-
plex computation is broken down into simpler computations
throughout multiple clock cycles. This, although resulting in
higher latency, allows sampling on every clock cycle.
Fig. 13 shows a photograph of the prototype chip and the
layout of the ring oscillator. The signal input stages, 0, 5, and
34, have been labeled. These same stages can be identified in
the schematics in Fig. 12. Special attention was given to the
layout of the clock signals to ensure equal propagation delay
CARAM et al.: TDC WITH SAMPLE-AND-HOLD AND QUANTIZATION NOISE SCRAMBLING USING HROs
Fig. 14. Test setup: Accurate phase shifting using a  feedback divider
fractional-N PLL.
from the clock buffer (right edge in the layout) to all FFs. The
decoder is not shown in the figure since it was automatically
synthesized, placed and routed along with other logic unrelated
to the TDC.
VI. M EASUREMENT T ECHNIQUES AND R ESULTS
Generating input signals with accurate time delay is typ-
ically as complicated as measuring such a delay with a
comparable accuracy.
For low resolution applications, in the order of tens of
picoseconds, an arbitrary waveform generator (AWG) is capa-
ble of generating the start and stop signals and sweeping the
time delay between them. In [1] we were able to use a direct-
digital synthesizer (DDS) to generate two sine waves with a
relative delay resolution close to 1 ps, although with a relative
RMS jitter of about 10 ps.
Smaller time delays with lower noise can be achieved
by using a voltage-controlled delay line, which is usually
implemented by a cascade of inverter gates whose propagation
delay is controlled with their supply voltage.
In this work we use a technique that allows for the adjust-
ment of the output phase in a fractional-N PLL with close to
perfect linearity and resolution only limited by the number of
fractional bits. The basic principle behind it is that the 
modulator in the feedback divider acts as a phase accumulator
which determines how the integer part of the divider value
is dithered. Adding an offset to the accumulator results in a
phase offset in the PLL’s output. This does not require any
modification of the  modulator, but only an external circuit
that switches the value of N (fractional) from N to N + N
in one reference cycle and back to N on the next. This adds a
fixed phase offset because the amount of phase accumulated
during the reference period is the result of integrating a slightly
different frequency, f +  f . The details of the technique can
be found in [27].
The test setup shown in Fig. 14 was fully integrated on chip.
One of the input signals to the TDC is from a reference crystal,
and the other is shifted in phase by a fractional-N PLL.
The first step in the characterization is to determine the
average τgate . The ring oscillator can be made to oscillate
in its first harmonic by supplying a rising edge on A, and
then on B past the measurement range of the TDC. Edges A
and A will vanish when they reach the input stage of B.
Then the B edge will be the sole edge propagating in the
ring. Direct measurement of the frequency at any node yields
81
Fig. 15. TDC response for an input of two 100 MHz signals swept in relative
phase for 360degrees in steps of 12.5ps.
Fig. 16. Integral Nonlinearity.
f ring = (2Nτgate )−1 . On a typical chip at room temperature
we observed f ring =143 MHz, therefore τgate = 55.5 ps.
In normal operation, the delay between inputs A and B can
be swept a whole period of f ref . Fig. 15 shows the response
of the TDC using m = 8 averaged samples per measure-
ment, taken at 100 Msamples/s, in steps of 12.5 ps, covering
360degrees of relative phase between the two 100 MHz input
signals. The range is confirmed to be 2.25 ns, slightly below
the theoretical maximum of 2.6 ns. Outside the range of
operation, the ring carries a single edge, and the decoded
values depend on the implementation of the decoder.
Measurement accuracy can be determined by the combi-
nation of precision and linearity. These can be determined
simply by collecting a large number of measurements for each
input value and determining first-order statistics. The average
measurements in the linear portion of the response in Fig. 15
subtracted from a linear fit are shown in Fig. 16. This is known
as integral nonlinearity.
The standard deviation is the RMS precision or error, σtdc .
Fig. 17 plots σtdc versus number of averaged ring-samples, m.
Each marker is for √ a different input value covering the whole
input range. The 1/ m profile confirms the quantization noise
scrambling as predicted.
The measurements shown for Fig. 17 have been carried out
at an increasing sampling rate for an increasing number of
ring-samples, such that the total time the quantity is held in
the ring is constant regardless of the number of samples per
measurement. This ensures that the device and circuit noise
accumulated during the measurement process stays constant.
82 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 1, JANUARY 2018
Fig. 17. Standard deviation in 200 measurements each carried out using
m = 8, 16, 32 and 64 samples from the ring taken in Tmeas = 87 ns, i.e. at
a frequency of f sample (m) = m/ Tmeas . Each marker for a given number of
samples corresponds to a different input value within the TDC’s linear range.
TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON
In contrast, those in Fig. 18 have all been collected at
733 MHz. Degradation is observed for large number of sam-
ples due to the increased time for noise to accumulate.
Since in Fig. 18 the noise flattens out (around 0.1τgate after
m ≈ 16) as m increases, then the additional noise (above √
quantization noise) must accumulate in proportion to m.
In other words, it must be uncorrelated in nature.
Considering that power and quantization noise directly
impact the performance of a DPLL, and that a bandwidth ver-
sus quantization noise trade-off can be leveraged, we propose
the following figure-of-merit (FOM):
 
P × σtdc
FOM = 10 log10 (16)
BWnorm
where BWnorm = BW/ f e is the bandwidth normalized to the
event or measurement rate.
A summary and comparison to state-of-the-art ring-
oscillator-based TDCs is presented in Table I.
Fig. 18. Standard deviation in 200 measurements each carried out using
m = 8, 16, 32 and 64 samples from the ring taken at a frequency
of f sample = 733 MHz. Each marker for a given number of samples
corresponds to a different input value within the TDC’s linear range.
VII. C ONCLUSION
Time-to-digital converters face the particular challenge of
measuring discrete events instead of continuous signals. This
limits when and how often they can carry out a measurement.
Since oversampling determines precision, the inability to con-
trol the measurement/event rate sets a bandwidth-precision
trade-off. By introducing sample-and-hold this trade-off is
broken, as precision is no longer dependent on event rate.
The HRO TDC not only provides a reliable analog stor-
age mechanism, suitable for a time-sample-and-hold in deep
submicron CMOS, where charge storage is becoming less
dependable due to leackage. It also takes advantage of prop-
erties of ring-oscillator-based TDCs that have recently been
identified in similar converters, such as intrinsic dynamic
element matching and quantization noise scrambling. Finally,
it requires no assumption about the periodicity or duty cycle of
the input signals, and its accuracy is independent of reference
clock phase noise.
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Juan Pablo Caram received the B.S. degree (Hons.)
in electrical engineering from Pontificia Universidad
Catolica, Santiago, Chile, in 2008, and the M.S.E.E.
from the Georgia Institute of Technology, Atlanta,
GA, USA, in 2014, where he is currently pursuing
the Ph.D. degree.
From 2006 to 2011, he was with the Atacama
Large Millimeter/Sub-Millimeter Array Observatory,
San Pedro de Atacama, Chile, as an Engineer for
the Electronics (prototype and production) Systems
Integration Group. Since 2013, he has been with
Silicon Creations LLC, Suwanee, GA, as a Senior Hardware Engineer,
researching and designing PLL and SERDES integrated circuits.
Jeff Galloway received the B.S. degree in electrical
engineering from Georgia Tech and the master’s
degree from Stanford University. He held positions
at Hewlett Packard and Agilent Laboratories design-
ing SERDES and data converter circuits. He is
currently a Co-Founder and the Vice President of
Silicon Creations. Since founding the company, he
has helped architect the PLL and SERDES prod-
uct lines. He has helped start, grow, and manage
successful design centers in Atlanta, GA, USA, and
Krakow, Poland. His interests include analog design,
design automation, and silicon test and evaluation. He holds 12 U.S. patents.
J. Stevenson Kenney (S’84–M’85–SM’01–F’08)
was born in St. Louis, MO, USA, in 1962.
He received the B.S.E.E. (Hons.), M.S.E.E., and
Ph.D. degrees from the Georgia Institute of Technol-
ogy in 1985, 1990, and 1994, respectively. He has
held engineering and management positions at Elec-
tromagnetic Sciences, Scientific Atlanta, and Pacific
Monolithics, and Spectrian. In 2000, he joined the
Georgia Institute of Technology, as a Faculty Mem-
ber, where he is currently an Associate Professor.
He is also teaching and conducting research in the
areas of power amplifier linearization, smart antenna design, and RFIC design.
He has authored or co-authored over 150 peer reviewed journal papers,
conference papers, and magazine articles, and has presented at numerous
IMS workshops. He has been an active member of the IEEE Microwave
Theory and Techniques Society (MTTS) for over 30 years. In 2008, he was
elevated to the IEEE Fellow for contributions to microwave power amplifier
design, characterization, and linearization. He received the 2005 IEEE MTTS
Application Award for the development of power amplifier linearization
techniques and insertion into cellular/wireless systems. He served as the
President of the MTTS in 2007.