8259A PROGRAMMABLE

INTERRUPT CONTROLLER
 NEED FOR 8259A
• 8085 Processor has only 5 hardware interrupts.
• Consider an application where a number of I/O devices
connected with CPU desire to transfer data using
interrupt driven data transfer mode. In this process more
number of interrupt pins are required.
• In these multiple interrupt systems the processor will
have to take care of priorities.
 8259A PIC
• Able to handle a number of interrupts at a
time.
• Takes care of a number of simultaneously
appearing interrupt requests along with
their types and priorities.
• Compatible with 8-bit as well as 16-bit
processors.
 8259A PIC- FEATURES
• Manage 8 interrupts according to the instructions
written into the control registers.
• Vector an interrupt request anywhere in the
memory map. However all the 8 interrupts are
spaced at an interval of four to eight locations.
• Resolve 8 levels of interrupt priorities in variety
of modes.
• Mask each interrupt request individually.
• Read the status of pending interrupts, in-service
interrupts and masked interrupts.
 8259A PIC- FEATURES
• Be set up to accept either the level triggered or
the edge triggered interrupt request.
• Be expanded to 64 priority levels by cascading
additional 8259As.
• Compatible with 8-bit as well as 16-bit
processors.
8259A PIC- BLOCK DIAGRAM
It includes 8 blocks.
• Control logic
• Read/Write logic
• Data bus buffer
• Three registers (IRR,ISR and IMR)
• Priority resolver
• Cascade Buffer
8259A PIC- PIN DIGRAM
8259A PIC- BLOCK DIAGRAM
8259A PIC- INTERRUPTS AND CONTROL
LOGIC SECTION
This section consists of
• IRR (Interrupt
IRR
Request Register) • 8 interrupt inputs set
corresponding bits of
• ISR (In-Service
IRR
Register)
• Used to store the
• Priority Resolver
information about the
• IMR (Interrupt Mask interrupt inputs
Register) requesting service.
• Control logic block
 8259A PIC- INTERRUPTS AND CONTROL
LOGIC SECTION

ISR PRIORITY RESOLVER

• Determines the priorities of

interrupts requesting services
• Used to store information (which set corresponding bits
about the interrupts of IRR)
currently being serviced. • It determines the priorities as
dictated by priority mode set
by OCWs.
• The bit corresponding to
* OCWs  Operation highest priority input is set in
Control Word. ISR during input.
• Examines three registers and
determines whether INT
should be sent to MPU.
8259A PIC- INTERRUPTS AND CONTROL
LOGIC SECTION

IMR
• This register can be programmed by an OCW to
store the bits which mask specific interrupts.
• IMR operates on the IRR.
• An interrupt which is masked by software (By
programming the IMR) will not be recognized
and serviced even if it sets corresponding bits in
the IRR.
 8259A PIC- INTERRUPTS AND CONTROL
LOGIC SECTION
CONTROL LOGIC
• Has two pins:
INT (Interrupt) Output
( Interrupt Acknowledge) Input
• INT Connected to Interrupt pin of MPU.
 When interrupt occurs this pin goes high.
 8259A PIC- BLOCK DIAGRAM
DATA BUS BUFFER
• 8 bit
• Bidirectional
• Tri-state Buffer used to Interface the 8259 to the
system data bus.
• Control words, Status words and vectoring data
are all passed through the data bus buffer.
 8259A PIC- READ/WRITE CONTROL LOGIC
SECTION

• Contains ICW and OCW registers which are

programmed by the CPU to set up the 8259 and to
operate it in various modes.
• Also accepts read command from CPU to permit the
CPU to read status words.
•  Chip Select  Active Low input
 Used to select the Device.
•  Read  Active Low input
 Used by CPU to read the status of
ISR,IRR,IMR or the Interrupt level.
•  Write  Active Low input
 Used to write OCW and ICW onto the 8259.
*ICW Initialization Control Word
 8259A PIC- CASCADE BUFFER/
COMPARATOR
• Generates control signals for cascade operation.
• Also generates buffer enable signals.
• 8259 cascaded with other 8259s
 Interrupt handling capacity to 64 levels
 Former is called master and latter is slave.
• 8259 can be set up as master or slave by
pin in non-buffered mode or by software if it is to
be operated in the buffered mode of operation.
 8259A PIC- CASCADE BUFFER/
COMPARATOR
CAS 0-2
• For master 8259 these pins are outputs and for slaves these are
inputs.
• When 8259 is a master the CALL op-code is generated by master in
response to the first Interrupt acknowledge.
• The vectoring address must be released by slave 8259.

• The master puts out the identification code to select one of the slave
from 8 slaves through these pins.
• The slave accepts these three signals as inputs and compare the
code put out by the master with the codes assigned to them during
initialization.
• The slave thus selected puts out the address of ISR during second
and third interrupt acknowledge pulses from the CPU.
 8259A PIC- CASCADE BUFFER/
COMPARATOR
Slave Program/ Enable Buffer:
• Used to specify whether 8259 is to act as a
master or a slave
High Master
Low  Slave
• In Non-Buffered Mode, this pin is used to specify
whether 8259 is to act as a master or a slave.
• In Buffered mode this pin is used as an output to
enable the data bus buffer of the system.
8259A PIC- INTERRUPT OPERATION

• To implement interrupt, the interrupt Enable FF must be

enabled by writing EI instruction.
• 8259A should be initialized by writing control words in
the control register.
• 8259 requires two types of control words:
ICW Used to set up proper conditions
and specify RST vector address.
OCW Used to perform functions such as
masking interrupts, setting up status
read operations etc.
• After 8259A is initialized, the following sequence of
events occurs when one or more interrupt request lines
go high.
8259A PIC- INTERRUPT OPERATION

• IRR stores the Interrupt requests.

• Priority Resolver Checks three registers:
IRR for interrupt requests.
IMR for Masking bits.
ISR for the interrupt request being serviced.
It resolves the
priority and sets the INT high when
appropriate.
• MPU acknowledges the interrupt by sending
interrupt acknowledge.
8259A PIC- INTERRUPT OPERATION

4. After is received, the appropriate priority

bit in the ISR is set to indicate which level is
being served and the corresponding bit in the
IRR is reset to that request is accepted. Then
op-code for CALL instruction is placed on the
Data Bus.
5. When MPU decodes the CALL instruction, it
places two more signals on the data
bus.
8259A PIC- INTERRUPT OPERATION

6. When 8259 receives second , it

places lower order byte of CALL address
on the data bus.
Third  High order byte.
The CALL address is the vector memory
location for the interrupt. This address is
placed in control register during
initialization.
8259A PIC- INTERRUPT OPERATION

7. During third pulse, the ISR bit is reset

either automatically (AEOI) or by a command
word that must be issued at the end of the
service routine (EOI). This option is determined
by the ICW.
8. The program sequence is transferred to the
memory location specified by the CALL
instruction.
AEOI  Automatic End of Interrupt Mode
EOI  End of Interrupt Mode
 8259A PIC- COMMAND WORDS
• Two types: ICW, OCW
ICW:
• Before start functioning, 8259 must be initialized
by writing two to four command words into their
respective command word registers.
• A0=0,D4=1: The control word is ICW1. ICW1
contains the control bits for edge/level triggered
mode, single/cascade mode, call address
interval and whether ICW4 is required or not etc.
• A0=1: ICW2Store details interrupt vector
addresses.
 8259A PIC- ICW1
The following initialization procedure Carried out internally
when ICW1 is loaded.
• The edge sense circuit is reset i.e. by default 8259A
interrupts are edge sensitive.
• IMR is cleared.
• IR7 input is assigned lowest priority.
• Slave mode address is set to 7.
• Special mask mode is cleared and status read is set to
IRR.
• If IC4=0, all functions of ICW4 are set to Zero.
Master/slave bit in ICW4 bit is used in buffered mode
only.
INITIALIZATION SEQUENCE OF 8259A

ICW1 & ICW2 are

Compulsory command
Words in the initialization
sequence.

ICW3 & ICW4 are

Optional.

ICW3 is read only when

More than one 8259 used
in the system ( SNGL bit in
ICW1 is 0).
ADI=1 for 8086 based system

For 8086 Don’t Care

p
For 8085 system they are filled by A15-A11 of the interrupt vector address and
Least significant 3 bits are same as the respective bits of the vector address.
For 8086 system they are filled by most significant 5 bits of interrupt type and
the least significant 3 bits are 0, pointing to IR0.
If BUF=0,M/S is to be neglected.
 8259A- OPERATING MODES
FULLY NESTED MODE:
• General purpose mode.
• All IRs are arranged from highest to lowest.
• IR0 Highest IR7Lowest

AUTOMATIC ROTATION MODE:

• In this mode, a device after being serviced, receives the
lowest priority.

SPECIFIC ROTATION MODE:

• Similar to automatic rotation mode, except that the user
can select any IR for the lowest priority, thus fixing all
other priorities.
8259-INTERRUPT PROCESS IN FULLY NESTED MODE
 8259A- OPERATING MODES
END OF INTERRUPT (EOI):
• After the completion of an interrupt service, the
corresponding ISR bits needs to be reset to update the
information in the ISR. This is called EOI command.
It can be issued in three formats:
NON SPECIFIC EOI COMMAND:
• When this command is sent to 8259A, it resets the
highest priority ISR bit.
SPECIFIC EOI COMMAND:
• This command specifies which ISR bit is to reset.
 8259A- OPERATING MODES
AUTOMATIC EOI:
• In this mode, no command is necessary.
• During the third interrupt acknowledge
cycle, the ISR bit is reset.
• DRAWBACK: The ISR does not have
information about which ISR is being
serviced. Thus, any IR can interrupt the
service routine, irrespective of its priority, if
the interrupt enable FF is set.
 8259A- OPERATING MODES
SPECIAL FULLY NESTED MODE:
• Used in case of larger system where cascading is used, and the has
to be programmed in the master using ICW4
• In this mode, when an interrupt request from a certain slave is in
service, this slave can further send requests to the master, if the
requesting device connected to the slave has higher priority than the
one being currently served.
• In this mode, the master interrupts the CPU only when the
interrupting device has the highest priority or the same priority than
the one currently being served.
• In normal mode, other requests than the one being served are
masked.

BUFFERED MODE

CASCADE MODE
 ADDITIONAL FEATURES OF THE 8259A

INTERRUPT TRIGGERING:
• 8259A can accept an interrupt request with either the
edge triggered or level triggered mode.
• Mode is determined by initialization instructions.

INTERRUPT STATUS:
• The status of the three interrupt registers (IRR, ISR and
IMR) can be read, and this status information can be
used to make the interrupt process versatile.

POLL METHOD:
• 8259A can be set up to function in polled environment.
• MPU polls the 8259A rather than each peripheral.