TI Logic Pocket Book (R)

Pin Assignments
00 04
QUADRUPLE 2-INPUT HEX INVERTERS
POSITIVE-NAND GATES positive logic:
positive logic: Y=A
Y=A•B
VCC 4B 4A 4Y 3B 3A 3Y VCC 6A 6Y 5A 5Y 4A 4Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND 1A 1Y 2A 2Y 3A 3Y GND
See page 139 See page 143
01 U04
QUADRUPLE 2-INPUT POSITIVE-NAND GATES HEX INVERTERS
WITH OPEN-COLLECTOR OUTPUTS positive logic:
positive logic: Y=A
Y=A•B
VCC 4Y 4B 4A 3Y 3B 3A VCC 6A 6Y 5A 5Y 4A 4Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1Y 1A 1B 2Y 2A 2B GND 1A 1Y 2A 2Y 3A 3Y GND
02 05
QUADRUPLE 2-INPUT HEX INVERTERS
POSITIVE-NOR GATES WITH OPEN-COLLECTOR OUTPUTS
positive logic: positive logic:
Y=A+B Y=A
VCC 4Y 4B 4A 3Y 3B 3A VCC 6A 6Y 5A 5Y 4A 4Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1Y 1A 1B 2Y 2A 2B GND 1A 1Y 2A 2Y 3A 3Y GND
03 06
QUADRUPLE 2-INPUT POSITIVE-NAND GATES HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR OUTPUTS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Y=A•B Y=A
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND 1A 1Y 2A 2Y 3A 3Y GND
71
Pin Assignments
07 11
HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR TRIPLE 3-INPUT
HIGH-VOLTAGE OUTPUTS POSITIVE-AND GATES
Y=A Y=A•B•C
VCC 6A 6Y 5A 5Y 4A 4Y VCC 1C 1Y 3C 3B 3A 3Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B 2A 2B 2C 2Y GND
1A 1Y 2A 2Y 3A 3Y GND
08 14
QUADRUPLE 2-INPUT POSITIVE-AND GATES HEX SCHMITT-TRIGGER
positive logic: INVERTERS
Y=A•B positive logic:
Y=A
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND
09 16
QUADRUPLE 2-INPUT POSITIVE-AND GATES HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR OUTPUTS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Y=A•B Y=A
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7
1 2 3 4 5 6 7
10 17
TRIPLE 3-INPUT HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR
POSITIVE-NAND GATES HIGH-VOLTAGE OUTPUTS
Y=A•B•C Y=A
VCC 1C 1Y 3C 3B 3A 3Y VCC 6A 6Y 5A 5Y 4A 4Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B 2A 2B 2C 2Y GND 1A 1Y 2A 2Y 3A 3Y GND
72
Pin Assignments
19 26
HEX SCHMITT-TRIGGER INVERTERS QUADRUPLE 2-INPUT HIGH-VOLTAGE
positive logic: INTERFACE POSITIVE-NAND GATES
Y=A positive logic:
Y = AB
VCC 6A 6Y 5A 5Y 4A 4Y VCC 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7
1 2 3 4 5 6 7
20 27
DUAL 4-INPUT TRIPLE 3-INPUT
POSITIVE-NAND GATES POSITIVE-NOR GATES
VCC 2D 2C NC 2B 2A 2Y
Y=A•B•C•D Y=A+B+C
VCC 1C 1Y 3C 3B 3A 3Y
14 13 12 11 10 9 8
14 13 12 11 10 9 8
1 2 3 4 5 6 7
1A 1B NC 1C 1D 1Y GND 1 2 3 4 5 6 7
NC – No internal connection
21 30
DUAL 4-INPUT 8-INPUT POSITIVE-NAND GATES
POSITIVE-AND GATES positive logic:
positive logic: Y=A•B•C•D•E•F•G•H
VCC 2D 2C NC 2B 2A 2Y VCC NC H G NC NC Y
Y=A•B•C•D
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B NC 1C 1D 1Y GND A B C D E F GND
NC – No internal connection NC – No internal connection

25 31
DUAL 4-INPUT POSITIVE-NOR GATES DELAY ELEMENTS
WITH STROBE
positive logic: VCC NC H G NC NC Y
Y = G (A + B + C + D)
STROBE 14 13 12 11 10 9 8
VCC 2D 2C 2G 2B 2A 2Y
14 13 12 11 10 9 8
1 2 3 4 5 6 7
A B C D E F GND
1 2 3 4 5 6 7
1A 1B STROBE 1C 1D 1Y GND NC – No internal connection
1G
73
Pin Assignments
32 38
QUADRUPLE 2-INPUT QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
POSITIVE OR GATES WITH OPEN-COLLECTOR OUTPUTS
Y=A+B Y=A•B
VCC 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8
14 13 12 11 10 9 8
1 2 3 4 5 6 7
See page 157

1 2 3 4 5 6 7
33 1A 1B 1Y 2A 2B 2Y GND
QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS

WITH OPEN-COLLECTOR OUTPUTS
positive logic:
Y=A+B See page 159
VCC 4Y 4B 4A 3Y 3B 3A
14 13 12 11 10 9 8 42
4-LINE-TO-10-LINE DECODERS
INPUTS OUTPUTS
1 2 3 4 5 6 7 VCC A B C D 9 8 7
1Y 1A 1B 2Y 2A 2B GND 16 15 14 13 12 11 10 9
See page 158
35 A B C D
HEX NONINVERTERS
0 1 2 3 4 5 6 7 8 9
positive logic:
Y=A
VCC 6A 6Y 5A 5Y 4A 4Y 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 GND
14 13 12 11 10 9 8
OUTPUTS
See page 160
45
BCD-TO-DECIMAL DECODER/DRIVER
1 2 3 4 5 6 7
See page 158
37 INPUTS OUTPUTS
QUADRUPLE 2-INPUT A
VCC B C D 9 8 7
POSITIVE-NAND BUFFERS
16 15 14 13 12 11 10 9
positive logic:
Y=A•B
A B C D
14 13 12 11 10 9 8
BCD-TO-DECIMAL
0 1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 GND
OUTPUTS
1 2 3 4 5 6 7
74
Pin Assignments
47 64
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS 4-2-3-2 INPUT AND-OR INVERT GATE
positive logic:
Y = ABCD + EF + GHI + JK
VCC D C B K J Y
14 13 12 11 10 9 8
OUTPUTS
VCC f g a b c d e
16 15 14 13 12 11 10 9
f g a b c d e
BI/
B C LT RBO RBI D A 1 2 3 4 5 6 7
A E F G H I GND
See page 167

1 2 3 4 5 6 7 8
B C LAMP
TEST
RB
OUT-
PUT
RB
IN-
PUT
D A GND
73
INPUTS INPUTS DUAL J-K FLIP-FLOPS WITH CLEAR
See page 164

1J 1Q 1Q GND 2K 2Q 2Q
51 14 13 12 11 10 9 8
AND-OR-INVERT GATES
’51, ’S51 DUAL 2-WIDE 2-INPUT
Q Q Q Q
positive logic:
CLR CLR
Y = AB + CD CK CK
J K K J
MAKE NO EXTERNAL CONNECTION

1 2 3 4 5 6 7
VCC 1B 1D 1C 1Y
1CK 1CLR 1K VCC 2CK 2CLR 2J
14 13 12 11 10 9 8
See page 168
74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET AND CLEAR
VCC 2CLR 2D 2CK 2PR 2Q 2Q

1 2 3 4 5 6 7
1A 2A 2B 2C 2D 2Y GND 14 13 12 11 10 9 8
PR
D Q
CK
Q
CLR CLR
Q
CK
AND-OR-INVERT GATES
D Q
‘LS51 2-WIDE 3-INPUT, 2-WIDE 2-INPUT PR
positive logic:
1Y = (1A • 1B • 1C) + (1D • 1E • 1F) 1 2 3 4 5 6 7
1CLR 1D 1CK 1PR 1Q 1Q GND
2Y = (2A • 2B) + (2C • 2D)
See page 170
75
4-BIT BISTABLE LATCHES
VCC 1C 1B 1F 1E 1D 1Y
14 13 12 11 10 9 8
ENABLE
1Q 2Q 2Q 1–2 GND 3Q 3Q 4Q
16 15 14 13 12 11 10 9
Q D D Q Q D D Q
G G G G
1 2 3 4 5 6 7
1Y 2A 2B 2C 2D 2Y GND Q Q Q Q
1 2 3 4 5 6 7 8
1Q 1D 2D ENABLE VCC 3D 4D 4Q
3–4
75
Pin Assignments
85 93
4-BIT MAGNITUDE COMPARATORS 4-BIT BINARY COUNTERS
DATA INPUTS
INPUT
VCC A3 B2 A2 A1 B1 A0 B0 A NC QA QD GND QB QC
16 15 14 13 12 11 10 9 14 13 12 11 10 9 8
A3 B2 A2 A1 B1 A0 QA QD QB
A
B3 B0 QC
A<B A=B A>B A>B A=B A<B B
IN IN IN OUT OUT OUT R0 (1) R0 (2)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7
B3 A<B A=B A>B A>B A=B A<B GND INPUT R0 (1) R0 (2) NC VCC NC NC
DATA B
INPUT
CASCADE INPUTS OUTPUTS
86 97
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIER
positive logic:
RATE INPUT
Y = A ⊕ B or Y = AB + AB ENA-
UNITY/ BLE
VCC D C CLEAR CASCADE INPUT STROBE CLOCK
16 15 14 13 12 11 10 9
14 13 12 11 10 9 8
D C CLEAR UNITY/ ENA- STROBE

CASCADE BLE
INPUT
B CK
ENABLE
E F A Z Y OUTPUT
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 B E F A Z Y ENABLE GND
OUTPUT
RATE INPUTS OUTPUTS
90 107
DECADE COUNTER DUAL J-K FLIP-FLOPS WITH CLEAR
INPUT
A NC QA QD GND QB QC
14 13 12 11 10 9 8 VCC 1CLR 1CK 2K 2CLR 2CK 2J
14 13 12 11 10 9 8
QA QD QB
A QC
J K K J
BD Q9 (2) CK CK
R0 (1) R0 (2) Q9 (1) CLR CLR
Q Q Q Q
1 2 3 4 5 6 7
BD R0 (1) R0 (2) NC VCC Q9 (1) Q9 (2)
INPUT 1 2 3 4 5 6 7
1J 1Q 1Q 1K 2Q 2Q GND
92 109
DIVIDE-BY-TWELVE COUNTERS DUAL J-K POSITIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH PRESET AND CLEAR
INPUT
A NC QA QB GND QC QD
VCC 2CLR 2J 2K 2CK 2PR 2Q 2Q
14 13 12 11 10 9 8
16 15 14 13 12 11 10 9
PR Q
J
QA QD QC
CK
A QD CLR
K Q K Q
CLR
B R0 (2) CK
R0 (1) Q
J
PR
1 2 3 4 5 6 7
INPUT NC NC NC VCC R0 (1) R0 (2)
1 2 3 4 5 6 7 8
B 1CLR 1J 1K 1CK 1PR 1Q 1Q GND
76
Pin Assignments
112 124
DUAL J-K NEGATIVE-EDGE-TRIGGERED DUAL VOLTAGE-CONTROLLED OSCILLATORS
FLIP-FLOPS WITH PRESET AND CLEAR WITH ENABLE INPUTS
2Cext
2 2G 2Y
VCC ∼ VCC RANGE ENABLE OUTPUT GND
VCC 1CLR 2CLR 2CK 2K 2J 2PR 2Q 16 15 14 13 12 11 10 9

16 15 14 13 12 11 10 9
RNG Cext
Y
FREQ
CONT EN
K CLR Q J PR Q
CK CK FREQ EN
CONT Y
J Q K Q
PR CLR RNG C
ext
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 2 1 1 1G 1Y ∼ GND
RANGE ENABLE OUTPUT
1CK 1K 1J 1PR 1Q 1Q 2Q GND
FREQUENCY 1Cext
CONTROL
121 125
MONOSTABLE MULTIVIBRATOR QUADRUPLE BUS BUFFER GATES
WITH THREE-STATE OUTPUTS
Rext／ positive logic:
VCC NC NC Cext Cext Rint NC
Y=A
14 13 12 11 10 9 8 VCC 4C 4A 4Y 3C 3A 3Y
14 13 12 11 10 9 8
1 2 3 4 5 6 7
Q NC A1 A2 B Q GND 1 2 3 4 5 6 7
1C 1A 1Y 2C 2A 2Y GND
122 126
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS QUADRUPLE BUS BUFFER GATES
WITH CLEAR WITH THREE-STATE OUTPUTS
positive logic:
Rext／
VCC Cext NC Cext NC Rint Q Y=A
VCC 4C 4A 4Y 3C 3A 3Y
14 13 12 11 10 9 8
14 13 12 11 10 9 8
Q
CLR
1 2 3 4 5 6 7
A1 A2 B1 B2 CLR Q GND 1 2 3 4 5 6 7
1C 1A 1Y 2C 2A 2Y GND
123 128
DUAL RETRIGGERABLE MONOSTABLE SN54128...75-Ω LINE DRIVER
MULTIVIBARATORS WITH CLEAR SN74128...50-Ω LINE DRIVER
positive logic:
1Rext／ 1 Y=A+B
VCC Cext Cext 1Q 2Q 2CLR 2B 2A VCC 4Y 4B 4A 3Y 3B 3A
16 15 14 13 12 11 10 9 14 13 12 11 10 9 8
Q CLR
Q
Q
CLR Q
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7
1A 1B 1CLR 1Q 2Q 2 2Rext／ GND 1Y 1A 1B 2Y 2A 2B GND
Cext Cext
77
Pin Assignments
132 138
QUADRUPLE 2-INPUT POSITIVE-NAND 3-TO-LINE DECODERS/DEMULTIPLEXRS
SCHMITT TRIGGERS
DATA OUTPUTS
positive logic:
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
Y=A•B
VCC 4B 4A 4Y 3B 3A 3Y 16 15 14 13 12 11 10 9
14 13 12 11 10 9 8
Y0 Y1 Y2 Y3 Y4 Y5
A Y6
B C G2A G2B G1 Y7
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 A B C G2A G2B G1 Y7 GND
SELECT ENABLE OUTPUT
133 139
13-INPUT POSITIVE-NAND GATES DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS
positive logic:
SELECT DATA OUTPUTS
Y=A•B•C•D•E•F•G•H•I•J•K•L•M ENABLE
VCC 2G 2A 2B 2Y0 2Y1 2Y2 2Y3
VCC M L K J I H Y 16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
G A B Y0 Y1 Y2
Y3
G
A B Y0 Y1 Y2 Y3
1 2 3 4 5 6 7 8
1G 1A 1B 1Y0 1Y1 1Y2 1Y3 GND
1 2 3 4 5 6 7 8 ENABLE
A B C D E F G GND
SELECT DATA OUTPUTS
136 140
QUAD 2-INPUT EXCLUSIVE-OR GATES DUAL 4-INPUT POSITIVE-NAND 50-Ω
WITH OPEN COLLECTOR OUTPUTS LINE DRIVERS
Y = A ⊕ B = AB + AB Y = ABCD VCC 2D 2C NC 2B 2A 2Y
14 13 12 11 10 9 8
14 13 12 11 10 9 8
1 2 3 4 5 6 7
1A 1B NC 1C 1D 1Y GND
1 2 3 4 5 6 7
137 145
3-TO 8-LINE DECODERS/DEMULTIPLEXERS BCD-TO-DECIMAL DECODERS/DRIVERS
WITH ADDRESS LATCHES FOR LAMPS, RELAYS, MOS
DATA OUTPUTS PARALLEL INPUTS OUTPUTS
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 VCC A B C D 9 8 7
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
A B C D
Y0 Y1 Y2 Y3 Y4 Y5
BCD-TO-DECIMAL
A Y6
B C GL G2 G1 Y7 0 1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A B C GL G2 G1 Y7 GND 0 1 2 3 4 5 6 GND
SELECT ENABLE OUTPUT OUTPUTS

78
Pin Assignments
147 151
10-TO-4 LINE PRIORITY ENCODER 8-TO-1 LINE DATA SELECTORS/MULTIPLEXERS
INPUTS DATA INPUTS DATA SELECT
VCC NC Y3 I3 I2 I1 I9 Y0 VCC 4 5 6 7 A B C
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
D 3 2 1 9 D4 D5 D6 D7 A B
4 A D3 C
5 6 7 8 C B D2 D1 D0 Y W S
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
I4 I5 I6 I7 I8 Y2 Y1 GND 3 2 1 0 Y W STROBE GND
INPUTS OUTPUTS DATA INPUTS OUTPUTS
148 153
8-TO-3-LINE OCTAL PRIORITY ENCODERS DUAL 4-LINE TO 1-LINE DATA
SELECTORS/MULTIPLEXERS
OUTPUTS INPUTS
DATA INPUTS
OUTPUT
VCC E0 GS 3 2 1 0 A0 STROBE A OUTPUT
VCC 2G SELECT 2C3 2C2 2C1 2C0 2Y
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
2C3 2C2 2C1 2C0 2Y

E0 GS 3 2 1 0 2G
B B A A
4 A0
5 6 7 EI A2 A1
B B A A
1G
1C3 1C2 1C1 1C0 1Y
1 2 3 4 5 6 7 8
4 5 6 7 EI A2 A1 GND
1 2 3 4 5 6 7 8
STROBE B 1C3 1C2 1C1 1C0 OUTPUT GND
INPUTS OUTPUTS 1G SELECT 1Y
DATA INPUTS
150 154
1-OF-16 DATA SELECTOR 4-LINE TO 16-LINE DECODER/DEMULTIPLEXER
DATA INPUTS DATA SELECT INPUTS OUTPUTS
VCC 8 9 10 11 12 13 14 15 A B C VCC A B C D G2 G1 15 14 13 12 11
24 23 22 21 20 19 18 17 16 15 14 13 24 23 22 21 20 19 18 17 16 15 14 13
E8 E9 E10 E11 E12 E13 E14 E15 A B A B C D G2 G1 15 14 13 12
E7 C 0 11
E6 E5 E4 E3 E2 E1 E0 S W D 1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
7 6 5 4 3 2 1 0 STROBE W D GND 0 1 2 3 4 5 6 7 8 9 10 GND
OUT- DATA
PUT SELECT
DATA INPUTS OUTPUTS
79
Pin Assignments
155 161
156 163
DECODERS/DEMULTIPLEXERS SYNCHRONOUS 4-BIT BINARY COUNTERS
OUTPUTS
OUTPUTS RIPPLE
CARRY ENABLE
SELECT VCC OUTPUT QA QB QC QD T LOAD
DATA STRB INPUT
VCC 2C 2G A 2Y3 2Y2 2Y1 2Y0
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
2Y3 2Y2 2Y1 2Y0 RIPPLE QA QB QC QD ENABLE

2G 2C CARRY T
B B A A OUTPUT
CLEAR LOAD
CK ENABLE
A B C D P
B B A A
1G 1C
1Y3 1Y2 1Y1 1Y0
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 CLEAR CLOCK A B C D ENABLE GND
P
DATA STRB SELECT 1Y3 1Y2 1Y1 1Y0 GND
1C 1G INPUT DATA INPUTS
OUTPUTS
See page 214, 216 See page 224, 226
157 164
8-BIT PARALLEL OUTPUT SERIAL SHIFT REGISTERS
158
QUAD 2-TO 1-LINE DATA SELECTORS/MULTIPLEXERS
INPUTS OUTPUTS INPUTS OUTPUTS OUTPUTS
VCC STROBE 4A 4B 4Y 3A 3B 3Y VCC QH QG QF QE CLEAR CLOCK
16 15 14 13 12 11 10 9 14 13 12 11 10 9 8
G 4A 4B 4Y 3A 3B QH QG QF QE CLEAR
S 3Y A CK
1A 1B 1Y 2A 2B 2Y B QA QB QC QD
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7
SELECT 1A 1B 1Y 2A 2B 2Y GND A B QA QB QC QD GND
INPUTS OUTPUTS INPUTS OUTPUTS SERIAL INPUTS OUTPUTS
See page 218, 220 See page 228
159 165
4-TO-16 LINE DECODER/DEMULTIPLEXER 8-BIT SHFT REGISTERS
INPUTS OUTPUTS PARALLEL INPUTS
CLOCK SERIAL OUTPUT

VCC A B C D G2 G1 15 14 13 12 11 VCC INHIBIT D C B A INPUT QH
24 23 22 21 20 19 18 17 16 15 14 13 16 15 14 13 12 11 10 9
A B C D G2 G1 15 14 13 12 CLOCK D C B A SERIAL
INHIBIT IN
0 11 SHIFT/ QH
LOAD
1 2 3 4 5 6 7 8 9 10 CK
E F G H QH
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8 9 10 GND SHIFT/ CLOCK E F G H OUTPUT GND
LOAD QH
OUTPUTS PARALLEL INPUTS
80
Pin Assignments
166 173
8-BIT SHIFT REGISTERS 4-BIT D-TYPE REGISTERS
DATA ENABLE
DATA INPUTS INPUTS
VCC CLEAR 1D 2D 3D 4D G2 G1
16 15 14 13 12 11 10 9
PARALLEL INPUTS
PARALLEL
SHIFT/ INPUT OUTPUT
VCC LOAD H QH G F E CLEAR
CLEAR 1D 2D 3D 4D DATA
ENABLE
16 15 14 13 12 11 10 9
OUTPUT
CONTROL 1Q 2Q 3Q 4Q CK
SHIFT/ H QH G F E
LOAD
SERIAL CLEAR
INPUT 1 2 3 4 5 6 7 8
CLOCK CK M N 1Q 2Q 3Q 4Q CLOCK GND
A B C D INHIBIT
OUTPUT CONTROL OUTPUTS

See page 238
1 2 3 4 5 6 7 8
SERIAL
INPUT
A B C D CLOCK CLOCK GND
INHIBIT 174
PARALLEL INPUTS HEX D-TYPE FLIP-FLOPS
VCC 6Q 6D 5D 5Q 4D 4Q CLOCK
See page 232
16 15 14 13 12 11 10 9
169 Q D
CK
D
CK
Q D
CK
Q
4-BIT UP/DOWN SYNCHRONOUS BINARY COUNTERS CLEAR CLEAR CLEAR
CLEAR CLEAR CLEAR

CK CK CK
Q D D Q D Q
OUTPUTS 1 2 3 4 5 6 7 8
RIPPLE
CARRY ENABLE CLEAR 1Q 1D 2D 2Q 3D 3Q GND
VCC OUTPUT QA QB QC QD T LOAD
16 15 14 13 12 11 10 9
See page 240
RIPPLE QA QB QC QD ENABLE
CARRY
OUTPUT
UP/DOWN
T
LOAD
175
QUAD D-TYPE FLIP-FLOPS
CK ENABLE
A B C D P
VCC 4Q 4Q 4D 3D 3Q 3Q CLOCK
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
U/D CK A B C D ENABLE GND
P
Q Q Q Q
DATA INPUTS CLR CLR
CK D D CK
See page 234 CK D D CK

CLR CLR
Q Q Q Q
170 1 2 3 4 5 6 7 8
4-BY-4-REGISTER FILES
CLEAR 1Q 1Q 1D 2D 2Q 2Q GND
See page 241
WRITE SELECT ENABLE OUTPUTS
DATA
181
VCC D1 WA WB WRITE READ Q1 Q2
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
16 15 14 13 12 11 10 9 INPUTS OUTPUTS
VCC A1 B1 A2 B2 A3 B3 G Cn+4 P A=B F3

D1 WA WB GW GR Q1
24 23 22 21 20 19 18 17 16 15 14 13
D2 Q2
D3 D4 RB RA Q4 Q3 A1 B1 A2 B2 A3 B3 G Cn+4 P A=B
B0 F3
1 2 3 4 5 6 7 8 A0 S3 S2 S1 S0 Cn M F0 F1 F2
D2 D3 D4 RB RA Q4 Q3 GND
DATA READ SELECT OUTPUTS 1 2 3 4 5 6 7 8 9 10 11 12

B0 A0 S3 S2 S1 S0 Cn M F0 F1 F2 GND
INPUTS OUTPUTS
81
Pin Assignments
182 193
LOOK-AHEAD CARRY GENERATORS SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS
INPUTS OUTPUTS INPUTS

INPUTS OUTPUTS
DATA BO- DATA DATA

VCC P2 G2 Cn Cn+x Cn+y G Cn+z VCC A CLEAR RROW CARRY LOAD C D
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
P2 G2 Cn Cn+x Cn+y G A CLEAR BO- CARRY LOAD C

RROW
G1 Cn+z B D
COUNT COUNT
P1 G0 P0 G3 P3 P QB QA DOWN UP QC QD
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
G1 P1 G0 P0 G3 P3 P GND DATA QB QA COUNT COUNT QC QD GND
OUTPUT B DOWN UP
INPUT
INPUTS
OUTPUTS INPUTS OUTPUTS
190 194
4-BIT BIDIRECTIONAL UNIVERSAL
191 SHIFT REGISTERS
SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS
INPUTS OUTPUTS INPUTS
VCC QA QB QC QD CLOCK S1 S0
DATA RIPPLE MAX/ DATA DATA
VCC A CLOCK CLOCK MIN LOAD C D
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
QA QB QC QD CLOCK S1
A RIPPLE MAX/ LOAD C
CLOCK MIN
CLEAR S0
R A B C D L
QB QA CTEN DN/UP QC QD
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 CLEAR SHIFT A B C D SHIFT GND
DATA QB QA ENA- DOWN/ QC QD GND RIGHT LEFT
B BLE UP SERIAL SERIAL
INPUT INPUT PARALLEL INPUTS INPUT
OUTPUTS INPUTS OUTPUTS
192 195
PRESETTABLE SYNCHRONOUS 4-BIT PARALLEL-ACCESS SHIFT REGISTERS
4-BIT UP/DOWN COUNTERS
OUTPUTS
SHIFT/
VCC P0 MR TCD TCU PL P2 P3 VCC QA QB QC QD QD CLOCK LOAD
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
QA QB QC QD QD CK
SHIFT/
CLEAR LOAD
J K A B C D
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
P1 Q1 Q0 CPD CPU Q2 Q3 GND CLEAR J K A B C D GND
SERIAL INPUTS PARALLEL INPUTS
82
Pin Assignments
221 241
DUAL MONOSTABLE MULTIVIBRATORS OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
1 Rext/ 1
VCC Cext Cext 1Q 2Q 2CLR 2B 2A VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
16 15 14 13 12 11 10 9 20 19 18 17 16 15 14 13 12 11
Q CLR
Q
Q
CLR Q
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10
1A 1B 1CLR 1Q 2Q 2 2 Rext/ GND 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
Cext Cext
237 243
3-TO-8 LINE DECODER DEMULTIPLEXER QUADRUPLE BUS TRANSCEIVERS
WITH ADDRESS LATCHES
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 VCC GBA NC 1B 2B 3B 4B
16 15 14 13 12 11 10 9 14 13 12 11 10 9 8
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7
A0 A1 A3 LE OE1 OE0 Y7 GND GAB NC 1A 2A 3A 4A GND
238 244
3-TO-8-LINE DECODERS/DEMULTIPLEXERS OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
16 15 14 13 12 11 10 9 20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10
A0 A1 A2 E1 E2 E3 Y7 GND 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
240 245
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS OCTAL BUS TRANSCEIVERS
ENABLE
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 VCC G B1 B2 B3 B4 B5 B6 B7 B8
20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
83
Pin Assignments
247 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS 257

WITH RIPPLE BLANKING QUAD DATA SELECTORS/MULTIPLEXERS
OUTPUTS INPUTS INPUTS
OUTPUT
CONTROL OUTPUT OUTPUT
VCC f g a b c d e VCC G 4A AB 4Y 3A 3B 3Y
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
f g a b c d e G 4A AB 4Y 3A 3B
S 3Y
BI/
B C LT RBO RBI D A
1A 1B 1Y 2A 2B 2Y
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
B C LAMP RB RB D A GND SELECT 1A 1B 1Y 2A 2B 2Y GND
TEST OUT- IN- OUTPUT OUTPUT
PUT PUT
INPUTS INPUTS INPUTS INPUTS
250 258
1-OF-16 DATA GENERATOR/MULTIPLEXER QUAD DATA SELECTORS/MULTIPLEXERS
DATA INPUTS INPUTS INPUTS
OUTPUT
CONTROL OUTPUT OUTPUT
VCC 8 9 10 11 12 13 14 15 A B C VCC G 4A AB 4Y 3A 3B 3Y
24 23 22 21 20 19 18 17 16 15 14 13 16 15 14 13 12 11 10 9
E8 E9 E10 E11 E12 E13 E14 E15 A B G 4A AB 4Y 3A 3B
E7 C S 3Y
E6 E5 E4 E3 E2 E1 E0 G W D 1A 1B 1Y 2A 2B 2Y
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8
7 6 5 4 3 2 1 0 STROBE W D GND SELECT 1A 1B 1Y 2A 2B 2Y GND
OUT- DATA OUTPUT OUTPUT
PUT SELECT
DATA INPUTS INPUTS INPUTS
251 259
DATA SELECTORS/MULTIPLEXERS 8-BIT ADDRESSABLE LATCHES
OUTPUTS
DATA INPUTS DATA SELECT
EN- DATA
VCC CLEAR ABLE IN Q7 Q6 Q5 Q4
VCC 4 5 6 7 A B C
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
CLEAR G D
A
D4 D5 D6 D7 A B B
C
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D3 C
D2 D1 D0 Y W S
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A B C Q0 Q1 Q2 Q3 GND
3 2 1 0 Y W STROBE GND
LATCH SEL OUTPUTS
DATA INPUTS OUTPUTS
253 260
DUAL DATA SELECTORS/MULTIPLEXERS DUAL 5-INPUT POSITIVE-NOR GATES
DATA INPUTS
positive logic:
OUTPUT
CONTROL A OUTPUT
Y=A+B+C+D+E
VCC 2G SELECT 2C3 2C2 2C1 2CO 2Y
VCC 1E 1D 2E 2D 2C 2B
16 15 14 13 12 11 10 9
14 13 12 11 10 9 8
2C3 2C2 2C1 2CO 2Y
2G
B B A A
B B A A
1G
1C3 1C2 1C1 1C0 1Y
1 2 3 4 5 6 7 8
OUTPUT B 1C3 1C2 1C1 1C0 OUTPUT GND
1 2 3 4 5 6 7
CONTROL SELECT 1Y 1A 1B 1C 2A 1Y 2Y GND
1G
DATA INPUTS
84
Pin Assignments
265 279
QUAD COMPLEMENTARY-OUTPUT ELEMENTS QUAD S-R LATCHES
positive logic:
Y = A, W = A
VCC 4A 4W 4Y 3B 3A 3W 3Y VCC 4S 4R 4Q 3S1 3S1 3R 3Q
Y = AB, W = AB
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
1A 1W 1Y 2A 2B 2W 2Y GND 1R 1S1 1S2 1Q 2R 2S 2Q GND
266 280
QUAD 2-INPUT EXCLUSIVE-NOR GATES 9-BIT ODD/EVEN PARITY INPUTS
WITH OPEN-COLLECTOR OUTPUTS GENERATORS/CHECKERS
VCC F E D C B A
positive logic:
Y=A⊕B 14 13 12 11 10 9 8
VCC 4B 4A 4Y 3Y 3B 3A
14 13 12 11 10 9 8
F E D C B
G A
Σ Σ
H I EVEN ODD
1 2 3 4 5 6 7
G H NC I Σ EVEN Σ ODD GND
INPUT
1 2 3 4 5 6 7
INPUTS OUTPUTS
1A 1B 1Y 2Y 2A 2B GND
273 283
OCTAL D-TYPE FLIP-FLOPS 4-BIT BINARY FULL ADDERS
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLOCK VCC B3 A3 Σ3 A4 B4 Σ4 C4
20 19 18 17 16 15 14 13 12 11 16 15 14 13 12 11 10 9
Q D D Q Q D D Q
CK CK CK CK
B3 A3 Σ3 A4 B4 Σ4
CLEAR CLEAR CLEAR CLEAR
Σ2 C4
CLEAR CLEAR CLEAR CLEAR
B2 A2 Σ1 A1 B1 C0
CK CK CK CK
Q D D Q Q D D Q
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8
CLEAR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND Σ2 B2 A2 Σ1 A1 B1 C0 GND
276 286
QUAD J-K FLIP-FLORS 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
WITH BUS DRIVER PARITY I/O PORT
INPUTS
VCC 4J 4CK 4K 4Q 3Q 3K 3CK 3J PRESET VCC F E D C B A
20 19 18 17 16 15 14 13 12 11 14 13 12 11 10 9 8
J K K J
PR CK CLR CLR CK PR
Q Q F E D C B
G A
Q Q PARITY PARITY
CK CLR CLR CK H XMIT I ERROR I/O
PR PR
J K K J
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7
CLEAR 1J 1CK 1K 1Q 2Q 2K 2CK 2J GND G H XMIT I PARITY PARITY GND
INPUT ERROR I/O
INPUTS
See page 292 See page 298 OUTPUTS
85
Pin Assignments
292 298
PROGRAMMABLE FREQUENCY QUAD 2-INPUT MULTIPLEXERS WITH STORAGE
DIVIDER/DIGITAL TIMER OUTPUTS
DATA
WORD INPUT
VCC C D TP3 NC CLEAR A NC VCC QA QB QC QD CLOCK SELECT C1
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
QA QB QC QD CK WS
C D TP3 CLR A
B B2 C1
E TP1 CLK1 CLK2 TP2 Q

A2 A1 B1 C2 D2 D1
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
B E TP1 CLK1 CLK2 TP2 QOUT GND B2 A2 A1 B1 C2 D2 D1 GND
NC – No internal connection DATA INPUTS

293 299
4-BIT BINARY COUNTERS 8-BIT BIDIRECTIONAL UNIVERSAL
OUTPUTS
SHIFT/STORAGE REGISTERS
INPUT INPUT
VCC RO(2) RO(1) B A QA QD SHIFT SHIFT
LEFT RIGHT
VCC S1 SL QH´ H/QH F/QF D/QD B/QB CLOCK SR
14 13 12 11 10 9 8
20 19 18 17 16 15 14 13 12 11
RO(2) RO(1) B A QA
S1 SL QH´ H/QH F/QF D/QD B/QB CK
QD S0 SR
QC QB G G/QG E/QE C/QC A/QA QA´ CLEAR
1 2 3 4 5 6 7
NC NC NC QC QB NC GND 1 2 3 4 5 6 7 8 9 10
S0 G1 G2 G/QG E/QE C/QC A/QA QA´ CLEAR GND
OUTPUTS
NC – No internal connection OUTPUT

See page 302 See page 310 CONTROLS
294 321
PROGRAMMABLE FREQUENCY CRYSTAL-CONTROLLED OSCILLATOR
DIVIDER/DIGITAL TIMER
XTAL XTAL
VCC C D NC NC CLEAR NC NC VCC 2 1 F/2 F VCC´ F´ F´
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
XTAL XTAL F/2 F F´

C D CLR A 2 1
B TANK1 F´
A TP CLK1 CLK2 Q
TANK2 FFQ FFD F/4 F
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
B A TP CLK1 CLK2 NC QOUT GND TANK TANK GND FFQ FFD F/4 F GND
1 2 1 2
297 323
DIGITAL PHASE-LOCKED-LOOP FILTERS 8-BIT BIDIRECTIONAL SHIFT/STORAGE REGISTERS
SHIFT SHIFT
LEFT RIGHT
ECPD EXOR VCC S1 SL QH´ H/QH F/QF D/QD B/QB CLOCK SR
VCC C D φ A2 OUT OUT φB φ A1
20 19 18 17 16 15 14 13 12 11
16 15 14 13 12 11 10 9
S1 SL QH´ H/QH F/QF D/QD B/QB CK
C D φ A2 ECPD EXOR φB S0 SR
OUT OUT
B φ A1 G G/QG E/QE C/QC A/QA QA´ CLEAR
K I/D I/D
A ENA CLK CLK U/D OUT
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8
S0 G1 G2 G/QG E/QE C/QC A/QA QA´ CLEAR GND
B A ENA K I/D U/D I/D GND
CLK CLK OUT
OUTPUT
CONTROLS
86
Pin Assignments
348 366
8-LINE TO 3-LINE PRIORITY ENCODER HEX BUS DRIVERS
HEX BUFFERS/LINE DRIVERS 3-STATE
VCC G2 6A 6Y 5A 5Y 4A 4Y
OUTPUTS INPUTS 16 15 14 13 12 11 10 9
OUTPUT
VCC EO GS 3 2 1 0 A0
16 15 14 13 12 11 10 9
EO GS 3 2 1 0
4 A0
5 6 7 EI A2 A1 1 2 3 4 5 6 7 8
G1 1A 1Y 2A 2Y 3A 3Y GND
1 2 3 4 5 6 7 8 See page 323

4 5 6 7 EI A2 A1 GND
INPUTS OUTPUTS 367

HEX BUS DRIVERS
See page 316 VCC G2 6A 6Y 5A 5Y 4A 4Y
16 15 14 13 12 11 10 9
354
356
8-INPUT MULTIPLEXERS/REGISTERS 3-STATE
SELECT
1 2 3 4 5 6 7 8
VCC Y W G3 G2 G1 S0 S1 S2 CONTROL G1 1A 1Y 2A 2Y 3A 3Y GND
20 19 18 17 16 15 14 13 12 11
See page 324
Y W G3 G2 G1 S0 S1 S2
D7 SC
368
HEX BUS DRIVERS
DATA
D6 D5 D4 D3 D2 D1 D0 C/C
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 11 10 9
D7 D6 D5 D4 D3 D2 D1 D0 DATA GND
CONTROL
/CLOCK
See page 318, 320
365 1 2 3 4 5 6 7 8
HEX BUS DRIVERS
G1 1A 1Y 2A 2Y 3A 3Y GND
See page 324
373
OCTAL D-TYPE LATCHES
16 15 14 13 12 11 10 9
ENABLE
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q G
20 19 18 17 16 15 14 13 12 11
Q D D Q Q D D Q
G G G G
OE OE OE OE
1 2 3 4 5 6 7 8 Q D D Q Q D D Q
G1 1A 1Y 2A 2Y 3A 3Y GND G G G G
OE OE OE OE
1 2 3 4 5 6 7 8 9 10
OUTPUT 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
CONTROL
87
Pin Assignments
374 390
OCTAL D-TYPE FLIP-FLOPS DUAL DECADE COUNTERS
OUTPUTS
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLOCK 2 OUTPUT

VCC 2A CLEAR 2 QA 2B 2 QB 2 QC 2 QD
20 19 18 17 16 15 14 13 12 11 16 15 14 13 12 11 10 9
Q D D Q Q D D Q QA B QB QC QD
CK CK CK CK CLEAR
OE OE OE OE A
Q D D Q Q D D Q
CK CK CK CK A
OE OE OE OE CLEAR
QA B QB QC QD
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8
OUTPUT 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1A 1 1 QA 1B 1 QB 1 QC 1 QD GND
CONTROL
CLEAR OUTPUT
OUTPUTS
375 393
4-BIT BISTABLE LATCHES DUAL 4-BIT BINARY COUNTERS
OUTPUTS
ENABLE 2
VCC 4D 4Q 4Q 3-4 3Q 3Q 3D VCC 2A CLEAR 2 QA 2 QB 2 QC 2 QD
16 15 14 13 12 11 10 9 14 13 12 11 10 9 8
Q Q Q Q QA QB QC QD
CLEAR
G D D G A
G D D G A
CLEAR
Q Q Q Q QA QB QC QD
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7
1D 1Q 1Q ENABLE 2Q 2Q 2D GND 1A 1 1 QA 1 QB 1 QC 1 QD GND
1-2 CLEAR
OUTPUTS
377 395
OCTAL D-TYPE FLIP-FLOPS 4-BIT UNIVERSAL SHIFT REGISTERS
OUTPUTS
CASCADE
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLOCK OUTPUT OUTPUT
VCC QA QB QC QD QD´ CLOCK CONTROL
20 19 18 17 16 15 14 13 12 11 16 15 14 13 12 11 10 9
Q D D Q Q D D Q
CK CK CK CK
G G G G QA QB QC QD QD´ CK
CLEAR OUTPUT
CONTROL
G G G G
CK CK CK CK SERIAL LOAD
Q D D Q Q D D Q INPUT A B C D SHIFT
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8
ENABLE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
G CLEAR SERIAL A B C D LOAD GND
INPUT SHIFT
PARALLEL INPUTS
378 399
HEX D-TYPE FLIP-FLOPS QUAD 2-INPUT MULTIPLEXER WITH STORAGE
VCC 6Q 6D 5D 5Q 4D 4Q CLOCK VCC QD D1 D2 C2 C1 QC CLOCK
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
Q D D Q Q D
CK CK CK QD D1 D2 C2 C1 QC
G G G
WS CK
G G G
CK CK CK QA A1 A2 B2 B1 QB
Q D D Q Q D
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ENABLE 1Q 1D 2D 2Q 3D 3Q GND WORD QA A1 A2 B2 B1 QB GND
G SELECT
88
Pin Assignments
423 520
RE-TRIGGERABLE MONO-STABLE MULTIVIBRATOR
positive logic:
521
Y=A 8-BIT IDENTITY COMPARATOR
1 Rext/
VCC Cext 1 Cext 1Q 2Q 2CLR 2B 2A VCC P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4
16 15 14 13 12 11 10 9 20 19 18 17 16 15 14 13 12 11
P=Q Q7 P7 Q6 P6 Q5 P5 Q4
CLR
G P4
CLR
P0 Q0 P1 Q1 P2 Q2 P3 Q3
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10
1A 1B 1CLR 1Q 2Q 2 2 Rext/ GND G P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND
Cext Cext
See page 335 See page 342, 344
442 533
QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS OCTAL D-TYPE TRANSPARENT LATCHES
VCC GC GB GA A1 A2 A3 A4 S1 S0
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q C
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
Q D D D D Q
C8 C7 Q Q C6 C5
OC OC OC OC
Q Q Q Q
C1 C2 C3 C4
OC D D OC OC D D OC
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10
CS B1 C1 C2 B2 B3 C3 C4 B4 GND
OC 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
465 534
OCTAL BUFFERS WITH 3-STATE OUTPUTS OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
VCC G2 A8 Y8 A7 Y7 A6 Y6 A5 Y5 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11
G2 A8 Y8 A7 Y7 A6 Y6 A5 8Q D D 7Q 6Q D D 5Q
CK CK CK CK
OC OC OC OC
G1 Y5
1Q 2Q 3Q 4Q
CK CK CK CK
A1 Y1 A2 Y2 A3 Y3 A4 Y4 OC D D OC OC D D OC
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
G1 A1 Y1 A2 Y2 A3 Y3 A4 Y4 GND OC 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
518 540
8-BIT IDENTITY COMPARATOR
541
OCTAL BUFFERS AND LINE DRIVERS
VCC P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4
20 19 18 17 16 15 14 13 12 11 VCC G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
20 19 18 17 16 15 14 13 12 11
P=Q Q7 P7 Q6 P6 Q5 P5 Q4
G P4
P0 Q0 P1 Q1 P2 Q2 P3 Q3
1 2 3 4 5 6 7 8 9 10
G P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND
1 2 3 4 5 6 7 8 9 10
G1 A1 A2 A3 A4 A5 A6 A7 A8 GND
89
Pin Assignments
543 569
OCTAL REGISTERED TRANSCEIVERS SYNCHRONOUS 4-BIT UP/DOWN COUNTERS
VCC CEBA B1 B2 B3 B4 B5 B6 B7 B8 LEAB OEAB VCC RCO CCO OC QA QB QC QD ENT SLOAD
24 23 22 21 20 19 18 17 16 15 14 13 20 19 18 17 16 15 14 13 12 11
CEBA B1 B2 B3 B4 B5 B6 B7 B8 LEAB
RCO CCO OC QA QB QC QD ENT
LEBA OEAB U/D SLOAD

CLK
DA DB DC DD ENP ACLR SCLR
OEBA A1 A2 A3 A4 A5 A6 A7 A8 CEAB
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10
LEBA OEBA A1 A2 A3 A4 A5 A6 A7 A8 CEAB GND U/D CLK DA DB DC DD ENP ACLR SCLR GND
561 573
SYNCHRONOUS 4-BIT COUNTER OCTAL D-TYPE TRANSPARENT LATCHES
VCC RCO CCO G QA QB QC QD ENT SLOAD ENABLE

VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q C
20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11
RCO CCO G QA QB QC QD ENT
Q OE Q OE Q OE Q OE Q OE Q OE Q OE Q OE
ALOAD SLOAD
D G D G D G D G D G D G D G D G
CLK
DA DB DC DD ENP ACLR SCLR
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
ALOAD CLK DA DB DC DD ENP ACLR SCLR GND
OC 1D 2D 3D 4D 5D 6D 7D 8D GND
563 574
OCTAL D-TYPE TRANSPARENT LATCHES OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH INVERTED OUTPUTS
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK
ENABLE
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q C
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
OC C D CK D CK D CK D CK D CK D CK D CK D CK
1D 2D 3D 4D 5D 6D 7D 8D
4D
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10 OC 1D 2D 3D 4D 5D 6D 7D 8D GND
564 575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS OCTAL D-TYPES EDGE-TRIGGERED FLIP-FLOPS
VCC NC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLK NC
24 23 22 21 20 19 18 17 16 15 14 13
20 19 18 17 16 15 14 13 12 11
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CLK
SCLR
OC CLK
OC D0 D1 D2 D3 D4 D5 D6 D7
1D 2D 3D 4D 5D 6D 7D 8D
1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7 8 9 10
SCLR OC D0 D1 D2 D3 D4 D5 D6 D7 NC GND
90
Pin Assignments
576 592
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS 8-BIT BINARY COUNTER WITH INPUT REGISTER
VCC QA CLOAD RCK CCKEN CCK CCLR RCO

16 15 14 13 12 11 10 9
20 19 18 17 16 15 14 13 12 11
QA CLOAD CCKEN CCLR

RCK CCK
Q OE Q OE Q OE Q OE Q OE Q OE Q OE Q OE QB RCO
D CK D CK D CK D CK D CK D CK D CK D CK QC QD QE QF QG QH
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 9 10
QB QC QD QE QF QG QH GND
577 593
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS 8-BIT BINARY COUNTER WITH INPUT REGISTER
VCC NC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLK NC VCC G G RCKEN RCK CCKEN CCKEN CCK CCLR RCO
24 23 22 21 20 19 18 17 16 15 14 13 20 19 18 17 16 15 14 13 12 11
G G RCKEN CCKEN CCKEN CCLR

RCK CCK
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CLK
SCLR A/QA RCO
OC D0 D1 D2 D3 D4 D5 D6 D7
B/QB C/QC D/QD E/QE F/QF G/QG H/QH CLOAD
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10
SCLR OC D0 D1 D2 D3 D4 D5 D6 D7 NC GND A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH CLOAD GND
580 594
OCTAL D-TYPE TRANSPARENT LATCHES 8-BIT SHIFT REGISTER WITH OUTPUT LACH
WITH INVERTED OUTPUTS
ENABLE
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q C VCC QA SER RCLR RCK SCK SCLR QH'
20 19 18 17 16 15 14 13 12 11 16 15 14 13 12 11 10 9
QA SER RCLR SCK SCLR

RCK
QB QH'
D G D G D G D G D G D G D G D G
QC QD QE QF QG QH
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8
OC 1D 2D 3D 4D 5D 6D 7D 8D GND QB QC QD QE QF QG QH GND
590 595
8-BIT BINARY COUNTER WITH OUTPUT REGISTER
596
8-BIT SHIFT REGISTER WITH OUTPUT LATCH
VCC QA G RCK CCKEN CCK CCLR RCO
VCC QA SER G RCK SCK SCLR QH'
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
QA G CCKEN CCLR
RCK CCK
QA SER G SCK SCLR
QB RCO RCK
QB QH'
QC QD QE QF QG QH
QC QD QE QF QG QH
1 2 3 4 5 6 7 8
QB QC QD QE QF QG QH GND 1 2 3 4 5 6 7 8
QB QC QD QE QF QG QH GND
91
Pin Assignments
597 624
8-BIT SHIFT REGISTER WITH INPUT LATCH VOLTAGE-CONTROLLED OSCILLATOR
FREQ
~ CONT- Z
VCC A SER SLOAD RCK SCK SCLR QH' VCC ROL NC NC NC VCC OUTPUT
16 15 14 13 12 11 10 9 14 13 12 11 10 9 8
A SER SLOAD SCLR FREQ

RCK SCK Z
CONTROL
B QH'
C D E F G H RANGE Y
Cext EN
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7
B C D E F G H GND ~ RANGE CX1 CX2 ENABLE Y GND
GND OUTPUT
598 628
8-BIT SHIFT REGISTERS VOLTAGE-CONTROLLED OSCILLATOR
FREQ Rext
~ CONT- Z
VCC DS SER0 SER1 G RCK SCKEN SCK SCLR QH' VCC ROL NC VCC OUTPUT
20 19 18 17 16 15 14 13 12 11 14 13 12 11 10 9 8
DS SER0 SER1 G SCKEN SCK SCLR

RCK
FREQ Z
CONTROL
A/QA QH'
RANGE Y
Cext EN
B/QB C/QC D/QD E/QE F/QF G/QG H/QH SLOAD
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7
A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH SLOAD GND ~ RANGE CX1 CX2 ENABLE Y GND
GND OUTPUT
620 629
VOLTAGE-CONTROLLED OSCILLATOR
621
623
OCTAL BUS TRANSCEIVERS
2Cext 2Y
~ 2 2 OUT-
VCC VCC RANGE ENABLE PUT GND
VCC OEBA B1 B2 B3 B4 B5 B6 B7 B8 16 15 14 13 12 11 10 9
20 19 18 17 16 15 14 13 12 11 RNG Cext
FREQ Y
CONT EN
FREQ EN
CONT Y
RNG Cext
1 2 3 4 5 6 7 8
2 1 1 1 1Y ~
RANGE ENABLE OUT- GND
1Cext PUT
1 2 3 4 5 6 7 8 9 10 FREQ
CONTROL
OEAB A1 A2 A3 A4 A5 A6 A7 A8 GND
See page 380, 381, 382 See page 385
92
Pin Assignments
638 641
645
ENABLE ENABLE
VCC G B1 B2 B3 B4 B5 B6 B7 B8 VCC G B1 B2 B3 B4 B5 B6 B7 B8
20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
639 646
647
648
OCTAL BUS TRANSCEIVERS AND REGISTERS
ENABLE
VCC G B1 B2 B3 B4 B5 B6 B7 B8 CONT-
CLOCK SELECT ROL
VCC BA BA G B1 B2 B3 B4 B5 B6 B7 B8
20 19 18 17 16 15 14 13 12 11
24 23 22 21 20 19 18 17 16 15 14 13
CLOCK SELECT
BA
CONT-
ROL
B1 B2 B3 B4 B5 B6 B7
BA
G
CLOCK B8
AB
SELECT DIREC-
AB TION A1 A2 A3 A4 A5 A6 A7 A8
1 2 3 4 5 6 7 8 9 10
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 11 12
CLOCK SELECT DIREC- A1 A2 A3 A4 A5 A6 A7 A8 GND
AB AB TION
See page 387 See page 392, 394, 396
640 651
642 652
653
654
OCTAL BUS TRANSCEIVERS AND REGISTERS
ENABLE
VCC G B1 B2 B3 B4 B5 B6 B7 B8
20 19 18 17 16 15 14 13 12 11 VCC
CLOCK SELECT ENABLE
BA BA GBA B1 B2 B3 B4 B5 B6 B7 B8
24 23 22 21 20 19 18 17 16 15 14 13
CLOCK SELECT ENABLE B1 B2 B3 B4 B5 B6 B7

BA BA GBA
CLOCK B8
AB
SELECT ENABLE
AB GAB A1 A2 A3 A4 A5 A6 A7 A8
1 2 3 4 5 6 7 8 9 10
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10 11 12
CLOCK SELECT ENABLE A1 A2 A3 A4 A5 A6 A7 A8 GND
AB AB GAB
See page 388, 390 See page 398, 400, 402, 404
93
Pin Assignments
657 670
OCTAL BUS TRANSCEIVERS 4-BY-4 REGISTER FILE
WITH 8-BIT PARITY GENERATORS/CHECKERS
WRITE SELECT ENABLE OUTPUT

OE B1 B2 B3 B4 GND GND B5 B6 B7 B8 PARITY
DATA
VCC D1 WA WB WRITE READ Q1 Q2
24 23 22 21 20 19 18 17 16 15 14 13
16 15 14 13 12 11 10 9
B1 B2 B3 B4 B5 B6 B7 B8
D1 WA WB GW GR Q1
OE PARITY
T/R ERROR
D2 Q2
ODD
A1 A2 A3 A4 A5 A6 A7 A8 /EVEN
D3 D4 RB RA Q4 Q3
1 2 3 4 5 6 7 8 9 10 11 12
T/R A1 A2 A3 A4 A5 VCC A6 A7 A8 ODD ERROR 1 2 3 4 5 6 7 8
/EVEN D2 D3 D4 RB RA Q4 Q3 GND
DATA READ SELECT OUTPUTS
666 673
16-BIT SHIFT REGISTER
667
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
STORAGE REGISTER OUTPUT
VCC Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5
VCC OE2 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q PRE C 24 23 22 21 20 19 18 17 16 15 14 13

24 23 22 21 20 19 18 17 16 15 14 13
Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6
OE2 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q PRE CS Y5
STORE
SH STORE CK DATA
OERB C CK R/W CLR I/O Y0 Y1 Y2 Y3 Y4
OE1 1D 2D 3D 4D 5D 6D 7D 8D CLR
1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7 8 9 10 11 12 CHIP SHIFT READ/ STORE STORE DATA Y0 Y1 Y2 Y3 Y4 GND
SELECT CLOCK WRITE CLR CK I/O
OERB OE1 1D 2D 3D 4D 5D 6D 7D 8D CLR GND STRAGE REGISTER
OUTPUTS
669 674
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER 16-BIT SHFT REGISTER
OUTPUTS PARALLEL INPUTS

RIPPLE
CARRY ENABLE
VCC OUTPUT QA QB QC QD T LOAD VCC P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5
16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 15 14 13
RIPPLE QA QB QC QD ENABLE P15 P14 P13 P12 P11 P10 P9 P8 P7 P6

CARRY T
OUTPUT
UP/DOWN LOAD CS P5
CK ENABLE DATA
A B C D P CK
R/W MODE I/O P0 P1 P2 P3 P4
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12
U/D CK A B C D ENABLE GND CHIP CLOCK READ/ NC MODE DATA P0 P1 P2 P3 P4 GND
P SELECT WRITE CONTROL I/O
DATA INPUTS PARALLEL INPUTS
94
Pin Assignments
679 688
ADDRESS COMPARATOR 8-BIT IDENTITY COMPARATOR
VCC P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4
VCC G Y P3 P2 P1 P0 A12 A11 A10
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
P=Q Q7 P7 Q6 P6 Q5 P5 Q4
G Y P3 P2 P1 P0 A12 A11 A10
G P4
P0 Q0 P1 Q1 P2 Q2 P3 Q3
A1 A2 A3 A4 A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10
G P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND
A1 A2 A3 A4 A5 A6 A7 A8 A9 GND
682 697
684 699
8-BIT IDENTITY COMPARATOR SYNCHRONOUS UP/DOWN COUNTER
WITH OUTPUT REGISTER, MULTIPLEXED
THREE-STATE OUTPUT
VCC P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4 3-STATE OUTPUT

RIPPLE OUTPUT
CAPPY ENABLE CONTROL R/C
20 19 18 17 16 15 14 13 12 11 VCC OUTPUT QA QB QC QD T LOAD SELECT
20 19 18 17 16 15 14 13 12 11
P=Q Q7 P7 Q6 P6 Q5 P5 Q4
RCO QA QB QC QD ENABLE LOAD G

P>Q P4 T
U/D R/C
P0 Q0 P1 Q1 P2 Q2 P3 Q3
ENA
CCK A B C D P CCLR RCK
1 2 3 4 5 6 7 8 9 10
P>Q P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND
1 2 3 4 5 6 7 8 9 10
UP/ A B C D ENABLE ESIST- GND
DOWN P COUNT- ER
COUNTER ER CLOCK
CLOCK DATA INPUTS CLEAR
See page 422, 424 See page 430, 432
686 756
8-BIT IDENTITY COMPARATOR OCTAL BUFFER/LINE DRIVER/LINE RECEIVER
VCC G2 P=Q Q7 P7 NC Q6 P6 Q5 P5 Q4 P4 VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
24 23 22 21 20 19 18 17 16 15 14 13 20 19 18 17 16 15 14 13 12 11
G2 P=Q Q7 P7 Q6 P6 Q5 P5 Q4
P>Q P4
G1 P0 Q0 P1 Q1 P2 Q2 P3 Q3
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10
P>Q G1 P0 Q0 P1 Q1 NC P2 Q2 P3 Q3 GND 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
95
Pin Assignments
757 808
OCTAL BUFFER/LINE DRIVER/LINE RECEIVER HEX 2-INPUT AND DRIVERS
WITH OPEN-COLLECTOR OUTPUTS positive logic:
Y=A+B
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
VCC 6B 6A 6Y 5B 5A 5Y 4B 4A 4Y
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1A 1B 1Y 2A 2B 2Y 3A 3B 3Y GND
760 821
OCTAL BUFFER/LINE DRIVER/LINE RECEIVER 10-BIT BUS INTERFACE FLIP FLOPS
WITH OPEN-COLLECTOR OUTPUTS WITH 3-STATE OUTPUT
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q CLK
20 19 18 17 16 15 14 13 12 11 24 23 22 21 20 19 18 17 16 15 14 13
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q
OC CLK
1D 2D 3D 4D 5D 6D 7D 8D 9D 10D
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND OC 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND
804 823
HEX 2-INPUT NAND DRIVERS 9-BIT BUS INTERFACE FLIP-FLOP
positive logic: WITH 3-STATE OUTPUT
A=A•B
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLKEN CLK
20 19 18 17 16 15 14 13 12 11 24 23 22 21 20 19 18 17 16 15 14 13
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLKEN
OC CLK
1D 2D 3D 4D 5D 6D 7D 8D 9D CLR
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12
OC 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND
805 825
HEX 2-INPUT NOR DRIVERS 8-BIT BUS INTERFACE FLIP-FLOP
positive logic: WITH 3-STATE OUTPUT
Y=A+B
VCC OC3 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLKEN CLK
24 23 22 21 20 19 18 17 16 15 14 13
20 19 18 17 16 15 14 13 12 11
OC3 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLKEN
OC1 CLK
OC2 1D 2D 3D 4D 5D 6D 7D 8D CLR
1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7 8 9 10
OC1 OC2 1D 2D 3D 4D 5D 6D 7D 8D CLR GND
96
Pin Assignments
827 841
10-BIT BUFFER/BUS DRIVERS 10-BIT BUS INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q C
VCC Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 OE2
24 23 22 21 20 19 18 17 16 15 14 13
24 23 22 21 20 19 18 17 16 15 14 13
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q
OC C
1D 2D 3D 4D 5D 6D 7D 8D 9D 10D
1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7 8 9 10 11 12 OC 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND
OE1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND
828 843
10-BIT BUFFERS/BUS DRIVERS 9-BIT BUS INTERFACE D-TYPE LATCHES
VCC Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 OE2 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q PRE C
24 23 22 21 20 19 18 17 16 15 14 13 24 23 22 21 20 19 18 17 16 15 14 13
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q PRE
OC C
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
OE1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND OC 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND
832 853
HEX 2-INPUT OR DRIVERS 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
positive logic:
Y=A+B VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB LE
VCC 6B 6A 6Y 5B 5A 5Y 4B 4A 4Y 24 23 22 21 20 19 18 17 16 15 14 13
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10 11 12
OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND
1 2 3 4 5 6 7 8 9 10
833 857
10-BIT TO 9-BIT PARITY BUS TRANSCEIVERS HEX 2-TO-1 UNIVERSAL MULTIPLEXERS
VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB CLK VCC S1 6A 6B 6Y 5A 5B 5Y 4A 4B 4Y T/C
24 23 22 21 20 19 18 17 16 15 14 13 24 23 22 21 20 19 18 17 16 15 14 13
S1 6A 6B 6Y 5A 5B 5Y 4A 4B 4Y
S0 T/C
1A 1B 1Y 2A 2B 2Y 3A 3B 3Y OPER=0
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND S0 1A 1B 1Y 2A 2B 2Y 3A 3B 3Y OPER GND
ZERO
97
Pin Assignments
861 873
10-BIT TRANSCEIVERS DUAL 4-BIT D-TYPE LATCHES
ENABEL ENABEL
VCC B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 OEAB VCC 1C 1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4 2C 2CLR
24 23 22 21 20 19 18 17 16 15 14 13 24 23 22 21 20 19 18 17 16 15 14 13
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
C C
CLR CLR
OC OC
D1 D2 D3 D4 D1 D2 D3 D4
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
OEBA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND 1CLR 1OC 1D1 1D2 1D3 1D4 2D1 2D2 2D3 2D4 2OC GND
863 874
9-BIT BUS TRANSCEIVER DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
VCC B1 B2 B3 B4 B5 B6 B7 B8 B9 OEAB2 OEAB1 VCC 1CLK 1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4 2CLK 2CLR
24 23 22 21 20 19 18 17 16 15 14 13 24 23 22 21 20 19 18 17 16 15 14 13
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLK CLK
CLR CLR
OC OC
D1 D2 D3 D4 D1 D2 D3 D4
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
OEBA1 A1 A2 A3 A4 A5 A6 A7 A8 A9 OEBA2 GND 1CLR 1OC 1D1 1D2 1D3 1D4 2D1 2D2 2D3 2D4 2OC GND

867 876
DUAL 4-BIT D-TYPE FLIP-FLOPS
869
8-BIT SYNCHRONOUS BIDIRECTIONAL COUNTER
ENABEL
VCC P QA QB QC QD QE QF QG QH CLK RCO VCC 1CLK 1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4 2CLK 2PRE
24 23 22 21 20 19 18 17 16 15 14 13 24 23 22 21 20 19 18 17 16 15 14 13
EN QA QB QC QD QE QF QG QH Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
P CLK CLK CLK
S0 RCO PRE PRE
EN OC OC
S1 A B C D E F G H T D1 D2 D3 D4 D1 D2 D3 D4
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
S0 S1 A B C D E F G H ENABEL GND 1PRE 1OC 1D1 1D2 1D3 1D4 2D1 2D2 2D3 2D4 2OC GND
T
870 885
DUAL 16-BY 4-BIT REGISTER FILES 8-BIT MAGNITUDE COMPARATOR
P<QOUT
VCC CLK SERIN B1 B2 B3 B4 B5 B6 B7 B8 Q8 VCC PLE P7 P6 P5 P4 P3 P2 P1 P0 P>QOUT
24 23 22 21 20 19 18 17 16 15 14 13 24 23 22 21 20 19 18 17 16 15 14 13
SERIN DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 PLE P7 P6 P5 P4 P3 P2 P1 P0 P<QOUT
CLK
S0 Q8 L/A P>QOUT
S1 S2 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 P<QIN P>QIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
S0 S1 S2 A1 A2 A3 A4 A5 A6 A7 A8 GND L/A P<Q P>Q Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GND
IN IN
98
Pin Assignments
990 1000
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES QUAD 2-INPUT NAND BUFFERS/DRIVERS
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q C VCC 4B 4A 4Y 3B 3A 3Y
20 19 18 17 16 15 14 13 12 11 14 13 12 11 10 9 8
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
OERB C
1D 2D 3D 4D 5D 6D 7D 8D
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7
OERB 1D 2D 3D 4D 5D 6D 7D 8D GND 1A 1B 1Y 2A 2B 2Y GND
992 1004
9-BIT D-TYPE TRANSPARENT HEX INVERTING DRIVERS
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q OEQ C VCC 6A 6Y 5A 5Y 4A 4Y
24 23 22 21 20 19 18 17 16 15 14 13 14 13 12 11 10 9 8
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q OEQ
OERB C
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7
OERB 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND
994 1005
10-BIT D-TYPE TRANSPARENT READ-BACK LATCHES HEX INVERTING BUFFER GATES
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q C VCC 6A 6Y 5A 5Y 4A 4Y
24 23 22 21 20 19 18 17 16 15 14 13 14 13 12 11 10 9 8
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q
OERB C
1D 2D 3D 4D 5D 6D 7D 8D 9D 10D
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7
OERB 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND
996 1008
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES QUADRUPLE 2-INPUT POSITIVE-AND BUFFERS/DRIVERS
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OE T/C CLR VCC 4B 4A 4Y 3B 3A 3Y
24 23 22 21 20 19 18 17 16 15 14 13 14 13 12 11 10 9 8
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7
1D 2D 3D 4D 5D 6D 7D 8D EN RD CLK GND
99
Pin Assignments
1032 1244
QUAD 2-INPUT OR BUFFERS/DRIVERS OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
positive logic:
Y = A+B
VCC 4B 4A 4Y 3B 3A 3Y VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
14 13 12 11 10 9 8 20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1034 1245
HEX DRIVERS OCTAL BUS TRANSCEIVERS
ENABLE
VCC 6A 6Y 5A 5Y 4A 4Y
20 19 18 17 16 15 14 13 12 11
14 13 12 11 10 9 8
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
1035 1640
HEX BUFFERS OCTAL BUS TRANSCEIVERS
ENABLE
VCC 6A 6Y 5A 5Y 4A 4Y
20 19 18 17 16 15 14 13 12 11
14 13 12 11 10 9 8
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
1240 1645
OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS OCTAL BUS TRANSCEIVERS
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 ENABLE
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10
100
Pin Assignments
2240 2373
OCTAL BUFFERS AND LINE DRIVERS/MOS DRIVERS 25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS WITH 3-STATE OUTPUTS
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1

VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10
OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
2241 2414
OCTAL BUFFERS AND LINE DRIVERS/MOS DRIVERS MEMORY DECODER WITH ON-CHIP VCC MONITOR
VCC Vbat 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
Vbat 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2
VS 2Y3
SD 1A 2A 1B 2B 1G 2G G
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10
VS SD 1A 2A 1B 2B 1G 2G G GND
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
2244 2541
OCTAL BUFFERS AND LINE DRIVERS/MOS DRIVERS NON-INVERTED 3-STATE OUTPUTS
WITH 3-STATE OUTPUTS OCTAL LINE DRIVERS/MOS DRIVERS
VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
VCC G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10
G1 A1 A2 A3 A4 A5 A6 A7 A8 GND
2245 2827 3-STATE OUTPUTS

OCTAL TRANSCEIVER AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS 2828 3-STATE INVERTING OUTPUTS
BUS/MOS MEMORY DRIVERS
OUTPUTS
ENABLE
VCC Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 OE2
20 19 18 17 16 15 14 13 12 11
24 23 22 21 20 19 18 17 16 15 14 13
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10
OE1 OE2
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10 11 12
OE1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND
101
Pin Assignments
2952 4015
OCTAL BUS TRANSCEIVERS AND REGISTERS DUAL 4-STAGE STATIC SHIFT REGISTER
VCC A8 A7 A6 A5 A4 A3 A2 A1 OEBA CLKBA BA

VCC 2D 2MR 2Q0 2Q1 2Q2 1Q3 1CP
24 23 22 21 20 19 18 17 16 15 14 13
16 15 14 13 12 11 10 9
A8 A7 A6 A5 A4 A3 A2 A1 OEBA CLKBA
B8 CEBA
CLKAB
B7 B6 B5 B4 B3 B2 B1 OEBA CEBA
1 2 3 4 5 6 7 8 9 10 11 12
B8 B7 B6 B5 B4 B3 B2 B1 OEAB CLKAB CEBA GND 1 2 3 4 5 6 7 8
2CP 2Q3 1Q2 1Q1 1Q0 1MR 1D GND
OUTPUTS
2953 4016
OCTAL BUS TRANSCEIVERS AND REGISTERS QUAD BILATERAL SWITCH
VCC A8 A7 A6 A5 A4 A3 A2 A1 OEBA CLKBA CEBA VCC 1E 4E 4Y 4Z 3Z 3Y

24 23 22 21 20 19 18 17 16 15 14 13
14 13 12 11 10 9 8
A8 A7 A6 A5 A4 A3 A2 A1 OEBA CLKBA
B8 CEBA
CLKAB
B7 B6 B5 B4 B3 B2 B1 OEAB CEAB
1 2 3 4 5 6 7 8 9 10 11 12
B8 B7 B6 B5 B4 B3 B2 B1 OEAB CLKAB CEAB GND
1 2 3 4 5 6 7
1Y 1Z 2Z 2Y 2E 3E GND
OUTPUTS
3245 4017
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT DECADE COUNTERS/DIVIDERS
VOLTAGE AND 3-STATE OUTPUTS OUTPUTS
VCCB NC OE B1 B2 B3 B4 B5 B6 B7 B8 GND VCC CLR CLK CLKEN CO Y9 Y4 Y8
24 23 22 21 20 19 18 17 16 15 14 13 16 15 14 13 12 11 10 9
CLR CLK CO Y9 Y4
Y5 Y8
Y1 Y0 Y2 Y6 Y7 Y3
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8
VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND Y5 Y1 Y0 Y2 Y6 Y7 Y3 GND
NC – No internal connection OUTPUTS

4002 4020
DUAL 4-INPUT POSITIVE-NOR GATES 14-STAGE BINARY COUNTERS
positive logic: OUTPUTS
Y=A+B+C+D OUTPUT
VCC QK QJ QH QI CLR CLK QA
VCC 2Y 2D 2C 2B 2A NC 16 15 14 13 12 11 10 9
14 13 12 11 10 9 8
QK QJ QH QI CLR CLK
QL QA
QM QN QF QE QG QD
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 QL QM QN QF QE QG QD GND
1Y 1A 1B 1C 1D NC GND
OUTPUTS
102
Pin Assignments
4024 4050
7-STAGE BINARY COUNTERS HEX INVERTING BUFFERS NON-INVERTING
OUTPUTS
OUTPUT
VCC NC QA QB NC QC NC
NC 6Y 6A NC 5Y 5A 4Y 4A
14 13 12 11 10 9 8
16 15 14 13 12 11 10 9
QA QB QC
CLK
CLR QG QF QE QD
1 2 3 4 5 6 7
CLK CLR QG QF QE QD GND
1 2 3 4 5 6 7 8
VCC 1Y 1A 2Y 2A 3Y 3A GND
OUTPUTS

4040 4051
12-STAGE BINARY COUNTERS 8-CHANNEL ANALOG
OUTPUTS
MULTIPLEXERS/DEMULTIPLEXERS
OUTPUT
VCC QK QJ QH QI CLR CLK QA
VCC Y2 Y1 Y0 Y3 A B C
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
QK QJ QH QI CLR CLK
QL QA
QF QE QG QD QC QB
1 2 3 4 5 6 7 8
QL QF QE QG QD QC QB GND 1 2 3 4 5 6 7 8
Y4 Y6 COM Y7 Y5 INH GND GND
OUTPUTS
4046 4052
PHASE-LOCKED-LOOP WITH VCO DUAL 4-CHANNEL ANALOG
VCC PC3OUT SIGIN PC2OUT R2 R1 DEMOUT VCOIN

VCC 1Y2 1Y1 1-COM 1Y0 1Y3 A B
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND
1 2 3 4 5 6 7 8
2Y0 2Y2 2-COM 2Y3 2Y1 INH GND GND
4049 4053
HEX INVERTING BUFFERS TRIPLE 2-CHANNEL ANALOG
NC 6Y 6A NC 5Y 5A 4Y 4A
VCC 2-COM 1-COM 1Y1 1Y0 A B C
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VCC 1Y 1A 2Y 2A 3Y 3A GND
2Y1 2Y0 3Y1 3-COM 3Y0 INH GND GND
103
Pin Assignments
4059 4075
CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER TRIPLE 3-INPUT OR GATES
positive logic:
Y=A+B+C
VCC Q J5 J6 J7 J8 J9 J10 J11 J12 Ka Kb
VCC 3C 3B 3A 3Y 2Y 2C
24 23 22 21 20 19 18 17 16 15 14 13
14 13 12 11 10 9 8
1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7
CP LE J1 J2 J3 J4 J16 J15 J14 J13 Kc GND
4060 4094
ASYNCHRONOUS 14-STAGE BINARY COUNTERS 8-STAGE SHIFT AND STORE BUS REGISTER,
AND OSCILLATORS THREE-STATE
OUTPUTS
VCC QJ QH QI CLR CKI CKO CKO

VCC OE Q4 Q5 Q6 Q7 QS2 QS1
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
QJ QH QI CLR CKI CKO
QL CKO
QM QN QF QE QG QD
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
QL QM QN QF QE QG QD GND STROBE DATA CP Q0 Q1 Q2 Q3 GND
OUTPUTS
4066 4245
QUADRUPLE BILATERAL SWITCHES OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
(3.3V) (3.3V)
VCCB VCCB OE B1 B2 B3 B4 B5 B6 B7 B8 GND
VCC 1C 4C 4A 4B 3B 3A
24 23 22 21 20 19 18 17 16 15 14 13
14 13 12 11 10 9 8
1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7
(5V) DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND
1A 1B 2B 2A 2C 3C GND VCCA
4067 4316
16-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER QUAD ANALOG SWITCH WITH LEVEL TRANSLATION
VCC I8 I9 I10 I11 I12 I13 I14 I15 E S2 S3

VCC 1S 4S 4Z 4Y 3Y 3Z VEE
24 23 22 21 20 19 18 17 16 15 14 13
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7 8
COMMOMN I7 I6 I5 I4 I3 I2 I1 I0 S2 S1 GND
INPUT/ 1Z 1Y 2Y 2Z 2S 3S E GND
OUTPUT
104
Pin Assignments
4351 4514
ANALOG MULTIPLEXERS/DEMULTIPLEXERS 4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS
WITH LATCH WITH LATCHES
VCC A2 A1 A0 A3 S0 NC S1 S2 LE
20 19 18 17 16 15 14 13 12 11
INPUTS DATA INPUTS
VCC G D C Y10 Y11 Y8 Y9 Y14 Y15 Y12 Y13
24 23 22 21 20 19 18 17 16 15 14 13
G D C Y10 Y11 Y8 Y9 Y14 Y15 Y12
LE Y13
1 2 3 4 5 6 7 8 9 10
A4 A6 NC A A7 A5 E1 E2 VEE GND A B Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
COMMON
See page 520 1 2 3 4 5 6 7 8 9 10 11 12
LE A B Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 GND
4352 INPUTS DATA INPUTS

ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LATCH
A
VCC A2 A1 COMMON A0 A3 NC S0 S1 LE See page 524
20 19 18 17 16 15 14 13 12 11
4515
4-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS
WITH LATCHES
INPUTS DATA INPUTS
1 2 3 4 5 6 7 8 9 10 VCC G D C Y10 Y11 Y8 Y9 Y14 Y15 Y12 Y13

B0 B2 NC B B3 B1 E1 E2 VEE GND
COMMON 24 23 22 21 20 19 18 17 16 15 14 13
See page 521
G D C Y10 Y11 Y8 Y9 Y14 Y15 Y12
4374 LE Y13
OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP A B Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

WITH 3-STAE OUTPUTS
1D 2D 3D 4D VCC 5D 6D 7D 8D CLK 1 2 3 4 5 6 7 8 9 10 11 12
LE A B Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 GND
20 19 18 17 16 15 14 13 12 11
INPUTS DATA INPUTS
See page 526
4518
1 2 3 4 5 6 7 8 9 10 DUAL SYNCHRONOUS COUNTERS
1Q 2Q 3Q 4Q GND 5Q 6Q 7Q 8Q OE
See page 522
4511
VCC 2MR 2Q3 2Q2 2Q1 2Q0 2E 2CP
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS
7-SEGMENT OUTPUTS
16 15 14 13 12 11 10 9
VCC f g a b c d e
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
1CP 1E 1Q0 1Q1 1Q2 1Q3 1MR GND
1 2 3 4 5 6 7 8
D1 D2 LT Bt LE D3 D0 GND
BCD INPUTS BCD INPUTS
105
Pin Assignments
4520 5400
DUAL SYNCHRONOUS COUNTERS 11-BIT LINE/MEMORY DRIVERS
D1 D2 D3 D4 D5 D6 VCC VCC D7 D8 D9 D10 D11 OE2
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC 2MR 2Q3 2Q2 2Q1 2Q0 2E 2CP
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Y1 Y2 Y3 Y4 Y5 Y6 GND GND Y7 Y8 Y9 Y10 Y11 OE1
1 2 3 4 5 6 7 8 See page 534

1CP 1E 1Q0 1Q1 1Q2 1Q3 1MR GND
5401
11-BIT LINE/MEMORY DRIVERS
See page 529

D1 D2 D3 D4 D5 D6 VCC VCC D7 D8 D9 D10 D11 OE2
28 27 26 25 24 23 22 21 20 19 18 17 16 15
4538
DUAL RETRIGGERABLE
PRECISION MONO STABLE MULTIVIBRATOR
VCC 2CX 2RXCX 1R 1A 1B 1Q 1Q

1 2 3 4 5 6 7 8 9 10 11 12 13 14
Y1 Y2 Y3 Y4 Y5 Y6 GND GND Y7 Y8 Y9 Y10 Y11 OE1
16 15 14 13 12 11 10 9
See page 534
5402
1 2 3 4 5 6 7 8
D1 D2 D3 D4 D5 D6 D7 VCC D8 D9 D10 D11 D12 OE2
1CX 1RXCX 1R 1A 1B 1Q 1Q GND
28 27 26 25 24 23 22 21 20 19 18 17 16 15
See page 530
4543 1 2 3 4 5 6 7 8 9 10 11 12 13 14
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS Y1 Y2 Y3 Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 OE1
See page 535
VCC f g
7-SEGMENT OUTPUTS
e d c b a
5403
16 15 14 13 12 11 10 9 WITH 3-STATE OUTPUTS
D1 D2 D3 D4 D5 D6 D7 VCC D8 D9 D10 D11 D12 OE2
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1 2 3 4 5 6 7 8
DL D2 D1 D3 D0 PH B1 GND
BCD INPUTS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Y1 Y2 Y3 Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 OE1
106
Pin Assignments
7001 7046
QUADRUPLE POSITIVE-AND GATES PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR
WITH SCHMITT-TRIGGER INPUTS
positive logic:
Y=A•B
VCC GLD SIGIN PC2OUT R2 R1 DEMOUT VCOIN
16 15 14 13 12 11 10 9
14 13 12 11 10 9 8
1 2 3 4 5 6 7 8
LD PC1OUT COMPIN VCOOUT INH C1A C1B GND
1 2 3 4 5 6 7
7002 7266
QUADRUPLE POSITIVE-NOR GATES QUAD 2-INPUT EXCLUSIVE-NOR GATES
WITH SCHMITT-TRIGGER INPUTS positive logic:
positive logic: Y=A⊕B
Y=A+B
14 13 12 11 10 9 8
VCC 4B 4A 4Y 3Y 3B 3A
14 13 12 11 10 9 8
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1A 1B 1Y 2Y 2A 2B GND
7032 8003
QUADRUPLE POSITIVE-OR GATES DUAL 2-INPUT POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
positive logic:
Y=A+B
VCC 2B 2A 2Y
8 7 6 5
14 13 12 11 10 9 8
1 2 3 4
1 2 3 4 5 6 7
1A 1B 1Y GND
107

TI Logic Pocket Book (R)

Încărcat de

Informații document

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

TI Logic Pocket Book (R)

Încărcat de

Drepturi de autor:

Formate disponibile

Pin Assignments

See page 139 See page 143

See page 140 See page 144

See page 141 See page 144

See page 142 See page 145

See page 145 See page 149

See page 146 See page 150

See page 147 See page 151

See page 148 See page 151

See page 152 See page 155

NC – No internal connection NC – No internal connection

See page 157

QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS

See page 160

See page 158

See page 159 See page 162

See page 167

See page 164

MAKE NO EXTERNAL CONNECTION

VCC 2CLR 2D 2CK 2PR 2Q 2Q

D C CLEAR UNITY/ ENA- STROBE

See page 174 See page 178

14 13 12 11 10 9 8 VCC 1CLR 1CK 2K 2CLR 2CK 2J

VCC 1CLR 2CLR 2CK 2K 2J 2PR 2Q 16 15 14 13 12 11 10 9

See page 188 See page 192

See page 192 See page 196

See page 193 See page 198

SELECT ENABLE OUTPUT OUTPUTS

INPUTS DATA INPUTS DATA SELECT

INPUTS OUTPUTS DATA INPUTS OUTPUTS

See page 202 See page 208

2C3 2C2 2C1 2C0 2Y

See page 204 See page 210

DATA INPUTS DATA SELECT INPUTS OUTPUTS

E8 E9 E10 E11 E12 E13 E14 E15 A B A B C D G2 G1 15 14 13 12

See page 206 See page 212

2Y3 2Y2 2Y1 2Y0 RIPPLE QA QB QC QD ENABLE

See page 214, 216 See page 224, 226

INPUTS OUTPUTS INPUTS OUTPUTS OUTPUTS

VCC STROBE 4A 4B 4Y 3A 3B 3Y VCC QH QG QF QE CLEAR CLOCK

INPUTS OUTPUTS INPUTS OUTPUTS SERIAL INPUTS OUTPUTS

See page 218, 220 See page 228

INPUTS OUTPUTS PARALLEL INPUTS

CLOCK SERIAL OUTPUT

See page 222 See page 230

OUTPUT CONTROL OUTPUTS

4-BIT UP/DOWN SYNCHRONOUS BINARY COUNTERS CLEAR CLEAR CLEAR

CLEAR CLEAR CLEAR

See page 234 CK D D CK

See page 241

WRITE SELECT ENABLE OUTPUTS

VCC A1 B1 A2 B2 A3 B3 G Cn+4 P A=B F3

DATA READ SELECT OUTPUTS 1 2 3 4 5 6 7 8 9 10 11 12

See page 236 See page 242

INPUTS OUTPUTS INPUTS

DATA BO- DATA DATA

P2 G2 Cn Cn+x Cn+y G A CLEAR BO- CARRY LOAD C

See page 244 See page 252

INPUTS OUTPUTS INPUTS

OUTPUTS INPUTS OUTPUTS

See page 246, 248 See page 254

SERIAL INPUTS PARALLEL INPUTS

See page 250 See page 256