IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO.
5, MAY 2016
A 2.4-GHz CMOS Class-E Synchronous Rectifier
Soroush Dehghani, Graduate Student Member, IEEE, and Thomas Johnson, Member, IEEE
Abstract— A class-E synchronous rectifier has been designed
and implemented using 0.13-μm CMOS technology. A design
methodology based on the theory of time-reversal duality has
been used where a class-E amplifier circuit is transformed
into a class-E rectifier circuit. The methodology is distinctly
different from other CMOS RF rectifier designs which use voltage
multiplier techniques. Power losses in the rectifier are analyzed
including saturation resistance in the switch, inductor losses, and
current/voltage overlap losses. The rectifier circuit includes a
50- single-ended RF input port with on-chip matching. The
circuit is self-biased and completely powered from the RF input
signal. Experimental results for the rectifier show a peak RF-to-dc
conversion efficiency of 30% measured at a frequency of 2.4 GHz.
Index Terms— Class-E amplifier, class-E rectifier, RF energy
harvesting, wireless power.
I. I NTRODUCTION
T HERE is great interest in developing fully integrated
wireless sensors that do not require battery power. Self-
powered sensors have many potential applications including
embedded sensors in infrastructure, biomedical implants, and
wearable sensors. One method for powering these sensors is to
use wireless power transmission methods [1]–[3] that rectify
either ambient or directed RF power. Most ultra-low power
radios in wireless sensors are fabricated in CMOS technology.
Therefore, a fully integrated design, which includes a CMOS
wireless power subsystem, motivates research in the design of
CMOS RF rectifier circuits.
Published work on the design of RF-to-dc rectifiers can be
broadly classified into integrated designs [CMOS and mono-
lithic microwave integrated circuits (MMICs)] and discrete
designs implemented with diodes or transistors. There are
different metrics that can be used to compare designs including
frequency, efficiency, dynamic range, area, matching, and cir-
cuit topology. Using these metrics, a summary of recent work
is shown in Table I. The comparison table is complemented
by Fig. 1, which shows the dynamic range versus power
efficiency for each design listed in the table.
CMOS rectifier designs in Table I span a frequency range
of 950 MHz to 5.8 GHz and designs [4]–[10] use voltage
multiplier circuits to rectify low-power RF input signals.
When comparing these designs, it is important to distinguish
the conditions under which power efficiency is reported.
In [6]–[8], [10], the designs include input matching circuits
Manuscript received December 7, 2015; revised February 12, 2016; accepted
March 20, 2016. Date of publication April 14, 2016; date of current version
May 10, 2016.
The authors are with the School of Engineering, University of British
Columbia, Kelowna, BC, Canada V1V 1V7 (e-mail: soroushd@ece.ubc.ca).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2016.2547393
0018-9480 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1655
with a single-ended RF input source and RF to dc power
efficiency ranges from 8.8% to 15.9%. In other work, [4], [5]
and [9], the power efficiency that is reported ranges from
29% to 67.5%, but these measurements have been
de-embedded to exclude input mismatch loss. Consequently,
higher power efficiency is reported in work that removes input
mismatch loss compared to other designs that report power
efficiency including on-chip and/or off-chip input matching
networks. Input mismatch loss can be quite significant if
the input impedance deviates significantly from the antenna
impedance.
Another important distinction between different designs is
whether the circuit requires a differential input signal. In a
differential design, if a single-ended antenna port is connected
to the rectifier, an input balun is required and losses associated
with the balun reduce the overall power efficiency of the
rectifier.
Frequency is also another variable that affects the reported
power efficiencies in Table I. Higher power efficiency is
reported for lower frequencies; for example, in [5, Fig. 7],
power efficiency was measured at frequencies of 100 MHz,
500 MHz, 953 MHz, and 2 GHz. The corresponding power
efficiencies measured for a differential input source and after
removing input mismatch loss are 82%, 73%, 67%, and 57%.
In other work [6]–[8] that includes mismatch loss and a single-
ended RF input, the power efficiency at 2.4 GHz ranges from
8.8% to 15.9%. In this work, we have obtained a power
efficiency of 30% at 2.4 GHz for a single-ended RF input
including on-chip matching.
For comparison with CMOS rectifier designs, Table I also
shows recent work in the implementation of RF to dc rectifiers
using MMICs [11] and discrete devices. Discrete RF rec-
tifier designs include diode circuits [12]–[17] and transistor
switching circuits [18]–[20]. The typical power efficiency of
discrete rectifier designs is higher than CMOS and ranges
from 51% to 83%. However, despite the high performance
of discrete designs, they are not easily integrated into ultra-
low-power CMOS wireless radio hardware.
In this paper we report on the design of a class-E switching
RF rectifier implemented in CMOS that is a distinctly different
from other CMOS designs that use voltage multiplier tech-
niques. There are several reasons to consider switching circuits
instead of voltage multiplier circuits. First, as demonstrated
by the discrete designs shown in Table I, very good power
efficiency has been obtained with transistor switching circuits.
Second, because the circuit is derived from the time-reversed
dual of a switch-mode power amplifier [21], the design
methodology includes input matching, which is fundamental
to the design of the amplifier circuit. Input matching required
1656 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 5, MAY 2016

TABLE I
P ERFORMANCE C OMPARISON OF R ECENTLY R EPORTED RF R ECTIFIER C IRCUITS

for voltage multiplier circuits can be more difficult and is
not inherently part of the design methodology; rather, the
voltage multiplier circuit is designed first, then the implications
of matching are considered. Third, rectifier duals derived
from switching amplifiers operate the device in the third
quadrant where drain voltage and current are reversed when
the switch is on. The diode-like behavior in the third quadrant
is dependent on the gate voltage and offers another degree of
freedom relative to diode connected MOS devices in voltage
multiplier circuits where the drain and gate are tied together.
Finally, CMOS circuits can have advantages in terms of gate
biasing. In most of the discrete rectifier designs with GaAs or
GaN devices, a separate gate bias supply is required and the
gate bias circuit is not included in the design. In the CMOS
rectifier design described here, zero gate biasing is used and no
separate gate supply is required. Therefore, the CMOS class-E
rectifier design is completely self-powered from the RF input.
In the following sections, the design and experimental test
results for a CMOS RF class-E synchronous rectifier are
described. We begin with a brief summary of the design
methodology to transform a class-E amplifier into a class-E
rectifier using the theory of time-reversal duality [21]. Since
the amplifier design serves as a prototype for the rectifier
circuit, the amplifier design is evaluated carefully with respect
to power-efficiency losses. A study of the incremental effect of
different losses versus power efficiency is presented and this
highlights factors that reduce power efficiency in the circuit.
A CMOS class-E amplifier is designed and transformed into a
synchronous class-E rectifier circuit by adding feedback from
the RF input to the gate. In Section V, simulation and exper-
imental test results are shown for the CMOS class-E rectifier.
II. C LASS -E S YNCHRONOUS R ECTIFIER
C IRCUIT T OPOLOGY
The circuit topology for the RF class-E rectifier is obtained
from the theory of time-reversal duality. As shown in [21],
time-reversal duality can be used to transform an amplifier
into a rectifier. The theory was first applied to circuits in power
electronics where an inverter (amplifier) was transformed into
a synchronous rectifier. The class-E amplifier and class-E
rectifier circuits used in this work are shown in Figs. 2 and 6,
respectively.
When the theory of time-reversal duality is used, it is
important to consider the assumptions and implications of
the transformation. First, the theory is based on lossless
switching. At low frequencies this is a good assumption;
however, at high frequencies this becomes less accurate and in
the case of RF CMOS circuits, the losses can be substantial.
DEHGHANI AND JOHNSON: 2.4-GHz CMOS CLASS-E SYNCHRONOUS RECTIFIER
Fig. 1. Performance comparison of recently reported RF rectifier circuits. (a) Discrete rectifier circuits. (b) Integrated rectifier circuits.
Fig. 2. Class-E amplifier circuit.
Despite the assumption of lossless switching, the theory pro-
vides an excellent starting point to investigate an appropriate
circuit topology that is suitable for rectification. Second, time-
reversal duality has implications in terms of the operating
region of the switch [22], [23]. In a switch-mode amplifier
like class E, current flows into the drain of the device and
the device operates in quadrant I. However, in the rectifier
1657
configuration, current flow is reversed and current flows out
of the drain, which means the device operates in quadrant III.
Third, the theory assumes the output match of the amplifier
under large-signal conditions is perfect and that the load
waveform is perfectly sinusoidal. The class-E amplifier output
circuit has finite Q and deviations from a perfectly real output
impedance mean that there are differences when the circuit is
reconfigured as a rectifier. Fourth, the gate drive is assumed
to be sufficiently large to switch the device. In RF rectifier
applications this means that the class-E rectifier conditions
are satisfied at peak power, but as the power is reduced,
the assumption becomes less valid and the operating mode
of the rectifier changes from a switch to a transconductor.
This ultimately constrains the dynamic range over which the
RF rectifier can be used. The implication of these points is
that a practical RF class-E synchronous rectifier needs some
adjustment from ideal theory.
1658 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 5, MAY 2016

III. A NALYSIS OF A C LASS -E A MPLIFIER W ITH L OSSES
Since the class-E synchronous rectifier is based on the
transformation of a class-E amplifier, the design methodol-
ogy begins with the amplifier. The theory of ideal class-E
amplifiers is well known [24], [25], and in the ideal analysis,
losses are assumed to be negligible. On the other hand, when
losses are not negligible, the values of circuit elements needs
to be modified to optimize power efficiency. In the following
sections, the implication of losses in the class-E amplifier and
the class-E rectifier are described.
A. Current and Voltage Equations for Class-E Amplifiers
A class-E amplifier circuit is shown in Fig. 2. In the circuit,
a switch M1 is shunted by a capacitance C. The switch closes
with a frequency of f sw , also called the fundamental switching
frequency. The switch and capacitor are combined into a
subnetwork indicated by the dashed box. At the output node
labeled A there are three currents that must satisfy Kirchoff’s
current law
i A = IDC − i L . (1)
ideal class-E design need to be modified to maximize power
efficiency in the presence of loss. As a first step, equations
for the ideal class-E amplifier with no loss are summarized.
These equations are then used to study losses.
All signals in the class-E circuit are assumed to be peri-
odic and in the steady state. Since the signals are periodic,
it is convenient to work with the instantaneous phase of
signals rather than time. The instantaneous phase is defined
as θ = ωsw = 2π fsw t. It is assumed the gate-drive signal has
a 50% duty cycle, and over a 2π interval, the switch is on
from 0 to π and off from π to 2π.
The output load current i L is sinusoidal and defined as
i L (θ ) = −Iom sin(θ − ϕ), for θ ∈ [0, 2π] (4)
where Iom is the peak amplitude of the load current. The
load current has an initial phase ϕ determined by imposing
a zero voltage switching condition on the capacitor voltage
waveform. The dc supply current is IDC , and the current into
the switch subnetwork is
i A (θ ) = IDC + Iom sin(θ − ϕ), for θ ∈ [0, 2π]. (5)

We now consider the different frequency components that Equation (5) can also provide an expression for the dc current
make up the currents at node A. A dc current, IDC , is the by noting that the current i A is zero at θ = 0. Evaluating this
power supply current for the amplifier and the dc current condition shows
passes through inductor L D D . The inductor is sufficiently IDC = Iom sin(ϕ). (6)
large and has high impedance at the fundamental frequency This equation also shows that the peak load current Iom can
switching frequency, f sw , and at all harmonics of the switching
be expressed as IDC csc(ϕ).
frequency. The series resonator (L S and C S ) has sufficiently
When the switch is on for the interval [0, π], the voltage is
high Q at f sw to ensure the load current, i L , is sinusoidal. ideally zero, and all the current i A flows through the switch.
Therefore, a harmonic-balance analysis of currents at node A
Using (5) and (6), the switch current is
shows that the current i A , which flows into the switch subnet-  
work, has only two frequency components: a dc component i sw (θ ) = IDC 1 + cot(ϕ) sin(θ ) − cos(θ ) (7)
and a sinusoidal frequency component at fsw .
for θ ∈ [0, π].
Inside the switch subnetwork, the current i A is split between
The voltage across the switch is found using (3). When
the switch current (i sw ) and the capacitor current (i C ).
the switch is open during the interval [π, 2π], the capacitor
Therefore,
current i C is equal to i A , and the corresponding voltage is
i A = i sw + i C . (2)
 θ
1
The switch state is controlled by the input gate signal VS . v A (θ ) = i A (θ ) dθ
When the switch is on, current i A flows through the switch, and 2π f sw C π
Iom
when the switch is off, current i A flows through the capacitor. = [(θ − π) sin ϕ − cos(θ − ϕ) − cos ϕ] (8)
The voltage waveform at node A, v A , is directly linked to 2π f sw C
the shape of the capacitor current waveform, i C . The relation for θ ∈ [π, 2π]. An ideal class-E amplifier has zero voltage
is given by  t switching, which requires v A (π) = v A (2π) = 0. The zero
1 voltage switching is satisfied providing
v A (t) = i C (t) dt. (3)
C 0  
2
Since the capacitor current has harmonic frequency compo- ϕ = arctan = 32.482°. (9)
π
nents, the voltage waveform at node A also has harmonic
frequency components. At this point, it is important to note The dc supply voltage for the amplifier is found by calcu-
that no assumptions have been made about switching time. lating the average value of the switch voltage waveform v A
Equations (1)–(3) are valid for both instantaneous switching over a 2π interval. Noting that the voltage is zero when the
as well as for finite switching times. switch is closed over the interval (0, π), and using (8) for v C
over the open switch interval,
 2π
B. Ideal Class-E Amplifier Equations 1 IDC
VD D = v A (θ )dθ = . (10)
In a CMOS design, losses are significant. Our goal is 2π π πωsw C
to investigate how different loss mechanisms impact power The last expressions required to design an ideal class-E
efficiency, as well as determine how component values for an amplifier are values for the phase-shift inductor L M and
DEHGHANI AND JOHNSON: 2.4-GHz CMOS CLASS-E SYNCHRONOUS RECTIFIER 1659

Fig. 3. Waveforms for the class-E amplifier circuit in Fig. 2 (top row): (a) drain and gate voltages for the switch (M1 ), (b) drain current through the switch M1
and current through the shunt capacitor C, (c) dynamic I -V curve for the switch. Waveforms for the class-E rectifier dual (bottom row): (d) drain and gate
voltages for the switch (M1 ), (e) drain current through the switch M1 and current through the shunt capacitor C, (f) dynamic I –V curve for the switch.
The gate-drive signal has rise and fall times equal to T /10 for both the class-E amplifier and class-E rectifier.

the shunt capacitance C. These values can be found from
the required impedance seen looking towards the load at
node A (see Fig. 2). The optimum load impedance at node A
is [25]–[27]
(0.1836 + j 0.2116)
Z A,opt (ωsw ) =
(ωsw C)
for the fundamental frequency. For harmonic frequencies,
Z A,opt (ω) is ideally open; however, in practical circuits the
loaded Q of the output network is finite and the impact of finite
harmonic impedance needs to be considered. This is discussed
more in Section III-E. From (11), the real and imaginary parts
can be used to find expressions for C and L M ,
0.1836
C = Re[Z A,opt (ωsw )] =
(ωsw R L )
and
Im[Z A,opt (ωsw )] 0.2116
LM = = 2 . (13)
(ωsw ) (ωsw C)
C. Current/Voltage Overlap Losses
When the gate-drive signal has finite switching times, this
modifies the waveforms in the class-E amplifier. Since the
switch current waveform follows the gate voltage, the current
i A has finite rise and fall times, which overlaps with the
voltage waveform v A . Other factors that affect the shape
of the waveforms are the threshold voltage of the device,
nonlinear transconductance during the switching interval, and
current saturation during the switching interval. These factors
complicate the analysis of modified waveforms resulting from
finite switching time and instead we investigate the effect of
switching times qualitatively by looking at simulated wave-
forms and dynamic I –V curves. A detailed analysis of overlap
loss is not particularly useful in the CMOS circuit because, as
(11) will be shown, other resistive loss mechanisms are much more
significant and limit power efficiency.
As a way to investigate the effect of finite switching
in class-E circuits, the switch in Fig. 2 is modeled as a
nonlinear transconductance that is extracted from the BSIM4
device model in the CMOS process design kit (PDK). All
other components are assumed to be ideal. The corresponding
waveforms for a class-E amplifier and a rectifier dual are
shown in Fig. 3. For these circuit simulations, the gate drive
(12) is a square wave with rise and fall times of T /10, where
T = 1/ f sw . The top row corresponds to the amplifier, while
the bottom row corresponds to the rectifier. The amplifier
waveforms are referenced here, and later, in Section IV, the
rectifier waveforms will be discussed.
Six points have been labeled in Fig. 3 to follow the evolu-
tion of one RF cycle over an interval of [0, 2π]. The RF cycle
in the amplifier begins at point A, which is defined as the start
of the rising edge of the gate-drive signal shown in Fig. 3(a).
As the gate voltage rises it eventually reaches the threshold
voltage of the device at point B. The threshold voltage for this
CMOS device is approximately 0.4 V, and the time it takes to
reach threshold creates a short period of time where the current
through the switch is zero. This is seen in the drain current
waveform in plot Fig. 3(b). The drain current has a small delay
1660 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 5, MAY 2016

and then steps up to the saturation current. Above threshold,

drain current flows through the switch. At point C, the drain
current peaks and current continues to flow until the switch
turns off at point D. The falling edge of the gate waveform
corresponds to the interval D–E and during this time the
current through the switch is chopped while the capacitor
current starts to rise. By the end of the switching interval
at point E, the capacitor carries all the current entering the
switch subnetwork. The zero crossing of the capacitor current
is at point F and this corresponds to peak drain voltage. After
Fig. 4. Class-E amplifier with dissipative losses in the switch and the
point F, the drain voltage falls and the voltage transitions to inductors.
zero at the end of the RF cycle returning to point A.
A dynamic I –V curve illustrating how the drain current and
drain voltage change over an RF cycle is shown in Fig. 3(c). a period from [0, π]. The corresponding power dissipation
Power loss associated with the overlap of the drain current in rsat is
and drain voltage as the switch turns off is evident by the
 π 2
contour D–E, which sweeps across the I –V plane. The power 1 rsat IDC
loss can be estimated by assuming the drain current and Prsat = i 2A (θ ) rsat dθ = (π 2 + 28). (19)
2π 0 16
capacitor current transition linearly over the interval D–E. The
switching transition time is τs , the phase at point D is θ D , and The power loss in the drain inductor L D D is
the phase at point E is θ E . Using these variables, the switch
current is Pr D D = r D D IDC
2
(20)
 
θ − θD
i sw (θ ) = i (θ D ) 1 − , for θ ∈ [θ D , θ E ] (14) and the power loss in the output inductor is
τs
 2π 2 r
and the capacitor current is 1 Iom m
Prm = i L2 (θ ) rm dθ = . (21)
  2π 0 2
θ − θD
i C (θ ) = i (θ D ) , for θ ∈ [θ D , θ E ]. (15)
τs Another way to express the loss from the resistance of the
output inductor is to combine resistance rm with the load R L
The corresponding drain voltage is found by integrating the
and then express the loss in terms of the dc supply power.
capacitor current and
Using this method,
i (θ D )  2
v A (θ ) = θ − θD , for θ ∈ [θ D , θ E ]. (16) rm
2ωsw Cτs Prm = PDC . (22)
rm + R L
The corresponding power dissipated from the overlap of
drain current and drain voltage during the on-to-off transition Equations (19)–(21) give expressions for the absolute power
interval is  θE losses created by resistive losses. It is also useful to normalize
1 these power losses to the total dc power (PDC ) to determine
Pov = i sw (θ )v A (θ ) dθ. (17)
2π θ D the relative significance of each specific loss mechanism.
Using (10) for the dc drain supply voltage, and rearrang-
The switch current at θ D is approximately equal to the ideal ing (12) to obtain the relation ωsw C = 0.1836/R L , the
switch current for θ = π. Therefore, from (7) it follows that dc supply power is
i sw (π) = i sw (θ D ) = 2IDC . Using this relation, and (14), (16),
and (17), 2 R
IDC L
2 τ2
IDC PDC = V D D IDC = . (23)
Pov = s
. (18) 0.1836 π
12π ωsw C
Normalized power losses are then expressed as

Prsat rsat
D. Resistive Losses = 1.365 (24)
PDC RL
In a CMOS implementation, the most significant loss mech- Pr D D rDD
anisms, which reduce power efficiency, are dissipation in = 0.5767 (25)
PDC RL
switch saturation resistance (rsat ), resistive losses (r D D ) in the
drain inductor L D D , and resistive losses (r M ) in the output and
inductor, L M + L S . A class-E circuit model with these losses is Prm rm
shown in Fig. 4. Equations for these power losses are derived = . (26)
PDC R L + rm
below.
The switch has an average saturation resistance rsat during These equations are used in Section III-E to compare analytic
the on state. Over one RF cycle, the switch is on for half results with simulations results.
DEHGHANI AND JOHNSON: 2.4-GHz CMOS CLASS-E SYNCHRONOUS RECTIFIER
TABLE II
S IMULATION R ESULTS FOR D IFFERENT C LASS -E A MPLIFIER C IRCUITS
E. CMOS Class-E Amplifier Reference Design
A 2.4-GHz class-E amplifier was designed using com-
ponents in the IBM CMRF8SF PDK for 0.13-μm CMOS
technology. The switch is an NMOS device and the device
has a maximum operating voltage of 3.3 V. A drain supply
voltage (V D D ) of 1 V is selected and provides headroom for
the peak voltage across the device [28], [29]. The NMOS
switch has a gate width of 360 μm and the device is sized
to directly match to a 50- load. The gate bias voltage (VGG )
for the switch is 500 mV and the bias is compatible with a 1-V
peak-to-peak gate-drive signal.
Initial component values for the design were found using
the ideal class-E design equations in Section III-B. From
the design equations, the switch capacitance C is 243.5 fF
and the phase-shift inductance L M is 3.8 nH. The series
resonator capacitance, C S , is 700 fF and has a loaded Q of
approximately 5. The Q needs to be sufficiently large to
ensure the load signal is sinusoidal. The corresponding res-
onator inductor, L S , is 6.3 nH for operation at a fundamental
frequency of 2.4 GHz. The estimated dc current is 11.5 mA
calculated from (10) and the total dc power supplied to the
drain is 11.5 mW.
Although the ideal class-E amplifier design equations pro-
vide a good starting point, a practical CMOS amplifier requires
further refinement in component values to compensate for
loss. Factors that modify the ideal design equation values
include finite switch resistance, finite inductor Q, tradeoffs
between area and inductance, and finite capacitor Q. These
factors reduce the power efficiency of the class-E design and
a sequential design methodology is adopted to independently
evaluate the effect of each nonideal component.
A summary of the design steps that were used to arrive
at the final values for the CMOS class-E amplifier design are
summarized in Table II. The table includes component values,
simulation results, and analytic results. For the simulation
results, the input signal to the amplifier is a 2.4-GHz square
wave with a peak-to-peak amplitude of 1 V and a dc offset
of 0.5 V. The first row in the table corresponds to the
1661
ideal class-E amplifier. The ideal amplifier uses a switch for
the active device, and the switch has negligible on resis-
tance (1 m) and changes state nearly instantaneously (trise =
t f all = 0.024 × T ). Since the output resonator has a Q of 5,
the harmonic impedances at reference plane A (see Fig. 2)
are not infinite. Therefore, the ideal values do not lead to zero
voltage switching and the values for C and L M are increased
by approximately 18% to obtain ideal zero voltage switching
conditions. The readjustment in component values leads to
nearly ideal performance with a power efficiency of 99.5%.
In row 2, the power loss associated with the output induc-
tors, L S and L M , are evaluated. The final inductor used in the
CMOS design is 14 nH (see row 6) and the Q of the inductor
is 13.9 at a frequency of 2.4 GHz. Based on these values, the
equivalent series resistance, rm , is 15 . A series resistance
is added to the ideal class-E amplifier, as shown in Fig. 4,
to model the inductor loss. The class-E is then re-optimized
to find the best values for C and L M with the addition of
the inductor loss. The simulated power efficiency including
rm is 76.5% and this compares very closely to the analytic
obtained using (26).
In row 3, the on state switch resistance is changed
from 1 m (ideal) to rsat . For this design, rsat is approxi-
mately 7.75 , and the switch loss reduces power efficiency
by 21.6%. The analytic estimate for the power loss associated
with rsat is 21.2%, very close to the simulated value. The
addition of rsat also changes the switching waveforms in the
amplifier, and C and L M are re-optimized to maximize
the power efficiency with the additional loss.
In row 4, the overlap loss from finite switching times
are evaluated. The switch model in row 3 is used for the
simulation. The results show that the additional power loss
generated by changing the gate waveform from instantaneous
switching to a waveform with rise and fall times of T /10 has
a very small effect on power efficiency—only 1% in this case.
In row 5, the power loss from the drain inductor is evaluated.
In the final design (row 6), a 18.7-nH inductor is used and
the inductor has a Q of 12 at a frequency of 2.4 GHz.
1662 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 5, MAY 2016
Fig. 5. Impedance of CMOS class-E amplifier load network: Z A ( f ).
The inductor loss is modeled by r D D in Fig. 4. The simulated
power efficiency with the addition of r D D is 75.2% and the
analytical estimate is 73% using (24).
Conclusions from the loss study show that the contribution
to power loss from rsat , rm , and r D D are similar and result in
power efficiencies that range from 75.2% to 78.4%. The study
also shows that each impairment requires a re-optimization
step to adjust the shunt capacitance C and the phase-shift
inductance L M to maximize power efficiency in the presence
of loss. Other conclusions are that it is difficult to predict the
superposition of all the losses, and the analytic results are most
useful to evaluate the relative significant of a specific loss.
In row 6, results are shown for a complete simulation
of the CMOS class-E amplifier. The simulation results were
generated using Spectra RF and the PDK for the CMOS
process. The design includes all loss mechanisms, which were
evaluated independently, as well as other impairments includ-
ing nonlinear device capacitances and models for the physical
layout of the inductors. In the final design, the intrinsic device
capacitance of the device is used for C and no additional
discrete capacitance is added. The simulated power efficiency
for the complete CMOS class-E amplifier design is 46.7%.
The impedance of the output network at reference plane A
is important and the simulation results for the final out-
put network design implemented with the CMOS PDK are
shown in Fig. 5. At the fundamental frequency, the real part
of the impedance is close to 50  and the reactive part
is 72 . The reactive part is associated with the choice
of L M . The harmonic impedances should ideally be an open,
and in this design the magnitude of the second and third
harmonic impedances are approximately 800 . The harmonic
impedances are more than an order of magnitude larger than
the fundamental harmonic impedance and provide a good
compromise between theory and implementation constraints
in CMOS.
IV. C LASS -E S YNCHRONOUS R ECTIFIER D ESIGN
The class-E rectifier circuit is developed from the class-E
amplifier by reversing the dc source and RF output nodes in
Fig. 6. Class-E synchronous rectifier circuit.
the amplifier. A feedback path from the RF input to the gate is
also added to provide a gate-drive signal. The class-E rectifier
circuit is shown in Fig. 6.
The effect of reversing the input and output nodes in the
amplifier is that the drain voltage and drain current waveforms
in the rectifier are time reversed compared to the amplifier
waveforms. In addition to time reversing the waveforms, the
current through the switch in the rectifier is flipped in terms of
amplitude because there is a net dc current, IDC , flowing out of
the drain inductor L D D into the dc load (see Fig. 6). Examples
of class-E rectifier waveforms are shown in Fig. 3(d) and (e).
The waveforms can be compared with the amplifier waveforms
in Fig. 3(a) and (b), and the time reversal is clearly evident.
A. Overlap Loss
The simulated class-E waveforms shown in Fig. 3 cor-
respond to a class-E rectifier model based on the class-E
amplifier model shown in row 4 of Table II. The switch is
modeled as a nonlinear transconductance based on extracted
characteristics from the CMOS BSIM4 device model, and
the gate-drive signal is a 1-V square-wave signal with rise
and fall times of T /10. For this simulation, the gate drive
is provided from an external source similar to the amplifier
configuration and the circuit model can be directly compared
with the amplifier dual. Although the shape of the amplifier
waveforms in Fig. 3(a) and (b) are similar to the time-reversed
rectifier waveforms in Fig. 3(c) and (d), there are differences
caused by the direction of current flow through the switch.
In the amplifier, current flows into the drain when the switch
is on; conversely, in the rectifier, current flows out of the drain
when the switch is on. Since the rectifier on state current flow
is out of the drain, the device operates in quadrant III, while
the amplifier on state operates in quadrant I. The difference
in the operating states is clearly seen in the corresponding
dynamic I –V plots shown in Fig. 3(c) and (f).
Another difference between the rectifier and amplifier duals
is the phase reversal of the voltage and current waveforms
with respect to the switching instants in the gate signal. In the
amplifier, the switch transition from off to on corresponds
DEHGHANI AND JOHNSON: 2.4-GHz CMOS CLASS-E SYNCHRONOUS RECTIFIER
Fig. 7. Dynamic I –V curve for the class-E rectifier. The gate drive is a
square-wave signal with 10% rise and fall times.
to interval A–B. During this interval, the drain voltage and
drain current are low, ideally zero. On the other hand, in the
rectifier, the switch transition from off to on corresponds to
interval D  –C  . During interval D  –C  , current transfers from
the capacitor to the switch, and the current through the switch
must change from zero to nearly maximum current (point B  ).
The negative drain current also means the on state voltage
drop is negative, and the combination of high current and
switch voltage leads to overlap loss. The overlap loss in the
rectifier is slightly higher than the amplifier. This is evident
in both the drain current and drain voltage waveforms where
there is a small peak at point C  . The overlap loss is also easily
seen by examining the loop area in the dynamic I –V curve for
the rectifier. This is shown in Fig. 7 and clearly the power loss
associated with the rising edge of the gate waveform (off to
on state) is much larger than the falling edge (on to off state).
Although the overlap loss is slightly higher in the rectifier,
the on state switch resistance is slightly lower in quadrant III
compared to quadrant I and the overall power efficiency of
the amplifier and rectifier are very similar. For the simulation
results in Fig. 3, the amplifier has an efficiency of 77.3% and
the rectifier has an efficiency of 78.8%. Therefore, the results
show that the net losses in the circuit duals are quite similar.
B. Gate Bias and Sinusoidal Drive Signals
The class-E amplifier is designed assuming a switching
signal is applied to the gate. The switched gate signal in the
amplifier is generated by a driver stage, and in a practical
design, the requirements for the gate drive can be established
independently. In a self-powered rectifier design, the gate drive
must be derived from the sinusoidal RF input signal, and the
input signal affects both the design of the gate bias circuit and
the phase-shift network.
The implementation of a bias circuit needs to consider
both complexity and performance. Since CMOS devices have
low threshold voltages, a zero bias scheme is used in this
design, and the gate is tied to ground through a 5.6-nH
bias inductor, L b . Ideally, the device should be biased near
1663
Fig. 8. Dynamic I –V curves for the class-E rectifier for different gate-drive
signals and different feedback phase.
threshold, and therefore the tradeoff using a zero bias scheme
is a reduction in power efficiency, especially for low amplitude
input signals.
The design of the phase-shift network is considered next.
The purpose of the phase-shift network is to create a gate-
drive signal that synchronously switches the device, and the
implication of converting the square-wave drive signal in the
amplifier into a sinusoidal gate-drive signal in the rectifier
needs to be considered. If an equal amplitude sine wave is
applied to the gate instead of a square wave, the peak is
delayed by T /4 relative to the rising edge of the square wave,
and the timing of on and off states in the device are shifted.
Therefore, the optimum phase shift for a sine-wave gate-drive
signal is not the same as for a square-wave drive signal.
The change in gate phase required to synchronously switch
the device was explored through simulation. For the first set of
simulations, the circuit model in row 4 of Table II was used.
In this model, the switch is modeled as a nonlinear transcon-
ductance and the model includes overlap and on-state losses.
Different gate-drive signals with different phase shifts relative
to the RF input signal were simulated and the conclusions are
summarized by the dynamic I –V plots in Fig. 8. A benchmark
for power efficiency was first established using a square-wave
drive signal with a peak-to-peak amplitude of 1 and a 0.5-V dc
offset. The rise and fall times are approximately instantaneous
and the power efficiency of the rectifier is 82.1% for a phase
shift of 120°. The square-wave drive was then replaced with an
equivalent sine-wave drive with a 1-V peak-to-peak amplitude
and a 0.5-V dc offset. For a phase shift of 120°, the power
efficiency is 51.4%, and if the phase of the sine-wave drive is
readjusted to 28°, power efficiency is improved significantly
to 78.7% within a few percent of the power efficiency for
a square-wave signal. The difference in phase between the
square-wave signal and sine-wave signal is 92° confirming the
change in phase delay is approximately T /4.
Similar simulation experiments were run with the full
CMOS design using post-layout models. A bridged tee phase
network was designed to create a gate-drive signal from
the RF input signal, as shown in Fig. 6. After optimizing
1664
Fig. 9. Microphotograph of the class-E synchronous rectifier.
the post-layout simulation for power efficiency, the phase
shift was readjusted to 89°. The final design values for the
phase shift network circuit elements are Csample = 29.7 fF,
L T 1 = L T 2 = 5.3 nH, C T = 1 pF, and C T P = 302 fF.
The simulated power efficiency of the CMOS rectifier is
43% at 2.4 GHz with a +11-dBm sinusoidal RF input signal.
This result can be compared with the simulation result for
the class-E amplifier dual shown earlier in Table II, row 6.
The amplifier power efficiency is 46.7% for a square-wave
gate-drive signal. The difference in power efficiency between
the amplifier with a square-wave gate signal and the rectifier
with a sine-wave gate signal is 3.7%. Referring back to Fig. 8,
a difference of 3.4% in power efficiency was obtained when
the gate-drive signal in the rectifier was changed from a
square wave to a sine wave. Therefore, the reduction in power
efficiency from a square-wave gate signal to a sine-wave gate
signal is relatively small in this design providing the phase
shift is optimized for the sine-wave drive.
V. E XPERIMENTAL R ESULTS
A photograph of the fabricated rectifier design is shown
in Fig. 9. The circuit has an area of 850 μm× 870 μm and
the rectifier circuit was verified using an EP6 Cascade probe
station with two coplanar-waveguide probes. Since power
efficiency is a key metric, it is very important to calibrate
the available power at the probe tips. A power meter was
connected to a directional coupler, which samples the input
signal to the probe station. The frequency response of the
coupler and cable were then measured to correct for fre-
quency response errors between the probe tip and the power
measurement point at the coupler. An Agilent vector network
analyzer (N5241A) was used as a signal source and a full
two-port calibration at the probe tip plane was made. With
this setup, the available input power at the probe tips was
known and S11 measurements could also be made.
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 5, MAY 2016
Fig. 10. S11 of the class-E synchronous rectifier for three different source
powers.
Fig. 11. Measured power efficiency as a function of frequency.
For this design, the input power range of the rectifier was
within the power range of the network analyzer and the
input match (S11 ) of the circuit could be measured directly
under large-signal conditions. The measurements are shown
in Fig. 10. As shown, the input match is centered at approxi-
mately 2.4 GHz and the return loss is greater than 10 dB over
a 200-MHz bandwidth. The input match is power sensitive,
which is expected since the gate amplitude changes with input
power. As the results show, the match is best at high input
power (12 dBm) and slowly starts to degrade as power is
reduced. These results show that at the design frequency input
mismatch loss is small and the power efficiency is determined
primarily by power losses in the circuit.
The phase-shift network is critical in terms of optimizing
power efficiency and insight into the performance of the
feedback network is obtained by measuring power efficiency
over frequency. The test results are shown in Fig. 11. As the
measurements show, 32% peak efficiency is obtained around
2.3 GHz, 100 MHz below the design frequency. The measure-
ments show that the feedback phase delay is slightly mistuned
and better alignment with the input match would likely yield
DEHGHANI AND JOHNSON: 2.4-GHz CMOS CLASS-E SYNCHRONOUS RECTIFIER
Fig. 12. Power efficiency and output voltage as a function of load resistance.
Fig. 13. Power efficiency and output voltage across a 250- load as a
function of available input power.
even better power efficiency than measured for this design.
However, for a first iteration of the design, the results are
very encouraging and demonstrate the potential of a class-E
synchronous rectifier in CMOS.
Other interesting measurement results include power effi-
ciency at 2.4 GHz as a function of dc load resis-
tance R L (Fig. 12) and power efficiency as a function of input
power (Fig. 13). In. Fig. 12, efficiency as a function of load
resistance is shown and the optimum load resistance is 225 
for an input power of 10 dBm. In Fig. 13, the power efficiency
of the rectifier as a function of available input RF power
is shown. The measurements are made at 2.4 GHz with a
load resistance of 250 . As the data show, power efficiency
peaks at 30% for an input power of 12 dBm, while power
efficiency remains above 24% for a 10-dB dynamic range
from 6 to 16 dBm. Full post-layout simulation results are also
shown for the measurements in Figs. 12 and 13. The physical
layout contributes significantly to the overall power efficiency
of the CMOS design. Of particular note is the importance of
modeling the gate resistance in the physical layout, as this can
significantly affect the power efficiency of the rectifier.
1665
VI. C ONCLUSION
A CMOS class-E rectifier has been designed. The syn-
chronous switching design is distinctly different from other
CMOS RF rectifier circuits that use voltage multiplication
techniques. The rectifier includes input matching, as well as a
self-biased gate.
Experimental results for the rectifier design show a power
efficiency of 30% at a frequency of 2.4 GHz. The design
provides a new benchmark for monolithic RF rectifiers imple-
mented in CMOS technology using a switching circuit topol-
ogy. Future work will focus on improving power efficiency by
migrating the design to 65-nm CMOS, broadening the band-
width of the phase-shift network to the gate and optimizing
the layout to improve power efficiency.
R EFERENCES
[1] H. Gao, Y. Wu, M. Matters-Kammerer, J.-P. Linnartz, A. van Roermund,
and P. Baltus, “System analysis and energy model for radio-triggered
battery-less monolithic wireless sensor receiver,” in IEEE Int. Circuits
Syst. Symp., May 2013, pp. 1572–1575.
[2] C.-Y. Liou, M.-L. Lee, S.-S. Huang, and S.-G. Mao, “High-power
and high-efficiency RF rectifiers using series and parallel power-
dividing networks and their applications to wirelessly powered devices,”
IEEE Trans. Microw. Theory Techn., vol. 61, no. 1, pp. 616–624,
Jan. 2013.
[3] S. Hemour et al., “Towards low-power high-efficiency RF and
microwave energy harvesting,” IEEE Trans. Microw. Theory Techn.,
vol. 62, no. 4, pp. 965–976, Apr. 2014.
[4] K. Kotani and T. Ito, “High efficiency CMOS rectifier circuit with self-
Vth-cancellation and power regulation functions for UHF RFIDs,” in
IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp. 119–122.
[5] K. Kotani, A. Sasaki, and T. Ito, “High-efficiency differential-drive
CMOS rectifier for UHF RFIDs,” IEEE J. Solid-State Circuits, vol. 44,
no. 11, pp. 3011–3018, Nov. 2009.
[6] K.-H. Chen, J.-H. Lu, and S.-I. Liu, “A 2.4 GHz efficiency-enhanced
rectifier for wireless telemetry,” in IEEE Custom Integr. Circuits Conf.,
Sep. 2007, pp. 555–558.
[7] J. Pandey, Y.-T. Liao, A. Lingley, R. Mirjalili, B. Parviz, and B. Otis,
“A fully integrated RF-powered contact lens with a single element
display,” IEEE Trans. Biomed. Circuits Syst., vol. 4, no. 6, pp. 454–461,
Dec. 2010.
[8] J. Masuch, M. Delgado-Restituto, D. Milosevic, and P. Baltus,
“Co-integration of an RF energy harvester into a 2.4 GHz transceiver,”
IEEE J. Solid-State Circuits, vol. 48, no. 7, pp. 1565–1574, Jul. 2013.
[9] C.-J. Li and T.-C. Lee, “2.4-GHz high-efficiency adaptive power,” IEEE
Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 2, pp. 434–438,
Feb. 2014.
[10] W. Lerdsitsomboon and K. Kenneth, “Technique for integration of a
wireless switch in a 2.4 GHz single chip radio,” IEEE J. Solid-State
Circuits, vol. 46, no. 2, pp. 368–377, Feb. 2011.
[11] M. Litchfield, S. Schafer, T. Reveyrand, and Z. Popovic, “High-
efficiency X-band MMIC GaN power amplifiers operating as rectifiers,”
in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2014, pp. 1–4.
[12] S. Abdelhalem, P. Gudem, and L. Larson, “An RF–DC converter with
wide-dynamic-range input matching for power recovery applications,”
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 6, pp. 336–340,
Jun. 2013.
[13] J. Guo, H. Zhang, and X. Zhu, “Theoretical analysis of RF–DC
conversion efficiency for class-F rectifiers,” IEEE Trans. Microw. Theory
Techn., vol. 62, no. 4, pp. 977–985, Apr. 2014.
[14] H. Takhedmit et al., “A 2.45-GHz low cost and efficient rectenna,” in
Proc. 4th Eur. Conf. Antennas Propag., Apr. 2010, pp. 1–5.
[15] J. Guo and X. Zhu, “An improved analytical model for RF–DC con-
version efficiency in microwave rectifiers,” in IEEE MTT-S Int. Microw.
Symp. Dig., Jun. 2012, pp. 1–3.
[16] T. Hoang, A. Douyere, J.-L. Dubard, and J.-D. Luk, “TLM design
of a compact PIFA rectenna,” in Int. Electromagn. Adv. Appl. Conf.,
Sep. 2011, pp. 508–511.
[17] H. Takhedmit et al., “A 2.45-GHz dual-diode RF-to-dc rectifier for
rectenna applications,” in Eur. Microw. Conf., Sep. 2010, pp. 37–40.
1666 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 5, MAY 2016
[18] M. Ruiz, R. Marante, and J. A. Garcia, “A class E synchro-
nous rectifier based on an E-pHEMT device for wireless powering
applications,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012,
pp. 1–3.
[19] S. Abbasian and T. Johnson, “High efficiency GaN HEMT class-F
synchronous rectifier for wireless applications,” IEICE Electron. Exp.,
vol. 12, no. 1, pp. 1–11, 2015.
[20] S. Yoshida et al., “The C-band MPT rectifier using a HEMT without
bonding-wire connection for a space health monitoring system,” in IEEE
Wireless Power Transfer Conf., May 2013, pp. 163–166.
[21] D. Hamill, “Time reversal duality and the synthesis of a double class
E DC–DC converter,” in 21st Annu. IEEE Power Electron. Specialists
Conf., 1990, pp. 512–521.
[22] M. Roberg, T. Reveyrand, I. Ramos, E. Falkenstein, and Z. Popović,
“High-efficiency harmonically terminated diode and transistor rectifiers,”
IEEE Trans. Microw. Theory Techn., vol. 60, no. 12, pp. 4043–4052,
Dec. 2012.
[23] Z. Popović, T. Reveyrand, S. Schafer, M. Litchfield, I. Ramos, and
S. Korhummel, “Efficient transmitters and receivers for high-power
wireless powering systems,” in IEEE Wireless Power Transfer Conf.,
May 2014, pp. 32–35.
[24] N. Sokal and A. Sokal, “Class E, a new class of high-efficiency tuned
single-ended switching power amplifiers,” IEEE J. Solid-State Circuits,
vol. 10, no. 3, pp. 168–176, Jun. 1975.
[25] F. Raab, “Class E, class C, and class F power amplifiers based upon
a finite number of harmonics,” IEEE Trans. Microw. Theory Techn.,
vol. 49, no. 8, pp. 1462–1468, Aug. 2001.
[26] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd ed.
Norwood, MA, USA: Artech House, 2006.
[27] A. Grebennikov, N. O. Sokal, and M. J. Franco, Switchmode RF and
Microwave Power Amplifiers, 2nd ed. Waltham, MA, USA: Academic,
2012.
[28] A. Mazzanti, L. Larcher, R. Brama, and F. Svelto, “Analysis of reliability
and power efficiency in cascode class-E PAs,” IEEE J. Solid-State
Circuits, vol. 41, no. 5, pp. 1222–1229, May 2006.
[29] T. Johansson and J. Fritzin, “A review of watt-level CMOS RF
power amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 1,
pp. 111–124, Jan. 2014.
Soroush Dehghani (GSM’14) was born in Tehran,
Iran, in 1990. He is currently working toward the
Ph.D. degree at the University of British Columbia,
Kelowna, BC, Canada.
In 2013, he joined the Microwave Technology
Laboratory (MTL), University of British Columbia.
His research interests include integrated RF cir-
cuit design and low-power integrated analog circuit
design with an emphasis on biomedical applications.
Thomas Johnson (S’06) received the MA.Sc.
and Ph.D. degrees from Simon Fraser Univer-
sity, Burnaby, BC, Canada, in 2001 and 2007,
respectively.
He is currently an Assistant Professor with
the School of Engineering, University of British
Columbia (UBC), Kelowna, BC, Canada. Prior to
joining UBC in 2009, he was a Technical Lead for
a number of companies, including PulseWave RF,
ADC Telecommunications, and Norsat International.
His research interests include the design of RF
circuits and systems, the application of electromagnetic field concepts in the
design of sensors, and industrial applications of RF/microwave power.