(optional)

4-Credits-Course : Audit ADV ANALOG DESIGN

Intention : Fundamentals related
Expected work load = 6-7 hours

4-Credits-Reading: CPPSIM
Overview : Inolves simulator-based study on the behavior profiles and the impact of
noises various ANALOG systems
ADC(this semester)
1. PLL
2. High speed communication circuits
3. Communication circuits

Intention to pickup the course : Knowledge on the circuit behavior at the

an advantage of saving a lot of time sparing on simulations.
As the behavior patterns are
programmed prior its lot easy to analyse the behavior

Outcome of the course : A brief overview on Modelling the ADC

working (python or cpp) - Helpful for the thesis
Two breifings a week, be for 20 minutes each ( 1st breifing - description of the
sub-system )
( 2nd briefing -
Simulated version - study and analysis)

Expected work load = 8-10 hours

4-Credits-Research: ADC
Intention to pickup the course : Keep aligned to the ADC related material

Expected work load = 10-11 hours

4-Credits-Research: ADC fine grained Analysis

Overview : Inolves simulator-based study on the behavior profiles and the impact of
noises various ANALOG systems
1. SNDR - frequency analyis based
2. Energy and power wise analysis
3. Verilog AMS wise implementation
4. Involvement of cpp or python to imitate the behavior
patters using the mathematical models
Parallelly would work on inter-disciplinary areas
Expected work load = 8-9 hours

Total work load 6.5+9+10.5+8.5 = A rough estimate of 36 hours

4-Credits-Research : Implemetation of analog system in MATLAB, python or cpp

Expected work load = 8-10 hours

4-Credits-Research : Work on a 'specific' topic if there

Expected work load = 10-12 hours

Would like to link a drive that i shall update every day, gives a track of work I
have been doing.