Lovely Professional University, Punjab

Course Code Course Title Course Planner Lectures Tutorials Practicals Credits
CSE211 COMPUTER ORGANIZATION AND DESIGN 13742::Mandeep Singh 3.0 1.0 0.0 4.0
Course Orientation 1 :DISCIPLINE KNOWLEDGE, 7 :COMPETITIVE EXAMINATION(Higer Education)

TextBooks
Sr No Title Author Edition Year Publisher Name
T-1 Computer System Architecture, 3/e M. Morris Mano 3rd 2013 PEARSON
Reference Books
Sr No Title Author Edition Year Publisher Name
R-1 Computer Organization and William Stallings 9th 2013 PEARSON
Architecture: Designing for
Performance, 9/e

Other Reading

Sr No Journals articles as Compulsary reading (specific articles, complete reference)

OR-1 http://nptel.ac.in/courses/Webcourse-contents/IIT-%20Guwahati/comp_org_arc/web/ ,

Relevant Websites
Sr No Web address (only if relevant to the course) Salient Features
RW-1 http://www.cs.uwm.edu/classes/cs458/Lecture/HTML/ch01s04.html Map Simplification

RW-2 http://www.cs.uwm.edu/classes/cs458/Lecture/HTML/ch01s06.html Flip-Flops

RW-3 http://www.cs.uwm.edu/classes/cs458/Lecture/HTML/ch08s03.html Stack Organization

RW-4 http://cse10-iitkgp.virtual-labs.ac.in/booth.html Booth's Multiplier

RW-5 http://csg.csail.mit.edu/6.823/studymaterials.html Study Materials

RW-6 http://www.seas.gwu.edu/%7Ebhagiweb/cs135/lectures/memory.pdf Memory

RW-7 http://www.seas.gwu.edu/%7Ebhagiweb/cs135/lectures/logic1.pdf Logic

Audio Visual Aids

Sr No AV aids (only if relevant to the course) Salient Features
AV-1 http://nptel.ac.in/video.php?subjectId=106102062 NPTEL

Virtual Labs
Sr No VL (only if relevant to the course) Salient Features
VL-1 http://cse10-iitkgp.virtual-labs.ac.in/rca_design.html Design of Ripple Carry Adders
 VL-2 http://www.softpedia.com/get/Others/Home-Education/CEDAR-Logic-Simulator.shtml CEDAR Logic Simulator
VL-3 http://sourceforge.net/projects/circuit/files/latest/download Simulations
VL-4 http://sourceforge.net/projects/qucs/files/latest/download?source=rw_dlp_t5 Simulations

LTP week distribution: (LTP Weeks)

Weeks before MTE 7
Weeks After MTE 7
Spill Over 7

Detailed Plan For Lectures

Week Lecture Broad Topic(Sub Topic) Chapters/Sections of Other Readings, Lecture Description Learning Outcomes Pedagogical Tool Live Examples
Number Number Text/reference Relevant Websites, Demonstration/
books Audio Visual Aids, Case Study /
software and Virtual Images /
Labs animation / ppt
etc. Planned
Week 1 Lecture 1 Basics Of Digital T-1:1 RW-7 L0: Introduction to the Understand the basic Demonstration Digital
Electronics(Logic gates) R-1:1 AV-1 course(Lecture Zero) concept of digital with simulator. electronics is
VL-4 L1: Introduction of computer based entirely
digital computer and on the
Logic fundamental
gates. principles of
Boolean logic.
Consider the
following
devices:
i . a soda
machine which
accepts coins
and dispenses
cans of soda
ii. a microwave
oven with
programmable
power levels and
timers
iii. a hand-held
calculator

Basics Of Digital T-1:1 RW-7 Introduction of boolean i. Understand the Demonstration A simple finite
Electronics(boolean algebra) R-1:1 AV-1 algebra basic concept of with simulator. state machine
VL-4 boolean algebra. for the soda
ii. Employ Boolean machine
algebra to describe
the function of logic
circuits.
Week 1 Lecture 2 Basics Of Digital T-1:1 RW-1 Describing about i. Understand about Demonstration A digital circuit
Electronics(map AV-1 boolean function and boolean algebra and with simulator. can be designed
simplification) VL-2 boolean expressions can map simplification to control the
be simplified using map ii. Analysis and movement of an
simplification design of digital elevator.
circuits.
Lecture 3 Basics Of Digital T-1:1 RW-2 i. Introduction of i. Learn about Demonstration Usage for S- R
Electronics(Flip flops) AV-1 combinational circuits. combinational and with simulator Flip Flop would
VL-2 ii. Flip Flop and its Flip Flop be a simple
types. ii. Understand the security system.
design and Usages of R is hooked up
Flip Flop to a key to arm
it and a trigger
or switch on a
door or window
is hooked up to
S to set it off.
Week 2 Lecture 4 Basics Of Digital T-1:2 AV-1 Introduction to i. Understand circuits Demonstration Wireless remote
Electronics(integrated VL-2 integrated circuits and design by with simulator. control system :
circuits) Decoders interconnection of When using a
various gates. wireless remote
ii. Formation of control system it
larger decoders by is desirable to
combining two or have a way of
more small decoders filtering out or
ignoring those
unwanted
signals to
prevent false
data from being
received.

A simple way to
accomplish this
is to use an
encoder IC at
the transmitter
and a decoder
IC at the
receiver. The
encoder
generates serial
codes that are
automatically
sent three times
and must be
received at least
twice before
data is accepted
as valid by the
decoder circuit.
Week 2 Lecture 4 Basics Of Digital T-1:2 AV-1 L4. Introduction to i. Understand circuits Demonstration Wireless remote
Electronics(Decoder and VL-2 integrated circuits and design by with simulator. control system :
Encoder) Decoders interconnection of When using a
L5. Decoders and various gates. wireless remote
Encoder ii. Formation of control system it
larger decoders by is desirable to
combining two or have a way of
more small decoders filtering out or
ignoring those
unwanted
signals to
prevent false
data from being
received.

A simple way to
accomplish this
is to use an
encoder IC at
the transmitter
and a decoder
IC at the
receiver. The
encoder
generates serial
codes that are
automatically
sent three times
and must be
received at least
twice before
data is accepted
as valid by the
decoder circuit.
Week 2 Lecture 5 Basics Of Digital T-1:2 AV-1 L4. Introduction to i. Understand circuits Demonstration Wireless remote
Electronics(Decoder and VL-2 integrated circuits and design by with simulator. control system :
Encoder) Decoders interconnection of When using a
L5. Decoders and various gates. wireless remote
Encoder ii. Formation of control system it
larger decoders by is desirable to
combining two or have a way of
more small decoders filtering out or
ignoring those
unwanted
signals to
prevent false
data from being
received.

A simple way to
accomplish this
is to use an
encoder IC at
the transmitter
and a decoder
IC at the
receiver. The
encoder
generates serial
codes that are
automatically
sent three times
and must be
received at least
twice before
data is accepted
as valid by the
decoder circuit.
Week 2 Lecture 5 Basics Of Digital T-1:2 AV-1 Introduction to i. Understand circuits Demonstration Wireless remote
Electronics(integrated VL-2 integrated circuits and design by with simulator. control system :
circuits) Decoders interconnection of When using a
various gates. wireless remote
ii. Formation of control system it
larger decoders by is desirable to
combining two or have a way of
more small decoders filtering out or
ignoring those
unwanted
signals to
prevent false
data from being
received.

A simple way to
accomplish this
is to use an
encoder IC at
the transmitter
and a decoder
IC at the
receiver. The
encoder
generates serial
codes that are
automatically
sent three times
and must be
received at least
twice before
data is accepted
as valid by the
decoder circuit.
Lecture 6 Basics Of Digital T-1:2 AV-1 Lecture orientation Design of integrated Demonstration Traffic Light
Electronics(Multiplexers and VL-3 about multiplexer and circuit package by with simulator. Control with
De multiplexers) demultiplexer two or more decoders and
multiplexer. multiplexers are
used for sharing
of a data
transmission
line by a number
of signals,
selection control
on a home
stereo unit.
Week 3 Lecture 7 Basics Of Digital T-1:2 AV-1 Discussion on register i. Understand the data Demonstration Buffer storage
Electronics(registers) VL-3 and register with parallel processing tasks with images e.g. video
Load performed by memory for
registers. graphics cards
ii. Understand the
working of clock
pulse of registers in
the system.
iii. Understand of
Load input : The load
input in the register
determines the action
taken with each clock
pulse.

Basics Of Digital T-1:2 AV-1 Discussion on Shift i. Understand of data Demonstration i. The most
Electronics(shift registers) VL-3 registers ( left and right storage in shift with images common uses of
shift registers etc.) registers. a shift register is
ii. Understand the to convert
movement of data in between serial
shift registers. and parallel
interfaces. This
is useful as
many circuits
work on groups
of bits in
parallel, but
serial interfaces
are simpler to
construct.
ii. Shift registers
can be used as
simple delay
circuits.
iii. Bidirectional
shift registers
could be
connected in
parallel for a
hardware
implementation
of a stack.
Basics Of Digital T-1:2 AV-1 Discussion on binary i. Implementation of Demonstration
Electronics(binary counters) VL-3 counters counters. with images
ii. Usages of memory
devices such as Flip-
flops for counters.
Week 3 Lecture 7 Basics Of Digital T-1:2 RW-6 Introduction of memory i. Understanding of Demonstration i. Storing
Electronics(memory unit) AV-1 and its types memory unit and how with images current time and
it store the data. date in a
ii. Understand the machine.
address line and data ii. Storing port
input line statuses.
ii. Understand iii. Storing
different type of messages in a
memory. mobile phone.
iv. Storing
photographs in a
digital camera.
Lecture 8 Register Transfer and Micro T-1:4 AV-1 Introduction of micro- i. Learn about Discussion i. A Counter
Operations(register transfer operations and internal information with parallel
language) hardware organization processing task of load is capable
of a digital computer. digital hardware of performing
modules. the micro-
ii. Understand the operations
Micro-operations of increment and
system. load.
ii. A
bidirectional
shift register is
capable of
performing the
shift right and
shift left micro-
operations.
Register Transfer and Micro T-1:4 Discussion on register i. Learn about Discussion with Internal
Operations(register transfer) transfer and control different diagram. hardware
function. representations of a organization of a
register. digital computer
ii.Understand the
register transfer
notation.
iii. Understand the
hardware
construction.
Register Transfer and Micro T-1:4 Discussion on Bus and i. Understand transfer Discussion with Digital
Operations(Bus and Memory Memory Transfers, Bus between Processor image. computer.
Transfer) selection and three - registers through
state bus buffers buses
ii. Understand
transfer between
Processor
register and memory
through buses
Week 3 Lecture 9 Register Transfer and Micro
Operations(arithmetic
microoperations)
Week 4 Lecture 10 Register Transfer and Micro
Operations(Logic Micro
Operations)
Register Transfer and Micro
Operations(Shift Micro
Operations)
Register Transfer and Micro
Operations(arithmetic logic
shift unit)
Lecture 11 Basic Computer
Organization(Instruction
codes)
Basic Computer
Organization(computer
registers)
Lecture 12 Basic Computer
Organization(Computer
instructions)
Basic Computer
Organization(Timing and
Control)
T-1:4 Arithmetic operations Learn how an Peer learning
performed on the arithmetic or logic
contents of registers. operation
performed by
sequences of
microoperations.
T-1:4 Operations are Learn about the 16 Peer learning
performed on the binary Logical micro-
data stored in the operations.
register
T-1:4 Serial data transfer of i. Understand about Peer learning
data data transfer.
ii. Understand about
data processing
operations.
T-1:4 Learn how an arithmetic Learn an ALU Peer learning
operation operation among 8
performed by sequences arithmetic and six
of microoperations logic operations.
T-1:5 RW-5 Introduction to basic i. Understanding of Discussion with
AV-1 computer and show how internal image.
its operation can be registers,control
specified with register structure and
transfer statement. instruction .
ii. Understanding of
Common bus system.
T-1:5 RW-5 Introduction to basic i. Understanding of Discussion with
AV-1 computer and show how internal image.
its operation can be registers,control
specified with register structure and
transfer statement. instruction .
ii. Understanding of
Common bus system.
T-1:5 OR-1 Discussion on basic Understand the Discussion with Control unit of
AV-1 computer instruction elements of modern Image. Computer
format and timing for instructions sets and system.
registers. explain their impact
on processor design.
T-1:5 OR-1 Discussion on basic Understand the Discussion with Control unit of
AV-1 computer instruction elements of modern Image. Computer
format and timing for instructions sets and system.
registers. explain their impact
on processor design.
Week 5 Lecture 13 Basic Computer T-1:5 AV-1 Explain the basics of i. Understand the Discussion with
Organization(Instruction R-1:14 instruction execution on characteristics of an Image
cycle) a computer. instruction set and
how it maps to
underlying hardware.
ii. Identify and
analyze the design
and function of the
basic instruction
execution elements of
a modern processor.
Basic Computer T-1:5 AV-1 Explain the basics of i. Understand the Discussion with
Organization(Memory R-1:14 instruction execution on characteristics of an Image
reference Instruction) a computer. instruction set and
how it maps to
underlying hardware.
ii. Identify and
analyze the design
and function of the
basic instruction
execution elements of
a modern processor.
Lecture 14 Basic Computer T-1:5 AV-1 Identify and explain the Learn about How to Discussion
Organization(input output different methods of I/O communicate with thorough
and interrupt) in a computer system process in the knowledge and
computer system for understanding of
other task key concepts.
Lecture 15 Central Processing Unit T-1:8 AV-1 Introduction to CPU and i. Understand the Discussion with
(major components of data processing functionality of image.
central processing unit) operation performed on central processing
it unit.
ii. Understand the
organization and
architecture of CPU.
Central Processing Unit T-1:8 AV-1 Introduction to CPU and i. Understand the Discussion with
(General Register data processing functionality of image.
Organization) operation performed on central processing
it unit.
ii. Understand the
organization and
architecture of CPU.
Week 6 Lecture 16 Central Processing Unit T-1:8 RW-3 Introduction to storage i. To understand Discussion
(Stack Organization) device that stores stack based processor
information. The organization.
operands and destination ii. Instruction set of a
of an instruction in a stack organized
stack-based organization processor.
implicit. iii. Learn Post Fix
Notations for Stack
based Computers.
Week 6 Lecture 17 Central Processing Unit T-1:8 AV-1 Describing about Learn about How to Peer learning
(instruction formats) different modes of change the value of
transfer Program Counter
Central Processing Unit T-1:8 AV-1 Describing about Learn about How to Peer learning
(Addressing Modes) different modes of change the value of
transfer Program Counter
Lecture 18 MCQ,Test1
Week 7 Lecture 19 Central Processing Unit T-1:8 AV-1 CISC variable length Learn the CISC and Peer learning Earlier when
(Data Transfer) instructions in RISC Architecture most computer
multiple cycles programming
was done in
assembly
language,
instruction set
architecture was
considered the
most important
part of computer
architecture,
because it
determined how
difficult it was
to obtain
optimal
performance
from the system.
Central Processing Unit T-1:8 AV-1 CISC variable length Learn the CISC and Peer learning Earlier when
(Manipulation) instructions in RISC Architecture most computer
multiple cycles programming
was done in
assembly
language,
instruction set
architecture was
considered the
most important
part of computer
architecture,
because it
determined how
difficult it was
to obtain
optimal
performance
from the system.
Week 7 Lecture 19 Central Processing Unit T-1:8 AV-1 CISC variable length Learn the CISC and Peer learning Earlier when
(Program control) instructions in RISC Architecture most computer
multiple cycles programming
was done in
assembly
language,
instruction set
architecture was
considered the
most important
part of computer
architecture,
because it
determined how
difficult it was
to obtain
optimal
performance
from the system.
Central Processing Unit T-1:8 AV-1 CISC variable length Learn the CISC and Peer learning Earlier when
(Reduced instruction set instructions in RISC Architecture most computer
computer) multiple cycles programming
was done in
assembly
language,
instruction set
architecture was
considered the
most important
part of computer
architecture,
because it
determined how
difficult it was
to obtain
optimal
performance
from the system.
Week 7 Lecture 19 Central Processing Unit T-1:8 AV-1 CISC variable length Learn the CISC and Peer learning Earlier when
(Complex instruction set instructions in RISC Architecture most computer
computer) multiple cycles programming
was done in
assembly
language,
instruction set
architecture was
considered the
most important
part of computer
architecture,
because it
determined how
difficult it was
to obtain
optimal
performance
from the system.

SPILL OVER
Week 7 Lecture 20 Spill Over
Lecture 21 Spill Over

MID-TERM
Week 8 Lecture 22 Control Unit(control T-1:7 Discussion on hardwired Learn about how to Demonstration
memory) control Unit design a control Unit with images

Control Unit(address T-1:7 Discussion on hardwired Learn about how to Demonstration Traffic manager
sequencing) control Unit design a control Unit with images

Lecture 23 Control Unit(Microprogram T-1:7 AV-1 Discussion on i. Learn about how to Discussion
sequencer) Microprogram design Micro
sequencer for control programmed control
memory unit.
ii. Learn about
Microinstructions
Lecture 24 Computer Arithmetic T-1:10 AV-1 Introduction to i. Understand sign Demonstration and
(introduction to computer Computer arithmetic extension of 2’s discussion
arithmetic) complement
number.
ii.To understand
adder circuit and
Subtractor circuit.
Week 8 Lecture 24 Computer Arithmetic T-1:10 AV-1 Introduction to i. Understand sign Demonstration and
(Addition and Subtraction Computer arithmetic extension of 2’s discussion
Algorithm) complement
number.
ii.To understand
adder circuit and
Subtractor circuit.
Week 9 Lecture 25 Computer Arithmetic T-1:10 Discussion on signed Learn Booth Peer learning
(Multiplication Algorithm) and booth encoding
multiplication.

Lecture 26 Computer Arithmetic T-1:10 Discussion on signed Learn Booth Peer learning
(Multiplication Algorithm) and booth encoding
multiplication.

Lecture 27 Computer Arithmetic T-1:10 Discussion on divide Learn about how to Demonstration and
(Division Algorithms) overflow and signed design division discussion
division algorithm algorithm using
computer register

Week 10 Lecture 28 Input-Output Organization T-1:11 AV-1 Introduction to input- Understand the the Discussion with
(Peripheral Devices) R-1:7 output subsystem of a mode of images
computer communication
between the central
system and out side
environment
Input-Output Organization T-1:11 AV-1 Introduction to input- Understand the the Discussion with
(Input Output Interface) R-1:7 output subsystem of a mode of images
computer communication
between the central
system and out side
environment
Lecture 29 Input-Output Organization T-1:11 RW-5 Discussion on Learn about source Discussion with
(Data transfer schemes) AV-1 asynchronous Data and destination images
transfer between initiated data transfer
independent units
Lecture 30 MCQ,Test2
Week 11 Lecture 31 Input-Output Organization T-1:11 Discussion on types Learn about types of Discussion Data Sharing
(modes of data transfer) of data transfer schemes data transfer Methods
techniques
means how to
transfer
data from memory to
processor and input
output devices
Week 11 Lecture 31 Input-Output Organization T-1:11 Discussion on types Learn about types of Discussion Data Sharing
(Priority interrupt) of data transfer schemes data transfer Methods
techniques
means how to
transfer
data from memory to
processor and input
output devices
Lecture 32 Input-Output Organization T-1:11 AV-1 Discussion on DMA i. Understand the Demonstration and A sound card
(Direct memory access used when multiple concept of Direct discussion may need to
transfer) bytes are to be memory access data
transferred between access to memory for stored in the
memory and IO devices data transfers computer's
ii. Learn how DMA RAM, but since
used when multiple it can process
bytes are the data itself, it
to be transferred may use DMA
between memory and to bypass the
IO CPU. Video
devices cards that
iii. Learn DMA Data support DMA
transfer mechanism can also access
between the system
I/O devices and memory and
system memory with process graphics
the least without needing
processor the CPU. Ultra
intervention using DMA hard
DMAC drives use DMA
to transfer data
faster than
previous hard
drives that
required the data
to first be run
through the
CPU
Lecture 33 Memory Unit(Memory T-1:12 Discussion on Memory Learn three levels of Discussion USB Flash
hierarchy) and its types hierarchy of cache, Drives
RAM/ROM and
secondary storage
Memory Unit(main T-1:12 Discussion on Memory Learn three levels of Discussion USB Flash
memory) and its types hierarchy of cache, Drives
RAM/ROM and
secondary storage
Week 12 Lecture 34 Memory Unit(auxiliary T-1:12 Describing about Learn about content Discussion with Contentaddressa
memory) Argument register addressable memory image. ble
Match memory is often
Logic etc used in
computer
networking
devices. For
example, when a
network switch
receives a data
frame from one
of its ports, it
updates an
internal table
with the frame's
source MAC
address and the
port it was
received on. It
then looks up
the destination
MAC address in
the table to
determine what
port the frame
needs to be
forwarded to,
and sends it out
on that port. The
MAC address
table is usually
implemented
with a binary
CAM so the
destination port
can be found
very quickly,
reducing the
switch's latency.
Week 12 Lecture 34 Memory Unit(Associative T-1:12 Describing about Learn about content Discussion with Contentaddressa
memory) Argument register addressable memory image. ble
Match memory is often
Logic etc used in
computer
networking
devices. For
example, when a
network switch
receives a data
frame from one
of its ports, it
updates an
internal table
with the frame's
source MAC
address and the
port it was
received on. It
then looks up
the destination
MAC address in
the table to
determine what
port the frame
needs to be
forwarded to,
and sends it out
on that port. The
MAC address
table is usually
implemented
with a binary
CAM so the
destination port
can be found
very quickly,
reducing the
switch's latency.
Lecture 35 Memory Unit(Cache T-1:12 Discussion on types of Learn about basic Peer learning
Memory) mapping techniques in concepts of cache
cache memory memory
Lecture 36 MCQ,Test3
Week 13 Lecture 37 Memory Unit(Virtual T-1:12 Discussion on page Learn about how to Discussion with
memory) table ,memory mapping manage memory images.
table space and address
space
Lecture 38 Introduction to Parallel T-1:9 AV-1 Simultaneous data Learn about Discussion
Processing(parallel processing task to processor with
processing) increase the speed of multiple functional
computer system. units.
Week 13 Lecture 38 Introduction to Parallel T-1:9 AV-1 Simultaneous data Learn about Discussion
Processing(Pipelining) processing task to processor with
increase the speed of multiple functional
computer system. units.
Lecture 39 Introduction to Parallel T-1:13 AV-1 Discussion on system To understand Discussion with
Processing(Characteristics bus interconnect multiprocessor images
of multiprocessors) network system
interconnects using
system and
time shared buses
Introduction to Parallel T-1:13 AV-1 Discussion on system To understand Discussion with
Processing(Interconnection bus interconnect multiprocessor images
Structures) network system
interconnects using
system and
time shared buses
Week 14 Lecture 40 Introduction to Parallel T-1:13 AV-1 Discussion on i. Learn about how to Discussion
Processing(Inter Processor arbitration logic and transfer information
Arbitration) mutual exclusion between
multiprocessor
components.
ii. Learn about
synchronization
Introduction to Parallel T-1:13 AV-1 Discussion on i. Learn about how to Discussion
Processing(Inter Processor arbitration logic and transfer information
Communication and mutual exclusion between
Synchronization) multiprocessor
components.
ii. Learn about
synchronization

SPILL OVER
Week 14 Lecture 41 Spill Over
Lecture 42 Spill Over
Week 15 Lecture 43 Spill Over
Lecture 44 Spill Over
Lecture 45 Spill Over

Scheme for CA:

Component Frequency Out Of Each Marks Total Marks
MCQ,Test 2 3 10 20

Total :- 10 20
 Details of Academic Task(s)
AT No. Objective Topic of the Academic Task Nature of Academic Task Evaluation Mode Allottment /
(group/individuals/field submission Week
work
Test1 To check the subject Will be covering syllabus from lecture 1 to lecture 15. All Individual On the basis of 5/6
understanding and questions should be of 5 marks each or in multiples of 5. answer attempted
learning ability of by student
the students.

Test2 To check the subject Will be covering syllabus from lecture 16 to lecture 27. All Individual On the basis of 9 / 10
understanding and questions should be of 5 marks each or in multiples of 5. answer attempted
learning ability of by student
the students.
MCQ1 To ensure Will be covering syllabus from lecture 1 to lecture 33. Individual No. of answers 10 / 12
understanding of the correctly marked by
concepts and check student (25%
the student's negative marking
progress for incorrect
answers)

Plan for Tutorial: (Please do not use these time slots for syllabus coverage)
Tutorial No. Lecture Topic Type of pedagogical tool(s) planned
(case analysis,problem solving test,role play,business game etc)

Tutorial1 Problem Solving on Encoders and Decoders, Logic Gates and Flip- Problem Solving
Flops
Tutorial2 Problems based on Bus and Memory transfer and Arithmetic and Problem Solving
shift Micro operations
Tutorial3 Problem Solving on Register transfer and Register transfer Problem Solving
language and Instruction Codes
Tutorial4 Problem Solving on Control Timing Signals and Instruction Cycle Problem Solving
Tutorial5 Problem Solving on Memory Reference Instructions and Input Problem Solving
Output interrupt
Tutorial6 Problem Solving on program and Micro Program Control, Problem Solving
Tutorial7 Problem Solving on Data Transfer, Manipulation and Addressing Problem Solving
Modes
After Mid-Term
Tutorial8 Problem Solving on Addition, Subtraction Algorithm, Multiplication Problem Solving
and Division Algorithm
Tutorial9 Problem Solving on Fixed, Floating Point Arithmetic and Priority Problem Solving
Interrupt
Tutorial10 Problem Solving on Data Transfer Schemes, Program Control and Problem Solving
Interrupts
Tutorial11 Problem Solving on Direct Memory Access and Memory Hierarchy Problem Solving
Tutorial12 Problem Solving on Cache Memory, Associative Memory and Problem Solving
Virtual Memory
Tutorial13 Problem Solving on Memory Management and Pipelining Problem Solving
Tutorial14 Problem Solving on Interconnection Structure, Inter processor Problem Solving
Arbitration and Synchronization