DESIGN AND IMPLEMENTATION OF RS FEC SUB

LAYER USING INVERSION LESS BERLEKAMP-MASSEY

ALGORITHM
A dissertation submitted in the partial fulfilment of the academic
requirements for the award of degree of

Bachelor of Engineering

in

Electronics and Communication Engineering

By
NAVYA CHERUPALLY 100514735020

BHARATH MULAGONDLA 100514735024

Under the guidance of

Internal Guide:

Dr. B. RAJENDRA NAIK (ASSOSCIATE PROFFESOR, DEPARTMENT OF ECE, UCE,

OU)

External Guides:

Mr. SAILESH RUPANI (Sr. MANAGER, DESIGN, MICROSEMI COMMUNICATIONS

INDIA LTD., PUNJAGUTTA, HYD.)

Mr. REVANTH KAMARAJ (MTS, DESIGN, MICROSEMI COMMUNICATIONS INDIA

LTD., PUNJAGUTTA, HYD.)

Department of Electronics and Communication Engineering

University College of Engineering (Autonomous)
Osmania University, Hyderabad-500007
2017-2018
 Department of Electronics and Communication Engineering

University College of Engineering (Autonomous)

Osmania University, Hyderabad-500007

Certificate

This is to certify that the Major project report titled

Design and Implementation of RS FEC Sub layer using Inversion
less Berlekamp-Massey Algorithm submitted by NAVYA
CHERUPALLY (roll no.100514735020) and BHARATH MULAGONDLA
(Roll no. 100514735024), students of Department of Electronics and
Communication Engineering, University College of Engineering, as part of the
Major Project, during the academic year 2017–2018.

Dr. B. Rajendra Naik Prof. P. Chandra Sekhar

Associate Professor Head of the Department
ECE Dept., UCE, OU ECE Dept., UCE, OU
(Project Supervisor)
 DECLARATION

We hereby declare that the results in this dissertation work entitled

“Design and Implementation of RS FEC Sub layer using
Inversion less Berlekamp-Massey Algorithm” is the bonafide work
done and carried out by us during the year 2016-17 in partial fulfilment of the
academic requirements for the award of Bachelor of Engineering in
Electronics and Communication Engineering from University College of
Engineering, OSMANIA UNIVERSITY, Hyderabad.

Further, we declare that the report has not been submitted by us to

any other institute or university for award of any other degree.

NAVYA CHERUPALLY BHARATH MULAGONDLA

(1005-14-735020) (1005-14-735024)
 ACKNOWLEDGEMENT

We express our deep sense of gratitude to our internal guide Dr.B.Rajendra

Naik (Associate Professor, Department of Electronics and Communication Engineering,
UCE-OU, Hyderabad) for his counsel, constant supervision and also for his support throughout
the project work. I sincerely thank her for motivating us to do the best and complete the project
successfully.
We gratefully acknowledge Dr. P. Chandrasekhar, Head, Department of Electronics
and Communication Engineering for his impulse and support during course of this work.
Our sincere thanks to Prof. Sameen Fatima, Principal, University college of
Engineering, Osmania University(A) for providing the support to carry out my project.
We would like to express our special thanks to Mr.Sailesh Rupani (Manger-Design,
Microsemi Communications India Limited) who gave us opportunity and kind support to carry
out our project at Microsemi Communications. We express our profound sense of veneration
and gratefulness to our external guide Mr. Revanth Kamaraj (MTS-Design, Microsemi
Communications India limited) who provided us erudite advice, momentum and useful
discussion. We gratefully acknowledge him for spending a time out of his busy schedule and
helping us to complete the project successfully.
Finally, we thank all our respective family members as well as friends for their
encouragement and all those who directly or indirectly helped us in this regard.

NAVYA CHERUPALLY BHARATH MULAGONDLA

(1005-14-735020) (1005-14-735024 )
 ABSTRACT

The IEEE 802.3 (Ethernet) standard specifies a networking protocol that allows multiple
devices connected to the network to communicate with each other. The PHY Coding
Sublayer (PCS) is a part of the physical layer of the Ethernet stack which performs
encoding/decoding and error correction and communicates the same to the MAC. On the
egress, the PCS accepts data from the MAC and sends encoded data to the serializer while
on the ingress, the PCS accepts data from the deserializer and provides decoded data to the
MAC.

As speeds of the backplane (BASE-R) Ethernet increase, the BER (Bit Error Rate) also goes
up. In the absence of a FEC scheme, the time taken by the Ethernet subsystem to identify
errors is large. It would be advantageous to detect and correct a reasonable subset of possible
errors as early as possible to greatly reduce the occurrence of retransmission which in turn
increases the efficiency of the link. By adding a FEC scheme like Reed Solomon coding to
traditional Ethernet, effective BER is significantly reduced. To allow error correction as
early as possible in the stack, the PCS sublayer must implement the FEC.

The RS-FEC scheme implemented allows for correction of 140-bit errors every 5280-bits
(BER of approximately up to 13 x 10-3). A method has also been proposed to predict variable
ingress and egress latency due to transcoding and gearbox conversion which will be useful
in MAC timestamping.
CONTENTS

LIST OF TABLES
LIST OF FIGURES
LIST OF ABBREVIATIONS

CHAPTER 1
INTRODUCTION................................................................................................................................. 1
1.1 Introduction ................................................................................................................................... 1
1.2 Objective ....................................................................................................................................... 2
1.3 Motivation ..................................................................................................................................... 2
1.4 Information and Coding Theory ................................................................................................... 2
1.5 Hardware solution ......................................................................................................................... 5
1.6 Superiority of RSFEC ................................................................................................................... 5
1.6 Overview of Report....................................................................................................................... 6
CHAPTER 2
PHYSICAL CODING SUBLAYER (PCS)......................................................................................... 7
2.1 INTERCONNECTION BETWEEN MODELS & LAYERS ....................................................... 7
2.2 CODES & BLOCK STRUCTURES .......................................................................................... 10
2.3 TRANSMISSION ....................................................................................................................... 14
2.4 RECEPTION............................................................................................................................... 17
CHAPTER 3
GALOIS FIELD & CYCLIC CODES .............................................................................................. 19
3.1 Galois Field (GF) .................................................................................................................. 19
3.1.1 Properties of Galois Field ................................................................................................. 19
3.1.2 Galois Field GF (2m) ............................................................................................................ 20
3.1.3 Representation of Galois Field Elements ............................................................................. 22
3.1.4 Basis of Galois Field GF (2m) .............................................................................................. 23
3.1.5 Implementation of GF (2m) Arithmetic ................................................................................ 24
3.1.6 Russian Peasant Multiplication algorithm ........................................................................... 25
3.2 Cyclic Codes ............................................................................................................................... 26
3.2.1 Description ........................................................................................................................... 26
3.2.2 Code words in Polynomial Forms ........................................................................................ 26
3.2.3 Generator Polynomial of a Cyclic Code ....................................................................... 26
3.2.4 Generation of Cyclic Codes in Systematic Form .......................................................... 27
 3.3 Properties of Reed-Solomon Codes ...................................................................................... 28
3.4 Applications of Reed-Solomon Codes .................................................................................. 30

CHAPTER 4
REED SOLOMON ENCODING....................................................................................................... 31
4.1 Rate compensation for codeword markers in the transmit direction ........................................... 31
4.2 64B/66B to 256B/257B transcoder ............................................................................................. 31
4.3 Codeword marker insertion........................................................................................................ 33
4.4 Reed-Solomon Encoding ............................................................................................................ 34
4.5 Systematic Encoding ................................................................................................................... 34
4.6 Reed-Solomon encoder ............................................................................................................... 36
CHAPTER 5
REED SOLOMON DECODING....................................................................................................... 38
5.1 Lock FSM ................................................................................................................................... 38
5.2 Error Detection “Syndrome Calculation” ............................................................................. 39
5.3 The Decoding Algorithm ............................................................................................................ 40
5.3.1Decoding of RS Codes Using Berlekamp-Massey Algorithm .............................................. 41
5.4 Chien Search Calculation ............................................................................................................ 48
5.5 Forney Algorithm........................................................................................................................ 49
5.6 256B/257B to 64B/66B transcoder ............................................................................................ 50
CHAPTER 6
IMPLEMENTATION& VERIFICATION ...................................................................................... 52
6.1 DESIGN OF RSFEC................................................................................................................... 52
6.2 REGISTER DESCRIPTION....................................................................................................... 56
6.3VERIFICATION.......................................................................................................................... 58
6.3.1 TESTBENCH ARCHITECTURE ....................................................................................... 58
6.3.2 SIMULATION RESULTS .................................................................................................. 59
6.4 SYNTHESIS REPORT ............................................................................................................... 65
CHAPTER 7
CONCLUSION & SCOPE ................................................................................................................. 67
7.1 Conclusion .................................................................................................................................. 67
7.2 Future Scope ............................................................................................................................... 67
ANNEX -RS-FEC code word examples ............................................................................................ 68
A.1 Input to the 64B/66B to 256B/257B transcoder ......................................................................... 68
A.2 Output of the RS (528,514) Encoder.......................................................................................... 69
REFERENCES .................................................................................................................................... 70
LIST OF TABLES

Table 1-4-1 : Codeword after only source coding…………………………………….2

Table 1-4-2 : Codeword after source coding and channel coding…………………….3

Table 1-6-1 : Comparison of RS-FEC (Clause 91 ), KR-FEC (Clause 74)…………...5

Table 2-2-1 : 64B/66B block formats………………………………………………...11

Table 2-2-2 : Control codes……………………………………………………...…...12

Table 3-1-1 : Modulo-2 addition (XOR operation) ………………………………….19

Table 3-1-2 : Modulo-2 Multiplication (AND operation) …………………………...20

Table 3-3 : Different representations of GF (23) elements…………………………22

Table 5-1 : B–M algorithm table for determining the error-location polynomial….46

Table A-1 : 64B/66B to 256B/257B transcoder input……………………………...68

Table A-2 : RS (528,514) code word……………………………………………….69

LIST OF FIGURES

Figure 1-4-1 : A communication system: source and channel coding……………....3

Figure 1-4-2 : Systematic form of a codeword of a linear block code………………4

Figure 2–1 : 25GBASE-R PCS relationship to the ISO/IEC Open Systems

Interconnection (OSI) reference model and IEEE 802.3 Ethernet model…7

Figure 2-1-2 : Functional block diagram…………………………………………….9

Figure 2–3-1 : PCS Transmit bit ordering…………………………………………...15

Figure 2-3-2 : Scrambler…………………………………………………………….16

Figure 2-4-1 : PCS Receive bit ordering…………………………………………….17

Figure 2-4-2 : Descrambler………………………………………………………….18

Figure 3-3-1 : A codeword of 255 bytes disturbed by 128-bit noise burst………….29

Figure 4-2-1 : Examples of the construction of tx_xcoded……………………….…32

Figure 4-3-1 : Alignment marker format…………………………………………….33

Figure 4-4-1 : The information bit sequence divided into symbols. ………….…….34

Figure 4-5-1 : A codeword is formed from message and parity symbols. ….……....34

Figure 4-6-1 : Reed-Solomon encoder functional model………………….……...…37

Figure 5-1 : Block Diagram of RS Decoder…………………………….…………38

Figure 5-1-1 : FEC synchronization state diagram…………………….…………….39

LIST OF ABBREVIATIONS

PMA PHYSICAL MEDIUM ATTACHMENT

PCS PHYSICAL CODING SUBLAYER
RSFEC REED SOLOMON FORWARD ERROR CORRECTION
XGMII 25 GIGABIT MEDIA INDEPENDENT INTERFACE
BMA BERLEKAMP MASSEY ALGORITHM
BER BIT ERROR RATE
CD COMPACT DISC
DVD DIGITAL VIDEO DISC
KRFEC KR FORWARD ERROR CORRECTION
QR QUICK RESPONSE CODE
DSL DIGITAL SUBSCRIBER LINE
WiMAX WORLDWIDE INTEROPERABILITY FOR MICROWAVE ACCESS
DVB DIGITAL VIDEO BROADCASTING
ATSC ADVANCED TELEVISION SYSTEMS COMMITTEE
MAC MEDIA ACCESS CONTROL
IEEE INSTITUTE OF ELECTRICAL AND ELECTRONIC ENGINEERS
GF GALOIS FIELD
ARQ AUTOMATIC REPEAT REQUEST
ASIC APPLICATION SPECIFIC INTEGRATED CIRCUIT
FPGA FIELD PROGRAMMABLE GATE ARRAY
NRZ NON-RETURN TO ZERO
MTTFPA MEAN TIME TO FALSE PACKET ACCEPTANCE
TXD TRANSMITTED DATA WORD
TXC TRANSMITTED CONTROL WORD
RXD RECEIVED DATA WORD
RXC RECEIVED CONTROL WORD
LPI LOW POWER IDLE
WIS WAN INTERFACE SUBLAYER
 1

CHAPTER 1

INTRODUCTION
1.1 Introduction
The IEEE 802.3 (Ethernet) standard specifies a networking protocol that allows
multiple devices connected to the network to communicate with each other. The Physical
Coding Sublayer (PCS) is a part of the physical layer of the Ethernet model. It resides at the
top of the physical layer (PHY), and provides an interface between the Physical Medium
Attachment (PMA) sublayer and the Media Independent Interface (MII). It is responsible for
data encoding/decoding, scrambling/descrambling, alignment marker insertion/removal, block
and symbol redistribution, and lane block synchronization and deskew. It transmits the data in
a protected form by providing security at a physical level which is important in this modern
day internet world where hackers try to steal the information. Apart from all these functions
the data from PCS is encoded using a special Forward Error Correction (FEC) technique called
Reed Solomon FEC.

This whole process of encoding and decoding is done in a separate layer called FEC
Sublayer. Generally, for 10G Ethernet (speeds up to 10 Gigabits per second) applications this
is implemented using KR-FEC also called as Fire Codes. But as the bit rates increase, KRFEC
cannot be used since Error Probability or Bit Error Rate (BER) on the lane also increases we
need to employ RS-FEC. The RS-FEC is based on Reed Solomon Codes which have many
applications in areas other than Ethernet like CDs, DVDs, Blu-ray Discs, QR Codes, data
transmission technologies such as DSL and WiMAX, broadcast systems such
as DVB and ATSC, and storage systems such as RAID 6. They are also used in satellite
communication.

In Coding Theory, the Reed-Solomon code belongs to the class of non-binary

cyclic error-correcting codes. The Reed–Solomon code is based on uni-variate
polynomials over finite fields. It can detect and correct multiple symbol errors. By
adding t check symbols to the data, a Reed–Solomon code can detect any combination of up
to t erroneous symbols or correct up to ⌊t/2⌋ symbols. As an erasure code, it can correct up
to t known erasures, or it can detect and correct combinations of errors and erasures. Reed–
Solomon codes are also suitable as multiple-burst bit-error correcting codes, since a sequence
of b + 1 consecutive bit errors can affect at most two symbols of size b. The choice of t is up
to the designer of the code and may be selected within wide limits.

This report focuses on our implementation of RSFEC sublayer along with PCS
Sublayer which is a leading-edge technology in Ethernet Applications Industries.
 2

1.2 Objective
To improved Error Correction Capability of IEEE 802.3 Ethernet by using Reed
Solomon FEC Coding. To use Inversion less Berlekamp Massey Algorithm which reduces the
need of complex inverters thereby reducing the complexity of the Decoder circuit. To also
reduce the variable data rates which are main concerns of MAC timestamping thereby
providing accurate timestamps.

1.3 Motivation
For designing of RS-FEC sublayer we used RS (528,514) code with m=10 and t = 14.
We used symbols which are Galois field elements GF (210 ) and 10-bits wide. The 14 check
symbols we add to a codeword block provided us a error correcting capability of 7 symbols
per codeword. This can be seen as correcting capability of 70 bits for every 5280 bits. This is
a huge improvement in reducing the bit error rate as it can handle up to 13 x 10-3. RS-FEC
layer is very important in Ethernet above 25G as it corrects the errors as early as possible
thereby reducing the retransmission requests from the MAC which in turn reduces the delay
in transmission.

1.4 Information and Coding Theory

Information theory analyses the communication between a transmitter and a receiver
through an unreliable channel. We can divide the information theory into two main parts,
the first part is used to analysis sources information, especially the information produced by
a given source, and, the second part states the conditions for performing reliable
transmission through an unreliable channel. One of the most used techniques in information
theory is called “Coding”, which is used to optimize transmission and to make efficient use
of the capacity of a given channel. In general, coding is a technique used to transmit a set of
messages in a set of binary bits called code words. This called “Source coding”, see an
example in Table 1-1, in this table we have four symbol messages and we coded each
symbol by two bits and this is called source coding. We notice that the optimum number of
bits to represent the messages is two bits and if we increased these bits, the effective rate
will be decreased. If these symbols are transmitted through a noisy channel, an error may
occur and the symbol may be decoded as another symbol leading to an undetectable error.

Table 1-4-1: Codeword after only source coding

MESSAGES CODEWORDS

S0 00

S1 01

S2 10

S3 11
 3

Table 1-4-2: Codeword after source coding and channel coding

MESSAGES BINARY CODEWORDS

MESSAGES

S0 00 0000

S1 01 0101

S2 10 1010

S3 11 1111

Figure 1-4-1: A communication system: source and channel coding

So another coding block is needed called channel coding which adds parity check bits
to each message to make a distance between valid code words as shown in Table 1-2. When
we increase the parity check length the distance between each two code words is increased
and the probability of error is decreased but the effective rate is decreased, so it is a trade-
off between the rate and the probability of error. A block diagram of a communication
system as related to information theory is shown in Figure 1-1.

The block diagram seen in Figure 1-1 shows two types of encoders/decoders

. • Source encoder/decoder.

• Channel encoder/decoder

In previous years there were an increasing interest in the reliability of data transmission
and storage mediums, as if a single error happened all the system may be damaged due to
 4

an unacceptable corruption for the data, e.g. in a bank account. The simplest way of
detecting a single error is a parity check sum. But in some applications this method is not
sufficient and different methods must be implemented.

If the transmission system transmits data in both directions, an error control strategy
may be determined by detecting an error and then, if an error is occurred, retransmitting the
corrupted data. These systems are called Automatic Repeat Request (ARQ). If transmission
transfers data in only one direction, e.g. information recorded on a compact disk, the only
way to control the error is with Forward Error Correction (FEC). In FEC systems some
redundant data is concatenated with the information data in order to allow for the detection
and correction of the corrupted data without having to retransmit it.

Error control coding mechanism is done in two inverse operations. The first one is a
mechanism of adding redundancy bits to the message and form a code word, this operation
called encoding operation, the second operation is excluding the redundancy bits from the
code word to achieve the message and this operation called decoding operation.

These types of codes are called block codes and are denoted by C (n, k). The rate of
the code, R = k/n, where k represents the message bits and n represents the coded bits. Since
the 2*k messages are converted into code words of n bits. This encoding procedure can be
understood a conversion from message vector of k bits located in space of size 2*k to a
coded vector of size n bits in a space of size, and 2*k only selected to be valid code words.

Linear block codes are considered the most common codes used in channel coding
techniques. In this technique, message words are arranged as blocks of k bits, constituting a
set of 2*k possible messages. The encoder takes each block of k bits, and converts it into a
longer block of n > k bits, called the coded bits or the bits of the code word. In this procedure
there are (n−k) bits that the encoder adds to the message word, which are usually called
redundant bits or parity check bits. The code words generated from the encoder is linearly
combined as the summation of any two code word is an existing code word so it is called
Linear Block Codes.

k bits message (n-k) bits parity check

n bit code word

Figure 1-4-2: Systematic form of a codeword of a linear block code

In this case, the first k bits are the message bits as it is and the remaining (n − k) bits
are called parity check or redundancy bits. The structure of a codeword in systematic form
is shown in Figure 1-3-1.
 5

In this thesis, the message bits are converted into symbols “non-binary code” called
Reed Solomon (RS) code which is a special type of cyclic code which will be explained
briefly in chapter 2. The message symbols are placed at the beginning of the codeword,
while the redundancy symbols are placed at the end of the codeword.

1.5 Hardware solution

Last years, implementation of Reed Solomon decoders was using Digital Signal
Processors (DSP) micro controllers, which are based on microprocessors but specialized in
signal processing. Recently, Field Programmable Gate Arrays (FPGAs) are used for these
applications, as they provide similar performance with more customized design.

FPGAs are customizable logic devices, as they give fast solution for specific problems.
FPGAs are considered a good step towards the ASIC design which is the most optimum
way in area, power consumption, and price. The solution we provided can be implemented
using a ASIC or FPGA.

1.6 Superiority of RSFEC

RSFEC despite its complexity compared to KRFEC is used in 25G/100G Ethernet
applications as it improves the maximum allowable BER thereby reducing the latency in
transmission. In Backplane/ Copper cable NRZ PHY RSFEC is important as it uses a
256/257B transcoding which results in no increase of line rate.

• Our implementation also provides accurate timestamps for the MAC as we used Rate
Compensators to provide a constant data rate over any period of time.
• It also solves MTTFPA concerns when sending un-encoded 64B/66B data with 5
lane bit interleaving on a 25G lane.
• No Auto Negation Needed
• ~4.9 dB of gain at 10-15 output BER assuming burst errors due to DFE
• ~5.3 dB of gain at 10-12 output BER assuming random errors
• It can be implemented for 100G on 4 lanes achieving maximum bandwidth.

Table 1-6-1 Comparison of RS-FEC (Clause 91 ), KR-FEC (Clause 74)[2]

 6

1.6 Overview of Report

The organization of this thesis is as follows. In Chapter 2, designing of PCS layer (Both
TX and RX) is explained. In Chapter 4, introduction to Reed Solomon (RS) codes and their
properties and applications and Galois Fields will be discussed, then RS encoder is
presented in Chapter 5. In Chapter 6, the general architecture of RS decoder is discussed,
then the decoding algorithm of Berlekamp Massey and Euclidean Algorithms are discussed.
The decomposed inversion less Berlekamp Massey algorithm with a new architecture called
the decomposed inversion less Berlekamp Massey architecture is discussed, finally, the
simulation results and synthesis reports and comparison between these proposals and the
other architectures are discussed. In Chapter 6, our implementation of RS encoder and
decoder are discussed. Chapter 7 provides the conclusion and scope of project. Annex
provides the example inputs & outputs of a transcoder.
 7

CHAPTER 2
PHYSICAL CODING SUBLAYER (PCS)

2.1 INTERCONNECTION BETWEEN MODELS & LAYERS

Figure 2–1:25GBASE-R PCS relationship to the ISO/IEC Open Systems

Interconnection (OSI) reference model and IEEE 802.3 Ethernet model[1]

MDI = MEDIUM DEPENDENT INTERFACE

PCS = PHYSICAL CODING SUBLAYER

PHY = PHYSICAL LAYER DEVICE

PMA = PHYSICAL MEDIUM ATTACHMENT

PMD = PHYSICAL MEDIUM DEPENDENT

WIS = WAN INTERFACE SUBLAYER

XGMII = 25 GIGABIT MEDIA INDEPENDENT INTERFACE

Encoding:

R = 64B/66B ENCODED WITHOUT WIS, W = 64B/66B ENCODED WITH WIS

 8

WAN Interface Sublayer (WIS)

The WIS provides a medium-independent means for the PCS to operate over WAN
links. It creates a 25GBASE-W encoding by encapsulating the encoded data steam from the
25GBASE-R PCS in frames compatible with SONET and SDH transmission formats[1].

Physical Medium Attachment (PMA) sublayer

The PMA provides a medium-independent means for the PCS to support the use of a
range of physical media[1]. The 25GBASE-R PMA performs the following functions:

a) Mapping of transmit and receive data streams between the PCS or WIS and PMA via the
PMA service interface.

b) Serialization (deserialization) of bits for transmission (reception) on the underlying serial

PMD.

c) Recovery of clock from the received data stream.

d) Mapping of transmit and receive bits between the PMA and PMD via the PMD service
interface.

e) Optionally provides data loopback at the PMA service interface

Physical Medium Dependent (PMD) sublayer

The MDI, logically subsumed within each PMD sub clause, is the actual medium
attachment for the various supported media[1].

Inter-sublayer interfaces

There are a number of interfaces employed by 25GBASE-R. Some (such as the PMA
service interface) use an abstract service model to define the operation of the interface. The
XGMII has an optional physical instantiation.

Figure 2-1-2 depicts the relationship and mapping of the services provided by all of
the interfaces relevant to 25GBASE-R.

The upper interface of the PCS may connect to the Reconciliation Sublayer through
the XGMII or the PCS may connect to an XGXS sublayer. The XGXS and the
Reconciliation Sublayer provide the same service interface to the PCS. The lower interface
of the PCS may connect to the WIS to support a WAN PMD or to the PMA sublayer to
support a 25GBASE-R LAN PMD[1].
 9

Figure 2-1-2: Functional block diagram

PCS service interface (XGMII)

The PCS service interface allows the 25GBASE-R PCS to transfer information to and
from a PCS client. A PCS client is generally the Reconciliation Sublayer or an XGXS
sublayer[1].

Functions within the PCS

The PCS comprises the PCS Transmit, Block Synchronization, PCS Receive, and BER
monitor processes for 25GBASE-R. The PCS shields the Reconciliation Sublayer (and
MAC) from the specific nature of the underlying channel. The PCS transmit channel and
receive channel can each operate in normal mode or, when not attached to a WIS, test-
pattern mode. When the PCS is attached to a WIS, the WIS provides the test-pattern
functionality [1].

When communicating with the XGMII, the PCS uses a four octet-wide, synchronous
data path, with packet delimiting being provided by transmit control signals (TXCn = 1) and
receive control signals (RXCn = 1). When communicating with the PMA or WIS, the PCS
 10

uses a 32-bit wide, synchronous data path that conveys 32 encoded bits. Alignment to
64B/66B block is performed in the PCS. The WIS and PMA sublayers operate independent
of block and packet boundaries. The PCS provides the functions necessary to map packets
between the XGMII format and the PMA service interface format [1].

When the transmit channel is in normal mode, the PCS Transmit process continuously
generates blocks based upon the TXD and TXC signals on the XGMII. The Gearbox
function of the PCS Transmit process then packs the resulting bits into 40-bit transmit data-
units. Transmit data-units are sent to the PMA or WIS service interface via the
PMA_UNITDATA.request or WIS_UNITDATA.request primitive, respectively. When the
WIS is present, the PCS Transmit process also adapts between the XGMII and WIS data
rates by deleting idle characters[1].

Use of blocks

The PCS maps XGMII signals into 66-bit blocks, and vice versa, using a 64B/66B
coding scheme. The synchronization headers of the blocks allow establishment of block
boundaries by the PCS Synchronization process. Blocks are unobservable and have no
meaning outside the PCS. The PCS blocks ENCODER and DECODER generates,
manipulates, and interprets blocks[1].

2.2 CODES & BLOCK STRUCTURES

Block structure

Blocks consist of 66 bits. The first two bits of a block are the synchronization header
(sync header). Blocks are either data blocks or control blocks. The sync header is 01 for
data blocks and 10 for control blocks.

Thus, there is always a transition between the first two bits of a block. The remainder
of the block contains the payload. The payload is scrambled, and the sync header bypasses
the scrambler. Therefore, the sync header is the only position in the block that always
contains a transition. This feature of the code is used to obtain block synchronization.

Data blocks contain eight data characters. Control blocks begin with an 8-bit block type
field that indicates the format of the remainder of the block. For control blocks containing
a Start or Terminate character, that character is implied by the block type field. Other control
characters are encoded in a 7-bit control code or a 4-bit O Code. Each control block contains
eight characters[1].

The format of the blocks is as shown in Table 2-2-1. In the figure, the column labelled
Input Data shows, in abbreviated form, the eight characters used to create the 66-bit block.
These characters are either data characters or control characters and, when transferred across
the XGMII interface, the corresponding TXC or RXC bit is set accordingly. Within the Input
Data column, D0 through D7 are data octets and are transferred with the corresponding TXC
or RXC bit set to zero. All other characters are control octets and are transferred with the
 11

corresponding TXC or RXC bit set to one. The single bit fields (thin rectangles with no
label in the Table 2-2-1) are sent as zero and ignored upon receipt [1].

Bits and field positions are shown with the least significant bit on the left. Hexadecimal
numbers are shown in normal hexadecimal. For example, the block type field 0x1e is sent
as 01111000 representing bits 2 through 9 of the 66-bit block. The least significant bit for
each field is placed in the lowest numbered position of the field.

All unused values of block type field are reserved.

Control codes

The same set of control characters are supported by the XGMII and the 25GBASE-R PCS.
The representations of the control characters are the control codes. XGMII encodes a control
character into an octet (an eight-bit value). The 25GBASE-R PCS encodes the start and
terminate control characters implicitly by the block type field. The 25GBASE-R PCS
encodes the ordered set control codes using a combination of the block type field and a 4-
bit O code for each ordered set. The 25GBASE-R PCS encodes each of the other control
characters into a 7-bit C code [1].

Table 2-2-1:64B/66B block formats

 12

The control characters and their mappings to 25GBASE-R control codes and XGMII
control codes are specified in Table 2-2-2. All XGMII and 25GBASE-R control code values
that do not appear in the Table 2-2-2 shall not be transmitted and shall be treated as an error
if received.

Ordered Sets

Ordered sets are used to extend the ability to send control and status information over
the link such as remote fault and local fault status. Ordered sets consist of a control character
followed by three data characters. Ordered sets always begin on the first octet of the XGMII.
The sequence ordered set control character is denoted /Q/. An additional ordered set, the
signal ordered set, has been reserved and it begins with another control code. The 4-bit O
field encodes the control code. See Table 1-2-2 for the mappings.

Valid and invalid blocks

A block is invalid if any of the following conditions exists:

a) The sync field has a value of 00 or 11.

b) The block type field contains a reserved value.

c) Any control character contains a value not in Table 2-2-2.

d) Any O code contains a value not in the table 2-2-2.

e) The set of eight XGMII characters does not have a corresponding block format in Table
2-2-1.

Table 2-2-2: Control codes

 13

Idle (/I/) and Low Power Idle (/LI/)

Idle control characters (/I/) are transmitted when idle control characters are received
from the XGMII. Idle characters may be added or deleted by the PCS to adapt between clock
rates. /I/ insertion and deletion shall occur in groups of 4. /I/s may be added following idle or
ordered sets. They shall not be added while data is being received. When deleting /I/s, the first
four characters after a /T/ shall not be deleted.

To communicate LPI, LPI control character /LI/ is sent continuously in place of /I/. LPI
control characters are transmitted when LPI control characters are received from the XGMII.
LPI characters may be added or deleted by the PCS to adapt between clock rates in a similar
manner to idle control characters. /LI/ insertion and deletion shall occur in groups of four. /LI/s
may only be added following other LPI characters [1].

Start (/S/)

The start controls character (/S/) indicates the start of a packet. This delimiter is only
valid on the first octet of the XGMII (TXD<0:7> and RXD<0:7>). Receipt of an /S/ on any
other octet of TxD indicates an error. Block type field values implicitly encode an /S/ as the
fifth or first character of the block. These are the only characters of a block on which a start
can occur.

Terminate (/T/)

The terminate control character (/T/) indicates the end of a packet. Since packets may
be any length, the /T/ can occur on any octet of the XGMII interface and within any character
of the block. The location of the /T/ in the block is implicitly encoded in the block type field.
A valid end of packet occurs when a block containing a /T/ is followed by a control block
that does not contain a /T/.

Ordered set (/O/)

The ordered set control characters (/O/) indicate the start of an ordered set. There are
two kinds of ordered sets: the sequence ordered set and the signal ordered set (which is
reserved). When it is necessary to designate the control character for the sequence ordered
set specifically, /Q/ will be used. /O/ is only valid on the first octet of the XGMII. Receipt
of an /O/ on any other octet of TXD indicates an error. Block type field values implicitly
encode an /O/ as the first or fifth character of the block. The 4-bit O code encodes the
specific /O/ character for the ordered set.

Sequence ordered sets may be deleted by the PCS to adapt between clock rates. Such
deletion shall only occur when two consecutive sequence ordered sets have been received
and shall delete only one of the two. Only Idles may be inserted for clock compensation.
Signal ordered sets are not deleted for clock compensation.
 14

Error (/E/)

The /E/ is sent whenever an /E/ is received. It is also sent when invalid blocks are
received. The /E/ allows physical sublayers such as the XGXS and PCS to propagate
received errors [1].

2.3 TRANSMISSION
64B/66B transmission code

The PCS uses a transmission code to improve the transmission characteristics of

information to be transferred across the link and to support transmission of control and data
characters. The encodings defined by the transmission code ensure that sufficient transitions
are present in the PHY bit stream to make clock recovery possible at the receiver. The
encoding also preserves the likelihood of detecting any single or multiple bit errors that may
occur during transmission and reception of information. In addition, the synchronization
headers of the code enable the receiver to achieve block alignment on the incoming PHY
bit stream. The 64B/66B transmission code specified for use in this standard has a high
transition density and is a run-length-limited code.

The relationship of block bit positions to XGMII, PMA, and other PCS constructs is
illustrated in Figure 2–3-1 for transmit and Figure 2–4-1 for receive. These figures illustrate
the processing of a block containing 8 data octets. See Table 2-2-1 for information on how
blocks containing control characters are mapped. Note that the sync header is generated by
the encoder and bypasses the scrambler.

Notation conventions

For values shown as binary, the leftmost bit is the first transmitted bit.

64B/66B encodes 8 data octets or control characters into a block. Blocks containing
control characters also contain a block type field. Data octets are labelled D0 to D7. Control
characters other than /O/, /S/ and /T/ are labelled C0 to C7. The control character for ordered
set is labelled as O0 or O4 since it is only valid on the first octet of the XGMII. The control
character for start is labelled as S0 or S4 for the same reason. The control character for
terminate is labelled as T0 to T7.

Two consecutive XGMII transfers provide eight characters that are encoded into one
66-bit transmission block. The subscript in the above labels indicates the position of the
character in the eight characters from the XGMII transfers.

Contents of block type fields, data octets and control characters are shown as
hexadecimal values. The LSB of the hexadecimal value represents the first transmitted bit.
For instance, the block type field 0x1e is sent from left to right as 01111000. The bits of a
transmitted or received block are labelled TxB<65:0> and RxB<65:0> respectively where
TxB<0> and RxB<0> represent the first transmitted bit. The value of the sync header is
 15

shown as a binary value. Binary values are shown with the first transmitted bit (the LSB)
on the left.

Transmission order

Block bit transmission order is illustrated in Figure 2-3-1 and Figure 2-4-1. Note that
these figures show the mapping from XGMII to 64B/66B block for a block containing eight
data characters [1].

Figure 2–3-1: PCS Transmit bit ordering

TRANSMIT PROCESS

The transmit process generates blocks based upon the TXD<31:0> and TXC<3:0>
signals received from the XGMII. Two XGMII data transfers are encoded into each block.
 16

It takes PMA_UNITDATA or WIS_UNITDATA transfers to send a block of data.

Therefore, if the PCS is connected to an XGMII and PMA sublayer where the ratio of their
transfer rates is exactly 16:33, then the transmit process does not need to perform rate
adaptation. Where the XGMII and PMA sublayer data rates are not synchronized to that
ratio, the transmit process will need to insert idles, delete idles, or delete sequence ordered
sets to adapt between the rates. The WIS data rate is always slower than the XGMII data
rate and a PCS connected to a WIS must delete idles or sequence ordered sets to adapt
between rates [1].

The transmit process generates blocks as specified in the transmit process state diagram.
The contents of each block are contained in a vector tx_coded<65:0>, which is passed to
the scrambler. tx_coded<1:0>contains the sync header and the remainder of the bits contain
the block payload.

Scrambler

The payload of the block is scrambled with a self-synchronizing scrambler. The

scrambler shall produce the same result as the implementation shown in Figure 2-3-2. This
implements the scrambler polynomial

There is no requirement on the initial value for the scrambler. The scrambler is run
continuously on all payload bits. The sync header bits bypass the scrambler [1].

Figure 2-3-2: Scrambler

Gearbox
The gearbox adapts between the 66-bit width of the blocks and the N-bit width of the
PMA or WIS interface. It receives the 66-bit blocks. When the transmit channel is operating
in normal mode, the gearbox sends N bits of transmit data at a time via
WIS_UNITDATA.request or PMA_UNITDATA.request primitives. The
UNITDATA.request primitives are fully packed with bits. For example, if one block
happened to start with the sync header on bits 0 and 1 of a PMA_UNITDATA.request, then
 17

the last two bits of that block would be on bits 0 and 1 of a PMA_UNITDATA.request and
the next block would begin with a sync header on bits 2 and 3 of that
PMA_UNITDATA.request.

When a PMA_UNITDATA.request or WIS_UNITDATA.request contains bits from

two blocks, then the bits from the first block shall be placed in the lowest numbered bits of
tx_data-group<N-1:0>. The bits shall be packed into the tx_data-group in sequence with the
lowest numbered bit of the block going into the lowest numbered bit of the part of tx_data-
group<N-1:0> bits containing bits from that block[1] (see Figure 2-3-1).

The gearbox functionality is necessary when the optional PMA compatibility interface,
XSBI, is implemented since that interface passes data over a N-bit wide path. It is also
necessary when connecting to a WIS since the WIS processes the data stream with 8-bit
granularity. When neither the WIS nor the XSBI is implemented, the internal data-path
width between the PCS and PMA is an implementation choice. Depending on the path
width, the gearbox functionality may not be necessary.

2.4 RECEPTION

Figure 2-4-1: PCS Receive bit ordering

 18

Receive process
Gearbox

The gearbox adapts between the N-bit width of the blocks and the 66-bit width of the
PMA or WIS interface. It receives the N-bit blocks. When the transmit channel is operating
in normal mode, the gearbox sends 66 bits of transmit data at a time via
WIS_UNITDATA.request or PMA_UNITDATA.request primitives.

Descrambler
The descrambler processes the payload to reverse the effect of the scrambler using the
same polynomial. It shall produce the same result as the implementation shown in Figure
2–4-2.

Figure 2-4-2: Descrambler

Decoder
The receive process decodes blocks to produce RXD<31:0> and RXC<3:0> for
transmission to the XGMII.Two XGMII data transfers are decoded from each block. Where
the XGMII and PMA sublayer data rates are not synchronized to a 16:33 ratio, the receive
process will insert idles, delete idles, or delete sequence ordered sets to adapt between rates.
The WIS data rate is always slower than the XGMII data rate and a PCS connected to a WIS
will insert idles to adapt between the rates[1].

Conclusion

In this chapter we showed how a PCS layer works in Ethernet Stack and all its encoding and
decoding functions which provide a superior security at the physical level. In the next chapter
we’ll introduce Galois Field which is a basis for the Reed Solomon Codes and theory behind
the Reed Solomon Codes.
 19

CHAPTER 3

GALOIS FIELD & CYCLIC CODES

3.1 Galois Field (GF)
3.1.1 Properties of Galois Field
The main properties of a Galois field [4] are:

• All elements of GF are defined on two operations, called addition and

multiplication.
• The result of adding or multiplying two elements from the Galois field must be
an element in the Galois field.
• Identity of addition “zero” must be exist, such that a + 0 = a for any element a in
the field.
• Identity of multiplication “one” must be exist, such that a∗ 1 = a for any element
a in the field.
• For every element a in the Galois field, there is an inverse of addition element b
such that a + b = 0. This allows the operation of subtraction to be defined as
addition of the inverse.
• For every non-zero element b in the Galois field, there is an inverse of
multiplication element b-1such that bb-1 = 1. this allows the operation of division
to be defined as multiplication by the inverse.
• Both addition and multiplication operations should satisfy the commutative,
associative, and distributive laws.

Galois field GF (2) “Binary Field”

The simplest Galois field is GF (2). Its elements are the set {0, 1} under
modulo-2 algebra. The addition and multiplication tables of GF (2) are shown in
Tables 3-1-1 and 3-1-2.
Table 3-1-1: Modulo-2 addition (XOR operation)

+ 0 1

0 0 1

1 1 0
 20

Table 3-1-2: Modulo-2 Multiplication (AND operation)

X 0 1

0 0 0

1 0 1

There is a one-to-one correspondence between any binary number and a

polynomial with binary coefficients as every binary number can be presented as a
polynomial over GF (2). A polynomial of degree K over GF (2) has the following
general form:

f (x) = f0+ f1X + f2X2+· · ·+fK XK (3.1)

where the coefficient f0……, fk are the elements of GF (2) i.e. it can take only values 0 or 1.
A binary number of (K + 1) bits can be represented as a polynomial of degree K by taking the
coefficients equal to the bits and the exponents of X equal to bit locations. In the polynomial
representation, a multiplication by X represents a shift to the right [4].

For example, the binary number 10011 is equivalent to the following polynomial:

10011 ↔ 1 + 0X + 0X 2 + X 3 + X 4

The first bit (“position zero” the coefficient of X0) is equal to 1, the second
bit (“position one” the coefficient of X) is equal to 0, the third bit (“position two “the
coefficient of X2) is equal to 0, and so on.

3.1.2 Galois Field GF (2m)

Galois field is considered extension to Binary Field[4]. Let us suppose that we wish to
create a finite field GF (q) where q must be a prime number [4,5].

For Example: assume we have GF (8) with the elements of {0, 1, 2, 3, 4, 5, 6, 7}. this
cannot be considered Galois Field as for the reasons:

• There is no multiplicative inverse for all elements in the field (e.g., 6 has no
inverse).
 21

• The identity element under multiplication is not unique for some elements (e.g.,

4 ∗ 1 = 4 ∗ 3 = 4).

So we can construct the GF (2m), where (m is an integer) by taking a primitive

element of the field and assign the symbol α “alpha” to it. The powers of α are from α0
𝑚 −2
to 𝛼 2 , (2m − 1) terms and the last term is zero.

The element α2m_1 will be equal to α0, and higher powers of α will repeat the lower
powers found in the finite field. The best way to understand how to add the powers of
alpha is to examine the case:
𝑚 −1
𝛼2 = α0 = 1

Since in GF (2m) algebra, plus (+) and minus (-) are the same, the last one can be
represented as follows:

𝑚 −1
𝛼2 +1=0

Construction of Galois field GF (2m) elements is based on Field Generator

Polynomial or primitive polynomial called p(X) with degree m, this polynomial mustbe
factor of X n + 1, where n = 2m-1 and should be not only irreducible but also primitive
to guarantee unique elements representation[4].

For example: In GF (23) the factors of (X 7 + 1) are:

3 2
X 7+ 1 = (X + 1) (X 3+ X + 1) (X + X + 1)

Both the polynomials of degree 3 are primitive and can be chosen, so let’s choose
the polynomial shown in equation 3.2

3
p(X) = X + X + 1 (3.2)

This polynomial has no solution in binary field. The primitive element α is the solution for
the primitive polynomial , so equation 3.2 is converted to equation

p(α) = α3+ α + 1 = 0 (3.3)

Since in GF (2m), +1 = −1, α3 can be represented as follows:

α3= 1 + α

So the other non-zero elements of the field are now found to be

 22

4
α = α.α3 = α.(1 + α) = α + α2
5
α
= α.α4 = α.(α + α2) = α2 + α3 = α2 + (1 + α) = 1 + α + α2

α6 = α.α5 = α.(1 + α + α2) = α + α2 + α3 = 1 + α2

α7 = α.α6 = α(1 + α2) = α + α3 = 1 = α0

Note that α7 = α0, and therefore the eight finite field elements (2m = 23 = 8) of GF
(23), generated by equation (3.2), are {0, α0, α1, α 2, α3, α4, α5, α6}, and all elements starting
from α4 to α6 are presented function of α0,α, and α2 which are called the basis of the Galois
field, and this is will be discussed in details in the following sections.

In general, extended Galois field GF (2m) includes 2m elements, where m is the

symbol size (in bits). For example, in ADSL systems, the Galois field is always GF (28)
= GF (256), where m = 8(is fixed number). It is generated by the following primitive
polynomial:

P (X) = 1 + X2 + X3 + X4 + X8 (3.4)

As we said in the previous section that there was a one-to-one mapping between
polynomials over GF (2) and binary numbers, now here in GF (2m) there is one-to-one
mapping between polynomials over GF (2m) and symbols of length m.

Each symbol can be presented in binary form of length m.

3.1.3 Representation of Galois Field Elements

Let α be a primitive element of GF (23) such that the primitive polynomial is given by:

p(α) = α3+ α + 1 = 0 (3.5)

The following table shows three different ways to represent elements in GF (23):

Table 3-3: Different representations of GF (23) elements.

Binary Form
Polynomial
α0, α1, α2
Power Form Form

− 0 000

0 1 100
 23

1 α 010

2 α2 001

3 1+α 110

4 α+α 2 011

5 1 + α + α2 111

6 1 + α2 101

The first column of Table 3-3 represents the powers of α. The second column shows
the polynomial representation of the field elements. This polynomial representation is
obtained from equation 3.5. And the last column of Table 3-3 is the binary
representation of the field elements[8], where the coefficient of α2, α1 and α0, taken from
the second column, are represented as binary numbers and present the basis of the field
and it will be discussed in details in the next section.

3.1.4 Basis of Galois Field GF (2m)

Basis in GF (2m) is a set of m linearly independent symbols which can represent
other symbols with a unique form with a linear combination of these basis based on the
primitive polynomial [8].

Assume that we have β = β0, β1, ..., βm-1is the basis of GF (2m). Let a is any
general element in the field and denoted by (a0, a1, ..., am-1), a can be represented as
shown in equation 3.6.

a =aoβ0+ a1β1+ .... + am−1βm−1 ai∈ GF (2).

(3.6)

There are a large number of possible basis for any GF (2m).

Basis can be classified into three types:

• Polynomial (Standard) Basis.

• Normal Basis.
• Dual Basis.

This classification based on the optimization for the hardware and the need of the
applications.

• Polynomial Basis
 24

In this type of basis, we choose the first m symbols excluding zero, i.e. we

choose {α0, α1, . . ., αm-1}.

For example, consider GF (23) with p(x) = x3 + x + 1. Take a as a root of p(x) then
the polynomial basis of this field will be {1, a, a2} and all 8 elements can be represented
as:

a = a0+ a1a+ a2a2 (3.7)

where the ai∈GF (2). These basis coefficients can be stored in a basis table of the
kind shown in Appendix B.

• Dual Basis

Dual basis is one of the most important types of basis which used to gain an
efficient hardware for RS encoders and decoders, as it is used in Galois field multipliers.
The difference between polynomial basis and dual basis is only re-ordering to the symbols.

For example: Let’s deal with GF (24) with primitive polynomial p(X) = X4 +X+1

• The standard (polynomial) basis for this field is {α0, α1, α2, α3}.
• The dual basis for this field is {α0, α3, α2, α1}.

• Normal Basis
Normal basis is a basis which is useful when we need squaring in our
calculations. Since if (a0, a1, ..., am-1) are the normal basis representation of a ∈ GF
(2m) then (am−1, a0, a1, ..., am−2) is the normal basis representation of a2. This property
make the hardware is more efficient

In this report we used only polynomial basis as in circuit implementation we needed

only polynomial basis multipliers.

3.1.5 Implementation of GF (2m) Arithmetic

Implementation of Galois field arithmetic is totally different to the implementation
of infinite field arithmetic, for example, multiplication in Galois field, if we need to
multiply 2 ∗ 4 it may give 3 or 5 or any other value based on the field implementation,
but in the infinite field arithmetic 2 ∗ 4 must equal to 8. So implementation of Galois
field arithmetic circuits is different.
 25

The most common implementation in Galois field arithmetic are addition and
multiplication.

• Addition operation may be considered as an XOR operation. Implementation of

Galois field adders regardless the basis representation of field elements can be
formulated as shown in equation 2.8. Hence a GF (2m) adder circuit can be
implemented with 1 or m XOR gates depending on whether the basis coefficients
are represented in series or parallel. This is an important feature of GF (2m) and
make the implementation of addition is easy operation and need limited
hardware.

a = b + c = (b0 + b1α + ... + bm−1αm-1) + (c0 + c1α + ... + cm−1αm-1) - (3.8)

= (b0 + c0) + (b1 + c1) α + ... + (bm−1 + cm−1) αm-1

• Multiplication is more complex than addition as the addition is only XOR

operation, but multiplication is different and depends on the Galois field
structure and its primitive polynomial and the type of basis coefficients. Finite
field multipliers can be implemented using Russian Peasant Multiplication
algorithm.

3.1.6 Russian Peasant Multiplication algorithm

In the Russian peasant method, the powers of two in the decomposition of the
multiplicand are found by writing it on the left and progressively halving the left column,
discarding any remainder, until the value is 1 (or −1, in which case the eventual sum is
negated), while doubling the right column as before[8]. Lines with even numbers on the left
column are struck out, and the remaining numbers on the right are added together.

For example, to multiply 238 by 13, the smaller of the numbers (to reduce the number of
steps), 13, is written on the left and the larger on the right. The left number is progressively
halved (discarding any remainder) and the right one doubled, until the left number is 1:

13 238

6 (remainder discarded) 476

3 952

1 (remainder discarded) 1904

Lines with even numbers on the left column are struck out, and the remaining numbers on
the right are added, giving the answer as 3094:
 26

13 238

6 476

3 952

1 + 1904

3094

We implement this algorithm in hardware using shifters and multiplexers as a combinational

logic

3.2 Cyclic Codes

Reed Solomon code is considered non-binary class of cyclic code[4], so first we will give a
brief introduction to cyclic code.

3.2.1 Description
Cyclic codes are considered class of linear block codes, with the advantage of
being easily implemented using sequential logic or shift registers.

Let C be a codeword where C = (c0, c1, ..., cn−1). The ith shifted version of this
codeword is:

C(i)= (cn−i, cn−i+1, ..., cn−1, c0, c1, ..., cn−i−1) (3.9)

A linear block code is said to be cyclic code if two properties exist:

• properties of linear block codes are valid.

• The ith cyclic rotation for any valid codeword is also valid codeword.

3.2.2 Code words in Polynomial Forms

A codeword can be represented in a polynomial form C(X) function of X,
with coefficients ci are defined under GF (2m) where i is an integer number
corresponds to the position of this coefficient
Let C = (c0, c1, ..., cn−1) be a code vector, the polynomial representation
for this vector is C(X) in the form of:
C (X) = c0+ c1X +· · ·+ cn−1Xn−1 (3.10)

3.2.3 Generator Polynomial of a Cyclic Code

The i-position right-shift rotation of a code vector C has the following polynomial
 27

expression:

C(i)(X) =cn−i+ cn−i+1X +· · ·+ cn−i−1Xn−1 (3.11)

The i-position right-shift rotated polynomial is denoted as C(i)(X) and the original
code polynomial C (X), with relation shown in equations 3.12 and 3.13:

XiC(X) = q(X)(Xn+1) + C(i)(X) (3.12)

C(i)(X) =XiC(X) mod (Xn+1) (3.13)

There is a certain polynomial with a minimum degree r, where r = n − k among all

polynomials which generate cyclic code Ccyc(n, k), this polynomial is called generator
polynomial with a valid coefficient gr and the coefficient g0 = 1, so we can form this
polynomial as:

g(X) = 1 + g1X+ · · ·gr-1Xr-1 + Xr (3.14)

This polynomial is used in the encoding procedure for a linear cyclic code, as Ccyc(n,
k)can be introduced as a multiplication between the message polynomial m(X)and the
generator polynomial g(X)as shown in equation 3.14, and this operation is sufficient to
generate any code polynomial of the code[4].

C(X) = m(X)∗ g(X) (3.15)

3.2.4 Generation of Cyclic Codes in Systematic Form

As we expressed in the previous chapter the linear block code [4] in systematic form,
we can express the cyclic code in systematic form based on certain steps:

• The message polynomial is of the form:

m(X) = m0+ m1X +· · ·+ mk−1Xk−1

• Multiply Xn−k by m(X) to give the following polynomial:

X n-k m(X) = m0Xn-k+ m1Xn-k+1+· · ·+ mk−1X n-1 (3.16)

• Divided the previous expression by the generator polynomial g(X):

X n-k m(X) = q(X)g(X) + p(X) (3.17)
 28

• Here p(X) is the remainder polynomial of the division of equation 3.16, which
has degree n-k-1 or less, since the degree of g(X) is r = n−k. By reordering
equation 3.17, we obtain can get equation 3.18 as we discussed in the previous
section that there is no difference between (+) and (−).
Xn−km(X) + p(X) = q(X)g(X) (3.18)

Where it is seen that the polynomial Xn−km(X) + p(X) is a code polynomial because
it is a factor of g(X). In this polynomial, the term Xn−km(X) represents the message
polynomial right shifted n-k positions, where p(X) is the remainder polynomial of this
division and acts as the redundancy polynomial. This procedure allows the code
polynomial to be in systematic form:

C (X) = X n-k m(X) + p(X)

= p0+ p1X +· · ·+ pn−k−1X n-k-1 (3.19)

+ m0X n-k+ m1 X n-k+1+· · ·+ mk−1X n-1

which can be expressed in the code vector form of:

C = ( mk-1, ….., m1, m0, pn-k-1, ..., p1, p0) (3.20)

3.3 Properties of Reed-Solomon Codes

This section summarizes the introduction to Reed Solomon (RS) codes [7] and their
properties.RS codes are non-binary cyclic codes. A RS code is specified as RS (n, k)
with m-bit symbols. RS (n, k) codes on m-bit symbols exist for all n and k for which

0 < k < n ≤ 2m − 1 (3.21)

where k is the number of data symbols to be encoded, and n is the total number of
code symbols after encoding, called codeword. This means that the RS encoder takes k data
symbols and adds parity symbols (redundancy) of (n − k) symbols to make an n symbol
codeword in systematic form as discussed in the previous section.

For the most conventional RS (n, k) code,

(n, k) = (2m − 1, (2m − 1) − 2t ) (3.22)

 29

where t is the number of symbols that can be corrected with this code, where tcan
be expressed as

t =b(n − k)/2c (3.23)

Equation 3.23 clarifies that for the case of RS codes, we need not more than 2t parity
symbols to correct t symbol errors. For each error, one redundant symbol is used to find
the location of the error in the codeword, and another redundant symbol is used to find
the value of the error.

Let the number of errors with an unknown location is nerrors and the number of errors
with known locations (erasures) as nerasures, the RS algorithm guarantees to correct a
codeword, provided that the following is true

n
2nerrors + erasures≤ 2t (3.24)

Expression 3.24 is called simultaneous error-correction and erasure-correction

capability. Erasure information can often be supplied by the demodulator in digital
communication system. In this report we do not deal with erasures, we only consider
the error correction.

Keeping the same symbol size m, RS codes may be shortened by making a number
of data symbols zero at the encoder, not transmitting them, and then re-inserting them
at decoder[7]. For example, the RS (255, 239) code with (m = 8) can be shortened to RS
(200, 184) with the same m = 8. The encoder takes a block of 184 data bytes, then adds
55 zero bytes, creates a RS (255, 239) code word and transmits only the 184 data bytes
and 16 parity bytes.

The main advantage of RS code is that it performs well against burst noise.

Figure 3-3-1: A codeword of 255 bytes disturbed by 128-bit noise burst

Consider a popular Reed-Solomon code RS (255, 223), where each symbol is made up
of m = 8 bits. Since (n − k) = 32, Equation 3.23 indicates that this code can correct any
16 symbol errors in a codeword of 255 bytes. Now assume that we have burst error in
a 128-bit duration and affected one codeword during transmission, as shown in Figure
3-3-1
 30

In this example, a burst of noise that lasts for a duration of 128 contiguous bits
corrupted exactly 16 symbols. The RS decoder for the (255,223) code will correct any
16 symbol errors regardless the type of damage suffered by the symbol. When the
decoder corrects a byte, it replaces the incorrect byte by the correct one, whether the
error was caused by one bit being corrupted or all eight bits being corrupted[7]. Thus if
a symbol is wrong, it might as well be wrong in all its bit positions. That is why RS
codes are extremely used because of their capacity to correct burst errors.

3.4 Applications of Reed-Solomon Codes

Due to the feature of burst error, RS codes provide powerful correction and high
rates with high channel efficiency, and thus have a wide range of applications in digital
communications and storage [9]

e.g.:

• Storage devices: Compact Disk (CD), DVD, etc.

• Wireless or mobile communications: cellular phones, microwave links, etc.
• Satellite communications
• Digital television /DVB
• High-speed modems: ADSL, VDSL, etc.

Conclusion

In this Chapter we showed how Galois fields form a basis for Reed Solomon Codes and
how the Reed Solomon Codes are constructed using these Galois Field elements followed
by the applications of Reed Solomon Codes. In the next chapter we’ll discuss about the RS
Encoding.
 31

CHAPTER 4

REED SOLOMON ENCODING

Before going into the details of the RSFEC Encoding, let us know how code word
markers are introduced for alignment purposes in RSFEC transmission.

4.1 Rate compensation for codeword markers in the transmit direction

The RS-FEC transmit process periodically inserts codeword markers into the
transcoded block stream. In order to maintain the same bit rate after codeword marker
insertion [6], the RS-FEC transmit process shall perform the rate compensation function
described below, or its functional equivalent:

a) Decode the PCS blocks received by descrambling and applying the PCS receive
process to obtain the 25GMII character stream.

b) Delete Idle control characters (/I/), Low Power Idle control characters (/LI/), and
ordered sets, to create room as necessary for the periodically occurring codeword
markers.

c) Re-encode the data stream obtained, by applying the PCS transmit process and
scrambler to obtain 64B/66B blocks.

4.2 64B/66B to 256B/257B transcoder

The transcoder constructs a 257-bit block, tx_scrambled<256:0>, from a group of

four 66-bit blocks, tx_coded_j<65:0> where j=0 to 3.
For each group of four 66-bit blocks, j=3 corresponds to the most recently
received block[6]. Bit 0 in each 66-bit block is the first bit received and corresponds to the
first bit of the synchronization header.

If for all j=0 to 3, tx_coded_j<0>=0 and tx_coded_j<1>=1, tx_xcoded<256:0> shall

be constructed as
follows:
a) tx_xcoded<0> = 1
b) tx_xcoded<(64j+64):(64j+1)> = tx_coded_j<65:2> for j=0 to 3
If for all j=0 to 3, tx_coded_j<0> ≠ tx_coded_j<1> (valid synchronization header)
and for any j=0 to 3, tx_coded_j<0>=1 and tx_coded_j<1>=0, tx_xcoded<256:0> shall be
constructed as follows:
a1) tx_xcoded<0> = 0
b1) tx_xcoded<j+1> = tx_coded_j<1> for j=0 to 3
c1) Let c be the smallest value of j such that tx_coded_c<0>=1. In other words,
tx_coded_cis the first 66-bit control block that was received in the current group of four
 32

blocks.
d1) Let tx_payloads<(64j+63):64j> = tx_coded_j<65:2> for j=0 to 3
e1) Omit tx_coded_c<9:6>, which is the second nibble (based on transmission order) of
the block type field for tx_coded_c, from tx_xcoded per the following expressions.
tx_xcoded<(64c+8):5> = tx_payloads<(64c+3):0>
tx_xcoded<256:(64c+9)> = tx_payloads<255:(64c+8)>

If for any j=0 to 3, tx_coded_j<0> = tx_coded_j<1> (invalid synchronization

header), tx_xcoded<256:0> shall be constructed as follows:
a2) tx_xcoded<0> = 0
b2) tx_xcoded<j+1> = 1 for j=0 to 3
c2) Let tx_payloads<(64j+63):64j> = tx_coded_j<65:2> for j=0 to 3
d2) Omit the second nibble (based on transmission order) of tx_coded_0 per the
following expressions.
tx_xcoded<8:5> = tx_payloads<3:0>
tx_xcoded<256:9> = tx_payloads<255:8>

Several examples of the construction of tx_xcoded<256:0> are shown in Fig 4-2-1

indicates the jth 66-bit block contains only data octets, c_jindicates the jth 66-bit block
contains one or more control characters, f_jdenotes the first nibble of the block type field
for 66-bit block j, and s_jdenotes the second nibble of the block type field for 66-bit block
j.
Finally, scramble the first 5 bits, based on transmission order, of tx_xcoded<256:0>
to yield tx_scrambled<256:0> as follows:
a3) Set tx_scrambled<4:0> to the result of the bit-wise exclusive-OR of the
tx_xcoded<4:0> and tx_xcoded<12:8>.
b3) Set tx_scrambled<256:5> to tx_xcoded<256:5>
For each 257-bit block, bit 0 shall be the first bit transmitted.
 33

Figure 4-2-1—Examples of the construction of tx_xcoded

4.3 Code word marker insertion

In order to support codeword alignment in the receive direction, the 25GBASE-R

RS-FEC shall periodically insert codeword markers into the stream of transcoded blocks as
the first 257 bits of every 1024th RS-FEC code word[3]. The distance between the beginning
of successive codeword markers is therefore 20480 257-bit transcoded blocks, equivalent to
81920 64B/66B blocks.
Room for codeword markers is created by the rate compensation for codeword
markers in the transmit direction process such that the bit rates at the input and the output of
the 25GBASE-R RS-FEC sublayer are equal.
The transmitted codeword marker is a 257-bit block, tx_cwm, constructed of four
alignment markers followed by a zero bit. Each alignment marker is built from eight octets
M0, M1, M2, BIP3, M4, M5, M6, andBIP7 with the bit order shown in Figure 4-3-1. The
BIP3 field is set to the constant value 0x33 and the BIP7field is set to the constant value
0xCC.

Figure 4-3-1—Alignment marker format

 34

4.4 Reed-Solomon Encoding

The main idea of RS encoding is to convert the message to codeword by adding
parity symbols to the message, where the message length is k symbols, and the
codeword length is n = (2m − 1) symbols, where m is the symbol length[4].

Each message block is equivalent to a message polynomial of degree k − 1, denoted

as:

m(X) = m0+ m1X + m2X2+· · ·+ mk−1Xk-1 (4.1)

where the coefficients m0, m1, . . ., mk−1 of the polynomial m(X) are the symbols of
message block. These coefficients are elements of GF (2m). So the information
sequence is mapped into a polynomial by setting the coefficients equal to the symbol
values.

For example, consider the Galois field GF (28), so the information sequence is
divided into symbols of eight consecutive bits as shown in Figure (3-8). The first
symbol in the sequence is 10000000. In the power representation, 10000000 becomes
α0GF (28). Thus, α0 becomes the coefficient of X0. The second symbol is 00100000, so
the coefficient of X1 is α2. The third symbol is 10111111, so the coefficient of X2 is
α80 and so on.

Figure 4-4-1: The information bit sequence divided into symbols.

4.5 Systematic Encoding

The encoding of RS codes can be performed in systematic form. In systematic
encoding, the encoded block (codeword) is formed by simply adding parity or
redundant symbols to the end of the k-symbols message block[6], as shown in Figure 4-
3-1. So code words are consisting of k-symbols message block, and 2t parity symbols,
where t is the number of error correction capability and 2t = n − k.

Figure 4-5-1 A code word is formed from message and parity symbols.
 35

Applying the polynomial notation, we can shift the information into the left most
bits by multiplying by X2t, leaving a code word of the form

C(X) = X2tm(X) + p(X) (4.2)

Where C(x) is the code word polynomial, m(X) is message polynomial and p(x) is
the redundant polynomial.

The parity symbols are obtained from the redundant polynomial p(X), which is the
remainder obtained by dividing X2tm(X) by the generator polynomial, which is
expressed as

p(X) = (X2tm(X))mod g(x) (4.3)

So, RS code word is generated using generator polynomial, which has such property
that all valid codewords are exactly divisible by the generator polynomial. The general
form of the generator polynomial is:

g(X) = (X + α)(X + α2)(X + α3)· · ·(X + α2t) (4.4)

= g0+ g1X + g2X2+· · ·+ g2t−1X2t−1+ X2t

Whereα is a primitive element in GF (2m), and g0, g1, g2, · ·, g2t−1 are the coefficients
from GF (2m). The degree of the generator polynomial is equal to number of parity
symbols (n − k). Since the generator polynomial is of degree 2t, there must be precisely
2t consecutive powers of α that are roots of this polynomial. We designate the root of
g(X) as α, α2. . . α2t. It is not necessary to start with the root α, because starting with any
power of α is possible. The root of a generator polynomial, g(X), must also be roots of
the code word generated by g(X), because a valid code word is of the following form:

c(X) = q(X) g(X) (4.5)

Where q(X) is a message-dependent polynomial. Therefore, an arbitrary code-

word, when evaluated at any root of g(X), must yield zero, or in other words

g(αi) =cvalid(αi) = 0, where i= 1, 2, . . . ,2t (4.6)

 36

4.6 Reed-Solomon encoder

The RS-FEC sub layer employs a Reed-Solomon code operating over the Galois Field
GF (210) where the symbol size is 10 bits. The encoder processes k message symbols to
generate 2t parity symbols[3], which are then appended to the message to produce a code
word of n=k+2t symbols. For the purposes of this clause, a Reed-Solomon code is denoted
RS (n, k).

(4.7)

In the above equation 4.7, α is a primitive element of the finite field defined by the
polynomial x10+x3 +1. Equation below defines the message polynomial m(x) whose
coefficients are the message symbols mk-1 to m0.

(4.8)

Each message symbol mi is the bit vector , which is identified

with the element of the finite field. The message
symbols are composed of the bits of the transcoded blocks tx_scrambled (including a
mapped group of alignment markers when appropriate) such that bit 0 of the first transcoded
block in the message is bit 0 of mk-1 and bit 256 of the last transcoded block in the message
is bit 9 of m0.

The first symbol input to the encoder is mk-1. Equation below defines the parity
polynomial p(x) whose coefficients are the parity symbols p2t-1 to p0.

(4.9)

The parity polynomial is the remainder from the division of m(x) by g(x). This may
be computed using the shift register implementation illustrated in Figure 4-4-1. The
outputs of the delay elements are initialized to zero prior to the computation of the parity
for a given message. After the last message symbol, m0, is processed by the encoder, the
outputs of the delay elements are the parity symbols for that message.

The code word polynomial c(x) is then the sum of m(x) and p(x) where the coefficient
of the highest power of x, cn-1 = mk-1 is transmitted first and the coefficient of the lowest
power of x, c0 = p0 is transmitted last[3]. The first bit transmitted from each symbol is bit 0.
 37

Figure 4-6-1—Reed-Solomon encoder functional model

Conclusion:
In this chapter we showed how a Reed Solomon Encoder can be implemented along with the
CWM insertions and transcoding function of a RSFEC Transmitter. In the next Chapter, we
deal about the RSFEC Decoder where different methods used to decode are shown along
with the inversion less Berlekamp Massey Algorithm.
 38

CHAPTER 5

REED SOLOMON DECODING

The received code word is entered to RS decoder to be decoded, the decoder
first tries to check if this code word is a valid code word or not. If it does not, errors
occurred during transmission[10]. This part of the decoder processing is called error
detection. If errors are detected, the decoder tries to correct this error using error
correction part.

Figure 5-1: Block Diagram of RS Decoder

Figure 5-1 shows the main block diagram of Reed Solomon decoder which consists
of two main parts:

1. Error detection part, in this part we use “Syndrome computation” block.

2. Error correction part, this part consists of three blocks:

➢ Decoding algorithm which used to find the coefficients of error-location

polynomialσ(x) and error-evaluator polynomial W (x) it sometimes called
“Key equation solver”.
➢ Chien search block which used to find the roots of σ(x) which present the
inverse of the error locations.
➢ Forney algorithm block which used to find the values of the errors.

After getting the values and locations of the error, we can correct the received
codeword by xor-ing the received vector with the error vector.

5.1 Lock FSM

Before Syndrome Calculation, LOCK FSM is placed which detects CWM in the
received data and achieves lock by detecting Code word markers and thus further
process follows. If lock isn’t achieved, FSM searches for CWM at different positions
until it gets LOCK[3].
 39

Figure 5-1-1—FEC synchronization state diagram

5.2 Error Detection “Syndrome Calculation”

The first step in RS decoder is to check if there is any error in the received
codeword or not. This done using Syndrome computation block[5].

• Let the transmitted code word polynomial c(X) formed as follow:

c(x) = c0+ c1X +· · ·+ cn−1Xn-1 ,where ci∈ GF (2m) (5.1)

 40

• Let the received code word polynomial r(X) formed as follow:

r(X) = r0+ r1X +· · ·+ rn−1Xn-1 ,where ri∈ GF (2m) (5.2)

• Let the error polynomial e(X) which added by the channel formed as:

e(X) = e0+ e1X +···+en−1Xn-1 ,where ei∈ GF (2m) (5.3)

Which is related to the received polynomial r(X) and the transmitted polynomial
c(X) as follows:

r(X) = c(X) + e(X) (5.4)

From equation 5.4, the transmitted polynomial c(x) must be multiple of the
generator polynomial g(X), and the received polynomial r(X) is evaluated form the
addition between c(X) and e(X). So the roots of g(X) should give zero in the received
polynomial if the error polynomial is zero. i.e., no errors occurred.

• Let the syndrome polynomial S(x) formed as:

(5.5)
Where i = 1, 2. . . 2t.

Each coefficients can be described as follows:

(5.6)

From equation 5.6, if there are no errors, all syndrome coefficients must give zero.
If there is any non-zero coefficient, it means that there is an occurrence for error.

5.3 The Decoding Algorithm

After calculation of the syndrome coefficients we can detect if there exist errors in
the received code word or not by checking these values, if all these coefficients are
zeros there will be no errors if not there will be error in an unknown location in the
code word with an unknown value [5].
 41

The main function of the decoding algorithm is to get the error location polynomial
σ(x), and the error evaluator polynomial W (x), which represent the locations and the
values of the errors respectively.

The first error correction procedure for Reed Solomon codes was found by
Gornstien and Zierler, and improved by Chien and Forney. This producer is known as
the key equation solver, as it will be discussed later.

Decoding algorithms can be categorized into two types:

• Serial algorithms in which the error locator polynomial σ(x) is calculated first
then we substituted in the key equation to calculate the error evaluator polynomial
W (x), e.g. (Berlekamp–Massey algorithm).

• Parallel algorithms in which the error locator polynomial σ(x) and the error
evaluator polynomial W (x) are calculated are in parallel, e.g. (Euclidean
algorithm).

5.3.1Decoding of RS Codes Using Berlekamp-Massey Algorithm

The Berlekamp–Massey (B-M) algorithm is a method used as decoding

algorithm used for RS and BCH codes. This method used in RS codes to calculate
the coefficients of the error locator polynomial for the error locations, and the
coefficients of the error evaluator polynomial for the error values. In BCH the
values of the errors are binary so we only calculate the coefficients of the error
locator polynomial.

Let the error polynomial e(X) contains τ errors placed at positions Xj1, Xj2. . . Xjτ
with error values ej1, ej2. . . ejτ then:

e(X) = ej1 Xj1+ ej2 Xj +· · ·+ejτXjτ

2
(5.7)

Now our target is to calculate the values of eji and the powers of Xji.

From equation 5.6 we have 2t syndrome coefficients. Each syndrome coefficient

Si can be expressed as:

Si= r(αi) = c(αi) + e(αi) = e(αi) (5.8)

From Equations [5.7 and 5.8] we can obtain set of equations that relate
the error locations and values to the syndrome coefficients in the form of:
 42

S1 = r(α) = e(α) = ej1αj1 + ej2αj2 + · · · + ejταjτ

S2 = r(α2) = e(α2) = ej1 α2j1+ ej2 α2j2+· · ·+ejτ α2jτ

S
2t = r(α2t) = e(α2t) = ej1 α2tj1+ ej2 α2tj2+· · ·+ejτ α2tjτ (5.9)

This set of equations can be simplified in the form:

1 = r(α) = e(α) = ej1 β1+ ej2 β2+· · ·+ejτ βτ

s

s2 = r(α2) = e(α2) = ej1 β12+ ej2 β22+· · ·+ejτ βτ2

. . .

s
2t = r(α2t) = e(α2t) = ej1 β12t+ ej2 β12t+· · ·+ejτ βτ2t (5.10)

Where βi = αji and i = 1, 2, 3, . . . , τ

From equation 5.10 we have 2t equations in 2t unknowns as worst case, but these
equation is not linear equations so we define the two polynomials:

• The error locator polynomial σ(x) which present the locations of the error.

• The error evaluator polynomial W (x) which presents the values of the errors.

As mentioned before that Berlekamp-Massey algorithm is a serial algorithm so the error

location polynomial σ(x) is calculated first then the error evaluator polynomial W (x).

a-B–M Iterative Algorithm for Finding the Error-Location Polynomial

Let’s assume that we have binary errors, as the values of the errors will not affect
the location of the errors[4], so for B-M algorithm, the error location polynomial can be
defined as:

σBM(X) = (1− β1X)(1− β2X)· · ·(1− βτ X) (5.11)

= σ0+ σ1X +· · ·+στxτ

 43

• The roots of this polynomial are β1-1, β2,-1 . . . , βτ−1, the inverse of the error
location numbers.
• Coefficients of this polynomial can be expressed as:
σ0 = 1

σ1 = β1 + β2 + · · · + βτ

σ2 =β1β2 + β2β3 + · · · + βτβτ−1 (5.12)

σ
τ = β1β2. . . βτ

It is possible to get a relation between the coefficients of σ(X) and the syndrome
coefficients Si’s :

s
1 + σ1= 0
S
2 + σ1s1= 0

S3 + σ1s2+ σ2s1+ σ3= 0 (5.13)

Sτ + σ1sτ−1 + · ·· + στ−1s2 + στs1 = 0

These equations are called Newton identities, and we can verify them as follow:

s1+ σ1 = (β1 + β2 + · ·· + βτ ) + (β1 + β2 + · ·· + βτ ) = 0

s2+ σ1s1 = (β1)2 + (β2)2 + · ·· + (βτ )2 +

(β1 + β2 + · ·· + βτ )(β1 + β2 + · ·· + βτ ) = 0

The remaining Newton identities can be derived in the same way.The objective from
the algorithm is to find the minimum degree polynomial σ(X) whose coefficients satisfy
these newton identities.

The algorithm proceeds as follows:

1. The first step is to determine a minimum-degree polynomial σBM(1) (X) that

satisfies the first Newton identity described in 5.13.

2.At the kth step, the polynomial of minimum degree will be: The second Newton
identity is tested. If the polynomial σBM(1) (X) satisfies the second Newton identity
in 5.13, then σBM(2) (X) = σBM(1) (X). Otherwise the
 44

(5.14)

Where lk presents the order of the polynomial, and 1 ≤ lk ≤ k, which coefficients

satisfy the following lk identities:

(5.15)

3. In the next step the new polynomial with minimum degree will be:

(5.16)

with coefficients that satisfy the following lk+1 identities:

(5.17)

4. Once the algorithm reaches step 2t, the polynomial σBM(2t) (X) is called as the error-
location polynomial σBM (X), i.e., σBM (X) = σBM(2t) (X).

To formalize these steps in a closed iteration form:

Assume that we just completed the kth iteration and got σ(k)(X). To find

σ (k+1)(X), we check whether σ(k)(X)satisfy the following Newton identity

 45

(5.18)

If yes, therefore σ(k+1)(X) = σ(k)(X) and there will not be any change in the
polynomial. If no, we add correction dµ, called the kth discrepancy. This term can be
obtained by using the following expression:

(5.19)

• If dk= 0, then the minimum-degree polynomial σBM(k) (X) satisfies (k + 1)th Newton
identity, and it becomes σBM(k+1)(X):

(5.20)
• If dµ= 0, then the minimum-degree polynomial σBM k (X) will not satisfy the (µ
( )

+ 1)th Newton identity, and a correction term is calculated to be added to σBM(k)

(X), in order to form σBM(k+1)(X) as shown in the following equation:

(5.21)
Where σBM ρ (X) is a previous polynomial such that the discrepancy dρ = 0 and
( )

ρ −l is a maximum, and the number lρ is the degree of the polynomial σBM(ρ) (X). So the
closed form of the algorithm will be:
If dk = 0 then σBM(k+1)(X) = σBM(k) (X), lk+1 = lk.

If dµ≠ 0, the algorithm take the previous row ρ, such that dρ≠ 0 and ρ − lρ is
maximum. Then,

(5.22)

The B–M algorithm can be implemented in the form of a table with 2t rows to give
the final value of the minimum degree error locator polynomial σBM(2t) (X) , as given in
Table 5-1.
 46

Table 5-1: B–M algorithm table for determining the error-location polynomial

Note that, if the degree of σBM(2t) (X) is larger than t, it means that its roots do not
correspond to a real error-location numbers, it means also that the number of errors are
more than t errors, which is more than the error-correction capability of the code.

For example: consider (15, 9) RS code under GF (24) with the following syndrome
coefficients:

By applying Berlekamp-Massey algorithm on it to calculate the minimum degree

error locator polynomial σ(X). The following table 5-2, clarify the steps of the
algorithm:
Table 5-2: B–M algorithm table for determining the error-location polynomial for (15, 9) RS Code.
 47

From Table 5-2, the minimum degree error locator polynomial σ(X) using
Berlekamp-Massey algorithm is:σ(X) = 1 + α7X + α4X2 + α6X3.

After the determination of the error-location polynomial, the roots of this poly-
nomial are calculated by applying the Chien search, which will be explained in the
following sections, by replacing the variable X with all the elements of the Galois field
GF (2m), 1, α, α2, . .. , α2m-2, in the expression of the obtained error-location polynomial,
looking for the condition σBM (αi) = 0, which present the inverse of the error locations.

b-B–M Algorithm for Finding the Error-Evaluation Polynomial

RS codes are non-binary codes, this means that for a given error location we have
error value. This value is under GF (2m), which add to the algorithm another step to get
the error evaluator polynomial W (X).

As mentioned before that B-M algorithm is a serial algorithm so, once the B–M
algorithm determines the error-location polynomial σ(X), it substitutes in the following
equation:

σ(X)S(X) = W (X) + µ(X)X2t (5.23)

This equation is called the Key equation, where µ(X) is a polynomial such that the
polynomials σ(X), S(X) and W (X) fit the key equation. Equation 4.2.17 can be proofed
as follow:

• Let syndrome polynomial S(X) defined as:

(5.24)

Then, from equation 3.24, the result of σ(X) *S(X) can be shown as:

Also the key equation can be written like that

 48

S(X) *σ(X) = W (X)mod X2t (5.25)

By substituting in the Key equation shown in equation 5.25, we can get the
coefficients of the error evaluator polynomial W (X), so B-M algorithm is called serial
architecture as the error locator polynomial is calculated first the error evaluator
polynomial.

After above explanation, it is clear from equation 5.21, the evaluation of σBM(µ+1)
needs the inverse of dρ(dρ-1) at each iteration which needs GF inverter. There are two
methods to implement the GF inverter. One of them is by designing actual GF inverter
to get the inverse of GF elements. The other method is by using inverse ROM to
calculate the inverse of each element [4]. But using the GF inverter at each iteration will
consume extra delay in the calculation of equation 5.21 and also extra hardware which
increases the complexity of the decoder either we used first or second method. So to
overcome this drawback of B-M algorithm we will use Decomposed inversion-less
Berlekamp-Massey (DiB-M) algorithm is introduced.

5.4 Chien Search Calculation

After getting the error locator and evaluator polynomials from the decoding
algorithm, we need to find the roots of the error location polynomial σ(X), which present
the inverse of the error locations. There is no closed form solution for solving the roots
of σ(X). Since the root has to be one of the elements of the field GF (2m) [5], so we search
for the roots by substituting each of the finite field elements in the error location
polynomial σ(X) and checking for the following condition:

σ(αi) = 0 (5.26)

• If this condition is satisfied, an error occurred in the inverse position of i, i.e. in

position (n − i).
• If this condition is not satisfied, there is no error.
For example, assume that the error location polynomial is

σ (X) = 1 + σ1X + σ2X2+ σ3X3

We evaluate σ(X) at each non-zero element in GF (2m) in sequence:

X = α, X = α2, X = α3, . . ., X = α2m−1 This

gives us the following:
σ(α) = 1 + σ1(α) + σ2(α)2+ σ3(α)3

σ(α2) = 1 + σ1(α2) + σ2(α2)2 + σ3(α2)3 (5.27)

 49

. .

σ(α2
m
−1) = 1 + σ1(α2m−1) + σ2(α2m−1)2 + σ3(α2m−1)3

After substitution we can evaluate the condition in equation 5.26.

The Chien’s search block gets also the value of W (x) at the field elements, i.e., W
(α), W (α2), W (α3) ... W (α255). The only difference is the loaded coefficients, they are
w0∼w7 instead of σ0∼σ8, which is used in calculating the error values.

5.5 Forney Algorithm

The final stage in decoding algorithm is to calculate the value of the errors. To
calculate the error value, there are two popular methods, the first one is “transform
decoding process” in the frequency domain and the second one is “Forney algorithm”
in the time domain. Although the transform decoding process does not need neither FFI
nor Chien search, but it requires t variable FFMs and N constant FFMs which are very
large area. The Forney algorithm is preferred because of its lower circuit complexity

Where the error value at location for a RS code is computed by the

formula

(5.28)

Where W (X) is the error evaluation polynomial, k is the number of errors, and σ’(X)is the
first derivative of the error locator polynomial σ(x) with respect to X[5].

Finally, after getting the error locations and error values, we finally can form the
error polynomial e(X) and correct the received polynomial r(X) just by adding (with
XOR operation) these two polynomials together, as shown in Figure 5-1.

σ (X) is the first derivative of the error locator polynomial σ(x) with respect to X.

Finally, after getting the error locations and error values, we finally can form the
error polynomial e(X) and correct the received polynomial r(X) just by adding (with
XOR operation) these two polynomials together, as shown in Figure 5-1.
 50

5.6 256B/257B to 64B/66B transcoder

The transcoder [3] extracts a group of four 66-bit blocks, rx_coded_j<65:0> where
j=0 to 3, from each 257-bitblock rx_scrambled<256:0>.
Bit 0 of the 257-bit block is the first bit received.

First, descramble the first 5 bits, based on reception order, of rx_scrambled<256:0>

to yield rx_xcoded<256:0> as follows.
a) Set rx_xcoded<4:0> to the result of the bit-wise exclusive-OR of the rx_scrambled<4:0>
and
rx_scrambled<12:8>.
b) Set rx_xcoded<256:5> to rx_scrambled<256:5>.
If rx_xcoded<0> is 1, rx_coded_j<65:0> for j=0 to 3 shall be derived as follows.
a1) rx_coded_j<65:2> = rx_xcoded<(64j+64):(64j+1)> for j=0 to 3
b1) rx_coded_j<0>=0 and rx_coded_j<1>=1 for all j=0 to 3

If rx_xcoded<0> is 0 and any rx_xcoded<j+1>=0 for j=0 to 3, rx_coded_j<65:0>

for j=0 to 3 shall bederived as follows.
a2) Let c be the smallest value of j such that rx_xcoded<j+1>=0. In other words,
rx_coded_cis the first66-bit control block in the resulting group of four blocks.
b2) Let rx_payloads be a vector representing the payloads of the four 66-bit blocks. It is
derived usingthe following expressions:
rx_payloads<(64c+3):0> = rx_xcoded<(64c+8):5>
rx_payloads<(64c+7):(64c+4)> = 0000 (an arbitrary value that is later replaced by s_c)
rx_payloads<255:(64c+8)> = rx_xcoded<256:(64c+9)>
c2) rx_coded_j<65:2> = rx_payloads<(64j+63):64j> for j=0 to 3
d2) Let f_c<3:0> = rx_coded_c<5:2> be the scrambled first nibble (based on transmission
order) of theblock type field for rx_coded_c.
e2) Descramble f_c<3:0> to yield g<3:0> per the following expression where “^” denotes the
exclusiveOR operation. When c=0, rx_coded_(c–1) corresponds to rx_coded_3 from the
previous 257-bitblock.
g<i> = f_c<i> ^ rx_coded_(c–1)<i+8> ^ rx_coded_(c–1)<i+27> for i=0 to 3
f2) The block type field may be uniquely identified by either its most or least significant
nibble. Sinceg<3:0> is the least significant nibble of the block type field (per the transmission
 51

order), deriveh<3:0> by cross-referencing to g<3:0> using Figure 82–5. For example, if

g<3:0> is 0xE thenh<3:0> is 0x1. If no match to g<3:0> is found, h<3:0> is set to 0000.
g2) If rx_xcoded<j+1>=0, rx_coded_j<0>=1 and rx_coded_j<1>=0 for j=0 to 3
h2) If rx_xcoded<j+1>=1, rx_coded_j<0>=0 and rx_coded_j<1>=1 for j=0 to 3
i2) If h<3:0> = 0000, rx_coded_c<1>=1 (invalidate synchronization header)

If rx_xcoded<0> is 0 and all rx_xcoded<j+1>=1 for j=0 to 3, rx_coded_j<65:0> for j=0 to 3

shall be derivedas follows.
a3) Set c = 0 and h<3:0> = 0000.
b3) Let rx_payloads be a vector representing the payloads of the four 66-bit blocks. It is
derived usingthe following expressions.
rx_payloads<(64c+3):0> = rx_xcoded<(64c+8):5>
rx_payloads<(64c+7):(64c+4)> = 0000 (an arbitrary value that is later replaced by s_c)
rx_payloads<255:(64c+8)> = rx_xcoded<256:(64c+9)>
c3) rx_coded_j<65:2> = rx_payloads<(64j+63):(64j)> for j=0 to 3
d3) rx_coded_j<0>=0 and rx_coded_j<1>=0 for j=0 and 2
e3) rx_coded_j<0>=1 and rx_coded_j<1>=1 for j=1 and 3

If rx_xcoded<0> is 0, scramble h<3:0> to yield s_c<3:0> and assign it to

rx_coded_cper the followingexpressions.
a4) s_c<i> = h<i> ^ rx_coded_(c–1)<i+12> ^ rx_coded_(c–1)<i+31> for i=0 to 3
b4) rx_coded_c<9:6> = s_c<3:0>
The 66-bit blocks are transmitted in order from j=0 to 3. Bit 0 of each block is the
first bit transmitted.

Conclusion:
In this chapter RSFEC decoding algorithms are discussed along with down
transcoding functions which are seen in the Reception side in order to maintain the correct data
rate. In the next chapter our Implementation of the RSFEC Encoder and Decoder along with
the PCS TX and RX is shown.
 52

CHAPTER 6

IMPLEMENTATION& VERIFICATION
Our implementation of Reed Solomon decoder includes modules from all the above-
mentioned chapters. We implemented FEC Sublayer of the IEEE 802.3 Ethernet model. The
input to the layer comes from PCS via PMA.

6.1 DESIGN OF RSFEC

TRANSMISSION

1. A gearbox converts the input of N-bit PMA width into 66-bit width.
2. This 66-bit data is descrambled and Decoded into 64-bit output.
3. CWM Rate compensator removes idles in order to compensate the insertion of CWM
4. This data is Encoded back and Scrambled again before it goes for CWM insertion
5. The Up transcoder compresses the data to make enough space required for insertion of
CWM.
6. CWM insertion is done once every 1024 codewords.
7. This output is Encoded using RS FEC encoder
8. The 66-bit output from the Encoder is converted into N- bit PMA output, which is
processed to further layers.

RECEPTION

1. The N- bit PMA input from physical layer is converted to 66 bit using a gearbox.
2. Lock FSM is used to align with the CWM which is inserted in the transmission phase.
3. After Lock is achieved, the output is sent into RS FEC Decoder where the error
detection and correction is done if the errors are less than or equal to 70 bits (or 7
symbols).
4. The CWMs in corrected output are removed. and then decompressed by Down
Transcoder.
5. The Decompressed output is then descrambled and decoded.
6. Idles are added in order to compensate the rate which is mismatched due to removal of
CWMs.
7. This output is again scrambled and encoded back to 66-bit output
8. A gearbox is used at the end to convert this 66 – bit output into N- bit PMA Width
output which goes into PCS and other layers for further processing.
 53

NOTE: Pipeline stall does

not propagate in PMA mode
since bandwidths are
matched. When using
XGMII, pipeline stall occurs
since PMA and XGMII
widths are different.

TX PIPELINE
 54

RX PIPELINE
 55

DESIGN FLOW OF REED-SOLOMON FEC SUBLAYER

PCS

Gear Box
Gearbox

Descrambler
Scrambler

Decoder Encoder

CWM Rate
CWM Rate Compensator
Compensator
Decoder
Encoder
Descrambler

Scrambler
Decompressor/CWM
Removal

Compressor/ CWM
Insertion RS FEC Decoder

RS FEC Encoder
Lock FSM

Gear Box Gear Box

Physical Layer

6.2 REGISTER DESCRIPTION[11]
Offset(HEX) Register Name
0 FEC_CONTROL
4 FEC_CWM_IRATE
8 FEC_CWM_0
C FEC_CWM_1
56
Description Default Access
[0]: Soft reset 0x0 RW
[1]: TX Scrambler
Bypass
[2]: TX Descrambler
Bypass
[3]: RX Scrambler
Bypass
[4]: RX Descrambler
Bypass
[5]: TX XGMII interface
select.
[6]: Loopback Enable
[7]: XGMII TX
Loopback
[8]: 0x0: Normal Lock
0x1: Fast Lock
[9]: 0x0: Look for exact
64-bit CWM to match.
0x1: Obey rules of IEEE
802.3 for CWM
detection.
[15:10]: Initial position
counter value for
normal lock mode.
[31:16]: Reserved.
Control insertion rate 1024 RW
of code word marker.
If set to 1024, a code
word marker is found
every 1024 RS FEC
code words. Range is 4
to 1024. Smaller
values are non-
compliant but may
lead to faster lock.
31:0 bits of code word 0x332168c1 RW
marker.
63:32 bit of code word 0xccde973e RW
marker.
 57

10 FEC_CWM_2 95:64 bit of code word 0x33e6c4f0 RW

marker.
14 FEC_CWM_3 127:96 bit of code 0xcc193b0f RW
word marker.
18 FEC_CWM_4 159:128 bit of code 0x339b65c5 RW
word marker.
1C FEC_CWM_5 191:160 bit of code 0xcc649a3a RW
word marker.
20 FEC_CWM_6 223:192 bit of code 0x333d79a2 RW
word marker.
24 FEC_CWM_7 255:224 bit of code 0xccc2865d RW
word marker.
28 FEC_CWM_8 Bit 256 of code word 0x0 RW
marker.
2C FEC_STATUS [0]: RS FEC lock 0x0 RO
achieved.
[7:1]: RS FEC barrel
shifter lock position.
[8] : RX ok signal
30 FEC_RX_OUT_FIFO_THX Output RX FIFO 0x20 RW
threshold.
34 TX_SCRAMBLER_SEED_0 Lower 32 bit of tx 0x0 RW
scrambler seed
38 TX_SCRAMBLER_SEED_1 Upper 26 bit of tx 0x0 RW
scrambler seed
3C TX_DESCRAMBLER_SEED_0 Lower 32 bit of tx 0x0 RW
descrambler seed
40 TX_DESCRAMBLER_SEED_1 Upper 26 bit of tx 0x0 RW
descrambler seed
44 RX_SCRAMBLER_SEED_0 Lower 32 bit of rx 0x0 RW
scrambler seed
48 RX_SCRAMBLER_SEED_1 Upper 26 bit of rx 0x0 RW
scrambler seed
4C RX_DESCRAMBLER_SEED_0 Lower 32 bit of rx 0x0 RW
descrambler seed
50 RX_DESCRAMBLER_SEED_1 Upper 26 bit of rx 0x0 RW
descrambler seed
54 CERR_REG Number of corrected 0x0 RO
code words so far.
58 NCERR_REG Number of 0x0 RO
uncorrectable code
words so far.
5C BAD_CWM_TOL Bad CWM tolerance. 0x3 RW
 58

These registers are used to program the controls used in RSFEC module. We used APB
functionality by implementing a Dual Rank Synchronizer in order to read the values from the
RSFEC module.

6.3 VERIFICATION
6.3.1 TESTBENCH ARCHITECTURE

A Data Simulator is used in testbench to generate Data or IDLES which are applied as
input to the DUT (Device Under Test). The RSFEC Module (i.e, DUT) processes the inputs to
give output. Initially IDLEs are applied from the Data Simulator until lock is seen on the output
of DUT. Once the lock is achieved Data Simulator starts sending Source data and the Output
of DUT is compared with the Source data using a Comparator which detects a data mismatch.

Data Format:
IDLES START DATA TERMINATE

The Data sent to the DUT is in the above format.

Start character ( /S/ ) : 0xfb
Terminate character ( /T/ ) : 0xfd
 59

6.3.2 SIMULATION RESULTS

When the data applied according to the testbench architecture shown in the previous
section the following results are seen.

RSFEC SUBLAYER:
PROCESSING THROUGH PMA:

PROCESSING THROUGH XGMII:

 60

RSFEC TX:

TX USING PMA

The inputs are applied through PMA as interface_sel signal is 0. The above waveform shows
the TX side of the RSFEC module .

TX USING XGMII

The inputs are applied through XGMII interface as interface_sel signal is 1. The above
waveform shows the TX side of the RSFEC module with XGMII inputs.

PCS ENCODER:

Signals:
 61

tx_clk_i: clock for TX of both PCS and RSFEC sublayers.

tx_rst_n_i : active low reset signal.
tx_raw_i: data input from XGMII each of width 72 bits. It is ofboth data and control signals
tx_dav_i: data valid signal indicating presence of data input.
tx_data_o:encoded data output of width 66 bitsto PCS Scrambler.
tx_dav_o: data valid signal indicating presence of data output.
err_0: error signal indicating fault data input which cannot be encoded and processed further.

PCS SCRAMBLER:

Signals:
tx_coded_i: data input from PCS encoder each of 66-bit width.
tx_dav_i: data valid signal indicating presence of data input.
tx_init_i: initial seed(58-bit) to scrambler.
tx_scrambler_bypass_i: input signal,if made high the input data bypasses scrambler else
scrambling is done.
tx_scrambled_o:scrambled data output of 66-bit width to RSFEC uptranscoder.
tx_dav_o: data valid signal indicating presence of data output.

RSFEC UP-TRANSCODER:

Signals:
tx_coded_i: data input from PCS scrambler each of 66-bit width.
tx_dav_i: data valid signal indicating presence of data input.
tx_scrambled_o:transcoded data output of 264-bit width to width converter.
tx_dav_o: data valid signal indicating presence of data output.
 62

WIDTH CONVERTER:

Signals:
data_i: data input from RSFEC up-transcoder each of 264-bit width.
dav_i: data valid signal indicating presence of data input.
data_o:converted data output of variable width (60,60,70,50,90) to RSFEC encoder.
dav_o: data valid signal indicating presence of data output.
state_r: state indicating width of data output.

RSFEC ENCODER:

Signals:
data_i: data input from width converter each of variable width.
dav_i: data valid signal indicating presence of data input.
data_o:encodeddata output of 66-bit width to physical layer.
dav_o: data valid signal indicating presence of data output.
generator_polynomial: value of g(x) used in RSFEC encoder.

RX:
RX USING XGMII
 63

The above waveform shows the RX side of the RSFEC module where the XGMII outputs are
taken from the PCS decoder .

RX USING PMA

The above waveform shows the RX side of the RSFEC module where the PMA outputs are
taken from the Output Gearbox.

RX RSFEC LOCK:

Signals:
data_i: data input from physical layer each of PMA WIDTH.
dav_i: data valid signal indicating presence of data input.
signal_ok_i: lock signal which goes high on detecting CWM.
data_o: data output from LOCK block RSFEC decoder.
dav_o:data valid signal indicating presence of data output.
 64

RSFEC DECODER:

Signals:
data_i: data input from LOCK block of RSFEC sublayer each of variable width.
dav_i: data valid signal indicating presence of data input.
data_o:decodeddata output to RSFEC syndrome decoder.
dav_o: data valid signal indicating presence of data output.

RSFEC SYNDROME DECODER:

Signals:
data_i: data input from RSFEC decoder each of variable width.
dav_i: data valid signal indicating presence of data input.
synd_o: output syndrome values to RSFEC down transcoder.
synd_dav_o:data valid signal indicating presence of syndrome output.
data_o: data output from RSFEC syndrome decoder.
dav_o: data valid signal indicating presence of data output.

RSFEC DOWN TRANSCODER:

Signals:
rx_scrambled_i: data input from LOCK block of RSFEC sublayer each of variable width.
rx_dav_i: data valid signal indicating presence of data input.
rx_coded_o: decoded data output to PCS descrambler each of 66-bit width.
rx_dav_o: data valid signal indicating presence of data output.
 65

PCS DESCRAMBLER:

Signals:
rx_scrambled_i: data input from RSFEC down transcoder each of 66-bit width.
rx_dav_i: data valid signal indicating presence of data input.
rx_valid_o: decoded data output to PCS decoder of 66-bit width.
rx_coded_o: data valid signal indicating presence of data output.

PCS DECODER:

Signals:
rx_coded_i: data input from descrambler each of 66-bit width.
rx_dav_i: data valid signal indicating presence of data input.
rxd_o: decoded data output to XGMII each of 64-bit width.
rxc_o: decoded control output to XGMII each of 8-bit width.

6.4 SYNTHESIS REPORT

The synthesis of RSFEC module is done using Xilinx Vivado for xc7v585tffg1157-3.
===============================================
Summary of Synthesis Report :
-------------------------------------------------
Total flip-flops : 74.8K
Total ROM bits : 10.24K
The maximum achievable TX clock frequency is 80MHz.
The maximum achievable RX clock frequency is 50MHz.
=================================================
 66

In this chapter we have shown our implementation which includes the RTL design of the both
PCS and RSFEC modules. The verification approach and simulation results are also showed.
In the next chapter, we conclude this thesis by showing what we have accomplished and the
future scope of this project.
 67

CHAPTER 7

CONCLUSION& SCOPE

7.1 Conclusion
This thesis presents architectures for both transmission and reception side of RSFEC
sublayer along with the PCS layer. The IEEE 802.3 (Ethernet) standard specifies a networking
protocol that allows multiple devices connected to the network to communicate with each
other. The PHY Coding Sublayer (PCS) is a part of the physical layer of the Ethernet stack
which performs encoding/decoding and error correction and communicates the same to the
MAC. On the egress, the PCS accepts data from the MAC and sends encoded data to the
serializer while on the ingress, the PCS accepts data from the deserializer and provides decoded
data to the MAC.
As speeds of the backplane (BASE-R) Ethernet increase, the BER (Bit Error Rate) also goes
up. In the absence of a FEC scheme, the time taken by the Ethernet subsystem to identify errors
is large. It would be advantageous to detect and correct a reasonable subset of possible errors
as early as possible to greatly reduce the occurrence of retransmission which in turn increases
the efficiency of the link. By adding a FEC scheme like Reed Solomon coding to traditional
Ethernet, effective BER is significantly reduced. To allow error correction as early as possible
in the stack, the PCS sublayer must implement the FEC.
The RS-FEC scheme we implemented allows for correction of 140-bit errors every 5280-bits
(BER of approximately up to 13 x 10-3). We proposed a method to predict variable ingress and
egress latency due to transcoding and gearbox conversion which will be also useful in MAC
timestamping.

7.2 Future Scope

The system is big enough to have a lot of work in the future. In fact, we can have four parallel
lanes which can process RSFEC individually resulting in increase of data bandwidth on the
PCS layer.
We can also reduce the latency of the decoding algorithm by increasing the number of
FFMs which include the bottleneck of the design to increase the through-put and reduce the
latency. we can replace the architecture of Berlekamp Massey algorithm with another
architecture for Euclidean algorithm.
We can convert the proposed decoder from RS (528,514) to multimode decoder, and this will
depend on the type of the channel and the application, as we can control the values of n, and k
to increase the rate if we have less noise in the channel or decrease the rate, if we have more
noise in the channel
 68

ANNEX -RS-FEC code word examples

This annex provides example RS-FEC codewords produced by the 64B/66B to 256B/257B
transcoding and Reed-Solomon encoding. The contents of the tables are transmitted from left to
right within each row starting from the top row and ending at the bottom row. The tables contain
both binary and hexadecimal representations of the data. For the hexadecimal representation, the
most significant bit of each hex symbol is transmitted first.

A.1 Input to the 64B/66B to 256B/257B transcoder

Table A-1 contains a sequence of 80 66-bit blocks corresponding to the PCS transmission of Idle
control characters.
Table A–1—64B/66B to 256B/257B transcoder input
 69

A.2 Output of the RS (528,514) Encoder

Table A–2 contains a RS (528,514) code word. Each row of Table A–1 is a set of four 66-bit blocks
that is converted to one 257-bit block using the procedure defined in 3.1. The resulting set of 20 257-bit
blocks constitute the message portion of the codeword. The parity is computed using the encoder
defined in3.2 and is appended to the message to complete the codeword.

Table A–2—RS (528,514) code word

 70

REFERENCES

[1] IEEE Standard 802.3TM – 2015 for Ethernet SECTION – IV

[2] IEEE Standard 802.3TM – 2015 for Ethernet SECTION – V
[3] IEEE Standard 802.3TM – 2015 for Ethernet SECTION – VI
[4] H. Burton, "Inversion less decoding of binary BCH codes," in IEEE Transactions on
Information Theory, vol. 17, no. 4, pp. 464-466, Jul 1971.
[5] Raymond S. Lim, A Decoding Procedure for the Reed-Solomon Codes, NASA Technical
Paper 1286, August 1978
[6] C.K.P. Clarke, Reed-Solomon Error Correction, R&D White Paper WHP 031, July 2002
[7] Mark Haiman, Notes on Reed-Solomon Code
[8] Christoforus Juan Benvenuto, Galois Field in Cryptography, May 31, 2012
[9] R.E Blahut, Theory and Practice of Error Control Codes, Addison Wesley, 1983
[10] James L. Massey, Shift Register Synthesis and BCH Decoding , January 1969
[11] https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html

[12] IEEE P802.3by™/D2.0 Draft Standard for Ethernet Amendment: Media Access Control
Parameters, Physical Layers and Management Parameters for 25 Gb/s Operation, The
Institute of Electrical and Electronics Engineers, Inc. Three Park Avenue, New York.