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Volume 9, Number 3


A Publication of The MicroElectronics Packaging & Test Engineering Council


for the Next Generation of
ASAT Holdings Limited has announced that the
Company’s board of directors has appointed
Robert Gange as president and chief executive
Semiconductor Packaging
officer, effective immediately. Mr. Gange suc-
ceeds Harry Rozakis. page 16
A User’s Perspective of
Evolving Technologies
One Day Technical Symposium and Exhibits
Tessera Technologies, Inc. has announced that
it has completed a successful chip-scale pack- Coming to San Jose November 17th ... page 5
aging (CSP) technology transfer to North
Dakota State University (NDSU) and has
partnered with NDSU in the development of a
fully functional microelectronics center at the

university. page 17
ith a unified appro-
DuPont Fluoroproducts has announced plans to ach to the market,
construct a new manufacturing facility to pro-
a growing product
duce nitrogen trifluoride (NF3), a key chamber
cleaning and etch gas used in semiconductor offering, and a clear
chip manufacturing and flat panel displays. view to the technology trends
The plant will be located in Changshu, Jiangsu driving needs for new materials,
Province in China. page 19 the outlook is bright for DuPont
Semiconductor Packaging and
Dynacraft Industries, one of the largest manu- Circuit Materials, and for its cus-
facturers of leadframes for the semiconductor tomers.
industry, announced that they recently signed
a patent license and technology transfer agree-
ment with Samsung Techwin. page 20

Headquartered at DuPont Electronic Tech- Semiconductor equipment bookings increase

nologies in Research Triangle Park, NC is 11% above July 2005 level. page 22
a new kind of team with intent to become

the leader in how integrated circuits are
connected to the external world. Drawing
on the company’s broad science capabilities
and long established positions in both semi-
conductor fabrication and circuit materials, to-Bill
DuPont Semiconductor Packaging and
Circuit Materials (DSPCM) is taking a Ratio
unique approach, and developing a portfolio
The second annual IWLPC returns to the FOR
Double Tree Hotel in San Jose for two days,
of new processing and permanent materials FOR
November 3th and 4th. page 8
for producing high reliability chip scale, flip AUGUST
chip, and wafer level packages. page 26 Q3 2005 / MEPTEC REPORT 1
consistent results

Honeywell Wafer Thinning Products — provide unsurpassed

consistency and uniformity from batch to batch, improving yield.
Thanks to our world-class technologies and production
techniques, Honeywell can provide consistent performance
and unsurpassed etch uniformity meeting our global customer
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visiting Or call 1-408-962-2000.
© 2005 Honeywell International Inc. All rights reserved.
Council Update
Volume 9, Number 3
A Publication of

The MicroElectronics Packaging
& Test Engineering Council
elcome to our Q3 issue. It’s Our other feature article came about from
801 W. El Camino Real, No. 258
Mountain View, CA 94040 been a tumultuous last few a seminar that MEPTEC held recently called
Tel: (650) 988-7125 months for many citizens who “Winning Strategies for New Product Launch-
Fax: (650) 962-8684 suffered so much in the terrible es”, taught by Doug Molitor and Charles DiLi-
aftermath of Hurricanes Katrina sio of D-Side Advisors. This was somewhat
Published By and Rita. Jim Walker of Gartner Dataquest, of a diversion for MEPTEC, since we usually
who presents to our members at our annual hold technical symposiums. With more of a
Bette Cooper packaging forecast luncheon each September, business slant, the seminar provided new ideas
Design and Production used the storm analogy to present his forecast and strategies to help our members become
Gary Brown in his presentation. Entitled “Riding Out the more market-savvy. Part of the seminar that
Sales and Marketing
Kim Barber Hurricane: Sink, Swim or Surf”, Jim gave us was led by Charles DiLisio included a section
Contributing Editor the outlook on the global economy, electronic on “Marketing Mavens”. Charles describes
Jody Mahaffey equipment, semiconductor, and packaging/test Mavens as “…a system thinker, the guy who
–––––––––––––– services market, and the packaging forecast. If looks out to the future and innovates new
MEPTEC Advisory Board you’d like a copy of Jim’s presentation please products.” He states that Mavens exist in every
Phil Marcoux
MEPTEC Executive Director contact MEPTEC. We appreciate his personal, organization, and he shows us how to identify
as well as Gartner Dataquest’s, continued sup- and utilize them. A very interesting concept;
Seth Alavi
SunSil port over the years. read all about it in his article “Markets Have
Joel Camarda Our next event will be held on November Changed but Marketing Has Not” on page 30.
Camarda Associates
17, 2005 at the Hyatt San Jose hotel in San Our Editorial this issue is contributed by
Gary Catlin
Plexus Jose, California – Roadmaps for the Next longtime MEPTEC Advisory Board member
Rob Cole Generation of Semiconductor Packaging: A Joel Camarda of Camarda Associates. As the
MiTech USA User’s Perspective of Evolving Technologies. symposium chair for the August event on Pack-
John Crane
J. H. Crane & Associates
MEPTEC Advisory Board members Marc aging Strategies, Joel was inspired to write
Jeffrey C. Demmin Papageorge of Semiconductor Outsourcing “The Profitability Challenge – Or Darwinism
Tessera Solutions and Abhay Maheshwari of Xilinx, in the Semiconductor Industry”. It is enlighten-
Mark DiOrio
MTBSolutions, Inc.
are chairing this unique event. Building on ing to read Joel’s thoughts on business climates
Bruce Euzent
MEPTEC’s successful Packaging Industry and models, market shares, and how things
Altera Corporation Roadmaps symposium in 2003, this event will have changed…or, to quote Joel, “So what’s
Skip Fehr continue looking ahead and predicting new new?” See page 38 for this evocative piece.
Julia Goldstein
Advanced Packaging Magazine
requirements for semiconductor packaging, Our Industry Analysis coverage this issue is
Chip Greely
assembly and test. Representatives from many
Qualcomm different sectors of the industry participated continued on page 9
Anna Gualtieri
SPEL Semiconductor Ltd.
in the 2003 event: subcontractors, IDMs, and
suppliers. The differentiating factor for the
Bance Hom
Consultech International, Inc. 2005 event will be the perspective of the pre- Issue Highlights
Ron Jones
N-Able Group International
senters: we’ll hear from the users themselves. Executive Director 4
Pat Kennedy
See page 5 for information on attending, exhib-
GEL-PAK iting or sponsoring. MEPTEC Events Follow-up 6
Nick Leonardi As usual, we also offer a follow-up look Industry Analysis 10
CMC Interconnect Technologies
Abhay Maheshwari
on a past symposium. In August we held an
Xilinx event on Semiconductor Packaging Strate- University News 13
Mary Olsson gies: Improving Costs, Productivity, and Total Industry News 16
Gartner Dataquest
Services to Customers. Chaired by MEPTEC
Marc Papageorge
Semiconductor Outsourcing Solutions Advisory Board member Joel Camarda of MEPTEC Technitorial 24
Doug Pecchenino Camarda Associates, the event brought togeth-
Member Company Profile 26
Ray Petit er factory managers, process specialists, logis-
Pacific Rim Technology
tic managers and technical gurus from many
Jerry Secrest Feature Articles
Secrest Research different companies to discuss how they have
Jim Walker improved costs, efficiencies, and total service • A Die Processors View of 28
Gartner Dataquest
to customers. See page 6 for Jody Mahaffey’s the Evolution of Bare Die
Russ Winslow
Six Sigma write-up on “The Evolution of Packaging Requirements
–––––––––––––– Companies”.
• Winning Strategies for 30
Our feature article this issue is from
MEPTEC Report Vol. 9, No. 3. Published quarterly by New Product Launches
MEPCOM, 801 W. El Camino Real, Mountain View, CA
Jim Rates of Chip Supply, Inc., a longtime
94040. Copyright 2005 by MEPTEC/MEPCOM. All rights MEPTEC Corporate member company. In “A • Thermal Management of 32
reserved. Materials may not be reproduced in whole or in
part without written permission.
Die Processors View of the Evolution of Bare LGA Packages
MEPTEC Report is sent without charge to members of Die Requirements” Jim gives us some history
MEPTEC. For non-members, yearly subscriptions are avail- on the introduction of Known Good Die and Calendar 37
able for $75 in the United States, $80US in Canada and
the reasons behind the demand for KGD, and
Mexico, and $95US elsewhere.
discusses WLCSP, CSP and SIP. See page 28 Editorial 38
For advertising rates and information contact Kim Barber,
Sales & Marketing at (408) 309-3900, Fax (650) 962-8684. for this informative piece. Q3 2005 / MEPTEC REPORT 3

MEPTEC Executive Director

There’s a Great Need

for Cooperation

he tragedy that has befallen Packaging Strategies” symposium in ers, they’ve even been able to report a
the U.S. following Hurricane August 2005, Maniam Alagaratnam, 10 to 15% increase in sales. LSI Logic,
Katrina, and the upcoming VP of Package Development for LSI with the help of it’s Low-K supplier
holidays for Thanksgiving in Logic discussed the critical need for and the very talented engineers under
many countries causes me to cooperation with co-design and co- Maniam, was able to avoid adversity.
reflect on the great need for cooperation development of packaging with the IC Sadly, many of the victims of Hur-
in the world. process. He’s very qualified to speak on ricane Katrina and the Southeast Asia
Hurricane Katrina is but one exam- this given his challenging experiences Tsunami won’t be as fortunate as ASE’s
ple where a calamity on a mighty entity, with the early Low-K layers and wire rapid rebound. They still need our help
in this case the Louisiana-Mississip- bonds on his ICs. and cooperation. Please, as you cel-
pi Region of the United States, has Dropping the walls of competition, ebrate Thanksgiving in your country,
exposed the weaknesses that a country, dismissing the differences in politics don’t forget these victims. There are
a region, and even a company have and ideologies, and paving over the several respectable agencies listed on
when the unforeseen strikes. chasms between religions after events the web that can direct you to how and
The tsunami in Southeast Asia is like these are the only way I can think what you can do.
another heart-wrenching example. of for the world to continue to strive to
Within our own semiconductor be a better place. Happy Thanksgiving and keep push-
packaging industry the fire in May 2005 ASE, with the support of its equip- ing cooperation! ◆
in ASE’s Chungli Taiwan factory sent a ment suppliers and customers, was
wave of fear that the IC industry would able to emerge from the fire with little
be adversely affected. adverse impact. Thanks to the swelling Phil Marcoux
At MEPTEC’s “Semiconductor market for entry-level personal comput- Executive Director, MEPTEC

4 MEPTEC Report / Q3 2005

MicroElectronics Packaging and Test Engineering Council Join Us!

A O N E - D A Y T E C H N I C A L S Y M P O S I U M & E X H I B I T S

Roadmaps for the Next Generation of

Semiconductor Packaging
A User's Perspective of Evolving Technologies

oo often, technology is developed for the sake of technology itself and not from the point of view of the ultimate customer
whose usage and requirements may dictate developments that are tailored towards actual applications. What lies in the
future is not clear to the users and even less so to the development community. As the device technology evolves into “next
generation”, the interfaces that make these devices useful to the external environment have to evolve as well. What future design
and integration manufacturing tools are needed?
Building on MEPTEC’s successful Packaging Industry Roadmaps symposium in 2003, this event will continue looking ahead and
predicting new requirements for semiconductor packaging, assembly, and test. Representatives from many different sectors of the
industry – sub-contractors, IDMS, and suppliers – participated in the 2003 event. The differentiating factor for the 2005 event will be
the perspective of the presenters: we’ll hear from the users themselves.
This forum will be a gathering of those “ultimate customers” and geared towards discussing future horizons in device applications
from their point of view. It will provide insight into requirements for the materials, processes, equipment, infrastructure test, and
methodologies required to improve and clear the path for future needs in the electronic packaging and assembly industry.
The attendees of this symposium will:
■ Learn about successful implementation strategies for evolving assembly and packaging technologies
■ Examine creative solutions to electrical and thermal performance design requirements
■ Increase knowledge of how to achieve successful end-product integration for next generation devices
■ Look at ways to improve integration and ease of use on for new materials
■ Gain better understanding of new applications to develop reliable device package approaches

Presenters will come from the following product/device sectors:

■ ASIC/PLD ■ Memory ■ Microprocessor ■ Emerging devices (MEMS, optoelectronics, etc.)
■ Analog ■ Graphics ■ FPGA



circuitnet ®


N O V E M B E R 1 7 , 2 0 0 5 • S A N J O S E , C A L I F O R N I A


Register Online Today at

MEPTEC Events Follow-up

The Evolution of Semiconductor

Packaging Strategies:
Packaging Companies Improving
Improving Costs,
Costs, Productivity,
Total Service
Service to
Productivity, and
to Customers



Jody Mahaffey
JDM Resources Presented by

rom DIP to SiP, from cans to Chen presented in the Cost Reduction to help facilitate these changes and
wafer scale, new packages are & Process Automation Session. provide more cost-effective packag-
being developed to meet or “It is not so much a matter of ‘chang- ing through process automation, yield
exceed the device requirements ing’ strategies,” said Joel Camarda of improvements, etc. Skip Fehr, Indus-
necessary to stay in the game. Camarda Associates, “our business try Consultant and Session Chair for the
But what about the packaging indus- is dynamic, not static, and therefore Cost Reduction & Process Automation
try…is it keeping up too? With changes business strategies must constantly Session, stated that he has seen “evolu-
coming so quickly, it is imperative evolve, adapt, and progress. From the tion in the last couple years in this area,
for the packaging industry to continue manufacturers’ perspective (captive and but no revolution.”
to evolve and change their business contract), efficiencies must constantly Nguyen also said that he has seen
strategies to keep up. With advances in improve for cost, quality, and service.” some evolutionary advances in process
capital equipment, packaging concepts, Camarda was Session Chair for the development, process automation, IT
factory logistics, and supply chain man- “Super-Factory” Management Session management (e.g., Web-based visibility
agement issues, determining where to of the symposium. and control), etc., but no single cure-all
change and how to change is not an Mark Stromberg, Semiconductor solution.
easy task. Of course the ultimate goal Equipment Market Analyst for Gart- “Software and automation tools are
has to be to keep the customer happy, ner/Dataquest and presenter in the extremely important elements which
while continually trying to improve Cost Reduction & Process Automation make the industry more efficient and
costs and productivity. To help com- Session of the symposium, said that it productive,” added Chen. “The para-
panies find the best approach to this is not just packaging companies that digm change today is for greater cus-
complex evolution, MEPTEC brought need to change their strategies, but tomization in products and zero inven-
together key factory managers, process device makers as well. “Device makers tories in the supply chain. For these
specialists, logistics managers and tech- need to adapt to an ever-changing pack- reasons, process automation and yield
nology gurus for a Packaging Strategies aging market. Multi-device packages, improvement must be considered at the
technical symposium to discuss how Wafer-Level Packaging (both in wafer system level.”
companies can change and grow, and fab and in packaging facilities) and Many of these advances in process
ultimately keep up with the demands the rise of packaging subcontractors as automation and software tools are being
of the technology world. Some of the major market players are all key drivers used by what some people are call-
speakers from the symposium gave us affecting packaging strategies.” ing the “Super Factory”. According to
a little insight into the topics that were Jeff Demmin, Director of Ad- Fred Hartung, Senior Director Global
discussed. vanced Programs for Tessera Tech- Logistics for Solectron Corpora-
Luu Nguyen, Senior Engineering nologies acted as Session Chair for tion, “The new “super factories” are
Manager for National Semiconduc- the Package R&D Session. He believes compact in terms of their layout, taking
tor, was a speaker in the Cost Reduc- the product miniaturization that results into consideration the flow of mate-
tion & Process Automation Session from today’s advanced packaging tech- rial, resources and the capital equip-
of the symposium. He feels that com- nologies is absolutely critical to the ment. The factories are flexible and
panies must change their packaging success of most products in the market- lend themselves to changes in orienta-
strategies to maintain flexibility in the place, so companies have to focus on tion and easy work flow. They are able
face of an ever-changing competitive finding the best solutions wherever they to adapt to the changes in customers’
landscape. might be. Finding that best solution requirements or changes in the environ-
William (Bill) Chen, Senior Tech- may require changes to a company’s ment.” Hartung presented in the Global
nical Advisor for ASE (US), believes business strategies. Logistics Session.
that packaging strategies need to Whether it’s evolution or revolution, Bill Chen believes the “super fac-
respond to the “consumerization” of the everyone agreed that changes in gen- tory” for today and the future should be
electronics market, which has resulted eral business strategies are necessary. a super-intelligent factory. “We need to
in packaging becoming a primary dif- There appears to be several technology add super-intelligence to our factories
ferentiator for consumer electronics. and/or software advances being made so we add maximum value to our cus-

6 MEPTEC Report / Q3 2005

tomer’s products”, said Chen. “A “super believes that the packaging R&D busi- packages that leverage their existing
factory” should be lean and intelligent ness needs to be a collaboration between tooling and materials. “It would be
with a diverse menu of products where material suppliers, equipment suppliers, smart of independent technology devel-
the factory manufacturing process adds purchasing subcontractors, customers, opers to create technologies that lever-
value, so packaging becomes the pri- and research institutions with the SATS age existing tooling and materials to
mary differentiator.” community continuing to take a leader- maximize the likelihood of the technol-
Many of the presenters believe that ship role in the development and imple- ogy being utilized,” said Demmin. “On
more changes are necessary to help mentation of next-generation packages. the other side of the coin, the volumes
these factories operate more produc- He elaborated, “With packaging, R&D for new products these days can be so
tively, and therefore, more cost effec- must become an important joint focus large that using new tooling or materi-
tively. Hartung pointed out, “Supply for our entire community. It is vital that als is a reasonable option.”
chains need to be flexible in order to for everyone to succeed, everyone must As new packages become more
meet changing sourcing origins of sup- get involved.” complex, managing the supply chain
plies and end-market destinations. Fac- Demmin stated that packaging R&D for those products becomes another
tories need to be able to adapt to shorter could belong in any or all of the busi- hurdle for packaging companies. While
life cycles of products. This requires ness sectors involved. He said that, most agree that the OEM or product
shrinking the value stream and building “Packaging sub-contractors can choose supplier must be ultimately responsible,
nimble factories which imbibe the spirit to provide advanced R&D, or they Chen believes that the industry has
of change and adopt flexible manufac- could choose to provide the lowest cost natural breakpoints in the supply chain,
turing so as to respond to customers or quickest turnaround, for example. so that there are individual companies
faster.” IDMs could also choose to provide who can take leadership to manage
Skip Fehr also pointed out that more advanced packaging technologies that their sector of the supply chain.
standardization would be of help, “But they have developed themselves, or Hartung, taking this one step fur-
while there will be more process stan- they could rely on sub-contractors or ther said, “The OEM should have final
dardization, I believe there will less pack- independent R&D firms. It is totally a responsibility unless this has been
age standardization. Factories need to business decision, reflecting the type purposefully outsourced to a contract
be set up to handle quicker changes, but of business that a company wants to manufacturer. The appropriateness of
need to establish automation tooling that be. Each firm needs to find the value / outsourcing the control of the sup-
allows changes with minimum issues.” cost point that makes sense for it. The ply chain will depend upon size and
There was general consensus from marketplace might steer R&D towards maturity of the OEM and the contract
the presenters that as process automa- a particular type of organization, but it manufacturer as well as the geographi-
tion improves and more logistics sys- is likely that there will always be pock- cal regions covered by the supply chain.
tem controls are developed for “super ets of packaging R&D in all types of The responsibility rests with the entire
factories”, there should be an increase companies in the industry.” value stream, so to speak, the different
in outsourcing. Mark Stromberg feels Camarda and Fehr both believe that entities would require adopting a col-
that, “As the ‘super factory’ concept the packaging factories need to do the laborative approach. They would need
emerges and capital costs continue to research. “You need a factory to test to take into consideration the needs of
rise, there will be fewer players that can R&D developments,” said Camarda. their value partners next in the overall
play the manufacturing game. Other “If you do not have a factory, testing supply chain so that the final customer
device IP companies will be forced into your R&D is very difficult.” benefits.”
the outsource model.” Fehr added, “In the end if an individ- As outsourcing becomes more and
Hartung agrees that these devel- ual company does the research, it may more common, many people think
opments will lead to an increase in be difficult to get that package installed there may be space for companies who
outsourcing as corporations are able to in the ‘super factory’ unless it can be provide logistics management services
take advantage of cost benefits through used across the board for many com- from start to finish of a product. This
the use of flexible supply chains, chang- panies. An individual company will not is already occurring, according to Har-
ing sourcing and markets offered by want to give away his research.” tung. “However,” he adds, “these 3PL
“super factories”. Hartung added that if the packag- companies need to develop a greater
But as Nguyen pointed out, “There ing companies are going to be the understanding of the non-logistics por-
are a number of factors which con- ones to develop new packages, they tions of the supply chain they operate.
trol the decision to outsource, such need to closely understand the chang- Again, this depends upon the relative
as a company’s packaging infrastruc- ing requirement of their customers for maturity along with system capabili-
ture (development, support, capacity, developing more reliable and better ties of the companies involved. These
etc.), its packaging portfolio, its cost quality packaging material, also pro- companies need to understand the value
structure, etc. Ultimately, outsourcing viding creative packaging solutions in stream and the flow of the inbound and
is each company’s business decision.” order to balance the packaging and outbound logistics, so they can optimize
While trends continue to lead to transportation costs. the movement of the consignments and
more outsourcing for packaging, who One big advantage to packaging enhance carrier utilization.”
develops the next generation of pack- subcontractors doing their own R&D Chen pointed out that in order for
aging is still up for discussion. Chen is that it allows them to develop new this to work, these logistics manage- Q3 2005 / MEPTEC REPORT 7

If the latest advances in chip-scale electronics, flip-
chip technology and wafer-level packaging and test
are important to your company’s success, you must
be in San Jose at the second annual IWLPC.
Plan now to attend this world-class, two-day event on November 3-4.

Presented by Chip Scale Review and the SMTA

Platinum Sponsors:

Dr. Ken Gilleo Dr. Luu Nguyen Dr. Bruce McWilliams

ET-Trends LLC National Semiconductor Tessera Technologies

We’re building on the success of our first IWLPC last October. This year there will be more of
what you asked for. More exhibits. More original, high-quality technical presentations.
We pledged last year to make this the best conference going. And our attendees said we kept
our promise!
We’ve reserved the same venue, the deluxe DoubleTree Hotel, only minutes from San Jose
International Airport, for this comprehensive, international meeting. We’ll have multi-track panel
presentations discussing the latest advances in the industry. Exhibits by industry leaders will
demonstrate the latest products and services for the packaging and test industry.
For more details, visit
Here are a few of the topics we’ll cover:
• Emerging technologies • WLP modeling and simulation • SIP vs. SOC • Multichip packages
• RF and microwave integration • Silicon/GaAs/MEMS/photonics • Wafer thinning
• Test and reliability • Flexible substrates • Interposers • Encapsulants and underfills • MEMS
fabrication and packaging • Flip-chip bumping • Wafer-level packaging • 3D packaging
• System-in-chip • System-on-chip • Impact of lead-free lithography options
• Materials/adhesives • On-die passives • Photomasks • Plasma treatments • RFID wafer-level
assembly • Singulation • Routing on wafer • Surface cleaning • Photoresist tradeoffs
• Wafer-level underfill • WLP trends
MEPTEC Events Follow-up

ment service companies would need to

show a significant value-add.
Of course there are now and prob-
ably always will be certain package
types that are more difficult to manage
through the supply chain, no matter
who is managing it. Specialty packages
which are commonly small volume/high
ASP packages are hardest to control
according to Fehr. “These packages are
usually less able to be put in some type
of repeat purchase level…too many
inventory dollars and too few users.”
“SiP and Subsystem packages are
prime examples today of consumer
product-oriented package types that are
difficult to manage”, said Chen. “This is
where a ‘turnkey organization’, offering
packaging, test, materials, logistics, and
EMS, has the natural advantage because
of the knowledge base they have to opti-
mize the solution.”
It looks like packaging companies
will certainly have their hands full try-
ing to keep up with all the technology
changes happening today. Between sup-
ply chain management decisions, R&D
for new packaging concepts, and incor-
porating new process automation and
software tools into their “super facto-
ries”, it is no wonder that some changes
in business strategies might be nec-
essary. ◆

MEPTEC Council Update

continued from page 3

contributed by Jan Vardaman, Karen Car- Fairbanks (UAF). Dr. Pramod C. Karulkar, page 32. Very soon we’ll be announcing
penter and Linda Matthew of TechSearch Director of the Office of Electronics Min- plans for our 2nd Annual “The Heat is
International. Jan and her team offer iaturization at UAF, joined us in August On” symposium…stay tuned for that!
“SIP: A New Version of the MCP?”. at our Packaging Strategies symposium to Another new feature is something we
They look at the history of MCMs and discuss the role of academia in packaging call a “Technitorial” (or “technical edito-
the entry of SiPs, and discuss numerous research and design. On page 13 you can rial”). We’ll be asking members and sup-
configurations and applications. See page read about the “World Class Electronic porters to write one-page “how-to” pieces
9 for this interesting article. Miniaturization Program at the Top of the on various technical subjects. The first
Our Member Company Profile this World”. Once again we have Jeff Dem- is from longtime Corporate MEPTEC
issue is MEPTEC Corporate member min of Tessera, and MEPTEC Advisory member and supporter, ASAT Inc. See
DuPont Semiconductor – their Packaging Board member, to thank for letting us page 24 to see “How to Meet the Demand
and Circuit Materials division. Headquar- know about this institution and its unique for Smaller Packages without Sacrificing
tered at DuPont Electronic Technologies programs. Performance”.
in RTP, NC, there is a “new kind of team We’re also introducing a couple of We’d like to thank all of our con-
with intent to become the leader in how new features this issue. With the great tributors for making this a great issue. If
integrated circuits are connected to the interest that arose surrounding our Q2- you’re reading our publication for the first
external world”. They have a unique 05 event on Thermal Management, we time at one of the many events where we
approach in developing new materials for decided to cover a thermal subject in each distribute, or if you’re a new member, we
many types of packages. See their story issue. Dr. Kaveh Azar of Advanced Ther- hope you enjoy it.
on page 26. mal Solutions will be writing these piec-
In our University News section this es. The first one is “Thermal Management Thanks for joining us! ◆
issue we profile the University of Alaska of LGA Packages”, and can be found on Q3 2005 / MEPTEC REPORT 9

MEPTEC Industry Analysis

A New Version of the MCP?
E. Jan Vardaman, Karen Carpenter, and Linda Matthew
TechSearch International, Inc.

he term multichip module layer laminate substrate. The module was A Variety of SiP Configurations
(MCM) has been around for packaged in a 256-pin PQFP. A seven-chip for a Growing Number of
decades and even saw a tran- phase controller unit was also developed Applications
sition to a few chip package for an industrial robot application. The Digital camcorders have been one of
coined multichip package mixed signal module was packaged in the first adopters of new and innovative
(MCP). Recently a new term has emerged an 80-pin PQFP. An encryption/decryp- packaging technology and the adoption
that has similar drivers and issues. Will tion module for wireless communications of SiP is no exception. Driven by goals of
this package be more successful that the contained four chips mounted on a four- smaller size and lighter weight, cameras
package concepts of the last decade? layer laminate substrate. The module was and camcorders continue to use advanced
What is the difference? packaged in a 104-pin PQFP. Additional packages, including SiPs. Hitachi/Mat-
applications for Fujitsu modules included sushita Electric Industrial jointly devel-
MCMs and MCPs: a magnetic tape system and a fax modem. oped a camcorder containing an SiP with
A History Lesson Although the MCP was a lower cost alter- stacked chips. Sony describes its solution
MCMs have been confined to high- native to MCMs, the KGD and test issues as “System Integrated Packaging.” Sony’s
end applications, where the value they seen in the MCM arena were also present DCR-IP220 contains a stacked package
contribute to the ICs is great enough to here. These issues continued to restrict with logic and 128M SDRAM in a 240-
absorb the cost of the custom design, broad market acceptance of the concept. pad array package. The Sony Cyber-Shot
assembly, and test. These applications In addition, many companies were able to digital camera (DSC-F77) has also been
include high-end computers, military, and design a single chip solution sometimes introduced with SiPs. One package con-
aerospace applications. The multichip called a system-on-chip (SOC). The SOC tains logic plus 32M flash and the other
package (MCP) was introduced as an provided the same function as the mod- contains logic plus 128M SDRAM.2 Sony
alternative to achieve the desired form ule.1 has also introduced stacked package SiP
factor needs, but at a cost affordable for solutions.
portable products. By having a busi- Enter the SiP Design and semiconductor packaging
ness model similar to that of individu- System-in-Package (SiP) is a func- for mobile phones are increasingly driven
ally packaged ICs, the MCP became a tional system or subsystem assembled by consumer demand for smaller prod-
low-cost solution – or so it seemed. It into a single package. It contains two or ucts with greater functionality. SiP is one
utilized existing die and existing package more dissimilar die, typically combined answer to this demand because it offers
structures. The most promising MCPs with other components such as passives, the following:
were functional blocks. Rockwell’s fax filters, antennas, and/or mechanical parts.
modem was well known for its three- The components are mounted together on • Reduced product cost
chip version featuring chips wire bonded a substrate to create a customized, highly • Added features
to a laminate substrate. Several genera- integrated product for a given applica- • Reduced size
tions of the S-MOS Cardio PC card used tion. SiPs may utilize a combination of • Improved performance
multichip packages, typically with three advanced packaging including bare die • Accelerated time-to-market
chips attached to a laminate substrate. (wire bond or flip chip), pre-packaged ICs
Oki Electric offered a credit card size PC such as CSPs, stacked packages, and/or A variety of SiPs are increasingly
containing a multichip BGA package. A stacked die. An SiP can by definition found in the RF, digital baseband, and
361 I/O PBGA contained the chip set of be an MCM or MCP but the converse is transceiver sections of mobile phones.
three ICs and was one of the first mul- not necessarily true. The fit depends on Some of these structures are planar con-
tichip BGAs in production. The package the type of devices being packaged and structions and several incorporate inte-
body size was 29 mm x 29 mm, and 2.6 whether the result creates a functional grated passive substrates. Philips has
mm thick. The eutectic solder ball pitch block. developed a thin-film-on-silicon module
was 1.5 mm. A digital cellular phone Among the advantages of SiP solu- that incorporates passive devices such as
introduced by Toshiba contained an MCP tions include smaller form factor, fast planar capacitors, pit capacitors, resistors,
consisting of five chips wire bonded to a turn-time, and low NRE costs (compared and inductors in the substrate. Philips
four-layer laminate substrate. The module to a single die design). These advantages calls the module a silicon-based SiP and
was packaged in a leadless chip carrier. are compared and contrasted with other is in production with the module. For
Fujitsu developed a ten-chip MCP for a alternatives such as SOC. improved electrical performance the typi-
digital cellular telephone using a seven- cal aluminum conductor was replaced by

10 MEPTEC Report / Q3 2005

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MEPTEC Industry Analysis

standardization of pin-out footprints (for

the top stacked package) was necessary,
and package-stacking equipment had to
be made available.5 All of these needs
have been met and the package is in pro-
duction. Amkor’s PoP, developed over the
last four years, is shown in Figure 2.
STATSChipPAC and Qualcomm are
promoting a package-in-package (PiP)
concept that Qualcomm refers to as a Figure 3 – Package-in-Package
stacked module package and is using in Structure. (Source: STATSChipPAC)
production today. While the package is
considered to be more expensive than a
stacked die package, it offers flexibility conventional packaging are able to absorb
Figure 1 – Intel’s Four-die Stacked
in the configuration of the memory and the cost of custom packaging.
Package. (Source: Intel) allows the memory to be fully tested There are still issues to be resolved
before the packages are molded together.6 and no one package construction meets
Figure 3 shows a drawing of the PiP con- all needs. SoC and SiP are complimen-
a thick copper layer.3 STMicroelectron- cept developed by STATSChipPAC. tary solutions for the electronics industry,
ics is shipping transceiver modules with SiP applications also include medical according to Renesas and other compa-
an RF ASIC flip chip mounted on top of electronics such as smart pills, defense nies in Japan. Each offer strengths and
an integrated passive device. SyChip’s electronics, and aerospace applications. weaknesses. The key to success for SiP
module incorporates integrated passives While these applications represent smaller is the word “system”. Consideration
in the thin film on silicon substrate. Flip unit volumes they represent higher value- must be given to the various alternatives
chip devices are mounted on the module added modules. Computer and telecom- in the planning stage of system design as
to provide a “plug and play” solution for munication systems also use SiPs. These an integral part of the overall strategy. To
a WLAN application. The module pro- configurations typically feature at bare accomplish this, a change must be made
vides a complete system with no external die surrounded by packaged memory. in the process to allow system archi-
components needed and no RF expertise The module allows reduced layer counts tects, IC designers, I/O planners, packag-
required by the customer.4 in the system board and total system ing engineers, and printed circuit board
Additional structures include stacked cost savings. SiPs can also be found in designers to work closely together. The
die packages or stacked modules. The automotive electronics and home controls industry structure, which has migrated
first stacked packages utilized in mar- including lighting. to one where these skills reside in many,
ket applications contained only memory, separate companies must be virtually re-
but increasingly logic devices are being The Future integrated to enable co-development and
added. Figure 1 shows a stacked memory Key issues for SiPs include avail- co-design. ◆
package. While the thinnest packages ability of bare die and testing, logistical
(important for mobile phones) feature and engineering issues, wafer thinning TechSearch International has just released
bare die stacked inside, issues of bare die for stacked die packages, and assembly. its new study on SiP: System-in-Package:
availability, logics, and test Issues such as the availability of known The New Wave in 3D Packaging.
have resulted in the introduction of a good die, logistics problems in obtaining
number of stacked package configura- die, and testing are the same issues that
1 E.Jan Vardaman, “Is SiP Haunted by the
tions. have plagued the MCM industry since its
The package-on-package (PoP) con- beginning. New package constructions MCM Ghost?” Circuits Assembly, Novem-
cept is being promoted by a number that feature packages for some or all the ber 2004, pp. 16-17.
of companies, including Amkor. In this die are helping to solve these issues. 2 K. Iwabuchi, “Packaging Technology
construction one package is stacked on With the volumes provided by mo- Trends in Digital Imaging Products,” IPSS,
top of another. The packages can be bile phones, this application acts as a key SEMICON Japan, December 2004.
mounted by the IC package subcontractor driver for the continued adoption of SiP. 3 D. Chevriw, et al., “A Silicon based System
or the board level assembly house. Infra- Other applications that require higher in Package (SbSIP) Technology, EMRC
structure developments were required, performance that cannot be obtained from 2005, June 12-15, Brugge, Belgium, p.
4 System-in-Package:The New Wave in 3D
Packaging, TechSearch International, Inc.
5 Akito Yoshida, “Package-on-Package
Space Savings with Flexibility,” Advanced
Packaging, August 2005, p. 12.
6 T. Gregorich, “SIP: Panacea or Pan-
dora? IEMT Symposium, SEMICON West,
San Francisco, CA, July 12, 2005.
Figure 2 – Amkor’s package-on-package (PoP).

12 MEPTEC Report / Q3 2005

MEPTEC University News

World Class Electronic

Miniaturization Program at the
Top of the World
Pramod C. Karulkar, Ph. D., Director, Office of Electronics Miniaturization
University of Alaska Fairbanks

hen one thinks of Alas-
ka, one visualizes a
vast, magnificent land-
scape of immense natu-
ral beauty, auroras and
glaciers, the midnight sun, and the
cold winter with very short periods
of daylight. In some circles, Alaska is
known for the regional supercomput-
ing center and the geophysical and
arctic research carried out at the Uni-
versity of Alaska with one of its cam-
puses located on a beautiful hillside in
Fairbanks. However, as perceptions
go, one does not easily think of Alaska
as the home of anything in high tech-
nology other than the oil pipeline.
A new ambitious project at the
University of Alaska Fairbanks
(UAF) is envisioning Alaska as a
home for high technology R&D, pilot
production, and commercialization.
This project, led by Dr. Pramod C.
Karulkar, director of UAF’s Office of
Electronic Miniaturization, is lever- licensed and transferred Chip Scale of the program is the chip scale pack-
aging the university’s infrastructure, Packaging (CSP) technologies from aging facility that occupies 1530 sq.
industrial partnerships, and govern- Tessera Inc., and passed test-parts ft. cleanroom in the state of the art,
ment sponsored programs to establish through JEDEC-like qualification 123,000 sq. ft. Natural Sciences Facil-
an advanced technology center that with excellent performance. The facil- ity (NSF). Although planned as a
will enhance the university’s training, ity has now started CSP projects for class 10,000 cleanroom, it has been
education, and research programs and customers and has capacity to accept operating well below class 1000
catalyze regional economic growth CSP and electronic miniaturization because of some added features such
in high technology area. UAF has projects from the government as well as an air shower at the entrance and
established the Office of Electronic as the commercial sector. controlled access. The cleanroom is
Miniaturization (OEM) to address the Research in the arctic has always equipped with the latest equipment
advanced technology needs of the uni- required specialized electronics de- for R&D and pilot production of Chip
versity, potential sponsors, and local signed for the extreme ambient with Scale Packages, stacked CSPs, and
economic development efforts. Tes- power sources lasting for months or Systems in Packages (SiP). Many of
sera Inc. ( is play- years of service. UAF has a long his- the CSP capabilities such as dicing,
ing an important role in this endeavor tory of in-house innovative fabrication screen printing, adhesive dispensing,
by licensing and transferring chip using discrete components and ICs. die attach, wirebonding, etc. have a
scale technology and by partnering on UAF’s new program in electronics broader use beyond CSP production.
R&D in the area of advanced electron- miniaturization with facilities in sev- A materials analysis and characteriza-
ics packaging. The university has built eral buildings adds a high technol- tion facility co-located in the NSF and
a cleanroom equipped with a com- ogy vigor and competitiveness to that equipped with many spectroscopic and
plete set of electronic packaging tools, innovativeness. The main investment microscopic techniques supports the Q3 2005 / MEPTEC REPORT 13

MEPTEC University News
SJSU’s educational philosophy emphasizes a
hands-on practical education, based on a sound
mercial sector the future.
understanding of engineering fundamentals. OEM’s staff has extensive indus-
trial and academic hands-on experi-
ence in sensors, embedded electron-
ics, advanced packaging, wafer fabri-
cation, pilot production, and systems.
The program is rapidly growing and
welcomes help in the form of equip-
ment donations or directing talent to
apply for OEM’s open positions. The
Office of Electronics Miniaturization
is aggressively pursuing customers,
collaboration, and sponsored pro-
grams in the following areas:
• Design, engineering, and produc-
tion of Tessera µBGA™ chip scale
packages (CSP), chip stacking.
• Application specific development
and implementation of Sensor Sys-
• Modeling and simulation of
mechanical and electrical performance
of miniaturized electronic systems.
• Design, engineering, prototyping
and pilot manufacturing of miniatur-
ized electronic Systems (Multi Chip
electronic miniaturization research. also opens the door for innovative
Module (MCM), System in a Package
X-ray and acoustic microscopic tools ways to increase the level of function-
(SiP), high density boards, stacked
that are vital to the packaging research ality in a very small volume by com-
circuits, and dense electronics).
and pilot production will be located bining different ICs. Most of the CSP
• Partnership on electronic miniatur-
in the materials analysis facility. The facilities in the world are outside the
ization projects involving moderniza-
program is also supported by other US and usually require very large pro-
tion and/or innovative ideas.
research laboratory facilities in the duction volumes. UAF’s facility will
• Executing complex electronics
physics (nano), electrical engineer- play a vital role in supporting R&D
projects by identifying and acquiring
ing (RF, wireless, sensors, and space and pilot production needs of entre-
necessary technology and partners.
electronics) and mechanical engineer- preneurial customers and those in the
• R&D, consulting, training, and
ing (thermomechanics) departments. government sector who cannot access
market search in electronic systems
Electronic Miniaturization adminis- offshore foundries. Customers will be
solutions, microelectronics design and
trative offices, microfabrication labo- able to combine CSP, stacked chip, or
fabrication; materials, process, and
ratory (under renovation), customer Flex MCM capabilities with the ser-
device Technologies; embedded sys-
service, and OEM’s design, engineer- vices of OEM’s design and engineer-
tems; RF technologies; power man-
ing, & test group are located in an ing group to obtain advanced elec-
agement; failure analysis and technol-
approximately 14,000 sq. ft. space in tronics solutions in a one-stop-shop.
ogy transfer.
a separate building near the campus. DMEA considers CSP technology
• Finding applications for your ideas
This facility houses design, layout, and UAF’s electronic miniaturization
or electronic products. ◆
modeling, simulation and electrical program with full range of services
characterization tools and has a sec- and technology critical to modern- For more information about University of Alaska’s
tion that can be secured separately for izing defense electronics. Although Electronic Miniaturization program see www. Specific further question should
proprietary or sensitive engineering the defense systems market is tough be addressed to OEM’s Director Dr. Pramod C.
work. to penetrate, UAF is expecting steady Karulkar (907 455 2000) or OEM’s PR Officer
OEM’s facility is qualified to fab- growth in demand. Industrial partner- Sonja Bickford (907 455 2000).
ricate Tessera’s µBGA, µBGA-L, ships are very valuable for OEM. In This material is based on research sponsored by
µBGA-W, and µZ versions of CSP. addition to partnership with Tessera, the Defense Microelectronics Activity (DMEA).
The chip scale stacking technology, OEM is partnered with Crane Aero- The United States Government is authorized to
reproduce and distribute reprints for Government
which has a proven track record in the space’s Advanced Integrated Systems purposes, notwithstanding and copyright notation
commercial world, is particularly valu- Division ( thereon. The views and conclusions contained
able to producing large compact solid in developing a sensor system project herein are those of the author and should not be
state memories for applications rang- that offers UAF learning opportunities interpreted as necessarily representing the official
policies or endorsements, either expressed or
ing from smart ammunition to space in electronic miniaturization and may implied, of the Defense Microelectronics Activity
systems. The stacked CSP approach result in more customers in the com- (DMEA).

14 MEPTEC Report / Q3 2005

MEPTEC Industry News

F&K Appoints New leadership was crucial to the

successful bond refinancing last
tions were announced at the an-
nual SEMI membership meet-
tion will support the stringent
requirements of the semicon-
Account Manager year and the recent $30 million
financing with the Company’s
ing, which was held during the
SEMICON West 2005 exposi-
ductor, flat panel display, tele-
com, optoelectronic and bio-
for European Sales two largest shareholders,” said tion in San Francisco. technology industries.
Henry Montgomery, chairman More information about Sili-
of the board of directors of
ASAT Holdings Ltd. ‘’Bob’s Silicon Border con Border is available online at
operations and financial experi- Taps Octavio Garza
ence will be invaluable as ASAT
enters its next level of growth.’’ to Run Office in Carsem Appoints
The Company also an-
nounced that effective Aug. 21, Mexicali New General
2005, Maura Wong, a board SAN DIEGO, CA – Sili- Manager for
member since June 2000, re- con Border Development has S-Site Factory
signed from the Company’s an-nounced that it has hired
board of directors coincident Octavio Garza as vice presi- SCOTTS VALLEY, CA – Car-
with her retirement from JPMor- dent of business development sem has announced that Mr.
gan Partners Asia (JPMP Asia). and administration. He will be M. H. Toh recently joined the
On Aug. 24, 2005, Eugene Suh, responsible for business devel- company as General Manager
a partner with JPMP Asia was opment for Silicon Border, as of the Carsem S-Site factory. He
elected to the board of directors, well as running the company’s reports to Carsem’s Chief Oper-
filling the vacancy left by the newest operations in Mexicali, ating Officer, Mr. S.W. Woo,
resignation of Ms. Wong. Prior Mexico. and is replacing the former Gen-
As of July 1st Philip Homami to joining JPMP Asia in 1999,
has taken on the position of Silicon Border’s Mexico eral Manager, Mr. Alex Khor,
Mr. Suh was an associate direc- offices will be based out of the who retired in June this year.
Account Manager within the tor at Bear Stearns in their spe-
F&K European Sales organiza- CETYS University in Mexicali, Mr. Toh has over 25 years of
cial situations debt investment Baja California. The new office experience in the semiconductor
tion. Over the past years he group, where he was respon-
has worked for F&K Delvotec is the most recent in a series of industry with an extensive back-
sible for sourcing and evaluat- milestones achieved for the ground in both the assembly
Ottbrunn’s project management ing debt investments in Korea,
and prior to that for their sales company in the past year. and test operations. He has held
Thailand, and Hong Kong. Garza comes to Silicon Bor- various management positions
subsidiary in California. Philip
Homami is responsible for our der from Sony Electronics Cor- in Production, Quality Assur-
customers in the zip codes 0-5 Ed Segal Named poration, where he spent nine
years in a variety of management
ance, and Process Engineering.
Prior to joining Carsem, he was
in Germany and all customers in
Belgium, Luxemburg and The Chairman of SEMI positions in strategic planning the Assembly Operations Direc-
Netherlands. All inquiries from and administration, including tor for National Semiconductor
these areas are coordinated by deputy director responsible for in Melaka, Malaysia.
him. manufacturing of $800M USD Carsem is a member of the
For more information visit in electronics products annually Hong Leong Group with facto- with over 3,600 employees in ries located in Ipoh, Malaysia,
Mexico. Garza is also a rec- Suzhou, China and sales offices
ognized leader in the Mexican across the USA, plus the UK
ASAT Announces electronics industry holding ac- and Taiwan. Carsem, Inc. sales
Management tive roles in business advisory
committees on curriculum for
headquarters is located in Scotts
Valley, CA.
Appointments and state and private universities.
Garza has also held prior man-
For more information visit
Board of Directors agement positions with Deloitte
Change & Touche and Monsanto.
Silicon Border is a 10,000- Maxtek Signs New
HONG KONG and PLEASAN- acre high-technology science
park catering to the specialized
TON, CA – ASAT Holdings
Limited has announced that the
needs of the semiconductor and Firms
Company’s board of directors other capital-intensive technol-
has announced the appointment ogy sectors. Planned for devel- BEAVERTON, OR – Maxtek
has appointed Robert Gange as Components Corporation, a
of Ed Segal, senior advisor to opment along the U.S.-Mexico
president and chief executive Tektronix, Inc. company and
Metron Technology, as chair- border in Mexicali, Silicon
officer, effective immediately. a custom microelectronics as-
man of the industry associa- Border enables a cost-effective
Mr. Gange succeeds Harry Ro- sembly and test service pro-
tion’s International Board of and competitive manufacturing
zakis, who was terminated by vider, has announced formal
Directors. Segal succeeds Tet- alternative in North America for
the board of directors. representation agreements with
suro (Terry) Higashi, chairman emerging and global companies.
“Bob has played a key role Dura Sales of Southern Califor-
and CEO of Tokyo Electron Improving upon the world’s
in managing the transition of nia, Hi-Peak Technical Sales,
Ltd., who served as chairman leading technology parks, the
ASAT’s manufacturing to Schoenduve Corporation, and
for the past year. The results of park’s 15 square miles of world-
China. In addition, his financial Somers-Stanton Incorporated,
the association’s annual elec- class infrastructure and educa-

16 MEPTEC Report / Q3 2005

MEPTEC Industry News

manufacturer’s representative (DMEA), Tessera has licensed this critical region with a local tionary new interconnect tech-
firms in Southern California, its MicroBGA® CSP technol- supply of leading technology nology, which offers greater
New England, Northern Cali- ogy to NDSU and has provided materials used for the produc- electromechanical performance
fornia and the Midwest respec- the university with the technical tion of semiconductors. at lower cost-of-ownership.
tively. knowledge and training neces- Honeywell’s current capa- This new package test technol-
“Maxtek’s success as a cus- sary to package and assemble bilities at the site include the ogy is based upon proprietary
tom microelectronics service semiconductor chips, such as production of materials sup- photolithographic technol-
provider is largely attributable EEPROM, DRAM and Flash porting 200mm semiconductor ogy developed exclusively by
to our deep technical experi- memory. These semiconduc- manufacturing, referring to the K&S.
ence and our ability to become tor devices are widely utilized diameter of the silicon wafer Quatrix is based on an ad-
an extension of our custom- in defense, medical, wireless, used to produce multiple inte- vanced photolithographic man-
ers’ development teams”, said consumer and computing elec- grated circuits or chips. ufacturing technology that pro-
Jeff Dick, Director of Business tronics to meet next-generation Scheduled to be completed duces no sliding parts and has
Development, Maxtek Compo- miniaturization, performance in the second half of this year, higher mechanical precision
nents. “When evaluating poten- and reliability requirements. Honeywell’s new Asia/Pacific with improved contacts, which
tial partners, technical expertise The announcement marks 300mm PVD target manufac- offers high consistency along
and a spirit of teamwork are the culmination of a joint effort turing is part of the company’s with excellent first pass yields.
at the top of the list of our by Tessera and NDSU to cre- overall commitment to the re- K&S plans to further expand
selection criteria. Our selection ate a regional microelectronics gion, where chips are increas- its Quatrix product portfolio to
of Dura Sales, Hi-Peak, Scho- center supporting the manu- ingly manufactured for export all of the most demanding re-
enduve and Somers-Stanton as facturing needs of government worldwide. Honeywell also quirements such as testing in
Maxtek representatives is the agencies while facilitating the manufactures 300mm PVD tar- QFN, BGA and LGA devices.
result of this evaluation process growth of technology compa- gets at its Spokane, Wash. facil- For more information on
and they are welcome additions nies. ity. Quatrix technology, visit www.
to the Maxtek team.” The work completed by For more information, please or email to Mark Sul-
Maxtek Components Cor- NSDU and Tessera was spon- visit livan, K&S Marketing Director,
poration is a proven micro- sored by the DMEA, an arm of at
electronics assembly and test the U.S. Department of Defense
K&S Quatrix
company providing a complete
range of custom design, proto-
(DoD). NDSU is currently in the
process of fabricating chip-scale Technology is STATS ChipPac
typing, manufacturing and test
services to equipment manufac-
packaged devices to be used in
the DoD-DMEA’s Chameleon Awarded APA Best Rapidly Expand-
turers. With 35 years of experi- program, which aims to develop
Product in SATS ing Capacity and
ence serving the measurement,
military and medical markets,
wireless, low-observable sur-
veillance sensors combined with Category Technology
Maxtek works as an extension
of our customers’ product teams
a high-sensitivity base station
receiver to provide a method of
Portfolio in China
to cost-effectively resolve the collecting more accurate intelli- SINGAPORE and UNITED
most demanding packaging and gence information for enhanced STATES – STATS ChipPAC
interconnect challenges. Head- security and safety, effective Ltd. has announced it is rapidly
quartered in Beaverton, Oregon, military engagement and rapid expanding both its manufactur-
Maxtek can be found on the dissemination of intelligence ing capacity in China and the
web at data to decision makers. depth of its technology portfo-
Tessera is headquartered in lio for advanced laminate pack-
ages and System-in-Package
Tessera Brings San Jose, CA. For more infor-
mation visit (SiP) solutions. The new facil-
Chip-Scale Pack- WILLOW GROVE, PA – Ku-
licke & Soffa Industries, Inc.
ity will almost double the cur-
rent manufacturing floor space,
aging Capabilities Honeywell recently received the 2005 further strengthening STATS
to North Dakota Expands Advanced Packaging Award
(APA) in the category of Semi-
ChipPAC’s position as the larg-
est full turnkey assembly and
State University Manufacturing conductor Assembly & Test test service provider in China.

SAN JOSE, CA – Tessera Tech- in Asia/Pacific Services for its new Quatrix
photolithographic package test
A new 300,000 square foot
facility will be built next to
nologies, Inc. has announced
that it has completed a suc-
Region technology. Advanced Pack-
aging Magazine and SEMI
STATS ChipPAC’s existing
430,000 square foot facility in
cessful chip-scale packaging MORRIS TOWNSHIP, NJ – (Semiconductor Equipment and the Qingpu District of Shang-
(CSP) technology transfer to Honeywell has announced that Materials International) sponsor hai. The building construction
North Dakota State University its Electronic Materials business the Advanced Packaging Award is scheduled to begin in the
(NDSU) and has partnered with will expand its Asia/Pacific man- (APA). A distinguished panel third quarter of this year and
NDSU in the development of a ufacturing capabilities to include of industry experts chooses the will be facilitized according to
fully functional microelectronics the production of 300mm PVD best technological advance- customer demand with a tar-
center at the university. As part (physical vapor deposition) ments in 19 categories, includ- geted completion of the factory
of a multi-year government pro- sputtering targets. Located in ing semiconductor assembly in mid 2006.
gram sponsored by the Defense Jincheon, Korea, Honeywell’s and test services. Beginning in the first quar-
Microelectronics Activity plant will provide customers in K&S’ Quatrix is a revolu- ter of 2005, STATS ChipPAC Q3 2005 / MEPTEC REPORT 17

MEPTEC Industry News

Shanghai has ramped a variety

of high volume laminate prod- SiliconPipe and
ucts to support multiple cus-
tomers in markets such as chip-
Nano Cluster
sets, PC computing, consumer, Agree to Develop
and broadband applications.
Research and development re-
Products Using
sources have been added to pro- Nanotechnology
vide customers with full product
development support for next SAN JOSE, CA – SiliconPipe,
generation emerging products Inc., of San Jose and Nano Clus-
as well as standard packaging ter Devices, Inc., have signed a
programs. Letter of Intent to jointly devel-
Further information is avail- op novel conducting structures
able at to be used in high-speed semi-
conductor packaging and metal-
lic-based interconnect designs.
Flextronics “We have identified key
Selects AIT for application areas where we can
use the methods developed by
From left to right: Kevin Grundy, SilcionPipe; Dr. Simon
Brown, Nano Cluster; Dr. Alan Rae, Nano Cluster.
Dual Chip QFN Nano Cluster Devices to cre-
ate circuit elements from self- and technical service headquar-
Package for Use assembled atomic clusters ters for China and the Asia- K&S Announces
in Consumer which will significantly improve
high-speed metallic circuit per-
Pacific region.
“This is an exciting and
Orders for 580
Electronics formance,” said Kevin Grundy, incredibly important day for Wire Bonders
CEO of SiliconPipe. our company, our customers,
SINGAPORE – Advanced In- “The combination of Sili- and the more than 1,000 Rohm from SPIL
terconnect Technologies (AIT) conPipe’s electronic design ex- and Haas employees working
has announced that Flextron- WILLOW GROVE, PA –
pertise and atomic cluster depo- in China and the surrounding
ics Semiconductor has chosen Kulicke & Soffa Industries, Inc.
sition techniques from Nano regions,” said Raj L. Gupta,
AIT’s QFN package for its has announced that Siliconware
Cluster Devices will enable the chairman and chief executive
devices used in next genera- Precision Industries Co., Ltd.
creation of unique structures officer of Rohm and Haas Com-
tion consumer electronics appli- (SPIL), a leading provider of
that are impossible to create pany. “For nearly 100 years,
cations. Utilizing AIT’s QFN comprehensive semiconduc-
economically by other tech- creative chemistry and the inno-
package, Flextronics will ben- tor assembly and test services,
niques”, comments Dr. Simon vative spirit of Rohm and Haas
efit from features of reduced has placed a series of purchase
Brown, Executive Director-Sci- researchers have delivered
footprint and improved perfor- orders for K&S wire bonders
ence and Technology for Nano amazing technologies and prod-
mance. for delivery to its Taichung,
Cluster Devices, Ltd. ucts serving hundreds of mar-
In addition, AIT will provide Taiwan facility. K&S provides
For additional information kets. With next year’s opening,
a turnkey service that includes the majority of SPIL’s wire
about Nano Cluster Devices this new research and devel-
assembly, final test and tape and bonder capacity and the Com-
Ltd., visit their website at www. opment center will mark our
reel services for Flextronics. pany now expects to receive ongoing commitment to serv-
AIT’s QFN packages have been additional Maxµm Ultra orders
For additional information ing a rapidly growing customer
selected due to their superior to meet SPIL’s ongoing pro-
about SiliconPipe, visit their base in the Asia-Pacific region,”
electrical and thermal perfor- duction demand. The orders
website at Gupta said.
mance. for 580 wire bonders include:
Nearly 200 guests attended 160 Maxµm Plus machines in
“AIT’s QFN package en-
ables us to leverage power, Rohm and Haas the event, including government
officials from Shanghai, Pudong
the final weeks of the quarter
ended June 30, 2005; current
footprint and performance that
renders improved reliability Celebrates New New Area and Zhangjiang Hi-
Tech Park. Other dignitaries
quarter-to-date orders for 113
while catering to the fast grow-
ing consumer electronics mar-
China R&D Center included officials from the Peo-
Maxµm Plus machines; and
307 of the newest Maxµm Ultra
ple’s Republic of China Minis- machines to meet the challenges
ket,” said Arnold Virrey, pack- PHILADELPHIA, PA, and try of Science and Technology
aging manager at Flextronics SHANGHAI, China – Rohm of increased package function-
and the U.S. Consulate General ality and small footprint devices
Semiconductor. “Our long term and Haas Company has cele- in Shanghai, managers from
relationship with AIT as well as brated the official ground break- being driven by low-cost, per-
Shanghai Zhangjiang (Group) sonal computers. Delivery dates
their ability to offer a complete ing for its new China Research Co., Ltd., representatives from
turnkey solution that includes and Development Center in are currently being scheduled.
customers and neighboring Kulicke & Soffa’s web site
assembly, test and tape and real Shanghai. Located on 33,000 companies, and Rohm and Haas
services made them a natural square meters (over eight acres) address is
employees and executives from For further information visit
choice.” in the Zhangjiang Hi-Tech Park, around the world.
For more information visit Pudong New Area, the world SPIL’s web site at www.spil.
More information about class facility will serve as the Rohm and Haas can be found at
company’s primary research

18 MEPTEC Report / Q3 2005

MEPTEC Industry News

Kyocera Receives As a result, the Company’s

flip chip capacity is currently IC Interconnect ous additional operations. This
created a significant challenge
Awards from expected to reach several mil-
lion units per month by the first
Adds New Back- for our customers in terms of
logistics, shipping costs, time
Freescale quarter of 2006. End Capabilities delays and subcontractor quali-
Semiconductor STATS ChipPAC’s flip chip
portfolio ranges from large sin- COLORADO SPRINGS, CO
fication and management,”
explains Tony Gaines, ICI’s
gle die packages with passive – IC Interconnect (ICI), a wafer regional sales manager. “Now
SAN DIEGO, CA – Kyocera bumping service company, an-
was presented with the “Suppli- components used for graphics all of these capabilities are in
and ASIC devices, to modules nounces its wafer test, laser the same location and managed
er of the Year Award” and the marking, die singulation, and
“Gold” Performance Excellence and complex three dimension- with the same ISO/TS quality
al (3D) packages that contain tape and reel capabilities avail- system as our bumping opera-
Award by Freescale Semicon- able as standard service offer-
ductor, Inc. at it’s annual Sup- logic, memory and radio fre- tion – saving time, cost and
quency (RF) devices and that ings. These back-end services worry for our customers.”
plier Day on August 2, 2005. round out IC Interconnect’s
The “Supplier of the Year integrate flip chip and wire IC Interconnect’s addition-
bonding interconnection within ability to offer a full turn-key al services can help custom-
Award” was given to Kyoc- solution as an integral part of
era for their outstanding sup- the same package. ers achieve these goals. A new
Further information is avail- the wafer bumping process. The automated optical inspection
port of the RF NI-360 base equipment set gives ICI installed
station packages from it’s U.S. able at (AOI) system enables ICI to
capacity to process approxi- inspect wafers for bump height,
manufacturing facility and high mately 2 million bumped die
performance PowerPC® proces-
sor programs in Kyocera’s HIT-
DuPont Fluoro- per week, making it an ideal
yield and circuit defects as an
independent service or as an
arrangement for small to moder-
CETM material manufactured products to Build ate volume processing of 100 to
integrated part of a customized
process flow. Combining this
at it’s Kokubu, Japan plant.
Of 90 suppliers, Kyocera NF3 Manufacturing 500 wafers/week.
“Traditionally IC Intercon-
data with an electronic wafer
was one of 13 that received the
“Gold Award.” Kyocera earned
Plant in China nect has limited itself to the
map allows for full wafer char-
bumping niche. That meant More information is avail-
this award by exceeding Fre- WILMINGTON, DE – DuPont after ICI bumped the wafers
escale’s performance ratings for Fluoroproducts has announced able at www.icinterconnect.
they were subsequently routed com.
all four quarters of the calendar plans to construct a new man- to other subcontractors for vari-
year. Kyocera understands and ufacturing facility to produce
continually shows the dedica- nitrogen trifluoride (NF3), a
tion and commitment it takes key chamber cleaning and etch
to achieve this degree of per- gas used in semiconductor chip
formance in the areas of cost, manufacturing and flat panel dis-
quality, delivery, service and plays. DuPont Fluoroproducts
technology. plans to install its patented puri-
These awards are shared by fication technology to deliver SILICON VALLEY
Kyocera Corporation’s Ceramic high-quality grades of DuPont™
Packaging and Communications Zyron® NF3 electronic gases
Device Divisions. to the global market. The new • FREE Wireless Internet Access
plant will have 450 tonnes per • 176 spacious guest rooms
STATS ChipPac year of initial capacity when
production starts in 2007.
• Full service restaurant
• In room coffee makers,
Increases Flip Chip The plant will be located
in Changshu, Jiangsu Province refrigerators, hairdryers, irons
Capacity in China, where DuPont Fluo- and ironing boards, am/fm
clock radios and digital safes
roproducts has established a
SINGAPORE and UNITED new multi-product complex, as • On demand movies
STATES – STATS ChipPAC part of a larger DuPont strat- • Voice mail
Ltd. has announced it is expand- egy to double its investment in • Heated outdoor pool and Jacuzzi
ing its flip chip assembly capac- this high-growth region from • Banquet/meeting space for 250
ity to support growing customer the existing US$600 million to • Japanese Tatami rooms
demand for flip chip packages. US$1.2 billion by 2010.
The increase in flip chip • Minutes from Light Rail, Santa Clara
Other products in the Du-
assembly capacity aligns with Pont offering of electronic gases Convention Center and Paramount's
STATS ChipPAC’s recently an- include Zyron® 116 (C2F6), Great America
nounced 300mm wafer bump- Zyron® 8020 (C4F8), Zyron® • 24 hour San Jose Airport transportation
ing service and reinforces the 23 (CHF3), and Zyron® 32 • Special group rates and packages
Company’s goal of providing (CH2F2).
a full turnkey service offering
for customers. STATS ChipPAC
will add assembly equipment
For more information on
DuPont ™ Zyron ® electronic The only full services Ramada in Silicon Valley
gases, please visit
and infrastructure specifically
tailored to high volume manu-
com/zyron/ or call 800-969- (408) 245-5330
facturing of flip chip packages. 1217 WILDWOOD AVENUE • SUNNYVALE• CA 94089 Q3 2005 / MEPTEC REPORT 19

MEPTEC Industry News

the Dynacraft facility, located in

Penang, Malaysia, by the end of Innovative RFID
Visit or
Smart Label for Technology for
more information.
the Converting
Kyocera Adds Industry
Subcontract Muehlbauer, a worldwide pro-
vider of technologically innova-
Plating Services tive solutions for the production
and assembly of RFID Smart
SAN DIEGO, CA – Kyocera Labels since 1995, announces
America, Inc. has announced the new Tag Module Assembly
that it will provide subcontract system (TMA), as a new in-line
plating services for a variety of equipment solution for the con-
New Web-based For more information about
EasySockets or to try this new microelectronic applications. verting industry. Many years of
BGA Test Socket software program, visit www. High quality plating is criti-
cal to the functionality of micro-
experience, in combination with
the close cooperation with cus- or contact Mark Sul-
Software livan at msullivan@kns,com. electronic parts, especially those tomers and partners, have led to
used in high reliability appli- exemplary concepts in machin-
Selection Tool cations. Electrolytic and elec- ery and technology. The many
from K&S Dyncraft Licenses troless gold, boron and phos- machines in use prove Muehl-


Samsung’s phorous nickel, palladium, and
copper are among the different
bauer’s exceptional quality and
reliability under the hardest of
licke & Soffa Industries, Inc. Patented Nickel- types of metals available for
plating. Kyocera’s subcontract
RFID technology is fre-
(K&S) has introduced the
EasySocketssm software tool to Palladium-Gold services include both a highly quently applied worldwide
meet today’s increasing need
for faster pricing and delivery
Plating Technology flexible plating line for special-
ized processes, as well as an
through the use of Smart Labels
in retail, supply chain and logis-
for many types of BGA test PENANG, MALAYSIA – Dyn- automated line for high-volume tics management. Renowned
sockets. This new software pro- acraft Industries, one of the larg- applications. market research institutes have
gram streamlines the quotation est manufacturers of leadframes With more than 30 years forecasted double-digit growth
process by enabling customers for the semiconductor industry, of experience handling complex rates for this technology in the
to enter their application criteria announced that they recently plating operations, Kyocera coming years. The market is
and submit a design drawing signed a patent license and tech- America, Inc. offers technical ready for the extensive growth
through the K&S public web- nology transfer agreement with support, quick turnaround and of this innovative RFID Smart
site, or at Samsung Techwin for the Micro personalized service for all ap- Label technology.
ockets . PPF (Pre-Plated Frame) tech- plications and requirements. The best Smart Label pro-
Oded Lendner, K&S senior nology. The technology gives Kyocera’s expertise in plating duction technology has to be
vice president, Package Test Dynacraft the ability to provide also includes full lab and func- specified, starting with the defi-
Business Unit, states, “Many of customers with Nickel-Palladi- tional test capabilities to meet nition of an application. Mue-
our customers want to reduce um-Gold alloy (NiPdAu-alloy) both military and commercial hlbauer is in the position to
their time-to-market. With pre-plated leadframes where specifications. provide all necessary systems
EasySockets, they can receive the Pd plating thickness is only
a detailed footprint diagram 0.1 micro-inch minimum rath-
immediately, and a quotation er than the more conventional
with accurate delivery dates 0.8 micro-inches minimum. It
within 24 hours.” He further also provides a substantially
explains, “K&S views Easy- improved process capability
Sockets as another value-added and consistency that produces
benefit for our worldwide pack- a superior level of quality and
age test customers.” product reliability.
The EasySockets products The agreement will allow
will be available with expedited Dynacraft the use of related
lead times and at a discounted patents, application and techni-
price. They are manufactured cal know-how, and associated
to provide the same high-per- plating equipment to manufac-
formance and quality that cus- ture leadframe products utiliz-
tomers expect from other K&S ing the Samsung Micro PPF
products. (µ-PPF™) technology. Techni-
Kulicke & Soffa launched cal teams from both compa-
EasySockets at SEMICON nies will transfer and install the
West 2005. technology and capability into

20 MEPTEC Report / Q3 2005

for HF and UHF Smart Label In that scenario, the market
production and the correspond- would ramp in 2007, continuing
ing test. into 1H08. With the upturn occur-
Information about Muehl- ring approximately 6 months
bauer is available on the Internet sooner, the downturn – which
at is currently forecast for 2009

June IPI Highest on

– would also occur 6 months
earlier in 2H08.
One caveat is that the three
Record – Robust
month rolling average for
semiconductor sales is down a
2006 in Sight slight 0.5%, from $18.1 billion
to $18.0 billion, triggering the

PHOENIX, AZ – Data going possibility that sales could flat-
back to 1984 shows Semico’s ten out for the remainder of the
Inflection Point Indicator (IPI) year.
registered a historical 16.5 in Semico will continue to
June, the highest IPI on record. closely monitor the IPI for in-
August’s IPI represents an im- dications the next inflection ���������������������
provement of 6.7% from the
May IPI. It also marked the
point has hastened. Along with
their quarterly forecast, the next �������������������������
second consecutive month the IPI update was scheduled to be �� �������
IPI increased, up from 14.9 in presented at Semico’s Semicon-
April and 15.5 in May. ductor Outlook Annual Forecast �� ������������������
Since Semico’s IPI is de- conference on September 15th.
signed to forecast the market 8 Semico Research developed �� �����������������
to 9 months in advance, the cur- the Inflection Point Indicator to
rent IPI points to the February- assist in forecasting semicon- �� �������������������������
March 2006 timeframe. With ductor revenues approximately
this nearly unprecedented jump two quarters in advance. IPI �� ��������������������
in the IPI pointing to the 1Q06, it –combined with their bill-of- �� ������������������ �����������������������
raises our optimism immensely materials, end-market analysis
– if such strength in the IPI con- and primary research – has help-
tinues for another month or two, ed Semico Research accurately ����������������
it will make a persuasive case forecast the industry ahead of all �� ��������������������
for a much more robust 2006. the other prognosticators.
Current expectations are for Semico is a marketing and
a moderate upswing in 2006. If consulting research company �� ��������������������
the trend continues, an upward located in Phoenix. Founded in
revision to the 2006 forecast 1994 by a group of semiconduc- �� �����������������������������
would be warranted, most likely tor industry experts, they have ������������
with growth reaching into the improved the validity of semi-
upper teens. In turn, a strong conductor product forecasts via �� ���������������������������
2006 start would accelerate new technology roadmaps in end-use ��������������������
plant and equipment expan- markets. For more information
sion by 6 months, from 2007 to
2H06. �� ������������
�� �����������������������
�� ��������������������
�� �������������������
�� ����������������������������
�� ����������������������
��� �����������������������
��� �����������������������


����������������������� Q3 2005 / MEPTEC REPORT 37
MEPTEC Industry News

New Kulicke & Soffa

Capillary Increases
Production Yields In
Demanding Applications
WILLOW GROVE, PA – Kulicke &
Soffa Industries, Inc. has developed a new
capillary called Arcus™ to increase yields
and productivity in demanding packaging
applications. Specifically, this new capil-
lary provides more accurate and reliable
looping in stacked die, quad-tier and other
complex, tight tolerance devices. Com- data from customers shows that this capil- lary is being shipped to contractors and
pared to the looping performance of other lary offers faster looping formations and IDMs around the world.
conventional capillaries, the new Arcus a very stable process, with less scrap and For more information on the Arcus
significantly decreases defects in the wire overall higher UPH. capillary visit or
bonding process, such as wire kinks, wire Now in full production at two K&S contact Mark Sullivan at msullivan@kns.
sag, wire sweep and wire leaning. Initial manufacturing facilities, the Arcus capil com. ◆

North American Semiconductor Equipment Industry

Posts August 2005 Book-To-Bill Ratio of 1.05
SAN JOSE, CA – North American- The SEMI book-to-bill is a ratio of Shipments and bookings figures are in
based manufacturers of semiconductor three-month moving average bookings to millions of U.S. dollars. ◆
equipment posted $1.12 billion in orders three-month moving average shipments.
in August 2005 (three-month average
basis) and a book-to-bill ratio of 1.05
according to the August 2005 Book-to- 12 Months Ending August 2005
Bill Report published by SEMI. A book-
to-bill of 1.05 means that $105 worth of
orders were received for every $100 of
product billed for the month. Average Shipments
The three-month average of world- in Millions of Dollars
wide bookings in August 2005 was
$1.12 billion. The bookings figure is
about 11% above the revised July 2005
level of $1.01 billion and 26% below the
$1.51 billion in orders posted in August 1000
The three-month average of world-
wide billings in August 2005 was $1.07
billion. The billings figure is one percent Average Bookings
below the revised July 2005 level of in Millions of Dollars 500
$1.08 billion and 29% below the August
2004 billings level of $1.50 billion.
“The book-to-bill ratio is above par- Book-to-Bill
ity for the first time in a year driven in
large part by orders for test and assem- Ratio
Ratio 0 Bar s
bly equipment,” said Stanley T. Myers, 5 per
president and CEO of SEMI. “While the .94 .96 .99 .94 1.05
wafer processing equipment segment has .84 .90 .93
.78 .77 .78 .81
yet to see the same growth levels as the
final manufacturing segment, our indus-
try views the overall trend as a positive Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug05
Data compiled for SEMI by the independent financial services firm of David Powell, Inc.

22 MEPTEC Report / Q3 2005


All Photos courtesy of Jody Mahaffey. Q3 2005 / MEPTEC REPORT 23

MEPTEC Technitorial

How To Meet the Demand

for Smaller Packages without
Sacrificing Performance
Sanjeet Uppal, Sales Manager

or over five decades the semicon- backs caused by leads. Package sizes are cur-
ductor industry has relied on leaded rently available up to 19x19mm with package
packages as the primary solution height as thin as .4mm.
for devices ranging in the 2 to 208- Another consideration is the emerg-
leadcount-market segments. Gen- ing market demand for lead-free packages.
eral industry familiarity with the package and While a growing number of packages offer
widespread acceptance among end customers lead-free solutions, the TAPP is inherently
kept products such as clocks, buffers, gate lead-free. All options are PB free and Green
arrays, and drivers for hand held applica- to meet the emerging demand for environmen-
tions from migrating to the newer packaging tally sensitive products.
technologies. In the last two years we have In designing a new IC, certain early
seen a slow transition start to occur. Changes considerations will allow for a TAPP like
in end market size constraints, new package Figure 1. package to be used. Grouping, on the die,
technologies, and perhaps most importantly of powers, grounds, and signals that can be
lower cost solutions are driving a migration to the TAPP technology the design was converted bundled at the package greatly simplifies the
leadless packages. to a 6x6mm package. Additional benefits are design of a single layer package and allows
QFP packages and its variations, the reduction of overall package height by 33% for a smaller overall package size. Die size to
MQFP, TQFP, etc. have been a significant and greater than 20% reduction of wire length. package size ratio considerations which meet
player in the leaded package market since The leadless package reduced the overall size, design guidelines ensure the manufacturability
being introduced in the sixties. In today’s met the pad requirements while exceeding of the package. Certain SATS providers have
market where space is a premium and high the electrical and thermal performance of the package design teams in local offices, which
frequency is desired, the QFP’s relatively large QFP. By reducing the body size to a fraction will work with customers to find the optimal
body size and leads present significant draw- of the original QFP size, the new package is package solution.
backs. In addition, the leads add complex- lower in cost and reduces overall product cost By no stretch of the imagination is it
ity to the manufacturing and test process via by allowing for the use of a smaller PCB. For anticipated that leaded packages disappearing
forming steps, inspection steps and handling even larger QFPs the size reduction is much all together as not all products are good can-
requirements. This drives to the requirement more dramatic. didates for conversion. In some cases leaded
to move to a leadless package. Enabling technologies in the TAPP are packages offer a better overall solution. The
Traditional leadless packages such as fpB- multiple rows of pads, which can be placed at focus of any packaging program should be
GAs and QFNs have been unable to gain virtually any pitch down to 0.4mm. The inno- to provide the most effective package for the
widespread acceptance as replacements for vative manufacturing technology allows for a application. However, as the market continues
leaded packages due to cost, pin count or segmented “ground” ring that is electrically to drive for increased performance in smaller
performance drawbacks. In 2003, a new isolated which can be used for powers and spaces, leadless packages such as the TAPP
leadless package entered the market, the Thin grounds to reduce the number of peripheral will be the replacement for traditional leaded
Array Plastic Package. Currently offered by pads. Direct paths for signals and heat offer packages that can no longer meet the market
more than one semiconductor company, the excellent performance without the RLC draw requirements. ◆
TAPP™offers a viable solution. The TAPP is
a high-density package with superior electri- Figure 2.
cal and thermal performance as compared to a
QFP. As an illustration of the superior thermal
performance, figure 1 shows a thermal per-
formance comparison between a 10x10 TAPP
and a 10x10 QFP. The TAPP’s performance is
far greater than the QFP. So when converting
from larger body QFPs to smaller TAPP the
inherent thermal performance characteristics
of the TAPP allow for a smaller package to
provide adequate if not better thermal dis-
Take for example the packages shown in 10x10 mm 64 LQFP (FP=2.0) 9x9 mm 64 QFN 6x6 mm 76 TAPP
Wire length = 91 mils Wire length = 150 mils Wire length = 71 mils
figure 2. The product was originally packaged Over-all thickness = 1.2 mm Over-all thickness = 1.0 mm Over-all thickness = 0.8 mm
in standard 10x10mm 64 lead QFP. By using PCB Area = 1.0 Area = 0.56 Area = 0.25

24 MEPTEC Report / Q3 2005

The Best QFN Just Got Better
ASAT’s Next Generation QFN: TAPP.
More I/Os, 3 Pad Rows, Smaller Form Factor.
If smaller is better, then this is the best: Announcing the next
step in QFN revolution; ASAT’s TAPP™ (Thin Array Plastic
Package). TAPP’s smaller size and thinner profile takes up
less circuit board space, making it ideal for high-performance
applications in today’s compact devices. And more than
just small, it offers enhanced thermal performance and
superior electrical characteristics along with natural strip test
capabilities. Plus, with its JEDEC approval, lead-free TAPP
meets today’s demanding industry standards.*

If anybody could make it better, it’s no surprise that it’s ASAT.

After all, we’re the company that pioneered the QFN in the
first place.

* TAPP packaging specifications have Microelectronics Outline MO-247B and Design Standard JEP95 Sec. 4.19
approval from the Joint Electron Device Engineering Council (JEDEC).

© 2005 ASAT Inc. The ASAT logo is a registered trademark of ASAT Ltd.
MEPTEC Member Company Profile

DuPont Semiconductor
Packaging and Circuit Materials – Peter Irvine heads up
DuPont’s efforts in

Connected by Science the IC Packaging and

Interconnects arena.

eadquartered at DuPont Electron-
ic Technologies in Research Tri-
angle Park, NC is a new kind of
team with intent to become the
leader in how integrated circuits
are connected to the external world. Drawing
on the company’s broad science capabilities
and long established positions in both semi-
conductor fabrication and circuit materials,
DuPont Semiconductor Packaging and Cir-
cuit Materials (DSPCM) is taking a unique
approach, and developing a portfolio of new
processing and permanent materials for pro-
ducing high reliability chip scale, flip chip,
and wafer level packages and MEMS.

A Fresh Approach
A few years ago, DuPont Electronic Tech-
nologies embarked on a strategy to extend be-
yond its leading position in circuit materials,
into semiconductor fabrication, semiconduc- Figure 1 – DuPont Semiconductor Packaging and Circuit Materials brings
tor packaging and large format display materi- material science into emerging packaging applications through its experi-
ence with both raw and engineered materials sold for rigid and flexible
als. These new areas were chosen because of
organic, ceramic and wafer based fabrication technologies.
their attractive growth rates and a belief that
increasingly more demanding performance
would play to DuPont’s broad strength in domain works to connect these businesses as to area array based packages. Array based
materials science. “one DuPont”, working closely together to packages are complex, varying from thin,
A critical element to executing this strat- create better awareness, and improve solutions small chip-scale packages used in mobile
egy was improving how DuPont leveraged to problems and challenges facing packaging devices to larger, high density, high power
its capabilities externally and internally. Peter and OEM customers. “That requires crossing flip chip packages used in performance com-
Irvine, a twenty-year veteran of the electronics traditional technology and product line barri- puting. Increasing I/O count requires high
industry, was chosen to head up efforts in the ers”, says Irvine. density interconnects that cannot be provided
IC Packaging and Interconnects arena. Key areas of interest for the domain are by perimeter arrays, such as dual in-line pack-
“My role quite simply is to build a bigger printed circuit boards, rigid-flex circuits, thick ages. The arrangement of I/Os in area arrays
business for DuPont in the space from the film hybrids, semiconductor packages, mod- allows the fan-out of more I/Os on several
back end of the wafer to the box,” said Irvine, ules and MEMS. The domain approach brings package planes, interconnected by microvias
“and to do this we must do a better job of together customer and market knowledge, sup- (see Figure 2).
marrying-up the right opportunities with our ports joint developments where appropriate, Material requirements for such packages
science capabilities.” and leverages resources and facilities across are very demanding to assure electrical and
Today, the nature of the group has changed the company, where beneficial. Because of reliability performance. They include low
and the focus has evolved. Irvine directs this “one DuPont” approach, there is a greater coefficient of thermal expansion, low moisture
DuPont Semiconductor Packaging and Cir- understanding of trends in packaging and the absorption, low Dk and Df, planarity, interfa-
cuit Materials as a “domain”, or broad based material sets needed to address them. cial integrity and compatibility with high den-
global team comprised of representatives from sity circuitization. To satisfy these sometimes-
about 12 different businesses across DuPont, Trends in Semiconductor conflicting requirements, highly engineered
and with functions ranging from corporate Packaging composite materials are often used.
R&D to key regional decision makers. Under DuPont has been providing enabling mate-
this approach, the individual business units rial solutions to electronic packaging through- Product Offerings
that are part of the domain work to develop, out the evolution of packaging technology. For wafer level packaging and MEMS
produce and market products for sale to their Semiconductor packaging has evolved from applications, DuPont offers a suite of com-
direct customer base as they always have. The through-hole technology to surface mount plementary materials, including advanced

26 MEPTEC Report / Q3 2005

gap filling applications such as System in
Package. Low cure, (225°C), low dielectric
constant (2.9), low moisture uptake (<.5%)
HD-8800 aqueous positive materials enable
low thermal budget memory technologies.

Cleaner and Remover Solutions

Cleaner and remover solutions from
DuPont EKC Technology leverage hydrox-
ylamine technology proven in integrated cir-
cuit interconnect cleaning applications. New
chemistries for removing resists used in C-4
and other fine pitch wafer bumping processes
Figure 2 – Effect of IC Evolution on Packaging Interconnects and Architectures. (both liquid and dry film) and for rework of
liquid polyimides (both cured and uncured)
are currently under development. EKC remov-
packaging lithography materials, high purity Permanent dry photopolymer film dielec- ers assure clean removal with no residues,
polyimide coatings, and cleaner and remover trics used in wafer bonding, redistribution, work faster at lower temperatures, and have
solutions. For chip scale packages, thin, all- and wafer protection applications are another longer bath life.
polyimide laminates are available. For the flip key product offering of this group. The newest
chip segment, DuPont is developing embed- DuPont™ WPR Series developmental film has Adhesiveless Laminates
ded passive technology for power decoupling exceptional resolution, adhesion and cured DuPont™ Microlux® all-polyimide lami-
and improved microvia build-up films. film properties. nates can be used for folded and stacked chip
For specialty applications like Micro scale packages. These will be commercially
Advanced Packaging Systems Technology (MST) and MEMS, available and in roll format by mid 2006.
Lithography DuPont™ MX dry film photoresists offer The benefits of DuPont™ Microlux® materia
The Advanced Packaging Lithography excellent resolution and resistance to a vari- ls include excellent thermal stability and high
group recently expanded its offering, introduc- ety of processing chemistries. MicroChem peel strength for fine pitch patterns.
ing a new family of polymer films. They now Corporation (MCC) was recently appointed
carry permanent and non-permanent Micro- as an exclusive global distributor for the full DuPont™ Interra™ Embedded
lithographic Polymer Films (MPF) for semi- line of DuPont MPF materials into MEMS Passive Materials
conductor packaging applications, including applications. MCC brings extensive material DuPont is also developing a broad portfolio
flip chip, backside wafer coating, wafer bump- and process knowledge to serve the MEMS of embedded capacitor and resistor materials
ing, other wafer level packaging and MEMS market and is well positioned in the industry for replacing discrete surface mount passives
applications. with products such as SU-8 resists. in circuit boards, modules and semiconductor
According to Mats J. Ehlin, sales and mar- packages.
keting manager, DuPont Advanced Packag- High Purity Liquid Polyimide DuPont™ Interra™ HK laminates are
ing Lithography, “DuPont Microlithographic Coatings based on thin polyimide, and are used as
Polymer Films provide the most advanced HD MicroSystems, a 50/50 joint venture power ground planes in printed circuit boards
negative working photoresist formulations for between DuPont and Hitachi Chemical, is the for high-end computers. Benefits of these
excellent productivity, smaller environmental largest supplier of polyimide based coatings materials versus epoxies include better han-
footprint, simple processing, and high yields. specifically engineered for microelectronic, dling, higher breakdown voltages and higher
These products allow solvent free, aqueous MEMS, optoelectronic and microfluidic appli- frequency performance. Interra™ ceramic
based developer and remover processing, cation areas. Their materials have proven pastes are currently being introduced for RF
without jeopardizing cleanliness and resolu- reliability as stress buffers because of superior module applications, where there is high value
tion. The combination of benefits is unique for mechanical and thermal properties, compared for size reduction through component integra-
most packagers.” with other dielectrics. The product line is tion. These are screen patterned as discretes
A broad family of thick (50-100µm) WB broad, consisting of photosensitive polyimides, onto copper foil, which is then fired and incor-
dry film photoresists enables fine pitch wafer standard polyimides, thermoplastic polyimide porated into standard printed circuit board
bumping via either stencil or electroplating adhesives and a full line of complementary processing. Because these capacitors are in
processes, with distinct advantages over spin ancillary products. A number of products are effect pure ceramics, capacitance densities
on liquids, like uniform thickness (hence full targeted at advanced packaging applications. of 150 nano-farads per square centimeter
wafer area utilization), higher productivity HD-4000 excels in 300mm, high temperature, are much higher than competitive products.
(from single pass application), and minimal C4, and redistribution applications. Thick film Further, large format panel processing reduces
waste. (65µm) HD-7000 is used for compliant and manufacturing costs.

With a unified approach to the market, a
growing product offering, and a clear view to
the technology trends driving needs for new
materials, the outlook is bright for DuPont
Semiconductor Packaging and Circuit Materi-
als, and for its customers. “We have a strong,
sustainable future in this industry”, said Irvine,
Figure 3 – DuPont Microlux all-polyimide laminates enable folded multi-chip “it’s about bringing DuPont science to bear on
packages. the challenges facing the industry.” ◆ Q3 2005 / MEPTEC REPORT 27

MEPTEC Die Processing Technology

A Die Processors View of

the Evolution of Bare Die
Jim Rates, Director, Advanced Interconnect Solutions
Chip Supply, Inc.

n the 25 plus years Chip Supply, (Known Good Die) had begun. This VP for major memory manufacturer
Inc. has been involved in the subject has been discussed, debated publicly stated “The good news is that
bare die supply business, techni- and reported for many, many years our mature products don’t need burn-
cal evolution has been notice- including several papers and articles in, the bad news is that we don’t have
able in several areas. Many years written by this author. However it is any mature products”
ago when multi-die assemblies were still a topic of interest as demonstrated As a value added die processor,
referred to as “hybrids”, semiconduc- by the number of papers on KGD that we receive wafers from over 30 semi-
tor die were fabricated using Critical were presented at the “KGD Packag- conductor manufacturers. These prod-
Dimensions (CDs) of 0.5 microns to ing and Test Workshop” in Napa, CA ucts include digital, linear and mixed
over 1.0 micron. A microprocessor in mid September this year. signal technologies. All are probed
hybrid would consist of several die For those new to bare die usage, differently. It is impossible to predict
including an ALU (Arithmetic Logic this article will briefly discuss the quality and reliability of die sawn
Unit), an I/O controller, a memory reasons behind the demand for KGD. directly from these wafers. As men-
controller, and SRAM. This is now a All semiconductor companies manu- tioned earlier, LATs provide some
single die fabbed using sub 0.5 micron facture their product in wafer form. degree of assurance of quality and
CDs. Wafer diameters include 4”, 6”, 8” reliability, but do not assure KGD.
In the “old” days, semiconduc- and 12”. Nearly all of these manufac-
tors were not very fast and because turers electrically probe their product Known Good Die
of the large lithography CDs, were at wafer level. Because of mechani- Needless to say, this evolution of
reasonably reliable. A simple LAT cal limitations imposed by the use the semiconductor challenges a die
(Lot Acceptance Test) accompanied of probe cards, it is difficult to com- supplier like Chip Supply to meet
by a 100 percent visual inspection pletely electrical test a die at full the also evolving requirements of our
would give the die user some prob- speed. In many cases, mostly memory customers. Form factor of the sup-
ability that some percentage of the products, it is impossible to screen out plied product (after all bare die is just
die lot would meet their quality and die that are infant mortality candidates another package style), and assured
reliability requirements. This gener- at probe. Instead, wafers are probed quality and reliability are all chal-
ally meant that between one and ten for “candidates” for packaging. If a lenges we had to meet.
die in a hundred die would fail at first die passes certain minimal parametric Customers began requiring pack-
hybrid test and no more than the same tests at probe it is presented to packag- aged part quality and reliability (note
percentage would fail in the first year ing. In its final package full paramet- that this is Chip Supply’s definition of
of operation. ric test and burn-in is simpler. KGD) in the complex and expensive
As die became more complex and There are die products on the mar- bare die they were designing into their
CDs dipped to and below 0.5 microns ket today that have become “mature”. (now) MCMs.
several things became evident. The die Generally this means that the product In 1997, Chip Supply began sup-
were more expensive and acceptable has remained active long enough for plying KGD for military and space
quality and reliability could no longer defects found at test to have been applications. Bare die are processed
be assured with a simple wafer probe traced to fabrication issues and cor- using Chip Supply’s patented SofT-
and LAT. In the late 80’s a young rected. These fixes allow the die to be AB™ KGD process. This process
hybrid engineer at Rockwell Collins reasonably fully tested at probe and while not inexpensive provides a
challenged the semiconductor indus- have reduced the Failures In Time method for performing full electrical
try to provide him with “Known Good (FIT) rate to an acceptable lever so as test and burn-in. It also provides the
Integrated Circuits”. The gauntlet was to preclude burn-in. These older, leg- user with a pristine gold plated bond
picked up by the Government spon- acy products usually are in the micro- pad for high reliability wire bonding
sored MCC Corporation. An Engineer processor or logic genre. Memory die and provides a degree of hermeticity
at MCC decided that KGD sounded don’t stay active long enough to make to the die. The search for lower cost
better than KGIC, and the age of KGD this trip. Several years ago a Sales KGD processes continued at Chip

28 MEPTEC Report / Q3 2005

Figure 1 – CS430F149
in a 64 pin, 6x6 mil

Supply and in the ensuing years we Comparisons

developed internal capabilities to pro- The drawings in Figure 2 illustrate
duce CSP (Chip Scale Packages) and size comparisons between using a
TCP (Tape Carrier Packages) and are bare die on the user’s main substrate COB-Wire bond-glob top.
now beginning to produce stacked die and various CSP methods of accom-
products. plishing the same thing. This com-
parison illustrates that all of the CSP
CSP processes occupy less main board real
CSP has been and is a most impor- estate than COB. CSP also enables
tant contributor to product miniatur- electrical screening and provides ease
ization. A bare die can be assembled of assembly and bare die protection. Wire bond CSP
onto a substrate, electrically connect-
ed via wire bond or flip chip, transfer SIP
molded and have balls attached to the System-in-a-package is the lat-
underside for less cost than any of the est evolutionary step. Looking back
available KGD processes including a Hybrid containing several die of
SofTAB™. The resultant part takes different functions became a micro-
up no more room on a substrate than processor, or maybe a function in a Flip Chip CSP
a bare die attached, wire bonded and package. Today a microprocessor is a
glob topped. Yet it offers electrical single die and several die encompass-
screenability (test and burn-in), ease ing unique functions is referred to as a
of assembly (standard surface pro- SiP.
cess) and physical protection of the SiPs come in two basic shapes.
die. WLCSP
Vertically stacked die and horizontally
placed die. Chip Supply is producing
WLCSP a flat SIP using nine DDR DRAM die. Figure 2 – Illustration of CSP size
With some constraints, it is pos- The die are connected so as to become comparisons.
sible to manufacture a CSP part at a 64 megabyte deep by 72 bits wide
wafer level. This can be accomplished memory system. This provides a ball
if all of the bond pads on the die, when grid array that is 25mm x 32mm and cluster the die used to produce a cer-
arranged into an array with a mini- less than 3 mm high. It provides a tain function in the MCM into a single
mum pitch of 0.5mm, will fit into the drop in memory system for micropro- CSP saving more board space and in
periphery of the die. In this process, cessors such as Freescale’s power PC some cases increasing performance.
the existing bond pads are redistrib- products that have a 64 bit data bus Today, in most Hybrid, MCM
uted into the array and solder balls are with 8 bits of parity. or SiP applications, Chip On Board
attached to the new bond pads all at Several microprocessor manufac- (COB) can be replaced by single and
wafer level. The wafer is then sawn turers are building vertical stacked multiple die CSPs. The advantages are
into individual CSPs. Of course the SiP’s containing their microprocessor little or no rework of the final product,
existing bond pads on a die can be die and other necessary die functions lower NRE and unit costs and a more
solder bumped at wafer level (assum- that are required by their customers robust final product. ◆
ing their pitch meets solder bump- that offer highly functional products
ing minimum spacing). However this that occupy very small spaces such
would be considered a “flip chip” as PDA’s, GPS systems and advanced
product and is not suitable for simple cell phones.
quality and reliability screening. Chip Supply also offers few die
CSPs. This allows the designer to Q3 2005 / MEPTEC REPORT 29

MEPTEC Marketing

Markets Have Changed

But Marketing Has Not
Charles DiLisio and Doug Molitor
D-Side Advisors

anaveral Communications Unfortunately for the sales team, History has recorded many Mavens
was in the pager business, in Mavens exist outside the vertical stove- who went against the status quo and made
the 1980’s. Canaveral owned pipe of product lines. In most cases your innovations for themselves and their firm.
FCC licenses, space on trans- sales force is told to avoid contact with For example, if Lee Iacocca (a Maven)
mission towers, a sales team Mavens, as they are not a traditional listened to the customer, he likely would
which leased out pagers at $750 a pop buyer such as purchasing or engineer- not have created the Ford Mustang or the
and a service for handling messages. As ing. And unlike the traditional customers Chrysler Minivan. Few customers would
the network became more sophisticated from engineering or purchasing, Mavens have envisioned a sporty new product
and the hardware cheaper, Canaveral got don’t want a process flow chart or spec line build on a Ford Fairlane chassis or a
out of the business, unable to support its sheets – he wants solutions and he wants “shoe box” on wheels with a large door
sales team. In the 90’s Egghead had over to know how your solution will solve his on the side? And what salesmen were
200 stores with software inventoried on new product issues and time to market working with Iacocca to create and sell
their shelves. Then manufacturers began (TTM) objectives. carburetors and shocks for the muscle car
to offer software downloads. Like pager And why is the Maven so insistent and sliding door hinges and locks for the
salesmen, Egghead stores are gone. The on solutions versus components? Solu- Minivan?
point is that markets change forcing sales tions give his company a time to market A common quality among Mavens
and marketing practices to change as the advantage in features and functions which is that they didn’t “grow-up” with the
customer becomes more sophisticated. results in greater product market and prof- company and thus don’t care about sacred
Survival in today’s IC industry requires its. cows. But he probably did work at a
that you to redefine your business or start-up. The Maven reports to the CEO
become extinct. What Are Mavens and Why Are or chief technology officer. The Maven is
In the SATS world marketing and They Important? not a price/performance guy; rather he’s a
sales has been reluctant to change. Rather The Maven is a change agent with the best of breed integrator of technologies.
SATS has waited for change to be forced authority to make change happen. The To meet the voracious needs of emerg-
on them. For example, the emergence of Maven is the person in the client firm ing consumer markets the Maven spends
the global supply chain has had a pro- who is interested in what’s happening most of his time thinking of approaches
found effect on SATS business, but other outside his company. He looks for new where he can assemble a product solution
than plugging into the supply chain, the ideas, emerging technologies and new from so many Lego-like functional build-
industry still relies on 30-year-old sales markets. He has the ability and authority ing blocks. These blocks can be home
and marketing practices. The result has to think across functional groups. In some grown or purchased from firms with the
been that while companies like Intel, Dell organizations he is an MBA-type, in other best solution. The Maven also looks for
and Samsung become more and more organizations he’s a rogue engineer. But ways to integrate existing services and
sophisticated about their design-build- in all cases the Maven is not the tradi- products with new ideas to create new
fulfillment process, SATS has not. Today, tional customer that the sales force calls services and products.
OEMs and especially the savvy ODMs upon. By not calling on the Maven you IC markets are listening to Mavens
want systems partners not component may miss the upside opportunities and because the driver has changed. Perfor-
providers. leave your firm vulnerable competitive mance like quality is becoming a given,
The big opportunity is to market to entry. a “must have” with no premium attached.
your customer Mavens. The Maven is a The Maven is a system thinker and Performance is yesterday’s pizza, cold,
system thinker, the guy who looks out seeks the Whole Product. He wants to soggy and doesn’t sell. In today’s IC
to the future and innovates new prod- deliver solutions to his customers and he market the value is more often in the
ucts. The Maven leads to the core of the expects you to do the same. Typically the software than in the hardware, while the
strategy: Find the systems guy who is Maven hates incrementalism. The Maven whole product includes a list of intan-
looking for new opportunities, and sell knows that incremental change and too gibles including things like ease of use,
your ability to solve his system needs. much “listening to the customer” leaves modularity, reliability, time to market,
Most importantly, the Maven is the guy an opening for competitors, but more etc.
who will increase your margin because he likely an opening for a new company
seeks the solution not a commodity. Much to steal the base. The Maven sees the Why Sales Don’t Happen –
like when buying a PC, the Maven wants greatest risk in missing big change or the Incrementalism vs. Innovation
everything he needs right out-of-the-box. emerging market. Sales organizations within companies

30 MEPTEC Report / Q3 2005

marketing to the Maven, the interac-
tion will change and may well include
whole product considerations such as
software, financials, process road map,
inventory management and other intan-
gibles. Remember, moving up also means
expanding your capabilities to deliver
a whole product, which means that you
really have to understand the customer’s
The concept of whole product comes
from the realization that there is today a
gap between the product and the customer
expectations. Most famously, Dell Com-
puter dictates to its supply chain what the
whole product must be. Learning from
this, customers in many types of busi-
nesses no longer accepts a ”component”;
rather the customer seeks a “whole prod-
uct” delivered with the services.
are focused on selling to the tradition- a value-added whole product. Interest- Delivering whole product means add-
al customer in purchasing or procure- ingly, many in your sales force may ing all the elements necessary to create a
ment. Sales is stuck is a small room off know the Maven, but can’t sell to him, compelling reason to buy. This is a para-
the lobby, not even welcomed into the because sales isn’t equipped to sell out- digm shift for a proven solution or whole
building. Sales finds itself in a vertical side the stovepipe or doesn’t have solu- product is the concept of Harvard’s Theo-
stovepipe where procurement is the only tions to sell. Conversely, Mavens don’t dore Levitt from his book The Marketing
opportunity. In these stove pipes exist- want spec sheets – they want solutions Imagination. What is new is following
ing products lead to incremental prod- and help in how your solution improves Dell’s lead and moving the concept down
uct improvements which lead to volume their product. the component sales pyramid.
sales. Unfortunately volumes are likely Whole product delivers the seller two
to lead to multiple vendors and com- New Paradigm for a Proven advantages:
moditization where price rules, delivering Solution
• Resistance to pricing pressure
relatively low margins. The sales team needs to rethink their
Although selling in the stovepipe is process. A simplistic approach is to work • Insight into the customer’s needs
a necessary function, it misses the high- at two levels. At level one, continue to which the competition does not have
margin opportunity by being included at meet current customer expectations by
the front end of innovative, high growth, working with existing contacts. At level Profitability Driver
product opportunities. The goal should be two, begin exploring new opportunities The equation becomes pretty clear:
to look to where the customer is going, with the Mavens. But above all, don’t sell on price or sell on whole-product.
to become a partner in reaching the goal neglect existing contacts within custom- Your firm can continue to focus on sell-
and become viewed as providing a value- ers. ing to purchasing or procurement where
added solution, not just a component In seeking out the Mavens, three key you compete on price and volume or your
provider. questions are: firm can seek out the Mavens within your
Another case for marketing to the customer’s organization. The difference is
Maven is to maintain account control. 1. Where are the decisions being seen in margin. Maven marketing brings
Because the Maven has the authority to made? higher margins because you are delivering
cause change, your account is at risk. The a unique solution that the customer values
Maven will likely go to a new vendor, 2. What are the emerging system level and can’t find from commodity providers.
rather than stick with the existing supplier needs? D-Side Advisors has years of experience
because the incumbent comes with bag- in identifying and interviewing Mavens
gage and a natural resistance to change. 3. How can we change our marketing to discover whole product requirements.
On the positive side, working with strategy to engage the Mavens? D-Side also is the premier company in
the Maven deepens your penetration with creating business models to determine
the customer and gives your firm greater When you can answer those three profitability, so that you know up-front
insight as to the future and where the cus- questions, then you can sell your ability how and where you will be making mar-
tomer is headed. The upshot is that you to deliver what the Maven will need, not gin. The choice is yours, you can get beat
are working to define key product ele- some offering procurement can price in a up by the buyer on price and delivery
ments with the customer, not just taking reverse auction on the internet. or you can partner with the customer to
orders after the product has been defined. The goal is to change who you sell delivery a value based, whole-product
A difference is in selling compo- to, because if the customer is purchasing, solution. The markets have changed, has
nents based on price and delivery or expectations are probably price and deliv- your marketing? If not, be prepared for
partnering with the Maven to deliver ery. But by moving up the sales pyramid, commoditization. ◆ Q3 2005 / MEPTEC REPORT 31

MEPTEC Thermal Management

Thermal Management
of LGA Packages
Kaveh Azar, Ph.D., President and CEO
Advanced Thermal Solutions, Inc. Figure 1 – A ceramic LGA package.

urrent trends in the electronics board. This plate further monopolizes prime available on the market. Figures 3 and 4
industry demand manufactur- real estate on the backside of the board show two such options.
ers increase speed and system which is often used for the placement of As shown in Figures 3 and 4, the heat
outputs to maximize both effi- discrete components. sink is held to the device via a plastic clip,
ciency and profit. To achieve In contrast with BGAs /flipchip pack- where this clip attaches to the device at the
these goals some manufacturers within the ages, widely utilized by the industry, LGA solder balls. The current configuration of the
industry are pushing to implement surface cooling solutions present a totally different most LGA packages does not make such
mounted packages instead of, or in con- challenge. Attractive solutions for heat sink a provision for attachment. Another thing
junction with, the standard Ball Grid Array attachment and BGA cooling are widely to consider is whether epoxies and double
(BGA) and other packages. One example of sided conductive adhesives may offer an
the new surface mounted technology is the attractive enough interface options, specifi-
Land Grid Array (LGA). cally when dealing with high power devices.
There are a number of reasons that Therefore, the mechanical attachment, as
such packages are receiving much attention depicted in Figure 2 or its extracts, remains
amongst them are: to be perhaps the most viable option for
• Increased number of pins – allowing for thermal management of LGA.
increase in the overall system output. The industry has developed a comfort
• Signal clarity and quality – the shorter level with the currently available cooling
distance between the pin and the connec- solutions for BGAs ; irrespective of the lack
tion point enhances signal clarity which is of reliability or poor performance of some
of paramount in any system, specifically, in (Courtesy of Advanced Thermal Solutions, Inc.) the available attachment methods. Over the
high frequency applications. years, the industry has shown major reluc-
Figure 1 shows a typical LGA package Figure 2 – LGA package with mount- tance to embrace mechanical attachments
ing hardware and norEASTER™ cool-
from Amkor corporation. and place holes on the PCB. The reliability
ing solution.
In conjunction with the LGAs attributes issues associated with the attachment and
we still need to be cognizant of power dis- the subsequent loss of real estate due to the
sipation and the subsequent cooling of the holes have been the major points of resis-
package, especially when one hears the tance. The cooling of current LGA pack-
words “frequency” or “higher-output”. The aging relies on this attachment approach.
LGAs unique packaging and their method Therefore, as LGA begin to get a foothold in
of attachment to the Printed Circuit Board tomorrows electronics, it is anticipated that
(PCB) creates challenges as to the cooling the cooling solution and its attachment of
as well as signal routing on the board. In the LGAs will rekindle issues of packaging
most applications where a cooling solution and manufacturing options at all levels of
is required, whether an air or liquid applica- system-packaging. If alternate approaches
tion, the need for through-board mechanical are not conceived, the packaging practices
fasteners is inevitable. Figure 2 shows a and associated reliability expectations may
schematic of such an attachment. Figure 3 – Tyco Corporation heat sink need to be reassessed. ◆
The need for through-board mechanical and clip attachment.
fasteners creates a major obstacle for both
device cooling and signal routing on the
board. The issue of holes on the PCB has
been an epic battle between mechanical
engineers, developing the cooling solution,
and circuit engineers. The lack of real estate
on the board and the need to route the signal
with a higher output device further compli-
cate the packaging issues and may lead to
larger and thicker PCBs to accommodate
this need. Furthermore, as shown in Figure
2, a stabilization mounting plate is required
on the opposite side of the board to hold
either the device or the heat sink on the Figure 4 – Advanced Thermal Solutions, Inc. (ATS) heat sink and clip attachment.

32 MEPTEC Report / Q3 2005

Clip N Cool ‘
The easy and reliable cooling solution


Ultimate Heat Sink Attachment System is

the new clip-on mounting method for fast, safe, and secure heat sink mounting

● No sink threading, cracked dies or detached components

● Extended cooling surface
● Easy heat sink removal and re-attachment

Innovation in Thermal ManagmentTM

Advanced Thermal Solutions, Inc.
© All Rights Reserved Q3 2005 / MEPTEC REPORT 37

MEPTEC Network


Problem Hidden in 2-D Problem Solved in 3-D

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Meetings at Hyatt San Jose.
Hestia Technologies, Inc. “The innovation Easier to Plan.
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plastic packages. This technology provides a • 1/2 mile from San Jose Airport
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more information about our services. 408-793-3979
34 MEPTEC Report / Q3 2005
MEPTEC Network

By Micro-Mechanics
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Please contact Jerry Kirby at, ■ Flip-chip, BGA, CSP assembly tified. Visit our website or contact Hal Shoemaker
408-749-9155, ext. 104. at (408) 969-9918 for more information. Q3 2005 / MEPTEC REPORT 35
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For Our Upcoming APEX 2006 Issue
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For Further Information Contact: Kim Barber at (408) 309-3900, or call the MEPTEC Administrative
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MEPTEC Editorial

The Profitability Challenge –

Or Darwinism in the
Semiconductor Industry
Joel J. Camarda
Camarda Associates

he business climate in our in the La Brea tar pits (Fremont?), or more participants, and the more suc-
industry has dramatically im- possibly just go into hibernation and cessful talk more softly.
proved, and slightly declined return years later (a la Apple and NSC, Our industry has been creating and
again, in the past two years. twice each). The good news is that there exporting jobs and wealth for decades,
Cautious optimism dominates. is a lot of cheap office space available in practically since its inception. In the
That is not so bad for a business that has Milpitas. That is more PR (public rela- past, it was mostly an issue of labor. We
long been sustained by near-sighted (not tions, not photo resist) for Fremont and in the United States have always man-
quite blind) optimism. All of our busi- Milpitas than you will ever see again. aged to continue creating jobs and start-
nesses have become more efficient. We So what is new? Nothing, except there ing new businesses based on our creativ-
accomplish more, with fewer resources, are many more participants. ity and development of new technology
lower COGS (cost of goods sold). Of One of the issues, in the semicon- and products. We have had significant
course, that has always been the modus ductor business, is that suppliers to competition from and then collaboration
operandi of the semiconductor industry, semiconductor companies are expected with Asia. Now we face another round
the essence of Moore’s law. So what’s to survive on half the profit margins of competition (and collaboration) with
new? Nothing, except there are many that their customers expect. I can quote Asia, notably India and China. We also
more participants. numerous industrial journal articles, but face competition on a financial front, ie.
Semiconductor industry Darwinism this modest publication does not have the availability of investment capital.
determines the next generation of busi- room for footnotes. That is the differ- Shall we maintain technology leader-
ness primates: microprocessor, memory, ence between “IP” (intellectual prop- ship? As Dr. Skip Fehr recently said,
RF transceiver, etc. Among the many erty) and service providers. So what is “Would you still allow your daughter
semiconductor firms and suppliers the difference? Well, most of the IDMs to marry a semiconductor packaging
(materials, equipment, manufacturing (integrated devices manufacturers) suc- engineer?” So what’s new?
services, logistics, software) we are see- ceeded on their device IP, abetted by I believe the venture capital com-
ing changes, and we are going to see high volume manufacturing efficien- munity in our business remains quite
more. The EMS (electronics manufac- cies, and sometimes manufacturing IP, strong, albeit the benchmarks for due
turing services) also participate in this be it wafer fab, assembly or test. Several diligence are more stringent. My inside
profitability challenge and evolution. still do, although this number is dimin- information is that there is still ample
They may, in fact, set the benchmarks ishing. Fabless semiconductor compa- capital seeking good investment oppor-
for global, high volume manufacturing/ nies survive, grow and prosper (or not), tunities. On the other hand, I know
operational efficiencies, albeit surviving entirely based upon their device IP, of a few good investment opportuni-
and succeeding on the slimmest margins since their manufacturing operations are ties still seeking investment. So what
in the supply chain. The idea has been shared with others, possibly their own has changed? Nothing, except there are
expressed that any, single, major EMS competitors. This formula for success more participants.
player could digest the entire SATS is one-dimensional, but has established The challenge, frustration, and joy
(semiconductor assembly and test ser- itself as a successful business model and of this business is the participation in
vices) industry in one bite and not have has vastly reduced the entry barriers for this high-tech, high-paced, 20th-21st
indigestion. “Godzilla meets Bambi”. new business start-ups. century business Darwinism. The evo-
None want to. They must know some- Knowing many colleagues in this lutionary cycle may occur in only a few
thing. business for many years, at IDMs years or decades, still quite short by
Some major semiconductor players (where I have spent most of my career), evolutionary standards. The battle for
(integrated circuit providers, material, fabless IC companies, material, service, market share and profit, the creation of
equipment, and services suppliers) are and equipment suppliers (all of which I new markets, drives the survival of the
losing their prominence. New lead- have participated in) our conversations business fittest. On the rewards side,
ers emerge and dominate some herds often dwell on the profitability chal- the bananas can be pretty good. So what
(except possibly microprocessors). lenge. It is a tough business. So what has changed? Nothing, except there are
Some will be eaten by others, disappear has changed? Nothing, except there are more… ◆

38 MEPTEC Report / Q3 2005

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