K-00382857 Prajapati Darshankumar A.

(1). Develop a model for a floating-point arithmetic unit with data inputs x and y, data output z and
function code inputs f1 and f0 of type bit. Function codes f1 = ‘0’ and f0 = ‘0’ produce addition; f1 = ‘0’
and f0 = ‘1’ produce subtraction of y from x; f1 = ‘1’ and f0 = ‘0’ produce multiplication; and f1 = ‘1’
and f0 = ‘1’ produce division of x by y.
Write a test bench for the multiplexer model, and test it using a VHDL simulator (Modelsim).

Code:

entity floatingpointarithunit_v2 is
port(x,y:in real;
z:out real;
f1,f0:in bit);
end entity floatingpointarithunit_v2;
architecture behav of floatingpointarithunit_v2 is
begin
fpaupro:process(x,y,f1,f0) is
variable ztt:real:=0.0;
begin
case f1 & f0 is
when "00" =>
ztt:=x + y;
when "01" =>
ztt:=x - y;
when "10" =>
ztt:=x * y;
when "11" =>
ztt:=x / y;
end case;
z<=ztt;
end process;
end architecture behav;
entity floatingpointarithunit_test_v2 is
end entity floatingpointarithunit_test_v2;
architecture behav of floatingpointarithunit_test_v2 is
signal xt,yt,zt: real:=0.0;
signal ft:bit_vector(1 downto 0);
begin
u1: entity work.floatingpointarithunit_v2(behav)
port map (xt,yt,zt,ft(1),ft(0));
process is
begin
xt<=22.0;
yt<=5.0;
ft<="00";
wait for 5 ns;
ft<="01";
K-00382857 Prajapati Darshankumar A.

wait for 5 ns;

ft<="10";
wait for 5 ns;

ft<="11";

wait for 5 ns;

wait;
end process;
end architecture behav;

Waveforms:

(2.) Write a model for a counter with an output port of type natural, initially set to 15. When the clk input
changes to ‘1’, the counter decrements by one. After counting down to zero, the counter wraps back to 15
on the next clock edge.
Write a test bench for the multiplexer model, and test it using a VHDL simulator (Modelsim).

Code:

entity hw2_2_counter_v1 is
port(z:inout natural:=15;
clk:in bit);
end entity hw2_2_counter_v1;
architecture behav of hw2_2_counter_v1 is
begin
counter_pro:process(clk) is
variable zt: natural;
begin
zt:=z;
if clk='1' then
if zt=0 then
zt:=15;
else
K-00382857 Prajapati Darshankumar A.

zt:=zt-1;
end if;
z<=zt;
end if;
end process;
end architecture behav;
entity hw2_2_counter_test_v1 is
end entity hw2_2_counter_test_v1;
architecture behav of hw2_2_counter_test_v1 is
signal ztt: natural;
signal clkt: bit;
begin
u1: entity work.hw2_2_counter_v1(behav)
port map (ztt,clkt);

clk_gen: process is

begin
clkt<='1' after 1 ns, '0' after 2ns;
wait for 2ns;
end process clk_gen;
test_v1:process is
begin
wait for 66 ns;
wait;
end process test_v1;
end architecture behav;

Waveforms:

(3.) Develop a model of an averaging module that calculates the average of batches of 16 real numbers.
The module has clock and data inputs and a data output. The module accepts the next input number when
the clock changes to ‘1’. After 16 numbers have been accepted, the module places their average on the
output port, then repeats the process for the next batch.

Write a test bench for the multiplexer model, and test it using a VHDL simulator (Modelsim).
K-00382857 Prajapati Darshankumar A.

Code:

package coeff_ram_address_pkg is
subtype coeff_ram_address is integer range 0 to 15;
end package coeff_ram_address_pkg;
use work.coeff_ram_address_pkg.all;
entity hw2_3_average_v1 is
port(
data_in:in real;
data_out:out real;
clk:in bit);
end entity hw2_3_average_v1;
architecture behav of hw2_3_average_v1 is
begin
average_pro:process is
type coeff_array is array (coeff_ram_address) of real;
variable coeff : coeff_array;
variable zt: coeff_ram_address;
variable sum: real;
begin
zt:=0;
sum:=0.0;
average_loop: loop
if clk='1' then

coeff(zt):=data_in;
sum:=sum+data_in;
if zt=15 then
zt:=0;
sum:=sum / 16.0;--coeff'length;
data_out<=sum;
sum:=0.0;
else
zt:=zt+1;
end if;
end if;
wait on clk;
end loop;
end process;
end architecture behav;
entity hw2_3_average_test_v1 is
end entity hw2_3_average_test_v1;
architecture behav of hw2_3_average_test_v1 is
signal data_int, data_outt: real;
signal clkt: bit;
begin
u1: entity work.hw2_3_average_v1(behav)
port map (data_int,data_outt, clkt);
K-00382857 Prajapati Darshankumar A.

clk_gen: process is
begin
clkt<='1' after 1 ns, '0' after 2ns;
wait for 2ns;
end process clk_gen;
test_v1:process is
begin
data_int<=5.0;
wait for 32 ns;
data_int<=20.0;
wait for 32 ns;
wait;
end process test_v1;
end architecture behav;

Waveforms:

(4.) Write a model that causes assertion violations with different severity levels. Experiment with your
simulator to determine its behavior when an assertion violation occurs. See if you can specify a severity
threshold above which it stops execution.
Write a test bench for the multiplexer model, and test it using a VHDL simulator (Modelsim).

Answer:

various severities display different colors when assert is executed. The severity failure cause the stop of
the execution.

Code:

entity hw2_4_assertion_v1 is
port(data_in:in natural);
end entity hw2_4_assertion_v1;
architecture behav of hw2_4_assertion_v1 is
begin
assertion_pro:process (data_in) is
begin
assert data_in<10 report "data_in>=10, note!!!" severity note;
assert data_in<20 report "data_in>=20, warning!!!" severity warning;
K-00382857 Prajapati Darshankumar A.

assert data_in<30 report "data_in>=30, error!!!" severity error;

assert data_in<40 report "data_in>=40, failure!!!" severity failure;
end process;
end architecture behav;
entity hw2_4_assertion_test_v1 is
end entity hw2_4_assertion_test_v1;
architecture behav of hw2_4_assertion_test_v1 is
signal data_int: natural;
begin
u1: entity work.hw2_4_assertion_v1(behav)
port map (data_int);
test_v1:process is
begin
report "data in [0,10] is correct!!!";
data_int<=5;
wait for 5ns;
data_int<=15;
wait for 5ns;
data_int<=25;
wait for 5ns;
data_int<=35;
wait for 5ns;
data_int<=45;
wait for 5ns;
wait;
end process test_v1;
end architecture behav;

Waveforms: