Cycle Time Management

Professor Robert C. Leachman

IEOR 130, Methods of Manufacturing Improvement
Spring, 2007

Introduction and Overview

“Cycle time” is semiconductor industry jargon for the elapsed time to pass manufacturing
lots through the manufacturing process, from lot creation until lot completion. The term
is also applied to individual manufacturing steps, measuring the elapsed time from
completion of the preceding step until completion of the step in question, or to a series of
manufacturing steps (the sum of the cycle times of the subject steps).

In produce-to-order environments, cycle time is part of the product/service apparent to

the customer and is therefore an important competitive issue. Suppliers able to offer
shorter cycle times will be preferred. In the case of goods experiencing a rapid pace of
technological obsolescence such as semiconductors, cycle time has a very strong
influence on realized average selling prices. Firms with shorter cycle times are able make
sales at earlier times when prevailing prices are higher. And by making those sales, they
tend to drive prices down and thereby diminish revenue available to competitors.

A general managerial strategy with respect to cycle time is proposed as follows:

(1) Management should impute an economic value to cycle time and declare this value to
the engineering and operations organizations. Management should require that any
proposals for changes to the manufacturing process or to operational policies that would
change cycle times must be justified by quantifying the overall economic impact,
including the gain or loss in value associated with changes in cycle time.

(2) Entitlement cycle times should be calculated for every product and process.
Entitlement cycle time is the result of an analytical calculation or simulation determining
what cycle time the manufacturing process is capable of, considering the process
specifications, the equipment released, statistics on process times, and statistics on
process and equipment trouble. Practical tools must be distributed to the engineering
organization enabling them to measure entitlement cycle times, not only for the current
situation, but also for any proposed changes to process, production volume or operational
policy.

(3) Management should establish cycle time goals for each product. These goals may be
dynamic, anticipating learning curve improvements. Where entitlement cycle time is
larger than the cycle time goal, the engineering organization must devise changes to
equipment, process or policy enabling the goal to be met.

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(4) Where actual cycle time is larger than entitlement cycle time, the manufacturing
organization needs to improve execution. Improved execution tools may be required, i.e.,
more advanced planning and scheduling systems.

In these notes we first impute economic value to cycle time reduction in terms of the
revenue gain resulting from increased selling prices enabled by shorter time to market.
Next, we review and adapt models from queuing theory as a practical means for
computing entitlement cycle times. Finally, we review important aspects of advanced
scheduling methodology aimed at closing the gap between actual and entitlement cycle
time.

1. Imputing the Economic Value of Cycle Time

Consider a new product that is qualified for production at time 0. The overall yield (line
yield times die yield) of the product at time 0 is Y. The product continues in production
with yield Y until time H, at which time it becomes totally obsolete and is withdrawn.

At time 0 the selling price of a 100%-yielding wafer of the product is P0. But this price
erodes with time; at time t, the average selling price is

P(t ) = P0 e −αt .

Suppose the manufacturing cycle time for wafers started at time t is CT(t), and suppose
the wafer starts per unit time at time t is W(t). Then the total lifetime revenue for the
product is expressed as

H H
R = ∫ W (t )YP(t + CT (t ))dt = ∫ W (t )Y P0 e −α ( t +CT ( t )) dt . (1)
0 0

Let’s consider the special simple case were the wafer starts and cycle time are constant
over the life of the product, i.e., W(t) = W and CT(t) = CT. Then the lifetime revenue
integral may be simplified as

− αH
−αCT ⎛ 1 − e ⎞
H H

∫0 0 ∫0
−α ( t + CT ) −αCT −αt
WYP e dt = WYP0 e e dt = WYP0 e ⎜
⎜ α ⎟⎟ .
⎝ ⎠

Now suppose cycle time is shortened by one day, i.e., CT → CT − 1 . Then the lifetime
revenue becomes

−α ( CT −1) ⎛ 1 − e −α H ⎞
WYP0 e ⎜⎜ ⎟⎟ .
⎝ α ⎠

The revenue gain from reducing cycle time by one day is therefore

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 ⎛ 1 − e −α H ⎞ ⎛ 1 − e − αH ⎞
ΔR = WYP0 e −α ( CT −1) ⎜⎜ ⎟⎟ − WYP0 e −αCT ⎜⎜ ⎟⎟
⎝ α ⎠ ⎝ α ⎠

or

⎛ 1 − e −α H ⎞
( )
ΔR = e α − 1 WYP0 e −αCT ⎜⎜ ⎟⎟ . (2)
⎝ α ⎠

To illustrate, suppose a fab is makes 10,000 wafer starts per week of product that yields
420 good die per wafer. The cycle time is 50 days. The selling price at time 0 is $4.50 per
die and is declining 25% per year. The product life is two years.

If time is expressed in days, then α satisfies

0.75 = e −α 365

or α = 0.00078817.

The value of one day of cycle time is then

1 − e − ( 0.00078817 )( 730 )
(
ΔR = e 0.00078817 − 1 )10,7000 (420)(4.50)e − ( 0.00078817 )( 50 )

0.00078817

or

ΔR = $1,136,000 ,

i.e., the revenue gain from cycle time reduction in this fab is worth about $1.14 million
per day.

Not included in the above analysis is the cost reduction associated with reducing cycle
time. The most important element of such cost reduction in semiconductor manufacturing
concerns the positive impact on yield from cycle time reduction. This occurs for two
reasons: (1) Some yield loss mechanisms involve equipment or process “excursions” in
which the process or equipment shifts out of control, but this excursion is not detected
until the first lot processed after the excursion reaches the end of the production line and
is tested. All lots that had passed the out-of-control point also will have poor yield. When
cycle time is reduced, the WIP is reduced, and therefore the number of lots with exposure
to excursion loss is reduced. (2) A process change that will improve yield must be
justified on the basis of an in-line experiment. Typically, some wafers from a selected
manufacturing lot are processed the old way, while others from the same lot are
processed the new way. The lot then must travel through the rest of the fabrication
process to the end of the line where all wafers are tested, and where it must be

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demonstrated statistically that the process change indeed improves yield. The shorter the
cycle time, the less time is required to implement process changes, and therefore the yield
learning curve is improved.

2. Estimating Entitlement Cycle Times Using Queuing Theory

Queuing Theory is a branch of operations research used to analyzing waiting times in

resource-constrained systems. In our context, cycle time consists of the following
components: execution time (process time and material movement time), waiting time,
and lot hold time (e.g., lot stopped from further processing because of an SPC out-of-
control alarm). Waiting time is typically the largest component of cycle time.

The terminology of queuing theory reflects a human waiting line. Customers randomly
arrive for service and await an available server. When all previous customers have been
served and server becomes free, the customer enters service. The time between customer
arrival and entry into service is called the queue time. The customer departs service after
a service time. In our manufacturing context, the customers are typically the production
lots and the servers are the machines qualified to perform the process step. The queue
time corresponds to the lot waiting time, and the service time corresponds to the process
time (i.e, the time between consecutive lots).

The mathematics of queuing theory is involved. Most of the useful results are
approximate formulas, and they typically stem from an assumption that the lot inter-
arrival time follows an exponential distribution, i.e., lot arrivals are Poisson. (This is also
called the Markovian assumption.) Considering the nature of fabrication process flows,
this is not a bad assumption for semiconductor fabrication. The typical work station
(photo, etch, diffusion, implant, etc.) experiences arrivals of lots coming from a variety of
work stations throughout the fab. If work stations operate independently, then the
aggregate arrivals from many work stations should reflect a Poisson distribution.

One of the simplest queuing systems to analyze is the M/M/1 queue. This is a model of a
production workstation that assumes the lot interarrival time is Poisson, the time to
“service” the lot (i.e., the process time) also has an exponential distribution, and there is
only one “server” (i.e., one machine). Let ta denote the mean time between arrivals and
let ts denote the mean service time. The arrival rate is then λ = 1/ta and the service rate is
μ = 1/ts. (It is customary in queuing theory to use the notation λ for the arrival rate and μ
for the service rate.) Because the interarrival and process time distributions are
memoryless, the time since the last arrival and the elapsed service time are irrelevant to
the future behavior of the queue. The only information we need to characterize the
current state of the system is the number of lots currently at the workstation; call this
number n. By computing for each possible value of n the long-run probability that the
number of lots in the system is n, we can in turn derive the expected waiting time and
cycle time for the workstation.

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Let pn denote the probability of finding the system in state n (i.e., the total number of lots
in queue and in process is n). Because jobs arrive one at a time and because the machine
works on only one job at a time, the system state can only change by one unit at a time.
Given the system is in state n, the rate the system moves from state n to state n+1 is λ.
And given the system is in state n+1, the rate the system moves from state n+1 to n is μ.
The unconditional rate at which the system moves from state n to state n+1 is therefore
λpn, i.e., the probability the system is in state n times the arrival rate. The unconditional
rate at which the system moves from state n+1 to n is μpn+1, i.e., the probability the
system is in state n+1 times the service rate. In long-run equilibrium, these rates must be
equal, i.e.,

λ
λpn = μpn +1 , or pn +1 = pn = upn .
μ

Here we have made the identification that the utilization of the server must equal the
arrival rate divided by the service rate. That follows from the following observation:
Utilization equals the fraction of time that the server is busy processing lots, which in
turn equals the arrival rate times the mean service time, i.e.,

u = (λ)(ts) = λ/μ .

Now the state probabilities must sum to unity, i.e.,

∞ ∞ ⎛ 1 ⎞
1= ∑ n 0 ∑ u n = p0 ⎜
p = p ⎟,
n =0 n=0 ⎝1− u ⎠

so therefore

p0 = 1- u .

Note that we must assume u < 1 for the sum to converge, i.e., utilization of the server
must be strictly less than 100% to have a stable queue in the presence of randomness.

The expected number of lots in the system is

∞ ∞ ∞ d ∞ n 1 u
∑ np n = ∑ n(1 − u )u n = u (1 − u ) ∑ nu n −1 = u (1 − u ) ∑ u = u (1 − u ) = .
n =0 n=0 n=0 du n =0 (1 − u ) 2
1− u

The cycle time, i.e., the expected total time a lot spends in the system is

∞
⎛ u ⎞ t
CT = ∑ t s (n + 1) p n = t s ⎜ + 1⎟ = s ’
n =0 ⎝1− u ⎠ 1− u

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and the waiting time, i.e., the expected time a lot spends in queue is just ts less than this,
i.e.,

ts u
QT = − ts = ts . (3)
1− u 1− u

Queuing theory includes a number of useful generalizations of the simple M/M/1 formula
given in (3). For manufacturing applications, we are interested in generalizations
modeling more than one machine in the work station, machine down time, and
interarrival and process time distributions that are different from exponential. Such a
general case defies exact solution. But a very useful and reasonably accurate approximate
formula for this case progressively developed by Kingman (1961), Sakasegawa (1977)
and Hopp and Spearman (1999) is as follows. This formula applies to the case where m
machines are qualified to perform a given manufacturing step. Other notation is as
follows:

u – the utilization of availability of the work station

PT – mean lot process time
c02 – the squared coefficient of variation in lot process time (i.e., the ratio of the variance
of lot process time to the square of the mean process time)
A – the average availability of the machines in the work station
MTTR – mean length of a machine down time event
cr 2 – the squared coefficient of variation in the length of a down time event
ce 2 - short-hand notation for the squared coefficient variation of the effective service
time, a function of A, MTTR, cr 2 , PT, and c02 .
ca 2 - the squared coefficient of variation in the lot inter-arrival time; for Poisson arrivals,
ca 2 =1.

The expected (average) waiting time is then

⎛ ca 2 + ce 2 ⎞⎛⎜ u 2 ( m +1) −1 ⎞⎟⎛ PT ⎞

QT = ⎜⎜ ⎟⎟ ⎜ ⎟ (4)
⎝ 2 ⎠⎜⎝ m(1 − u ) ⎟⎠⎝ A ⎠

where

⎛ MTTR ⎞
ce 2 = c02 + (1 + cr 2 ) A(1 − A)⎜ ⎟.
⎝ PT ⎠

Note that if ca = ce = m = A = 1, i.e., we have Poisson arrivals and service in a single-

machine system with no down time, then (4) reduces to (3).

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Let us examine this general waiting time formula qualitatively. It is the product of three
terms. The first term in (4) is a term involving the variability of lot arrivals and the
variability of service time. More variability increases cycle time.

The second term in (4) concerns the utilization of the work station and the number of
qualified machines. Note the (1-u) in the denominator; as utilization is pushed to 100% of
the availability, queuing theory predicts wait time will explode. The behavior of this term
is graphed in Figure 1 for various values of m and for u ranging from 0 up to 100% of
availability. Note that wait time is reduced as m is increased, even for the same
utilization. At 90% utilization of availability, average wait time when only one machine
is qualified is more than nine times higher than when eight machines are qualified.

The third term in (4) expresses a ratio of process time to availability. All else being equal,
a longer process time also means a longer average wait time. All else being equal, a lower
availability means a longer average wait time (even if utilization is reduced to the same
utilization of availability).

Wait Time vs. Utilization

10
9
8 Wait Time (1 machine)
7 Wait Time (2 machines)
Wait Time

6
Wait Time (3 machines)
5
Wait Time (8 machines)
4
3
2
1
0
05

15

25

35

45

55

65

75

85

95
1

9
0.

0.

0.

0.

0.

0.

0.

0.

0.
0.

0.

0.

0.

0.

0.

0.

0.

0.

0.

Utilization

Figure 1. Wait Time as a Function of the Number of Qualified Machines and the
Utilization of Availability

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Cycle time may be reduced if any of the three terms in (4) is reduced. This suggests the
general avenues for cycle time reduction: reducing variability (i.e., reducing ca or
reducing ce), increasing m or reducing u, and reducing PT or increasing A.

To obtain an overall estimate of cycle time for a manufacturing step, we need to add up
the following components: wait time (estimated as above) and standard cycle time.
Standard cycle time is the time required for a lot to move from completion of the
previous step to completion of the step in question when there is no waiting for other lots
or down equipment. The estimate of the cycle time for a product/step is then

CT = QT + SCT .

For many types of equipment, the standard cycle time is simply the sum of the lot process
time and the material transport time. But for some types of equipment, a lot is resident at
the equipment for a duration longer than the process time. For example, in the case of
photolithography scanners linked to coat and develop tracks, the time between lots (lot
process time, determined by the scanner) is much less than the total time for a lot to
traverse the coat track, scanner and develop track (standard cycle time). In other types of
equipment, there may be additional material handling time besides the time to transport
lots between manufacturing steps. For example, at diffusion furnaces, time is required to
unload wafers from the transport cassette into a quartz diffusion boat and then reload the
transport cassette after the step is completed. This unload/reload time does not tie up the
furnace and is therefore not part of process time, but it nevertheless contributes to
standard cycle time.

The basic queuing model introduced above needs to be modified for the cases of
machines whose operation requires the lots to be grouped into batches that are sequenced
through the machine. Batching may be performed because of a large load size for the
equipment (e.g., diffusion furnaces), or because of significant setups applicable to classes
of manufacturing steps (e.g., species setups on ion implanters). We treat the case of large
load sizes as follows.

Batch Machines

To model machines with load sizes larger than one lot, we proceed as follows. Lots
experiencing a common process recipe must be batched together to make up a load. For
example, in semiconductor fabrication, a number of different product/steps may share the
same furnace recipe; lots arriving for performance of these product/steps may share one
equipment cycle. We therefore view batches of lots for a given recipe as the customers of
the queuing system rather than lots of a given product/step. Even if a furnace is available
when it arrives, a random lot may experience an additional delay waiting for other lots to
arrive in order to make up a batch. Suppose the average load size is b lots and the overall
arrival rate of lots sharing a common recipe is S lots per hour. Then the average lot
experiences the following delay (in hours) for building up a batch (“batching time”):

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 b −1
BT = . (5)
2S

The overall cycle time is then estimated as

CT = SCT + BT + QT

where QT is estimated as in (4) and BT is estimated as in (5). The extra batching-time

term presents another cycle time issue. The batch size can be set too small (resulting to
very-high utilization of the furnace) or too large (resulting in too much wait time to build
up a batch). Figure 2 illustrates this trade-off.

Cycle time vs. Batch size for TEL_OXWETG

5.5
Avg. cycle time (hours)

5.25
5
4.75
4.5
4.25
4
3.75
3.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Avg. batch size (Lots)

Figure 2. Cycle time vs. Batch Size for a Particular Diffusion Furnace Type

Application Issues

Many different product/steps are performed by a typical work station. The process time
input to (4) needs to be a weighted average of the process times for the various
product/steps. However, the number of qualified machines m and the standard cycle time
SCT can be specific in the estimation of cycle time for a given product/step.

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3. Advanced Scheduling Methodology

The most common methodology for factory floor scheduling involves the application of
dispatching rules. The work-in-process awaiting processing in a given work station is
prioritized using dispatching rules. When a machine is made free and available, the
highest-priority lot is assigned for processing. Typically, dispatch priority is a function of
a pre-established due-date for completion of the lot. The intent is to give priority to lots
behind schedule.

In semiconductor fabrication practice, there are a number of problems associated with

application of dispatching rules. First, the lot due-dates become stale and may not reflect
true priorities. Most fabrication facilities process many lots of the same product.
Customers are indifferent as to which of these lots they receive. Because of inspection
sampling, process holds and other issues, it is very common for lots to get out of their
starting order. When one lot of a given product passes another lot of the same product,
ideally they should exchange due dates, but this typically does not happen. Moreover,
manufacturing yields are variable; when yields of downstream lots are worse than
planned, the due dates of the upstream lots should be advanced (and when downstream
yields are better than planned, the due dates of upstream lots should be delayed), but
again this typically does not happen. Even worse, the target output schedule may be
changed, but lot due dates not updated to reflect this change.

A second problem concerns the fact that a dispatch list is not really a schedule, it is
simply a priority list for a group of parallel machines comprising a workstation. It still
requires the humans to determine and define the arrangement of lots among the
alternative machines.

A third and related problem arises if the way lots are allocated among the machines in a
work station can significantly impact yield or lot throughput, then strictly following the
dispatch order can be undesirable. In such cases, the manufacturing organization may
give little heed to the dispatch list, as the list provides no basis for assessing trade-offs
between on-time delivery and workstation efficiency.

An alternative approach is described in Leachman, Kang and Lin (2002). The so-called
SLIM (Short cycle time and Low Inventory in Manufacturing) system was developed and
implemented at Samsung Electronics Corp., Ltd. to provide shift production targets and
on-line scheduling of fabrication activity in Samsung’s fab lines. Certain aspects of SLIM
will be highlighted in these notes, but the reader should refer to full paper to fully
comprehend the methodology.

The methodology of SLIM is summarized as follows. A target output schedule for the
fabrication facility is established by the planning function. Target cycle time from fab-in
to fab-out also is established for each product of the fab. The SLIM methodology breaks
out the target cycle time by step in a manner that establishes cycle time buffers in each
masking layer in proportion to the cycle time variability in that layer.

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Once each shift, the target fab out schedule is translated into equivalent production
targets for each step on each product. These targets are termed the ideal production
quantities (IPQs). The use of the IPQs is as follows: Arrangement of lots on machines to
facilitate better process control or throughput is acceptable as long as completion of the
IPQs is not jeopardized. That is, we strive to be current with the cycle time plan and the
fab out plan by the end of each production shift. Next, on-line scheduling logic within
SLIM assigns all on-hand work-in-process to the machines in the workstation. This logic
strives to complete IPQs by the end of the shift, prevent starvation of downstream
bottlenecks, and make arrangements of lots on the machines that are efficient. The logic
must be customized for each workstation reflecting the process and equipment
peculiarities in that workstation.

Determining Target Cycle Times and Target WIP Levels by Layer

Given a target cycle time TCT for an entire fab process, we can determine target cycle
times and target WIP levels for each photo layer according to the following procedure.

Let SCT denote the sum of standard cycle times for all steps in the process flow. The
difference between total target cycle time TCT and total standard cycle time SCT is the
total buffer time TBT to be allocated across the process flow.

Using Little's Law, we can express the same relationship in terms of WIP. The target total
WIP level is TW = (TCT)(λ), where λ is the production rate. The total active WIP in the
process is given by ActvW = (SCT)(λ), The difference TW – ActvW = (TCT - SCT)(λ) is
the buffer inventory TBW to be allocated across the process flow.

The primary purpose of the buffer time or buffer inventory is to protect bottleneck
resources against utilization losses. In most wafer fabs, the photolithography steppers are
the bottleneck. When the process is operating in control and all equipment is operating,
the buffer WIP across all steps between visits to the steppers will be concentrated right
before the stepper processing step. But because of random machine down times or
process out-of-control events, WIP is sometimes more distributed over the steps in the
layer, and there is a risk the WIP at the stepper operation may be drawn down below the
active WIP level, i.e., there is a risk of undesired idle time.

It is often the case that the steppers are somewhat inflexible, i.e., certain mask layers
must be performed using certain steppers. It is also often the case that changing which
layer a stepper is processing involves a setup time that consumes capacity. In such cases,
it is valuable to have a WIP buffer in each layer. Logically, the size of the buffer should
be proportional to the amount of uncertainty in the WIP supply to that layer. That is, the
more uncertainty, the more risk of starvation of the photo machines performing that layer,
and the greater the need for a WIP buffer.

We decompose the process flow into layers for the purposes of WIP control as follows.
Layer 1 consists of all processing steps from fab start up through the first

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photolithography exposure. Layer j consists of all processing steps after layer j-1 up
through the jth photolithography exposure. (NOTE: this definition of layers is different
from the way a designer would describe the physical layers of the device.)

As a proxy for the uncertainty in the WIP supply to each layer, we can consider the
uncertainty in the elapsed cycle time from completion of the bottleneck processing step in
layer j-1 to arrival in the queue for the bottleneck processing step in layer j. (If j=1, we
consider the standard deviation in the cycle time from the start of the process flow until
arrival in the queue for the first bottleneck step.) The idea here is that, if the WIP flow
through some layer has many disruptions because of equipment or process trouble, there
should be a high variance of cycle time in that layer.

Let σj denote the standard deviation of the cycle time for the layer ending at the jth photo
operation, j = 1, 2, ... , L. Data must be collected empirically to establish σj. To prevent
starvation of the photo machines performing the layer j exposure operation, we would
like to plan a buffer time BTj in layer j of size k * σj, where k is as large as possible.
Equivalently, we would like to plan a buffer WIP level BWj = (BTj )( λ ).

We can equalize the protection against starvation in all layers by choosing the same "k"
factor for all layers. That is, we take

TCT − SCT
k= L

∑σ
j =1
j

The target cycle time for layer j, TCTj, is then set to TCTj = SCTj + BTj, where BTj = k
* σ j.

Equivalently, we set the target WIP level for layer j, TWj, to be TWj = ActvWj + BWj,
where ActvWj is the active WIP in layer j and BWj = ( k * σj ) ( λ ) is the target buffer for
layer j. (The active WIP in layer j is given by (SCTj )( λ ), where SCTj is the sum of
standard cycle times for all process steps in layer j and λ is the production rate.)

For the series of process steps after the last photo step in the process, we simply set the
target cycle time equal to the standard cycle time, i.e., we set the target WIP equal to the
active WIP. There is no need for a buffer after the last visit to the bottleneck.

In some cases, data on σj are not available or impractical to derive, but data on actual
cycle times ACTj are available. In such a case, we may use ACTj – SCTj is an index of the
uncertainty in the cycle time for layer j. (The idea is, layers in which the discrepancy
between actual and standard cycle time is large must have more waiting time and
therefore require a larger downstream buffer to maintain throughput.) We therefore re-
define the “k” factor as

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 TCT − SCT
k=
∑ (ACT − SCT j )
L

j
j =1

And we set the target cycle time for layer j, TCTj, to be TCTj = SCTj + BTj where BTj =
k*(ACTj – SCTj).

Production Targets and Scheduling Priorities

The target WIP levels allow us to determine production targets. We define the ideal
production quantity (IPQ) of a particular process step to be the quantity we should
complete by the end of a production shift such that the downstream WIP is made exactly
equal to the amount required to fulfill the production rate over the target cycle time to fab
out.

We illustrate the computation of the IPQ for photo bottleneck steps assuming line yields
are 100%. Let AWj denote the actual WIP in layer j, and let TWj denote the target WIP in
layer j. Let λ denote the target production rate per shift, and let ΔFO denote any shortage
(surplus if negative) of fab outs to date compared to the target production rate. Then

L +1
IPQ j = ΔFO + ∑ (TWl − AWl ) + λ
j =1

where TWL+1 and AWL+1 denote the target and actual WIP levels, respectively, in the string
of process steps after the last photo layer. We remark that IPQj may have any positive or
negative value. (It is negative when production is more than one shift ahead of schedule.)
Even if positive, it may be impossible to finish the IPQ in one shift if the supply of WIP
is insufficient and/or if the available capacity is insufficient. Hence the adjective ideal.

The production targets can be turned into schedule priorities simply by dividing by the
production rate. We define the schedule score (SS) of a photo step to be

SSj = -IPQj / λ

We can prioritize photo steps by least SS first in order to decide which step to set up first
on an available machine. Note that we have prioritized steps rather than lots. Suppose we
wish to economize on changeovers between different product/steps which utilize different
masks and different settings of the photo machine. Then once a step is selected for
processing, we should try to dispatch enough lots of that step to fulfill its IPQ. If we can
continue to process lots of that product/step without jeopardizing fulfillment of the IPQs
for the other product/steps we may do so, but otherwise we need to change to process a
different product/step with a negative schedule score and on-hand WIP.

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SLIM Scheduling Logic

An optimization problem may be defined and solved to schedule the available WIP so as
to meet the SLIM priorities as much as possible, or a heuristic algorithm may be
developed. We outline a heuristic algorithm as follows. We suppose changing the
product/step performed by the machine is a productivity and/or process control issue and
that such changeovers are to be economized.

1. Prioritize product/steps by schedule score.

2. For running machines, if there is available unassigned WIP and SS < 0 for the current
product/step, assign lots to the machine until the IPQ is reached or the available WIP is
exhausted or the available machine time in the shift is exhausted, whichever limit is
reached first. Update IPQ scores as assignments are made (simply subtract the
assignment).

2. Proceed down the priority list of product/steps. Choose the preferred machine to assign
the highest-priority product-step. The preference ordering of machines might reflect
setups common across a group of product/steps, the remaining available time on the
machines, difference in process times among the machines, the total amount of candidate
WIP for each machine, or other factors. Assign lots to that machine until the WIP is
exhausted or the IPQ is reached or all available machine time is exhausted, whichever
occurs first.

Continue performing step 2 for all product/steps with negative schedule scores until as
much progress towards fulfillment of the IPQs has been made as is feasible.

3. Go back through the list of product/steps and repeat. This time, assign up to all
available WIP or available machine time.

4. In situations of low WIP, one or more machines may be idled as a result of applying
the above assignment algorithm. In this case, one can adapt the algorithm by removing a
lot from a busy machine, assigning it to the idle machine, and pretending this lot is
already running (and therefore treated in step 2).

References

Kingman, J. F. C., “The Single-Server Queue in Heavy Traffic,” Proceedings of the

Cambridge Philosophical Society, 57, p. 902-904 (1961).

Hopp, Wallace and Mark Spearman, Factory Physics, McGraw-Hill, New York (2001).

Leachman, Robert C., Jeenyoung Kang and Vincent Lin, “SLIM: Short Cycle Time and
Low Inventory in Manufacturing at Samsung Electronics,” Interfaces, 32 (1), p. 61-77
(Jan.-Feb. 2002).

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