Evolium BSC Hardware Description

Alcatel-Lucent GSM
9120 BSC Hardware Description
BSC & TC Document

Sub-System Description
Release B10
3BK 21239 AAAA TQZZA Ed.04

BLANK PAGE BREAK
Status RELEASED
Short title BSC HW Descr.

All rights reserved. Passing on and copying of this document, use
and communication of its contents not permitted without written
authorization from Alcatel-Lucent.
2 / 142 3BK 21239 AAAA TQZZA Ed.04

Contents
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2 Common Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2.1 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2.2 Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 CPRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 CEPK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1 Onboard Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.2 OBC Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.3 Common RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.4 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.5 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.6 Inventory EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.7 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 CENK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.1 OBCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.2 OBCI SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.3 Cyclic Redundancy Check and Bit-Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.4 Cyclic Redundancy Check Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.4 CEBK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.4.1 Broadcast Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.4.2 Driver and Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.5 External Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5.1 DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.5.2 SCC/SCSI SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.5.3 SCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.5.4 X.25 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.5.5 Man-Machine Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.5.6 Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.5.7 Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6 Memory Disk Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.7 Memory Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.7.1 CMDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.7.2 CMFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.8 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.9 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.10 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.10.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.10.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.10.3 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.11 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3 TCUC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.2 Abis Logic Cell Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.2.1 Abis Multirate Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2.4 BIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3 BSI Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3.1 Drivers and Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3.2 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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Contents
3.3.3 External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.4 ILC Signaling Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.5 Signaling Link Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.6 Multirate Traffic Channel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.7 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.8 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.8.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.8.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.8.3 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4 DTCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.2 Trunk Access Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.2.1 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.2.2 2048 kbit/s PCM Trunk Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.3 4096 kbit/s PCM Link Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.2.4 Clock Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.2.5 OBC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.2.6 Diagnostic Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3 ILC Signaling Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3.1 HDLC Formatters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3.2 Signaling Link Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3.3 Transmit Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3.4 Receive Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4 Ater Logic Cell Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.4.1 Ater Multirate Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.5 BSC Clock A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.6 Signaling Link Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.7 Multirate Traffic Channel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.8 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.9 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.9.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.9.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.9.3 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5 SWCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.1.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.1.2 Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.1.3 Functional Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.2 Switching Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2.1 Switching Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2.2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2.3 Phase-locked Loop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3 Serial Line Receivers and Line Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.4 Clock Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.5 Voltage-controlled Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.6 Power-on Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.7 Clock Buffers and Frame Delay Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.8 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6 BCLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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6.2.1 Reference Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.2.2 Phase-locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.2.3 Master Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.2.4 Output Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.1 SYS-BCLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.2 RACK-BCLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4 Broadcast Bus Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4.1 SYS-BCLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4.2 RACK-BCLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.5 Remote Inventory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.6 DTCC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.6.1 Clock Control Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.6.2 Alarm Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.6.3 Status Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.7 External Alarm Scanning and Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.7.1 Alarm Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.7.2 Alarm Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.8 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.8.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.8.2 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7 DC/DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.1.1 Output Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.1.3 Automatic Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.2.1 Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.2.2 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.3 Voltage and Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.3.1 Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.3.2 Output Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.4 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8 ASMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.2 Onboard Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.3 Ater Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.3.1 Clock Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.3.2 HDB3 to NRZ Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.3.3 Re-timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.3.4 Frame Alignment Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.3.5 CRC4 Monitoring and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.3.6 Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.3.7 Fault Indications Sent to Remote End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.3.8 TCC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.4 Ater Mux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.5 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.5.1 Sub-rate Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.5.2 Time Space Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.6 TS0 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.7 Serial Communication Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.8 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.9 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.10 Remote Inventory EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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8.11 Local Qmux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

8.12 Remote Qmux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.13 Qmux Address Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.14 Man-Machine Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.15 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.15.1 Onboard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.15.2 TS0 Logic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.15.3 SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.15.4 TSSW Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.15.5 SRS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.16 Watchdog Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.17 Long Range Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.18 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.18.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.18.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.18.3 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.19 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9 BIUA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.3 Abis Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.3.1 Clock Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.3.2 HDB3 to NRZ Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.3.3 Re-timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.3.4 Frame Alignment Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.3.5 CRC4 Monitoring and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.3.6 Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.3.7 Fault Indications Sent to Remote End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.3.8 TCC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.4 BSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.5 Sub-rate Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.6 Time Space Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.7 TS0 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.8 Serial Communication Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.9 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.10 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.12 Local Qmux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.13 Remote Qmux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.14 Qmux Address Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.16 LAPD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.17 Alarm Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.18 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.18.1 Onboard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.18.2 TS0 Logic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.18.3 SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.18.4 TSSW Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.18.5 SRS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.20 Long Range Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.21 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.21.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.21.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.21.3 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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10 TSCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.4 Memory Controller and Register Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.5 Serial Communication Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.5.1 SCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.5.2 SCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.5.3 SCC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.6 Local Qmux Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.7 Remote Qmux Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.9 LAPD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.12 Long Range Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.13 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.13.1 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.13.2 Extended Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.14 Onboard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.14.1 SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.14.2 DRAM Bank Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.14.3 FLASH EPROM Bank Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.14.4 Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.14.5 Wait State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.14.6 Parity Location Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.14.7 Remote Inventory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.14.8 LED Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.15 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.15.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.15.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.15.3 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
3BK 21239 AAAA TQZZA Ed.04 7 / 142

Figures
Figures
Figure 1: BSC Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2: Simplified CPRC PBA Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3: CEPK Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4: CENK Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5: Broadcast Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 6: External Communication Interface Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 7: DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 8: CMDA Simplified Functional Diagram for 3BK 06428 Ax Variant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 9: CMFA Simplified Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 10: CPRC PBA - Main Data Flow Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11: CPRC Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12: TCUC PBA Simplified Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 13: Abis LCA Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 14: Signaling Termination Data and Control Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 15: Multirate Traffic Switching - Data and Control Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 16: TCUC PBA - Main Data Flow Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 17: TCUC Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 18: DTCC PBA Simplified Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 19: Signaling Link Handling - Data and Control Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 20: Ater LCA Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 21: Multirate Traffic Switching - Data and Control Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 22: DTCC PBA - Main Data Flow Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 23: DTCC Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24: Switch PBA, AS Variant Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 25: Switch PBA, GS Variant Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 26: SWCH Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 27: SYS-BCLA Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 28: RACK-BCLA Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 29: BCLA Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 30: DC/DC Converter Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 31: ASMB PBA Simplified Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 32: Ater Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 33: Clock Selection and Synchronization Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 34: TS0 Logic - Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 35: ASMB Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 36: BIUA PBA Simplified Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 37: Abis Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 38: BSI Drivers and Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 39: Clock Synchronization Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8 / 142 3BK 21239 AAAA TQZZA Ed.04

Figures
Figure 40: TS0 Logic - Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 41: BIUA Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 42: TSCA PBA Simplified Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 43: TSCA Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
3BK 21239 AAAA TQZZA Ed.04 9 / 142

Tables
Tables
Table 1: PBA Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2: PCR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3: EPCR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4: TOR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5: NMIR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6: MREG Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7: INVR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8: CBR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9: MCR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 10: CPR LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 11: TCUC LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 12: DTCC LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 13: DTCC LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 14: BCLA PBA - LED 4 Flashing Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 15: Maximum Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 16: Static Regulation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 17: Output Ripple and Noise Peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 18: Maximum Output Current - Short-Circuit Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 19: DC/DC Converter LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 20: TS0 Logic - Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 21: ASMB Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 22: ASMB Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 23: RINVR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 24: QAR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 25: ASMB LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 26: TS0 Logic - Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 27: BIUA Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 28: BIUA Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 29: RINVR Bits BIUA PBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 30: QAR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 31: LAPD Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 32: BIUA LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 33: TSCA Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 34: TSCA LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10 / 142 3BK 21239 AAAA TQZZA Ed.04

Preface
Preface
Purpose This document describes the hardware of the 9120 BSC.
What’s New In Edition 04

Update for new equipment naming.
In Edition 03
Overall document quality was improved following a quality review.
In Edition 02
Update of system title.
In Edition 01
First official release of document.
Audience This document is intended for:
Commissioning personnel
System support engineers
Any other personnel interested in the structure of the BSC hardware.
Assumed Knowledge The reader must have general knowledge of telecommunications systems and
terminology, electronics and the BSC functions.
3BK 21239 AAAA TQZZA Ed.04 11 / 142

Preface
12 / 142 3BK 21239 AAAA TQZZA Ed.04

1 Introduction
1 Introduction
This document provides an introduction to the hardware of the functional units

of the BSC. It also provides information which is common to a number of PBAs.
3BK 21239 AAAA TQZZA Ed.04 13 / 142

1 Introduction
1.1 Functional Units

The following figure shows the breakdown of the BSC into functional units. As
can be seen from the figure, each functional unit comprises one or more PBAs.
n n
Abis TSU 1 Ater TSU 1

8 5−8 2 MSC
BTS BIUA DSN
1 1−4 1
TCUC SWCH DTCC ASMB
MSC
Qmux bus
Common TSU
Standby Standby
Active Active
OSI−CPRC SYS−CPRC BC−CPRC
Transcoder Submultiplexer
Controller Clock and Alarm System
n S 1 S n
M n
Clock/BC A
1 M 1
TSCA SYS−BCLA RACK−BCLA Clock/BC B
TSC Terminal OMC−R BSC Terminal External Alarms

M : Master
S : Slave
BC : Broadcast
TSU : Terminal Sub-Unit
OSI : Open System Interconnection
SYS : System
Figure 1: BSC Functional Units
Refer to the following sections for more information about the PBAs which
compose the functional units.
14 / 142 3BK 21239 AAAA TQZZA Ed.04

1 Introduction
1.2 Common Information

This section describes information which is common to a number of PBAs.
1.2.1 Dimensions
The following table gives the physical dimensions of the PBAs and the number
of PBA slots occupied.
Width (PBA
PBA Height Depth Slots)
All except DC/DC Converter 221 mm 254 mm 1.6 mm (1)
DC/DC Converter 221 mm 254 mm 3.2 mm (2)
Table 1: PBA Dimensions
1.2.2 Temperature Range

At altitudes between sea level and 500 meters, the temperature range is + 10C
and 30C. The relative humidity must be within a range from 20% to 80%.
For further information about the environmental characteristics of the BSC
equipment, refer to the BSC Cabinet and Subrack Description.
3BK 21239 AAAA TQZZA Ed.04 15 / 142

1 Introduction
16 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC
2 CPRC
This section describes the hardware architecture of the CPRC PBA.
3BK 21239 AAAA TQZZA Ed.04 17 / 142

2 CPRC
2.1 Introduction
The following figure shows a simplified diagram of the hardware architecture
of the CPRC PBA. Some functions of the CPRC PBA are common to the
TCUC and DTCC PBAs.
These functions are the:
CEPK (Control Element Processor Kernel)
CENK (Control Element Network Kernel)
CEBK (Control Element Broadcast Kernel).
Although these functions are common, there are some differences between
the functions provided in the CPRC, TCUC and DTCC PBAs. Refer to the
corresponding sections of this document for more information.
Two functional variants exist for the CPRC PBA (see the following sections):
3BK 06428 Ax
3BK 06428 Bx
CPRC PBA
SCSI for 3BK 06428 Ax
PCM
Links
* Control
Element
* External Ethernet 10BaseT for 3BK 06428 Bx
Network Communication X.25 Link

To/From Interface
DSN Kernel RS−232 Link
* Control
Element Broadcast
Broadcast Bus
Kernel
Memory Disk
External
Alarms * Control
Element Memory Disk − Code/Data Backup
Processor LEDs or
Push Button Interface
Remote Kernel − Measurements Data
Inventory Storage
*= Common Parts with other Control Element PBAs

Digital Switching Network (DSN)
Pulse Code Modulation (PCM)
Only the main functions are shown. Ancillary circuits such as the bus control, chip select logic, reset, etc., are not shown.
Figure 2: Simplified CPRC PBA Hardware Architecture
There are three main types of CPRC PBA:
SYS-CPRC
OSI-CPRC
Broadcast-CPRC.
Most of the CPRC PBA hardware is the same, irrespective of its type. The
main difference is whether a memory disk is fitted and, if so, what type (see
Memory Disk (Section 2.7)).
18 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC
2.2 CEPK
The following figure shows a simplified functional diagram of the CEPK. The
CEPK includes all the processor-related functions.
Control Element Processor Kernel
To/From Other Circuits on PBA

On−Board
Controller
On−Board
Controller
Data Buffer Peripherals Data Buffer
32−bit 32−bit
Common
DRAM/SDRAM
External − Data Storage
Alarms Control and − Code Storage
Status LEDs
Push button
Registers
Remote
Inventory
EPROM
Inventory FLASH Memory − Program
EEPROM Storage
Figure 3: CEPK Functional Diagram
2.2.1 Onboard Controller

The heart of the CPRC PBA is the Onboard Controller, which is a 32-bit
microprocessor operating at 25 MHz.
The OBC has the following integrated features:
32-bit 386DX microprocessor
Very large address range
Memory management unit.
2.2.2 OBC Peripherals

The OBC does not have any integrated peripherals (e.g., timers, interrupt
controller, etc.). Therefore, these are implemented either by discrete logic
or as part of an integrated device.
The OBC provides the following devices:
Counter/Timer
Interrupt Controllers
Bus Arbitration Logic.
3BK 21239 AAAA TQZZA Ed.04 19 / 142

2 CPRC
2.2.2.1 Counter/Timer
An integrated counter/timer provides three programmable counter/timers (0, 1
and 2). An 8 kHz signal, derived from the network frame pulse, provides the
input clock for the counter/timers.
The three programmable counter/timers are used as follows:
Counter/Timer 0 operates as an Interval Timer and System Timer. It
generates cyclic interrupts under software control, typically at 10 millisecond
(ms) intervals.
Counter/Timer 1 operates as a Watchdog Timer (or Sanity Timer)
Counter/Timer 2 operates as a Software Timer. It generates cyclic interrupts

under software control, typically at 2 ms intervals.
2.2.2.2 Interrupt Controllers

The OBC can only receive one interrupt. Therefore, all the interrupt requests
generated on the PBA are applied to two programmable interrupt controllers.
These controllers are connected in a master/slave configuration. The interrupt
controllers merge the interrupt requests on a priority basis.
2.2.2.3 Bus Arbitration Logic

The bus arbitration logic enables the OBCI (Onboard Controller Interface),
BCU (Broadcast Control Unit), SCC (Serial Communication Controller), and
the SCSI controller to operate independently of the OBC. This allows these
devices to transmit and receive data packets at their own speed, without
interrupting the OBC. When the OBC wants to access one of these devices
during a Direct Memory Access cycle, extra wait states prevent the processor
seizing control immediately.
On the TCUC and DTCC PBAs, the bus arbitration logic allows the OBCI, the
BCU and the ILC (Integrated Services Digital Network Link Controllers) to
operate independently of the OBC.
2.2.3 Common RAM

2.2.3.1 Case of 3BK 06428 Ax Variant
There are 8 Mbytes of common DRAM connected to a 32-bit data bus. The
DRAM, which is organized as four 16-bit banks, can be addressed in byte, word
or double-word mode. Byte-based parity detection is provided. Programmable
logic controls the DRAM. This logic supports OBC pipeline and interleaved
memory access.
2.2.3.2 Case of 3BK 06428 Bx Variant
There are 16 Mbytes of common SDRAM connected to a 32-bit data bus. The
SDRAM, which is organized as four 16-bit banks can be addressed in byte,
word or double-word mode. Programmable logic controls the SDRAM. This
logic supports OBC pipeline and interleaved memory access.
2.2.4 EPROM
The EPROM stores power-on and autonomous recovery firmware. It has 256
kbytes of non-volatile read-only memory organized as 128 kwords.
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2.2.5 FLASH Memory

The FLASH memory is non-volatile read/erase/write memory based on EPROM
technology. There are 512 kbytes of FLASH memory organized as a number of
16-bit banks of various sizes.
Access is as follows:
Read access to the FLASH memory can be in byte, word or double-word

mode. During an erase or program write sequence, read access is not
possible.
Write access is always in word mode. At the start of a write access, the
software disables the FLASH write protection logic.
2.2.6 Inventory EEPROM

The Inventory EEPROM stores remote inventory information.
The remote inventory information includes items such as:
PBA manufacturing information
PBA identification information
Repair information
Calibration information
PBA history information
Miscellaneous information.
Access to the Inventory EEPROM is via the inventory register (see Control and
Status Registers (Section 2.2.7)).
2.2.7 Control and Status Registers

The control and status registers comprise the:
PCR (Processor Control Register)
EPCR (Extended Processor Control Register)
TOR (Take-Over Register)

NMIR (Non Maskable Interrupt Register)
SRR (Special Reset Register)
SRC (Special Reset Command)
LTEC (Level-to-Edge Converter)

MREG (Miscellaneous Register)
INVR (Inventory Register)
ALR (Alarm Register).
The bits of the control/status registers can be Read-only, Write-only, Read/Write

or Read-only/Write-clear. Access to all the registers can be in byte, word or
double-word mode.
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2.2.7.1 Processor Control Register

The PCR is a 16-bit register that allows software control of memory and
processor-related states. Access to the register can be in 8-bit or 16-bit mode.
The following table describes the used bits of the PCR.
Bit Name Access Description
PARDIS RW Parity Disable This bit enables the testing of the DRAM and the associated parity
error detection logic. The bit inhibits the writing of the parity code during a write
access to the common DRAM. This means that for a write operation, the data field
in the memory is changed while the parity code field remains unchanged.
For a read operation from the DRAM, the parity disable bit prevents parity error
detection. The OBC reads the unchecked data field. Memory errors are not
detected and an NMI due to memory errors is not generated.
The PARDIS bit is sometimes known as the check inhibit bit.
WDXPTH RW Watchdog Timer Expired Path Select. This bit controls the function of the watchdog
timer. Depending on the state of the bit when the watchdog timer expires, either
a reset signal, or an NMI is generated. A reset signal causes the PBA circuits to
be reset.
LEDs 1 - 3 RW These bits each control one of the three LEDs mounted on the lower part of the front
edge of the PBA. The LEDs provide status indications during diagnostic tests.
LED 4 RW This bit controls a LED mounted on the upper part of the front edge of the PBA. This
maintenance bit is also known as the Prompt Maintenance Alarm bit. The software
writes this bit, which is also activated when the watchdog timer expires. When the
watchdog timer is active, the software cannot write this bit.
When the reset button is pressed, LED 4 toggles. If the button is pressed for more
than two seconds, LED 4 toggles again. This toggling is not reflected by the LED
4 bit.
BSCG RO BSC Back panel Generation. These bits define the generation of the BSC back
panel in which the PBA is used. The bits indicate the state of the BSC strapping
input on the back panel.
DSKPR RO Disk Present (not used on the TCUC and DTCC). This bit indicates whether a
Memory Disk daughter board is fitted to the PBA.
CEID RO Control Element Identity. This bit indicates the state of the back panel Control
Element identity strap. The bit is 0 for even network addresses and 1 for odd
network addresses.
Table 2: PCR Bits
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2.2.7.2 Extended Processor Control Register

The EPCR is a 16-bit register that allows software control of memory and
processor-related states. Access to the register can be in 8-bit or 16-bit mode.
The following table describes the used bits of the EPCR.
SREN RW Special Reset Enable. This bit allows the firmware or software to reset one or more
single devices. Each device must be programmed in the SRR and the reset is
initiated by writing to the SRC Register.
FWPE RW FLASH Write Protection Enable. This read/write bit enables and disables write
cycles to the FLASH memory. When the bit is 0, the write protection hardware is
enabled and the FLASH write hardware is disabled. An attempt to write to the
FLASH memory results in the generation of an NMI. When the bit is 1, the write
protection hardware is disabled and the FLASH write hardware is enabled.
FRDY RW FLASH Ready. This bit indicates the status of the FLASH memory. A 1 indicates
that the memory is ready.
REFALM RO Refresh Alarm. This bit indicates whether or not the refresh counter is operating
correctly. 1 indicates correct operation, and 0 indicates a failure of the refresh
counter.
T250US RO Time 250 microseconds (T250US). This bit, which reflects the frame pulse divided
by two, toggles every 125 [mu ]s.
RAPON RO Reset After Power On. This bit indicates whether the PBA was reset as a result of
power on (1) or for any other reason (0). The bit cannot be reset by the firmware
or software. It can only be reset by the first reset which is not due to a power-on
condition.
Table 3: EPCR Bits
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2.2.7.3 Take-Over Register

An 8-bit register controls the takeover function if the active CPRC fails. Two bits
are read/write and the other six are read-only (only three of these bits are used).
The OBC writes two status bits to the TOR via the peripheral data bus. One
status bit is the own-CPRC status; the other is the takeover test status. The
TOR signals the own-CPRC status to the other CPRC.
Each CPRC stores the status of the other CPRC.
The following table describes the used bits of the TOR.
OAVL RW Own Processor Available. This bit controls the status of its own CE processor. Only
the firmware and software can write to the bit.
PAVL RO Partner Processor Available. This bit indicates the status of the partner CE
processor. 0 indicates that the partner processor is available. 1 indicates that the
partner processor is not available, e.g., has been pulled out. A transition of this bit
from 0 to 1 indicates that the partner CE has become inactive.
TOTST RW Take-Over Test. This bit tests the takeover function.
TOINT RO Take-Over Interrupt. This indicates that the other CPRC has become inactive. In
conjunction with the takeover test bit, the bit can also test the takeover function.
PDI RO Power Down Indicator. (not used on the TCUC and DTCC). This read-only bit
indicates whether a battery backup unit is equipped, or provides power backup for
the Memory Disk daughter board type CMDA (Common Memory Disk Assembly).
The bit is not used when the CPRC is fitted in an BSC.
Table 4: TOR Bits
2.2.7.4 Take-Over Test Function

A test function checks the operation of the takeover function. The OAVL and
TOTST bits control the test function.
A takeover test can be performed with or without interrupts being generated.
Test Without Interrupt The test function performs the following actions (under
software control) for a test without interrupt activity:
Sets the TOTST bit to 1 (after a hardware reset, this bit is set to 1)
Resets the OAVL bit to 0

Checks if the TOINT bit is set to 1. The bit remains unchanged until the
OAVL bit is set to 1 again.
Test With Interrupt A takeover test with interrupt activity is similar to a test
without interrupt activity. However, when the OAVL bit is reset to 0, a maskable
take-over interrupt is generated. The interrupt controller performs masking
of the interrupt. A read of the TOR during a takeover test with interrupt
activity does not reset the takeover interrupt. This is done by setting the
OAVL bit to 1 again.
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2.2.7.5 Non-Maskable Interrupt Register

The OBC can obtain the source of an NMI by reading the 8-bit NMIR. A write
operation on the NMIR clears bits 0 to 6, allowing a new NMI to be generated.
The following table describes the used bits of the NMIR.
MMPERR RORC Main Memory Parity Error. This indicates that a parity error was detected during
a read operation on the DRAM. The bit is set to 1 (parity error) only if the parity is
enabled (see the PARDIS bit of the PCR).
This bit is not used in case of CPRC variant 3BK 06428 Bx.
WDALM RORC Watchdog Alarm. This bit is set if the watchdog timer expires and the NMI path
is enabled (see the ENNMI bit below).
DSKERR RORC Disk Error (not used on the TCUC and DTCC). This bit is set if the hardware detects
an error during a read operation on the memory disk daughter board. Errors include
parity error, backup power failure, etc. The bit can only be set when the NMI is
enabled in the memory disk registers.
DSKWPV RORC Disk Write Protection Violation (not used on the TCUC and DTCC). This bit is set if
a write protection violation of the disk memory occurs after a PBA reset.
FWPV RORC FLASH Write Protection Violation. This bit is set if a write protection violation of the
FLASH memory occurs.
UPSDN RORC Microprocessor Shutdown. The OBC sets this bit if a processor shutdown occurs.
The bit can be set together with the watchdog alarm bit.
PBNMI RORC Push button NMI. This bit indicates that the NMI was generated as a result of the
front panel push button being pressed.
ENNMI RORC Enable NMI. When a 1 is written to this bit, the NMI path is enabled. The NMI path
cannot be disabled until a PBA reset is performed.
Table 5: NMIR Bits
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2.2.7.6 Special Reset Register

The 16-bit SRR allows one or more devices to be reset without resetting the
complete PBA. The reset function has no effect on the RAPON bit of the EPCR.
The SRR programs the devices which are to be reset. A reset is triggered by
writing to the SRC.
On the CPRC, the used SRR bits are:
Special reset OBCI
Special reset SCC
Special reset DMA controllers

Special reset SCSI controller
This bit is not used in case of CPRC variant 3BK 06428 Bx.
Special reset broadcast hardware.
On the TCUC, the used SRR bits are:
Special reset OBCI

Special reset ILC0
Special reset ILC1
Special reset ILC2
Special reset Abis logic
On the DTCC, the used SRR bits are:
Special reset OBCI

Special reset ILC0
Special reset Trunk Access Circuit
Special reset Ater logic
Special reset BCLA PBA

When one of these RW bits is set to 1, a write to the SRC resets the related
device.
2.2.7.7 Special Reset Command

The SRC resets the devices programmed in the SRR. Provided the SREN bit of
the EPCR is set, a write operation to any of bits 0 to 7 resets the devices. The
value written to the bit does not matter.
Bit 0 of the register indicates whether the SRC is active or not.
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2.2.7.8 Level-To-Edge Converter

The interrupt controllers are initialized in the edge mode. The OBCI and the
BCU, however, operate in the level mode. The LTEC register generates a
special end of interrupt at the end of the OBCI and BCU interrupt routines. This
interrupt clears the level-to-edge flip-flop.
The used LTEC bits are:
LTEC for OBCI interrupt
LTEC for BCU interrupt
LTEC for ILC interrupts (only DTCC and TUCC).
Writing a one-to-one of these write-only bits clears the OBCI converter or BCU
converter flip-flop as appropriate.
2.2.7.9 Miscellaneous Register

The MREG monitors and controls various functions of the DTCC PBA. The
register is not provided on the CPRC and TCUC PBAs. The following table
describes the used bits of the MREG.
BPE RW BCLA Interface Parity Error. When set, this bit indicates that the BCLA PBA
Interface has detected a parity error. Writing a zero to the bit resets it. It can only be
reset in this way.
ATERLCA RO Ater LCA. When set, this indicates that the Ater LCA is present.
ILCSLP RW ILC Loop. If this bit is set, the outputs of the ILC are looped back to its inputs.
ELPR RO External Loop Plug Present. When this bit is set, it indicates that the trunk loop plug
is present on the back panel.
TAVL RW Trunk Available. This bit is set by the software/firmware to indicate the status of the
trunk. Setting the bit enables the extracted clock output driver.
FCLK RW Force Clock. This bit is used for test purposes. It enables the extracted clock output
driver irrespective of whether there are trunk alarms or the TAVL bit is set.
Table 6: MREG Bits
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2.2.7.10 Inventory Register

The INVR controls access to the Inventory EEPROM. The following table
describes the bits of the INVR.
SK RW EEPROM Clock Signal. This bit drives the clock signal of the Inventory EEPROM.
The firmware/software toggles the bit from 0 to 1 to enable the EEPROM clock input.
CS RW EEPROM Chip Select. This bit enables the Inventory EEPROM when it is set (1).
DI RW EEPROM Data Input. This bit enables the Inventory EEPROM data inputs.
DO RO EEPROM Data Output. This bit enables the Inventory EEPROM data outputs.
PRE RW Protected Register Enable. This bit enables the protected register when it is set (1).
IAE RO Inventory EEPROM Indication Access Enabled. This bit indicates whether the OBC
can access the Inventory EEPROM.
Table 7: INVR Bits
2.2.7.11 Alarm Register

An 8-bit read-only register stores external alarm events.
2.3 CENK
The following figure shows a simplified functional diagram of the CENK. The
CENK includes all the network related functions.
Control Element Network Kernel

On−Board
Controller
Data Buffer
16−bit
PCM On−Board Cyclic Cyclic

Links Controller OBCI SRAM Redundancy Redundancy
To/From Interface −DMA Check Check and
DSN Registers Bit−Flip
Static Random Access Memory (SRAM)
Figure 4: CENK Functional Diagram
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2.3.1 OBCI
The OBCI provides a control and transmission interface between the terminals.
2.3.1.1 Switching
The main task of the OBCI is to switch incoming channels from one port, to
outgoing channels. The outgoing channel can be on the same or another port.
The switching of ports is transparent. The OBC controls the OBCI.
The OBCI switches paths from the terminals to the OBC and vice versa.
It does this by receiving, executing and transmitting packets in a series of
commands. This sets up a link in both directions between one of the port’s
channels and the OBC. The OBCI also obtains and alters read and write
OBCI internal information.
2.3.1.2 Loopback
The loopback facility allows the OBCI to switch any incoming channel to any
outgoing channel of any port. In addition, the OBCI supports temporary links
via the command register.
2.3.1.3 Scratch Pad Memory

The RAM scratch pad memory connects the channels to each other. The
memory stores the incoming data from the input channels and writes it to
the output channels.
2.3.1.4 Commands
When commands are received, the OBCI connects its command register to
a channel. The OBCI interprets the channel contents as a command and
executes the required actions.
One-word commands initiate the OBCI tasks. The commands are assembled
into packets and usually appear in the following order:
1. OBCI select-frame command.
2. Task commands to set up or unassign a path.
3. Task commands to read or write a register.
4. OBCI deselect-frame command.
The frame commands inform the OBCI that all successive words are
commands, or terminate the work.
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2.3.1.5 Control and Status Registers

The OBCI uses numerous control and status registers to achieve these tasks.
The OBCI has four main parts:
Serial Interface Ports
Interface for the OBC

Switch
Clock and Synchronization Circuit.
Serial Interface Ports Ports 2 and 3 connect to the DSN (Digital Switching
Network) via two independently-operating duplex PCM (Pulse Code
Modulation) links.
Each PCM link operates at 4 Mbit/s and carries 32 channels. Port 4 is provided
for the auxiliary links, which connect the PBA to the OMC-R or the BSC
Terminal (only the CPRC). Each auxiliary link transmits one channel per frame
at a rate of 64 kbit/s or 128 kbit/s.
Interface for the OBC The interface is connected to port 4. This is where
the serial bit stream, to and from a channel of the OBCI, is converted into
parallel input and output.
The mechanism for transferring data between the OBCI and the OBC is based
on DMA operations. The DMA works in cycle-stealing mode. This means that
during the transfer, the OBC is put in the hold state. The OBC suspends its
normal operation and relinquishes control of the data and address bus. The
OBC acknowledges the hold. From now on, the data and address bus is under
the control of the OBCI. Memory transfer without OBC intervention is now
enabled to and from the common SRAM.
Termination of the DMA transfer is performed when the DMA controlling part
detects the End Of Packet. The OBCI generates an interrupt for the OBC. The
OBC is informed that data has been received or that output data has been
transmitted.
Up to eight DMA transfers in both directions can be made in one frame.
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Switch
The switch connects the serial ports with each other or the OBC via the OBCI.
It comprises:
A scratch pad memory
Command and status registers

A logic part.
The switch detects packets from the switch links or the OBC. It switches the
links and sends packets to the OBC or the switch.
The OBCI continuously scans all channels for a select command. When the
OBCI detects such a command, it assigns one of the five available command
registers to the incoming channel. The OBCI unassigns the command register
when it detects an unassign command.
There are six categories of OBCI commands:
Frame commands direct the packet to the right destination address

Assignment commands join and release an incoming and outgoing channel
Read/write commands read from, and write to, registers and memory
Transfer commands send data to, or receive data from, the OBC
Copy commands manipulate temporary register addresses and content
Miscellaneous commands without operation.
Clock and Synchronization Circuit

This circuit generates the timing signals for the OBCI.
2.3.2 OBCI SRAM

The 256 kbytes of SRAM are word organized. On the CPRC PBA, the OBCI
uses 64 kbytes of SRAM for DMA transfers. The SRAM is always enabled
for DMA access. The BCU shares the same memory. The firmware and
software use 192 kbytes.
On the TCUC and DTCC PBAs, the OBCI uses 64 kbytes during DMA
transfers. The ILCs use 192 kbytes during memory transfers (the BCU shares
this memory).
2.3.3 Cyclic Redundancy Check and Bit-Flip

2.3.3.1 Cyclic Redundancy Check
The Cyclic Redundancy Check circuit detects transmission errors in the
received serial data streams. To allow detection of errors, at the transmitter, the
bit stream is divided by a constant bit pattern. The CRC word is the result of the
division and is added to the data stream. When the CRC circuit receives the
data stream, it makes another CRC check. If no errors have occurred, this CRC
word is the same as that received in the bit stream. The CRC circuit stores the
CRC result in the CRC Result Register.
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2.3.3.2 Bit-Flip
The Bit-Flip circuit modifies the order of the data bits sent between the OBC
and the RAM to allow channel 16 to be used. In channel 16, bits 0 to 4 and D
of the channel word are assigned to Negative Acknowledgement data. This
means that they cannot transfer data as in the 30 other channels. The Bit-Flip
facility means that different software handling is not needed for the data on
the other channels.
During CRC and/or bit-flip operations, the Bit-Flip circuit performs byte to word,
or word to byte, format conversion.
The CRC and Bit-Flip Register controls the CRC and Bit-Flip circuits.
2.3.4 Cyclic Redundancy Check Registers

There are two CRC registers:
CBR
CRCRR.
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2.3.4.1 CRC and Bit-Flip Register

The CBR controls the CRC and bit-flip functions. The following table describes
the used bits of the CBR.
BITEN RW Bit-Flip Enable. When set to 1, this bit enables the bit-flip function.
CRCEN RW CRC Enable. When the bit-flip function is enabled, this bit is automatically set to
enable CRC generation. When the bit is set, only accesses to and from the OBCI
SRAM are affected.
IAB RW Interrupt Active Bit. When this bit is set to 1, the CRC and bit-flip functions are
suspended (if they are active). When the bit is set to 0, the CRC and bit-flip functions
are resumed (provided they were originally active when the bit was set to 1).
D_Bit RW D_Bit (NACK of channel 16). This is the NACK validation bit for channel 16. The bit
is automatically added to the word written into the OBCI SRAM when the following
conditions are met:
The BITEN or CRCEN bit is set to 1

A transmit packet is being moved from the DRAM or SRAM to the OBCI SRAM.
If these conditions are not met, and the bit is set, the OBCI SRAM operations are
not affected.
Protocol RW Protocol bits (E_bit and F_bit). These protocol bits are automatically added to the
bits word written into the SRAM when the following conditions are met:
The BITEN or CRCEN bit is set to 1

A transmit packet is being moved from the DRAM or SRAM to the OBCI SRAM.
If these conditions are not met, and the bit is set, the OBCI SRAM operations are
not affected.
PRCRC RW Preset CRC Register. A set (1) / reset (0) sequence of this bit initializes the CRCRR
for a new CRC calculation.
Table 8: CBR Bits
2.3.4.2 CRC Result Register

The 16-bit CRCRR stores the results of the CRC calculations.
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2.4 CEBK
The following figure shows a simplified functional diagram of the CEBK. The
CEBK includes all the broadcast-related functions.
Control Element Broadcast Kernel

On−board
Controller
Broadcast Bus
A B
Broadcast Control Unit
Transmit Driver
Bus A Receiver
Receive
Bus B Receiver
Figure 5: Broadcast Hardware Architecture
2.4.1 Broadcast Control Unit

The BCU is an FPCA (Field-Programmable Gate Array) chip which provides
a fast paging mechanism. It can also be used to download software and
data to the CEs of the BSC.
2.4.2 Driver and Receivers

2.4.2.1 Broadcast Bus
A driver and two receivers connect the BCU to the broadcast bus. This bus
comprises one transmit link and two receive serial links. The broadcast bus
uses a type of High Level Data Link Control protocol. This protocol is bit
oriented and code independent.
2.4.2.2 Transmit Link

On the transmit link, the BCU performs:
Flag generation
Bit stuffing
DMA under-run detection
Abort (and idle) sequence generation

CRC generation.
The transmit link is not used on the TCUC and DTCC.
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2.4.2.3 Receive Links

On the receive links, the BCU performs:
Abort (and idle) detection
Flag detection
Bit de-stuffing
CRC checking
DMA overrun detection.
Under software or hardware control, the BCU selects one of the receive links.
2.4.2.4 DMA Channels

The BCU has four receive DMA channels. The first byte of a frame contains
the station address. The BCU uses this as a pointer to a lookup table. If the
bit accessed in this table is set, the BCU accepts the frame. If the bit is not
set, the BCU discards the frame.
The BCU transfers accepted frames received on the selected link to memory
using DMA transfers. If the length of a frame exceeds a predefined threshold,
the BCU discards it. The BCU then reports a frame too long error to the
software.
The BCU has two transmit DMA channels. From a software point of view, a
transmit DMA channel is identified by:
A 20-bit byte pointer
A 16-bit message length counter.
The BCU scans both channels. When the software activates a transmit
channel, the BCU starts transmitting the message on that channel. When the
frame has been transmitted, the BCU starts to transmit the frame on the other
transmit channel (if it is active). The BCU reports under-run errors to the
software. To reduce the probability of under-run, the BCU has an 8-byte first
in-first out register.
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2.4.2.5 OBC Interface Registers

The interface with the OBC comprises a set of registers:
A Broadcast Control Register
An Event Register
A Channel Status Register
A Broadcast Bus Status Register

A Bus Quality Register
16 Station Address Registers
Eight Transmit DMA Descriptor Registers
13 Receive DMA Descriptor Registers.
All the registers are word-oriented. The BCU generates a level type interrupt
when:
A frame is transmitted
A frame is received
The Received Frame Counter or the CRC Error Counter reaches its
maximum count.
The OBC polls other error and status information.
2.5 External Communication Interface

The following figure shows a simplified functional diagram of the External
Communication Interface. This interface provides for all external communication
to the BSC, other than for telecommunication purposes.
External Communications Interface

On−Board
Controller
X.25 Interface X.25 Link

Serial
Communication
Data Buffer Controller Man−Machine RS−232
Interface Link
16−bit
SCC/SCSI SRAM Modem SCSI SCSI Link

DMA for 3BK 06428 Ax
−DMA Control
Controllers
−BC Functions Register Ethernet 10 BaseT
Ethernet
for 3BK 06428 Bx
Figure 6: External Communication Interface Functional Diagram
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2.5.1 DMA Controllers

Four devices perform DMA transfers:
OBCI
SCC
SCSI controller
BCU.
The OBCI and the BCU have built-in DMA controllers. A DMA controller is
provided for the SCC and the SCSI controller.
This controller can operate in three modes:
Single transfer
Block transfer
Demand transfer.
As shown in the following figure, the DMA controller comprises two external
DMA controllers connected in cascade. The controllers transfer data between
the SCC, SCSI controller and the SCC/SCSI SRAM.
To/From
Control Ch0 SCC A TX
Logic
Ch1 SCC A RX
DMA
Controller 1
SCSI
Ch2 Controller
Ch3 Ch0 SCC B TX
Ch1 SCC B RX
DMA
Controller 2
Ch2 Not used
Ch3 Not used
Figure 7: DMA Controllers
The DMA controllers can only handle 64 kbytes of memory. External DMA
page registers extend this range to 256 kbytes. A page register is provided for
each used DMA channel.
The SCC transmit channels have DMA request flip flops. These flip flops allow
the DMA controllers to be connected to the SCC. During DMA operations,
the hardware clears the flip flops.
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2.5.2 SCC/SCSI SRAM

The DMA controllers use this 256 kbyte SRAM to transfer data to and from
the SCC and the SCSI interface. The BCU shares the SRAM, which is word
organized.
2.5.3 SCC
The SCC provides an X.25 connection and a serial RS-232 interface for a
man-machine terminal (the BSC Terminal). The X.25 connection can be to
the OMC-R or to the BSC Terminal, depending on whether the PBA is used
as an S-CPRC or an OSI-CPRC.
The SCC is a dual channel, multi-protocol data communication controller. It
functions as a serial-to-parallel and as a parallel-to-serial converter/controller.
Two independent full-duplex channels can be programmed for use in:
Common synchronous communication
Asynchronous data communication.
2.5.3.1 Links
The two links are:
Channel A, a full duplex X.25 link with synchronous data transfer (DMA
mode) which can be used for:
Low-speed mode (9600 bit/s) using a V.28 interface
High-speed mode (64 kbit/s) using an X.21 interface
Connection to the AUX1 port of the OBCI.
Channel B, can be used for:

A full duplex MMI link with asynchronous data transfer (interrupt vector
mode)
A full duplex X.25 link (relay function) (DMA mode) connected to the
AUX2 port of the OBCI.
2.5.3.2 Interrupt Vector Mode

In the interrupt vector mode, when the SCC generates an OBC interrupt, it
also delivers a valid interrupt vector in response to two back-to-back cycles
originated by the OBC.
2.5.3.3 DMA Mode
In the DMA mode, when the SCC has data to transfer it sends a request to the
DMA controller (see DMA Controllers (Section 2.5.1)). The DMA controller
then performs the transfer. At the end of the transfer, the DMA controller
generates an interrupt.
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2.5.4 X.25 Interface

The X.25 Interface comprises a number of receivers and drivers. The X.25
Interface connects to a 25-pin female connector mounted on the front of
the PBA.
The interface can operate in the following modes:
Low-speed mode with synchronous transmission (up to 9600 bit/s)
High-speed mode according to X.21 circuits (up to 64 kbit/s).
2.5.4.1 Low-Speed Mode

In low-speed mode, a V.24/V.28 modem or a null-modem X.25 terminal can
be connected to the CPRC PBA.
2.5.4.2 High-Speed Mode
In high-speed mode, a high-speed modem using X.21 circuits can be connected
to the CPRC PBA.
2.5.5 Man-Machine Interface

The MMI comprises a number of receivers and drivers that connect the BSC
Terminal via the RS-232 interface.
The MMI connects to a 9-pin female connector on the front of the PBA.
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2.5.6 Modem Control Register

The 16-bit MCR controls and scans the status of the X.25 link and the MMI.
The lower byte relates to SCC channel A and the upper byte relates to SCC
channel B. The following table describes the used bits of the lower byte.
X.25DTR RW X.25 Data Terminal Ready (X.25DTR). This bit controls the Data Terminal Ready
signal of the DCE (Data Control Equipment). This is connected to a connector on
the front of the PBA. When a modem is connected, the signal is also known as
connect Data Set to Line Circuit.
MODCLP RW Modem Local Loopback. This bit controls the Local Loopback (loop 3) signal of the
DCE. The bit is only used in low-speed mode when a modem is equipped.
MODRML RW Modem Remote Loopback. This bit provides firmware and software compatibility
with earlier versions of the CPRC PBA. The bit is not used by the hardware, so it
has no impact on the CPRC PBA.
OBCISEL RW OBCI Select. This bit controls the SCC channel A connection so that the SCC
X.25 port is connected to:
The front connector (for connection to a modem or an X.25 terminal)

Auxiliary port 1 of the OBCI.
X.25DSR RO X.25 Data Set Ready (X.25DSR). In low-speed mode, this bit indicates the presence
of a DCE (X.25 link or modem) which is ready to operate. In high-speed mode, the
bit indicates the state of the X.25DTR signal.
MODTST RO Modem Test Indicator. In low-speed mode, this bit signals a maintenance condition.
This can be either a local loopback or a remote loopback. The signal is only effective
if a modem is equipped. The bit is not used in high-speed mode.
MMIDSR RO MMI Data Set Ready. This bit relates to SCC channel B. It is only provided for
firmware and software compatibility with earlier versions of the CPRC PBA.
X.21/V.28 RO X.21/V.28. This bit selects the X.25 front connector type/interface mode. When the
bit is 1, the X.25 Interface mode is selected. When the bit is 0, the V.28 interface
mode is selected.
Table 9: MCR Bits
The used bits of the upper byte are:
Interface Selection
MMI DSR.
2.5.6.1 I/F SEL

This RW bit controls the connection made to the B channel of the SCC. When
the bit is set to 1, the channel is connected to Auxiliary port 2 of the OBCI.
When the bit is set to 0, the channel is connected to the MMI 9-pin connector
on the front of the PBA.
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2.5.6.2 MMIDSR
This RO bit indicates the state of the Data Set Ready circuit of the MMI link.
The signal indicates that the terminal is ready to operate. If a terminal is
not connected, the bit is set to 0.
2.5.7 Interface Controller

2.5.7.1 SCSI Controller for 3BK 06428 Ax Variant
The SCSI controller allows either the:
Memory of the CPRC PBA to be extended (by external devices), or
Fast loading of the CPRC memory.
Connection to the SCSI controller is via the back panel. The controller operates
in both the target and initiator modes.
The main functions of the SCSI controller are to:
Provide an SCSI interface with a minimum DMA transfer rate of 1 Mbytes/s
Generate parity bits on the SCSI and provide optional checking of these bits
Support the bus arbitration function

Directly control the bus signals
Provide high current outputs to allow direct driving.
2.5.7.2 Ethernet Controller for 3BK 06428 Bx Variant

The Ethernet controller provides an Ethernet interface at 10 Mbps link rate.
2.6 Memory Disk Interface

The memory disk interface allows additional memory (on a daughter board)
to be added to the CPRC PBA. All the address, data and control signals are
connected to the daughter board (known as the memory disk) via this interface.
2.7 Memory Disk

There are two types of daughter board which can be added to extend the
memory of the CPRC PBA.
These are the:
CMDA, which is used on the OSI-CPRC functional variant 3BK 06428 Ax
CMFA (Common Memory Flash Disk A), which is used on the S-CPRC.
On the CPRC functional variant 3BK 06428 Bx the CMDA is integrated in

SDRAM.
The BC-CPRC does not have a memory daughter board.
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2.7.1 CMDA
The following figure shows the simplified functional diagram of the CMDA
daughter board. This provides an additional 32 Mbytes of DRAM for the
backup storage of code and data.
For the functional variant 3BK 06428 Bx the CMDA function is integrated
in onboard SDRAM.
CPRC Buses
Address
and Byte Data
Enable Control
Signals
Direction and CPRC Data
Address Tri−state Control
Latches and Transceivers
Multipexers Logic
Data Bus
CMDA
CPRC Logic Cell Parity Bus
5V (from
CPRC) Supply Array
Monitor Power Down
Indicator
DRAM Data
To other circuits Transceivers
Buffers
DRAM Control
Signals
Data and Parity

DRAM Banks
Figure 8: CMDA Simplified Functional Diagram for 3BK 06428 Ax Variant
The DRAMs are organized in eight 4-Mbyte blocks, each with an additional
parity DRAM block.
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Functions performed by the CMDA include:

Memory write in byte or word mode. This includes the generation of one or
two parity bits, if parity write is enabled. The parity bit is written into the
parity DRAM
Memory read in byte or word mode, including parity checking. If parity

checking is enabled and an error is detected, the CMDA sends an NMI
interrupt to the OBC
Write protection of the complete memory range. If an attempt is made to

write to protected memory, the write protection circuit generates an NMI
Generation of all the DRAM control signals, e.g., write enable, output
enable, etc.
Power down detection
Status monitoring
Last accessed address storage. If a write protection violation or parity error
occurs, the address of the access which caused the problem is frozen.
The address remains unchanged until all the control registers have been
read by the OBC.
The CMDA Logic Cell Array performs most of the memory control functions.
2.7.2 CMFA
The following figure shows a simplified functional diagram of the CMFA
daughter board. The CMFA provides 124 Mbytes of FLASH memory and 4
Mbytes of SRAM for the storage of measurements data. The memory is
organized as eight 16-Mbyte banks. Six of the banks have eight FLASH
devices, each with 2 Mbytes of storage. The other two banks have 2 Mbytes of
SRAM and 14 Mbytes of FLASH memory.
CPRC Buses
Transceiver Buffer
Isolation
Buffers
Control
Data Address
Logic
Data Address
Memory Banks
SRAM FLASH
(4 Mbyte) (124 Mbyte)
To other circuits Backup Supply
5V Supply Battery Lithium

(from CPRC) Supervision Battery
Figure 9: CMFA Simplified Functional Diagram
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2.7.2.1 Memory Control Logic

The memory control logic comprises two status registers and an identification
register. The status registers store the ready/busy states of the FLASH devices.
The OBC use these states to control access to the devices.
The hard-wired identification register stores the size of the disk and an
indication that it has FLASH and SRAM devices.
2.7.2.2 Battery Supervision

The battery supervision circuit constantly monitors the power supply from the
CPRC PBA. If the supply voltage decreases below 4.65 V, a lithium battery
supplies standby power to the SRAM devices. The battery is connected to
the battery supervision circuit via the back panel.
The normal output of the lithium battery is 3.6V. The supervision circuit
monitors the voltage and sets an alarm bit in a status register if it decreases to
less than 2V. This allows the OBC to generate an alarm to indicate that the
battery must be replaced.
Danger of explosion if battery is incorrectly replaced

Replace only with the same or equivalent type as recommended by the
manufacturer.
Dispose of the used batteries according to the manufacturer’s instructions.
2.8 Reset Circuit

The reset circuit resets the OBC, OBCI, BSR, MCR and PCR:
During power-up
When the supply voltage decreases below the nominal value
When the front panel push button is pressed
When an external reset is received
When the watchdog timer expires.
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2.9 Data Flow

The following figure shows the main data flow paths of the CPRC PBA.
9 pin
MMI MUX
AUX2
A
OBCI To/From DSN
X,25 B
MUX
25 pin AUX1
Cable
Ch A Ch B
OBC OBC
15 pin Memory
SCC
SCSI
Interface SCSI
for 3BK 06428 Ax
Ethernet
Ethernet
Interface
for 3BK 06428 Bx
Broadcast BCU
Interface
Figure 10: CPRC PBA - Main Data Flow Paths
2.10 O&M
This section describes the O&M facilities provided on the CPRC.
It comprises:
LEDs
Push button
Replacement.
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2.10.1 LEDs
As previously stated, there are four LEDs mounted on the front panel. The
following table describes the functions of the LEDs.
LED Description
4 Indicates a Prompt Maintenance Alarm and is lit when:
An NMI is generated
A watchdog timeout occurs
A PMA is generated.
3 Indicates a service alarm when lit.
1 and 2 When Flashing (normal condition), indicate that the OBC is

active.
Table 10: CPR LED Description
2.10.2 Push Button

The push button on the front edge of the PBA generates either a reset or an
NMI, depending on the period for which it is pressed. If the push button is
pressed for less than two seconds, a reset signal is generated. If the push
button is pressed for longer than two seconds, an NMI is generated.
When the push button is pressed, the top LED (LED 4) toggles to the opposite
state, e.g., if it was off, it is lit. After two seconds, the LED toggles again. When
the push button is released, the reset or an NMI is generated.
2.10.3 Replacement
Hot insertion circuits allow the PBA to be inserted into, or removed from, the
back panel with the power still on.
These circuits ensure that:
The hardware of the PBA is not damaged
Power drops do not occur on the other PBAs.
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2.11 Physical Description

Dimensions
Refer to Common Information (Section 1.2) .
Power Supply
The CPRC operates from a +5 V +/-5% supply.
Front Panel
The following figure shows the front panel layout.
Turn−button Turn−button
Latch Latch
LED 4 (Red)
LED 4 (Red)
Push button
Push button
RJ−45 Connector
(Ethernet)
9−pin Connector
(MMI)
9−pin Connector
(MMI)
PBA Identifying PBA Identifying
Label Label
25−pin Connector
(X.25 Interface)
25−pin Connector
(X.25 Interface)
LED 3 (Red)
LED 2 (Red)
LED 3 (Red)
LED 1 (Red) LED 2 (Red)

LED 1 (Red)
Turn−button Latch Turn−button Latch
CPRC Variant 3BK 06428 Ax CPRC Variant 3BK 06428 Bx

Figure 11: CPRC Front Panel
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3 TCUC
This section describes the hardware architecture of the TCUC PBA.
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3.1 Introduction
The following figure shows a simplified diagram of the hardware architecture of
the TCUC PBA. The CEPK, CENK and CEBK are similar to those of the CPRC.
For more information about their functions, refer to CPRC (Section 2)).
TCUC PBA
PCM
Links
* Control
Element Abis Logic Base Station
2 Mbit/s PCM Links
To/From the Base
To/From Network Cell Array Interface Buffers Station Interface and
DSN Kernel the Abis Interface
* Control
Element Broadcast
Broadcast Bus
Kernel
External
Alarms
* Control
Element Light ILC
Push Button Emitting Signalling
Processor Diodes
Remote Kernel Handling
Inventory
* = Common Parts with other Control Element PBAs

Figure 12: TCUC PBA Simplified Hardware Architecture
3.2 Abis Logic Cell Array

The following figure shows a simplified functional diagram of the Abis LCA
(Logic Cell Array).
The LCA is an FPGA which is involved in two main functions performed by
the TCUC PBA:
Termination of the signaling links

Multirate switching of the traffic channels.
Abis LCA
To/from Base Signalling Link

Station
Interface Multiplexer and Multirate Signalling Link To/from
Buffers Pulse Absence Switch Multiplexer OBCI
Detector
To on−board
loop circuit
ILC1 Base Station

Interface
Switch Registers
To/from To/from From OBC

ILC0 and ILC1
ILC2
Figure 13: Abis LCA Functional Diagram
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As shown in the figure above, the Abis LCA comprises:

An SLM (Signaling Link Multiplexer) and Pulse Absence Detector
This provides the interface with the BSI and multiplexes the signals to
the Multirate Switch and the ILCs. It also monitors the status of the links
with the BSI.
A Multirate Switch
This performs the multirate switching of the traffic channels. It also performs
frame re-timing and resynchronization of the clock signals.
An SLM
This provides the interface with the OBCI. It also multiplexes the signal from
the DSN to the Multirate switch and the ILC1 switch.
An ILC1 switch
This connects ILC1 to BSI-A, BSI-B or the DSN (via the OBCI), as required.
BSI Registers.
These allow the OBC to control the Abis LCA and monitor the operations of
the BS Interfaces.
The registers include the:
Abis Multirate Registers 0, 1 and 2
BSI Register.
The AMBR and BIR are 16-bit registers. The bits of the registers can be
read-only, read/write or read-only with clear. The registers can be written and
read together in word access, or low and high byte separately in byte access.
For more information about the bits, refer to:
Abis Multirate Register 0 (Section 3.2.1)
Abis Multirate Register 2 (Section 3.2.3)
BIR (Section 3.2.4).
3.2.1 Abis Multirate Register 0

The used bits of the ABMR0 are as follows:
Channel block 1 - quadruple-rate Traffic Channel (TCH) 0
Channel block 1 - quadruple-rate TCH 1
Channel block 3 - quadruple-rate TCH 1.
Quadruple-rate TCH
This is a read/write Channel Block n- Quadruple-rate TCH n bit that allows a 64
kbit/s TCH to be allocated to a channel block. For example, the Channel block
1 - quadruple-rate TCH 0 bit allows TCH 0 to be allocated to channel block 1.
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Channel block 1 - double-rate TCH 0


Mode select bit 0
Mode select bit 1
Submode select bit 0
Submode select bit 1
SPC (Semi-Permanent Connection) selection.
3.2.2.1 Double-rate TCH

The read/write Channel Block n - Double-rate TCH n bits allow the 32 kbit/s
TCH to be allocated to the appropriate channel block.
3.2.2.2 Mode Select

The read/write mode select bits configure the operating mode of the multirate
switch, e.g., mode 3.
3.2.2.3 Submode Select

The read/write submode select bits configure the operating mode (the
submode, e.g., 1) of the multirate switch, when mode 3 is selected.
3.2.2.4 SPC Selection
When the read/write SPC selection bit is set to 1, it enables transparent
switching of eight 64 kbit/s channels (per BSI) through the multirate switch. This
overrides other switching arrangements in the involved time slots (TSs).
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Channel block 1 - full-rate TCH 0


Channel block 2 or 3 - full-rate TCH 0

Channel block 2 or 3 - full-rate TCH 7.
Full-rate TCH The read/write full-rate TCH n bits allow a full-rate TCH to be
allocated to channel block 1.
3.2.4 BIR
The used bits of the BIR are:
ILC1 switch select bit 0
ILC1 switch select bit 1
Internal loop selection

External loop present
Pulse absence detect on frame of BSI-A
Pulse absence detect on clock of BSI-A
Pulse absence detect on frame of BSI-B
Pulse absence detect on clock of BSI-B.
3.2.4.1 ILC1 Switch Select

The read/write ILC1 switch select bits select the 2 Mbit/s link which is to be
terminated by ILC1.
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3.2.4.2 Internal Loop Selection

The read/write internal loop selection bit controls the internal looping of both
the BSIs at the same time (see BSI Buffers (Section 3.3)). In switching mode
2, signaling packets sent by ILC1 to a BSI-B can be looped back to the input
of ILC1. During loopback, the BSI receivers and drivers are set to the high
impedance state.
3.2.4.3 External Loop Present

The read-only external loop present is set when an external loop is connected
(see BSI Buffers (Section 3.3)).
3.2.4.4 Pulse Absence Detect

The pulse absence detect bits on the clock (or frame) of BSI-A (or BSI-B)
indicate the absence of either the:
4 MHz clock or
8 kHz frame signal.
The bits remain set until they are written to with a 0, provided the related
signal is no longer absent.
3.3 BSI Buffers

3.3.1 Drivers and Receivers
A number of drivers and receivers connect the PCM links to and from the BSI.
3.3.2 Internal Loopback

An internal loopback test facility tests the BSIs of the TCUC by allowing traffic
to be sent back to the OBCI and the ILCs. For example, traffic sent from the
output of the OBCI in TS0 is looped back to the input of the OBCI in the same
TS. The OBC controls the internal loopback facility via the BIR. The loopback is
performed at the inputs and outputs of the Abis LCA. In addition, the frame and
clock outputs of the OBCI are looped to the frame and clock inputs of the Abis
LCA. This means that the drivers and receivers are not tested.
3.3.3 External Loopback

A loopback plug or cable connected to the back panel in which the PBA is
inserted allows the TCUC to perform an external loopback. In this case, the BSI
cable is disconnected. The external loopback facility is the same as the internal
loopback except that it tests the BSI drivers and receivers.
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3.4 ILC Signaling Handling

Three ILCs perform handling of layer 1, and part of layer 2, of the LAPD protocol
on the signaling channels of the BSI or the DSN Interface. Each ILC terminates
two signaling channels. ILC0 and ILC2 always terminate signaling on the BSI-A.
ILC1 can terminate links on BSI-A, BSI-B or from the DSN (via the OBCI).
Each ILC has two HDLC formatters. Each formatter, which handles a serial full
duplex channel from a 2 Mbit/s PCM link, performs:
Generation of HDLC flags
Automatic zero insertion and deletion

Abort generation and detection
Generation of inter-frame fill characters
Frame check sequence.
The ILCs operate in the 2 Mbit/s mode. They can terminate either 64 kbit/s
or 16 kbit/s signaling links. If a link is terminated, the ILC sends all 1s in
the unused TSs.
When a message is to be sent to an ILC, the OBC stores it in the SRAM.
The OBC then sends an appropriate command to the ILC. The ILC gets the
message packet from the SRAM using a DMA access.
When an ILC receives a messages, it stores it in the SRAM using a DMA
access. After a complete packet has been received, the OBC can access it
in the SRAM.
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3.5 Signaling Link Termination

The following figure shows the main signaling data and control paths for
terminating the signaling links on the TCUC PBA.
Abis LCA
Multirate
SLM and PADR Switch SLM OBCI
BSI−B BSI Internal DSN
Buffers Loopback Interface
BSI−A
ILC1 BSI
Switch Registers
ILC0 ILC2 ILC1
SRAM
Signalling Data
Control Data
OBC
Alternative Paths
Figure 14: Signaling Termination Data and Control Paths
As previously stated, ILC1 can terminate two signaling links on BSI-A or BSI-B,
or on the DSN side. The ILC1 switch selects the links to be terminated. The
OBC controls this switch by writing to the BIR of the Abis LCA.
Signaling can also be switched through the multirate switch using SPCs.
An ILC receives the complete bit stream from the 2 Mbit/s link to which it is
connected. The ILC receives data in either one or two TSs of the bit stream.
The 2 Mbit/s stream from an ILC is ANDed on the appropriate 2 Mbit/s link
in the Abis LCA. An ILC can send data in one or two separate TSs of this bit
stream (the same TSs as in the receive bit stream). A 1 is transmitted in all
the other TSs.
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3.6 Multirate Traffic Channel Switching

The following figure shows the main signaling data and control paths for the
multirate traffic switching function on the TCUC PBA.
Abis LCA
Multirate
SLM and PADR Switch SLM OBCI
BSI−B BSI Internal DSN
Buffers Loopback Interface
BSI−A
BSI
Registers
Traffic Data
Control Data OBC
Alternative Paths
Figure 15: Multirate Traffic Switching - Data and Control Paths
The multirate switch performs switching of the different rate TCHs under the
control of the BSI registers. At the L port of the OBCI, each TCH is contained
in one complete TS.
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3 TCUC
3.7 Data Flow

The following figure shows the main data flow paths for the TCUC PBA.
Abis LCA
BSI−A
Multirate L port A
Switch
BSI−B
OBCI DSN Interfaces
ILC1 B
Switch
OBCI DMA
A B A B A B
ILC0 ILC2 ILC1
ILC DMA OBC

OBC
Memory
Broadcast BCU DMA

Interface BCU
Figure 16: TCUC PBA - Main Data Flow Paths
3.8 O&M
This section describes the O&M facilities provided on the TCUC.
It comprises:
LEDs
Push button
Replacement.
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3.8.1 LEDs
There are four LEDs mounted on the front panel. The following table describes
the functions of the LEDs.
LED Description
4 Indicates a Prompt Maintenance Alarm and is lit

when:
A non-maskable interrupt is generated
A PMA is generated.
1 and 2 When flashing (normal condition) indicate that the

OBC is active.
Table 11: TCUC LED Description
3.8.2 Push Button

the push button is released, a reset or an NMI is generated.
3.8.3 Replacement
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Dimensions
Refer to Common Information (Section 1.2) .
Power Supply
The TCUC operates from a +5 V +/-5% supply.
Front Panel
Turn−button
Latch
LED 4 (Red)
Push Button
PBA Identifying
Label
LED 3 (Red)
LED 2 (Red)
LED 1 (Red)
Turn−button Latch
Figure 17: TCUC Front Panel
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4 DTCC
This section describes the hardware architecture of the DTCC PBA.
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4 DTCC
4.1 Introduction
the DTCC PBA. The CEPK, CENK and CEBK are similar to those of the CPRC.
For more information about their functions, refer to CPRC (Section 2)).
DTCC PBA
PCM * Control
Element Ater Logic Trunk Access
2 Mbit/s PCM
Link To/From
Links Network Cell Array Circuit
To/From the Ater
DSN Kernel Interface
BSC Clock
To/From
Interface BCL PBA
External
Alarms * Control
Element Light
ILC * Control
Element Broadcast
Emitting Signalling
Push Button Processor Broadcast Bus
Remote Kernel Diodes Handling Kernel
Inventory
* = Common Parts with other Control Element PBAs

Figure 18: DTCC PBA Simplified Hardware Architecture
4.2 Trunk Access Circuit

4.2.1 Signal Processing
The TRAC is an LSI (Large Scale Integration) device which performs all the
signal processing functions necessary to:
Control one 2 048 kbit/s duplex PCM trunk (the Ater Interface)
Control one 4 096 kbit/s PCM link to the OBCI
Supply a regenerated clock signal for use by the BSC clock system
Perform signaling functions
Connect to an ILC to terminate signaling channels

Provide a multislot connection service.
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4.2.2 2048 kbit/s PCM Trunk Control

The TRAC performs the following functions to control the 2 048 kbit/s PCM
trunk:
Digital clock recovery, i.e., the extraction of the clock signal from the
incoming bit stream for re-timing and clock generation purposes
Conversion of the High Density Bipolar of order 3 (HDB3) or Alternate

Mark Inversion (AMI) coded signals, received on the Ater Interface, to the
binary-coded signals used in the DTCC
Conversion of binary-coded signals, used in the DTTC, to the HDB3 or

AMI-coded signals used on the Ater Interface
Frame, multiframe and CRC4 synchronization
Spare bit decoding
Generation of the Alarm Indication Signal
CRC4 generation and monitoring

Re-timing to allow for frequency differences, jitter and wander
Alarm monitoring for transmission errors as follows:

Loss of Signal
Loss of Frame Alignment
RAI (Remote Alarm Indication (A-Alarm))
AIS (Alarm Indication Signal)
Loss of Multiframe Alignment
Remote Signaling Alarm
Slip
Loss of CRC4 Alignment
Auxiliary Pattern.
Error counting for CRC4, Channel 0 (CH0), and HDB3
Channel Associated Signaling extraction and insertion
Insertion of a fixed pattern into idle channels
Automatic A-bit generation

Automatic E-bit insertion.
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4 DTCC
4.2.3 4096 kbit/s PCM Link Control

The TRAC performs the following functions to control the 4 096 kbit/s PCM
link to the OBCI:
PCM link synchronization

Conversion from the 2.048 Mbit/s 8-bit signals received on the Ater Interface
to the 4.096 Mbit/s 16-bit format used in the BSC
Conversion from the 4.096 Mbit/s 16-bit signals received from the OBCI to
the 2.048 Mbit/s 8-bit format used on the Ater Interface
Insertion of frame count bits for multislot connection service.
4.2.4 Clock Functions

The TRAC supplies the BSC clock system with:
The extracted (regenerated) 2.048 MHz clock signal for possible use in the
generation of the BSC system clock
An Alarm To Clock qualifying signal.
4.2.5 OBC Control

The OBC controls some functions by writing to, and reading from, the TRAC
internal registers and RAM.
4.2.6 Diagnostic Test Functions

For diagnostic test purposes, the TRAC can perform two loop tests:
An inner loop, which loops back the transmit bit stream to the received
bit stream
An outer loop, which loops back the AIS bit stream into the receive bit
stream.
The OBC control the loops by writing to the TRAC command register.
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4 DTCC
4.3 ILC Signaling Handling

The ILC terminates two signaling channels mapped into any TS of the Ater
Interface (except TS0). The following figure shows a simplified functional
diagram of the signaling link handling.
Ater TRAC Ater LCA

Interface
Signalling Data ILC

Control Data OBCI
SRAM
OBC
Figure 19: Signaling Link Handling - Data and Control Paths
4.3.1 HDLC Formatters

The ILC, which has two HDLC formatters, is configured in the 2 Mbit/s mode.
Each formatter handles a serial full duplex channel from a 2 Mbit/s PCM
link and performs:
Generation of HDLC flags

Automatic zero insertion and deletion
Abort generation and detection
Generation of inter-frame fill characters
Frame check sequence.
4.3.2 Signaling Link Speeds

The ILC can terminate either 64 kbit/s or 16 kbit/s signaling links. If a 16 kbit/s
link is terminated, the ILC sends all 1s in the unused TSs.
4.3.3 Transmit Messages

The OBC places messages to be sent to the ILC in the OBCI SRAM. It then
sends an appropriate command to the ILC. The ILC gets the message packet
from the SRAM using a DMA access.
4.3.4 Receive Messages

The ILC places received messages in the SRAM using a DMA access. After a
complete packet has been received, the OBC can access it in the SRAM.
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4 DTCC
4.4 Ater Logic Cell Array

The following figure shows a simplified functional diagram of the Ater LCA. The
LCA is an FPGA which performs switching of the traffic channels.
As shown in the following figure, the Ater LCA comprises:
A Multirate Switch, which performs the switching of the traffic channels and
provides frame re-timing and resynchronization of the clock signals
ATMRs (Ater Multirate Registers) 0, 1 and 2, which allow the OBC to

control the Ater LCA.
Ater LCA
4 Mbit/s TRAC 4 Mbit/s OBCI OBCI

Interface Interface
2 Mbit/s Ater Multirate 4 Mbit/s DSN
Interface TRAC Interface
Switch
Ater Multirate
Registers
From OBC
Figure 20: Ater LCA Functional Diagram
The ATMRs are 16-bit registers, the bits of which are all read/write. Write and
read access to the registers is by word access or byte access (with separate
low and high byte access). Ater Multirate Register 0 (Section 4.4.1) to Ater
Multirate Register 2 (Section 4.4.3) describe the bits.
4.4.1 Ater Multirate Register 0

The used bits of the ATMR0 are as follows:

Channel block 2 - quadruple-rate TCH 1.
Quadruple-rate TCH These bits allocate the 64 kbit/s TCH to the appropriate
channel block. The bits are only used in switching mode 1.
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Mode select bit.
Double-rate TCH
The channel block n - double-rate TCH n bits allocate the 32 kbit/s TCH to
the appropriate channel block. The channel block n - double-rate TCH n bits
are only used in switching mode 1.
Mode Select
The mode select bit configures the operating mode of the multirate switch, i.e.,
mode0 or mode1. In mode0, the multirate switch operates transparently.
In mode1, the multirate switch operates according to the channel block n
- double-rate TCH n bits.
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4 DTCC




Channel block 2 - full-rate TCH 7.
Full-rate TCHs These bits allocate a full-rate TCH to channel block 1 or 2. If

this bit is zero, two bits of channel 1 are used for separate half-rate TCHs. The
channel block n - full-rate TCH n bits are only used in switching mode1.
4.5 BSC Clock A Interface

The BSC Clock A Interface allows communication between the DTCC PBA and
a BCLA PBA for control purposes. This interface is an address-data multiplexed
8-bit parallel bus. It performs parity checks on the data signals. In addition to the
data signals, there are four control signals, an error signal and a parity signal.
A set of registers on the BCLA PBA allows the DTCC to control this PBA. When
the software on the DTCC PBA accesses one of the registers, the interface
sequence is started. Only a reset of the DTCC PBA can interrupt this sequence.
If a parity error occurs, the interface generates an interrupt and the BPE bit is set
in the MREG. A new interrupt can only be generated if the bit has been cleared.
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4.6 Signaling Link Termination

The ILC can terminate two signaling links on any TS of the Ater Interface
(except TS0).
The ILC receives the complete bit stream from the 2 Mbit/s link to which it is
connected. The ICL receives data in either one or two TSs of the bit stream.
The 2 Mbit/s stream from an ILC is ANDed on the appropriate 2 Mbit/s link in the
TRAC. An ILC can send data in one or two separate TSs of this bit stream (the
same TSs as in the receive bit stream). A 1 is transmitted in all the other TSs.
4.7 Multirate Traffic Channel Switching

The following figure shows the main signaling data and control paths for the
traffic switching function on the DTCC PBA.
Ater LCA
Multirate 4 Mbit/s DSN

Ater−Interface TRAC OBCI
Switch Interface
Ater Interface
Registers
Traffic Data
OBC
Control Data
Figure 21: Multirate Traffic Switching - Data and Control Paths
The multirate switch performs switching of the different rate TCHs under the
control of the BSI registers. At the L port of the OBCI, each TCH is contained
in one complete TS.
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4 DTCC
4.8 Data Flow

The following figure shows the main data flow path for the DTCC PBA.
TRAC
2 MHz Ater
G.703 Ater A
Interface Interface LCA L port
OBCI DSN Interface
Test Loop
OBCI DMA
A B
ILC DMA OBC OBC
Memory
ILC
Broadcast BCU DMA

BCU
Interface
Figure 22: DTCC PBA - Main Data Flow Paths
4.9 O&M
This section describes the O&M facilities provided on the DTCC.
It comprises:
LEDs
Push Button
Replacement.
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4 DTCC
4.9.1 LEDs
As previously stated, there are four LEDs mounted on the front panel. The
following table describes the functions of the LEDs.
LED Description
4 Indicates a Prompt Maintenance Alarm, and is lit when:

A PMA is generated.
1 and 2 When flashing (normal condition) indicate that the OBC is active.
Table 12: DTCC LED Description
4.9.2 Push Button

the push button is released, the reset or an NMI is generated.
4.9.3 Replacement
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4 DTCC

Dimensions
Refer to Common Information (Section 1.2).
Power Supply
The DTCC operates from a +5 V +/-5% supply.
Front Panel
Turn−button
Latch
LED 4 (Red)
Push Button
PBA Identifying
Label
LED 3 (Red)
LED 2 (Red)
LED 1 (Red)
Turn−button Latch
Figure 23: DTCC Front Panel
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5 SWCH
5 SWCH
This section describes the hardware architecture of the SWCH PBA.
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5 SWCH
5.1 Introduction
5.1.1 Functions
The SWCH PBA performs the following functions:
Terminates 16 asynchronous, serial 32-channel PCM duplex transmission

links. Each port terminates one PCM link
Synchronizes the received serial bit streams to its own time reference
Stores the current status of each of the 32 channels for each PCM link
Analyzes the protocol bits in each channel and the current status of the
channel. This provides information about the type of data the channel
contains, e.g., a speech sample
Sets up, maintains and releases simplex connections between the input
channels and the output channels connected to the PBA. This is in
accordance with commands received in the channels of the PCM links
Diagnoses internal malfunctions
Minimizes transmission delays for connections through the DSN by

assigning the first channel available on the chosen output PCM link.
5.1.2 Variants
There are two variants of the SWCH PBA, depending on whether the PBA is
used as an Access Switch or as a Group Switch. Unbalanced signals are used
to connect the CEs to the ASs. Balanced signals are used for connections
between the ASs and the GSs, and between the GSs. Figure 24 shows the AS
variant, which has unbalanced signals connected to ports 0 to 7. Figure 25
shows the GS variant, which has balanced signals connected to all its ports.
Both variants perform the same basic functions:
5.1.3 Functional Areas

The SWCH PBA comprises the following functional areas:
SWEL (Switching Element)

Serial Line Receivers and Line Drivers
Clock Input Circuit
VCO (Voltage Controlled Oscillator) Circuit
Power-on Reset Circuit

Hot Replacement Protection (not shown in the figures)
Odd or Even Port Interchange (SWAP)
Clock Buffers and Frame Delay Circuit (only AS variant).
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5 SWCH
Line Receivers and Line Drivers Line Receivers and

4 MHz0 SWEL Line Drivers
FRAME0
TX0 TX8
Port 0 Port 8
RX0 RX8
4 MHz1
FRAME1
TX1 TX9
Port 1 Port 9
RX1 RX9
4 MHz2
FRAME2
TX2 TXA
Port 2 Port A
RX2 RXA
4 MHz3
FRAME3
TX3 TXB
Port 3 Port B
RX3 RXB
To/From To/From Associated
Associated CE 4 MHz4 Switching Stage
FRAME4
TX4 TXC
Port 4 Port C
RX4 RXC
4 MHz5
FRAME5
TX5 TXD
Port 5 Port D
RX5 RXD
4 MHz6
FRAME6
TX6 TXE
Port 6 Port E
RX6 RXE
4 MHz7
FRAME7
TX7 TXF
Port 7 Port F
RX7 RXF
Clock Input
Circuit Power−On
Reset Circuit
From Clock Clock A

and Alarm Clock Clock
System Clock Buffers
Frame and Frame Frame
Clock B Delay Circuit
Phase−locked
Down Up Loop Control
1 Voltage Controlled
Odd or Even Port Interchange Signal Oscillator Circuit
(SWAP) from the backpanel
Figure 24: Switch PBA, AS Variant Functional Diagram
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5 SWCH
Line Receivers and Line Receivers and

Line Drivers Line Drivers
SWEL
TX0 TX8
Port 0 Port 8
RX0 RX8
TX1 TX9
Port 1 Port 9
RX1 RX9
TX2 TXA
Port 2 Port A
RX2 RXA
TX3 TXB
Port 3 Port B
RX3 RXB
To/From Associated To/From Associated
Switching Stage Switching Stage
TX4 TXC
Port 4 Port C
RX4
RXC
TX5 TXD
Port 5 Port D
RX5 RXD
TX6 TXE
Port 6 Port E
RX6 RXE
TX7 TXF
Port 7 Port F
RX7 RXF
Clock Input
Circuit Power−On
Reset Circuit
Clock A
From Clock and
Alarm System FRAMET
1
Clock B
Down Up Phase−locked
Loop Control
1
Odd or Even Port Interchange Signal Voltage Controlled
(SWAP) from the backpanel Oscillator Circuit
Figure 25: Switch PBA, GS Variant Functional Diagram
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5 SWCH
5.2 Switching Element

The SWEL performs the following main functions:
Switching
Clock Selection
PLL (Phase-locked Loop) Control
Odd or Even Port Interchange (SWAP) mechanism.
Note: The 16 duplex ports in a SWEL are indicated hexadecimally. Ports 8, 9, A and
B are sometimes called low-numbered ports. Similarly ports C, D, E and F are
sometimes called high-numbered ports.
5.2.1 Switching Function

The SWEL performs time-space switching between 16 incoming, 32-channel
PCM links and 16 outgoing, 32-channel PCM links. This allows any channel
(time) of any incoming PCM link (space), to be connected any channel
(time) of any outgoing PCM link (space). The SWEL is therefore a combined
time-space-time switch.
The SWEL uses its own path search and path map mechanisms to establish
the connections.
These internal functions include:
Transferring the incoming data to the required outgoing link and channel
Temporarily storing the incoming PCM channel words.
The SWEL performs the following operations to set up paths between the
PCM links:
1. The receiver of each port synchronizes its incoming serial PCM bit stream to
the SWEL internal time reference.
2. The receivers store the current status of each of the 32 channels for the
connected PCM link.
3. The receivers analyze the protocol information in each channel word and the
current status of the channel. This analysis determines the type of data
contained in the channel, e.g., a Path Select Word or SPATA.
4. Each receiver uses the channel words to set up, maintain and release
simplex connections between any channel of the receiver to any transmitter.
5. The transmitter assigns the first free channel available on the chosen
output PCM link.
5.2.2 Clock Selection

When power is applied to the PBA, the SWEL randomly selects one of the two
8.192 MHz clock signals. These signals are received from the Clock and Alarm
System via the Clock Input Circuit (see Clock Input Circuit (Section 5.4) ).
If the selected clock continues as an uninterrupted pulse train, the selection
is maintained. If, however, the selected clock pulses are absent, the other
clock is selected.
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5 SWCH
5.2.3 Phase-locked Loop Control

The SWEL, in conjunction with the external VCO circuit (see Voltage-controlled
Oscillator Circuit (Section 5.5) ), forms a Phase-locked Loop circuit. The PLL
circuit provides a continuous internal clock signal. This signal is phase and
frequency synchronous with the selected 8.192 MHz source clock. If the
selected source clock fails, the source clock is reselected. During this source
clock reselection, the clock signal produced by the PLL circuit remains stable.
5.3 Serial Line Receivers and Line Drivers

The Serial Line Receivers and Line Drivers match the impedance and line
characteristics for the 16 duplex PCM links. They also isolate the switch ports
from the external network connections.
Balanced Lines
In the GS variant, all the incoming PCM signals are fed over balanced lines.
Line receivers convert the balanced signals to unbalanced (single-ended)
signals before applying them to the SWEL.
Line drivers convert the unbalanced outputs from the SWEL into balanced
signals before applying them to balanced lines.
Unbalanced Lines
In the AS variant, eight of the incoming PCM signals (Ports 0 to 7) are fed over
unbalanced lines. All 16 of the signals are applied to identical line receivers.
Different resistor terminations are used for the balanced and unbalanced
signals.
Eight of the outputs from the SWEL are fed to Ports 0 to 7 as unbalanced
signals. Ports 0 to 7 use different line drivers from those used by the other ports.
5.4 Clock Input Circuit

The clock input circuit receives two external, balanced-line 8.192 MHz clock
signals, from the Clock and Alarm System. It converts the balanced signals into
unbalanced signals for the SWEL.
5.5 Voltage-controlled Oscillator Circuit

The VCO circuit forms part of a PLL circuit (the other parts are in the SWEL).
The VCO circuit provides a continuous clock signal that is phase and frequency
synchronized with the selected 8.192 MHz clock.
5.6 Power-on Reset Circuit

A power-on reset circuit performs an initialization sequence when the SWCH
PBA is inserted into the back panel. This sequence ensures that the PBA is
initialized before it handles traffic.
5.7 Clock Buffers and Frame Delay Circuit

The clock buffers and frame delay circuit use the clock and frame signals from
the SWEL to provide for the timing requirements of the CEs.
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5 SWCH
5.8 O&M
The only O&M facility provided on the SWCH is hot replacement. Hot insertion
circuits allow the PBA to be inserted into, or removed from, the back panel
with the power still on.

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5 SWCH

Dimensions
Power Supply
The SWCH operates from a +5 V +/-5% supply.
Front Panel
Turn−button
Latch
PBA Identifying
Label
Turn−button
Latch
Figure 26: SWCH Front Panel
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6 BCLA
6 BCLA
This section describes the BCLA PBA.
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6 BCLA
6.1 Introduction
There are two variants of the BCLA PBA:
System-BCLA (only in the first cabinet). It provides the Clock Generation

and Distribution Function at the system level
Rack-BCLA (in all cabinets). It distributes the clock signal in the associated
cabinet.
The BCLA PBA performs the following main functions:
Clock Generation
Broadcast Bus Distribution

DTC Interface
Remote Inventory
External Alarm Scanning and Driving (SYS-BCLA only)
LEDs.
The following figures respectively show the functional diagrams of the

SYS-BCLA and RACK-BCLA variants.
Clock Signals from DTCs
1 2 3 Broadcast Bus
Clock
Generation
Local Clock
Status Outputs Buffer
Reference Selector
Control Inputs
Status Outputs PLL

Distribution
(16 MHz) To Partner SYS−BCLA

From Partner SYS−BCLA
1 2 6
Status Outputs Status Information from
Partner Broadcast Bus
Master Selector
Control Inputs
Status Information to
Partner
DTC
Interface
(8 MHz)
Distribution 10 Input
External Alarms
Alarms Remote
I/O 6 Output Inventory
(8 MHz) Alarms Information
1 2 3 11 12
System Clock to RACK−BCLA
Figure 27: SYS-BCLA Functional Block Diagram
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6 BCLA
System Clocks from SYS−BCLA

Broadcast Bus
A 3
Clock regeneration
Buffer
Status Outputs
Reference Selector
Control Inputs
Distribution
Status Outputs PLL
Status Information from 1 2 n

Output Clock Partner RACK−BCLA Broadcast Bus
Disable n = maximum of 10)
Status Information to
Partner RACK−BCLA
DTC
Interface
Distribution
Remote
Inventory
(8 MHz) Information
1 2 3 12 13
Distributed Rack Clock
Figure 28: RACK-BCLA Functional Block Diagram
6.2 Clock Generation

The Clock Generation function comprises:
Reference Selector
PLL
Master Selector (SYS-BCLA only)
Output Clock Disable (RACK-BCLA only).
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6 BCLA
6.2.1 Reference Selector

6.2.1.1 SYS-BCLA
The reference selector selects one of the input (2 MHz) clocks as the reference
clock for the PLL. The input clocks are:
Three medium-priority clocks from Ater incoming trunks, i.e., from DTC
PBAs
A low-priority local clock derived from an onboard oscillator.
The local clock is used:
For test purposes

During worst case conditions (i.e., the Ater trunks are not working correctly)
During startup and reset.
During normal operations, the onboard logic/micro-controller selects an

appropriate clock as the reference. In Test mode, control bits from the DTC
control register select the reference clock used.
6.2.1.2 RACK-BCLA
The reference selector selects an 8 MHz clock from the input clocks (clock A or
clock B), as the reference for the regeneration PLL.
During normal operations, the onboard logic/micro-controller selects an
appropriate clock as the reference. In Test mode, control bits from the DTC
control register select the reference clock used.
6.2.2 Phase-locked Loop

6.2.2.1 SYS-BCLA
The PLL generates a jitter-free and wander-free clock signal using the selected
reference signal. In addition, it filters out any phase gaps caused if the selected
reference clock at the input of the PLL is switched.
6.2.2.2 RACK-BCLA
The PLL regenerates the 8 MHz clock using the clock from one of the
SYS-BCLA PBAs. This regenerated clock has a duty-cycle of approximately
50%.
6.2.3 Master Selector

Although two SYS-BCLA PBAs are used to provide redundancy of the system
clock, only the clock generated by one of them is distributed in the BSC.
Both the SYS-BCLA PBAs exchange their clocks and status with each other.
The onboard micro-controller compares the status of its own PBA with that of
the partner BCLA. It then ensures, if both PBAs are operating correctly, that
a clock is selected and distributed.
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6 BCLA
6.2.4 Output Clock Disable

On the RACK-BCLA PBA, this function disables the distribution of the clock
by the PBA if both the following conditions apply:
Its own PLL is not operating within the control range

The PLL on the partner PBA is operating correctly.
This is the only time when the output clock is disabled.
6.3 Clock Distribution

6.3.1 SYS-BCLA
Drivers distribute the 8 MHz clock to the RACK-BCLA PBAs in the different
cabinets. There are 12 separate outputs, each of which can distribute the clock
to the RACK-BCLA PBAs.
6.3.2 RACK-BCLA
On the RACK-BCLA PBA, drivers distribute the 8 MHz clocks to the users in the
cabinet (GS Elements, AS Pairs). It also distributes the clocks to other users
such as BIUA PBAs. A maximum of 13 separate outputs are provided.
6.4 Broadcast Bus Distribution

Each BCLA PBA receives and distributes one broadcast bus, either A or B,
depending on its position in the system. The broadcast bus is not duplicated.
6.4.1 SYS-BCLA
There are six drivers on the SYS-BCLA PBA. Each driver distributes the
broadcast bus to one RACK-BCLA PBA.
6.4.2 RACK-BCLA
There are ten drivers on the RACK-BCLA PBA. Each driver distributes the
broadcast bus to a maximum of eight CEs.
6.5 Remote Inventory Register

The RINVR stores inventory information. This register can be read by the
DTCC which controls the BCLA PBA.
When the power is off, a back panel interface can provide access to the
inventory information.
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6 BCLA
6.6 DTCC Interface

This parallel bi-directional interface allows a controlling DTCC to access the
control inputs and the status outputs of the BCLA PBA.
6.6.1 Clock Control Status Registers

Access is by reading from and writing to a number of registers, the CCSRs.
6.6.2 Alarm Registers

External input alarms are read via two Alarm Input Registers. External output
alarms are written to an Alarm Output Register.
The RINVR transfers inventory commands and information between the DTCC
and the BCLA.
All the CCSRs and RINVR are implemented in the memory of the onboard
micro-controller. Access to these registers is relatively slow, since they have an
access time of approximately 10 micro-seconds.
6.6.3 Status Change Register

The ST-CHNG-R provides fast access to allow changes in the status of the
BCLA PBA to be detected quickly. After the register is read, detailed information
about the current status of the PBA is then obtained by reading the CCSRs.
The Alarm Input Registers and the ST-CHNG-R are fast accessible registers,
with an access time of a less than one micro-second. These registers are read
by the DTCC software to monitor the BCLA PBA.
6.7 External Alarm Scanning and Driving

This function is only provided on the SYS-BCLA PBA.
6.7.1 Alarm Inputs

All the input alarm signals are written into the CCSRs where the DTCC can
read them.
6.7.2 Alarm Outputs

All the alarm outputs are written to a Control Register by the DTCC.
6.8 O&M
This section describes the O&M facilities provided on the BCLA.
It comprises:
LEDs
Push Button
Replacement.
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6 BCLA
6.8.1 LEDs
6.8.1.1 SYS-BCLA
Five LEDs are provided on the SYS-BCLA PBA.
The functions of the LEDs are as follows:
LED 1, LED 2 and LED 3 indicate which clock is selected on the BCLA (1 = on,
0 = off) as follows:
LED 1 LED 2 LED 3 Reference clock
0 0 0 No reference
0 0 1 Local
1 0 0 Ater 1
1 0 1 Ater 2
1 1 0 Ater 3
Table 13: DTCC LED Description
LED 4 is:
Off in normal conditions
On in the case of an error (PLL out of range, broadcast bus failure, etc.)
Flashing (see following table).
LED 5 indicates the status of the master selector and is:

On when the BCLA uses one of its own reference(s) for clock distribution
Off when the BCLA uses a reference from the partner BCLA.
Flashing rate Meaning Explanation
1s On/1s Off Power-on The PBA is initialized and a time out is started to get the PLL locked on
to the local oscillator.
150ms On/150ms Error The PLL locked on time out has expired. Either the PLL Out of Range
Off after (POOR) still exists or a reference failure has been detected. The PBA
power-on does not start the normal function and waits until the POOR and, or, the
reference failure clears. Normally, the PBA must be repaired.
300ms On/300ms Test The PBA is in Test Mode.

Off Mode
600ms On/600ms Local The PBA is forced to the local oscillator state by means of a plug on
Off (SYS-BCLA Oscillator the back panel.
only)
Table 14: BCLA PBA - LED 4 Flashing Indications
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6 BCLA
6.8.1.2 RACK-BCLA
Three LEDs are provided on RACK-BCLA:
LED 1 is On if System Clock A is selected
LED 2 is On if System Clock B is selected
LED 3 is not equipped
LED 4 is:
Off in normal conditions
On in case of an error (PLL out of range, broadcast bus failure, etc.)
Flashing (see the table below).
LED 5 is not equipped.
6.8.2 Replacement
back panel with the power still applied.
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6 BCLA

Dimensions
Power Supply
The BCL operates from the following supplies:
+5 V +/-5%
+12 V +/-5%
-12 V +/-5%
Front Panel
Turn−button
Latch
LED 4
(Red)
LED 5
(Red)
Push Button
PBA Identifying
Label
LED 3
(Red)
LED 2
(Red)
LED 1
(Red)
Turn−button
Latch
Figure 29: BCLA Front Panel
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6 BCLA
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7 DC/DC Converter
7 DC/DC Converter
This section describes the DC/DC converter used in the BSC.
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7 DC/DC Converter
7.1 Introduction
The DC/DC converter is a switching type. It has a separate output transformer
for each supply it generates. Each transformer drive circuit uses a common
160 kHz oscillator. This provides two phases of output drive, each at 80 kHz.
Full DC isolation between the input and output is provided. All the output
voltages are independently regulated and protected against out-of-tolerance
voltages and currents.
7.1.1 Output Diodes

All the outputs have diodes that allow the converters to operate in the N + 1
configuration. This means that each output is doubled and separated by the
diodes. The outputs are called A and B.
7.1.2 Modes of Operation

The converter has two modes of operation:
Run, in which it is operating correctly and all the output voltages are within
the specified ranges.
Alarm, in which an overvoltage or undervoltage has occurred on one or

more of the outputs and the converter has shut off. The converter cannot be
restarted from alarm mode unless the input supply is interrupted.
7.1.3 Automatic Start

The converter automatically starts when the input voltage reaches 38.4 V.
7.2 Characteristics
This section describes the electrical characteristics of the DC/DC Converter.
7.2.1 Input Characteristics

The DC/DC Converter meets all the output requirements specified in Output
Characteristics (Section 7.2.2) for the input voltage conditions specified
in this section.
7.2.1.1 Static Input Voltage

The input voltage range is 34.4 V DC to 74 V DC.
At input voltages below the above-specified minimum, regulation may not be
provided but the unit will not be damaged.
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7.2.1.2 Transient Variations

The input can rise to 80 V for one second at a maximum rate of 10 V/ms,
starting from any voltage within the static input range.
The input voltage can change by up to +/-8 V within the static input range
at a maximum range of 50 V/ms. The output(s) must stay within the static
regulation limits.
The input is protected against a surge wave with a peak of 150 V and a pulse
shape of 0.3/0.6[thinsp]ms.
The input voltage can drop from the maximum to zero for 100[thinsp]ms, and
then increase to the maximum at a rate of 50 V/ms +/-20%. During the voltage
drop, the unit must stay in RUN-mode and the output(s) must stay within
the static regulation limits.
7.2.1.3 Electrical Noise Feedback to Source

Within the frequency range 160[thinsp]Hz to 5[thinsp]kHz, noise must not
exceed the psophometric value A-filter weighted at 0.1 mV rms.
7.2.2 Output Characteristics

This section describes the output voltage and current characteristics of the
DC/DC Converter.
7.2.2.1 Output Current

The outputs can continuously provide the maximum current at the A and B
output, or a combination of both, as listed in the following table.
Output Voltage Maximum Current
+5 V 22 A
+5 VM 1A
+12 V 0.6 A
-12 V 0.1 A
Table 15: Maximum Output Currents
7.2.2.2 Output Power

The maximum output power is 120 W.
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7.2.2.3 Static Regulation

The following table lists the static regulation parameters.
With no load on any of the outputs, none of the outputs must:
Exceed the overvoltage limit
Decrease below the undervoltage limit.
Output Output Voltage Range Load Current Range
+5 V 4.97 V - 5.25 V 1 A - 22 A
+5 VM 4.99 V - 5.25 V 0.05 A - 1 A
+12 V 11.76 V - 12.36 V 0.05 A - 0.6 A
-12 V 11.76 V - 12.36 V 0.002 A - 0.1 A
Table 16: Static Regulation Parameters
7.2.2.4 Dynamic Load Regulation

For dynamic load changes of up to 50% of the full load, in 100 ms:
The percentage change of the original static output voltage must not exceed
0.15[thinsp] times the percentage load change
The output must return to the static regulation limits within 5[thinsp]ms.
This means, for example, that if a 20% change occurs in the load, the voltage
must not change by more than 3%.
7.2.2.5 Dynamic Load Interaction

The percentage deviation for any one output must be less than 0.05[thinsp]times
the percentage load change on any other output. The output must return to
the static regulation limits within 5 [thinsp]ms. For a 20% load change on one
output, the other outputs must not deviate by more than 1%. The load change
must be 50% of the full load within the specified load range in 100[thinsp]ms.
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7.2.2.6 Ripple and Noise

The output ripple and noise peak in the frequency range DC to 20[thinsp]MHz
must not exceed the values given in the following table. The values apply to all
load conditions between the minimum and maximum.
Output Output Ripple and Noise Peak
+5 V/+ 5 VM 50 mV
+12 V/- 12 V 120 mV
Table 17: Output Ripple and Noise Peak
7.2.2.7 Output Voltage Rise Time

The rise time of the +5 V output must be less than 50[thinsp]ms (from 10% to
90%) with an input of 50[thinsp]V.
7.3 Voltage and Current Protection

The DC/DC Converter provides both input and output protection.
7.3.1 Input Protection

The input protection features of the DC/DC Converter are as follows:
An internal 10 A fuse protects the input circuit from over-current

Diodes provide protection against accidental reversal of the input voltage
The inrush current during the application of power is limited to 1.5 A for
between 100 [mu ]s and 100 ms.
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7.3.2 Output Protection

Output over-current protection is as follows:
All the outputs are protected if a short-circuit is applied to the output

terminals
The output current with a short-circuit applied does not exceed the limits
specified in the following table
The converter is not damaged if continuous overloads or short-circuits

occur on any or all the outputs. The undervoltage shutdown circuit can set
the converter to the alarm mode.
All the outputs return to normal when an overload or short-circuit is removed,

provided the converter is not in the alarm mode.
Output Maximum Current
+5 V < 37.5 A, with all other outputs at zero

> 25 A, with all other outputs at full load
+5 VM 2.9 A
+12 V 2.9 A
-12 V 2.9 A
Table 18: Maximum Output Current - Short-Circuit Applied
Each output has undervoltage and overvoltage protection. If the voltage drifts
beyond the limits shown below, the undervoltage or overvoltage supervision
circuits operate.
The overvoltage trip range for each voltage is as follows:
+5 V, +5.5 V to +6 V
+5 VM, +5.5 V to +6 V
+12 V, +13.0 V to +13.8 V
-12 V, -13.0 V to -13.8 V.
The undervoltage trip range for each voltage is as follows:

+5 V, +4.175 V to +4.450 V
+5 VM, +4.175 V to +4.450 V
+12 V, +10.125 V to +10.750 V
-12 V, -10.125 V to -10.750 V.
If an output voltage decreases below the undervoltage set point for more than 1
s, the converter switches to the alarm mode. If the voltage remains low for less
than 500 ms, the converter remains in the run mode.
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7.4 O&M
The only O&M facilities provided on the DC/DC Converter are the LEDs.
There are two LEDs mounted on the front panel. The following table describes
LED Description
Green (RUN) Indicates that the converter outputs are present

and within the normal limits.
Red (ALARM) Indicates that one or more of the converter outputs

are not within the preset limits. All the outputs are
inhibited and an external alarm signal is activated.
Table 19: DC/DC Converter LED Description
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Dimensions
Power Supply
Refer to Input Characteristics (Section 7.2.1).
Front Panel
Turn−button
Latch Hot to Touch
Warning
Label
LED
(Red)
LED
(Green)
Turn−button Identifying
Latch Label
Figure 30: DC/DC Converter Front Panel
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8 ASMB
This section describes the hardware architecture of the ASMB PBA.
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8.1 Introduction
of the ASMB PBA.
Switch
Ater 1 Ater Clock
Sub−rate Circuits
Interface
Switch 1
Ater 2 Ater
Interface Remote
Qmux Qmux
Interface
Sub−rate
Ater 3 Switch 2
Ater
Interface
Ater 4 Ater TS0 Logic

Interface
Time Space
Switch 2
Watchdog
Reset Ater Mux
Ater Mux
Interface
Time Space
Switch 1 LEDs
On−Board Control
and Status
Controller Registers
Local
Local Qmux
Remote Qmux
Inventory Remote Serial Interface
Inventory Memory Communication RS−232
EEPROM Controller Man− Interface
Machine
Interface
Figure 31: ASMB PBA Simplified Hardware Architecture
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8.2 Onboard Controller

The OBC manages the local operations and maintenance of the ASMB PBA.
The OBC:
Configures and reconfigures the ASMB PBA
Monitors the alarms and status of the PBA
Sets up the mapping of the multiplex/demultiplex function
Monitors the performance of the Ater and Ater Mux Interfaces

Controls and monitors the insertion of the tributary (Ater Interface)
information
Controls the insertion and extraction of the embedded Qmux information
Runs self-tests
Controls the PBA alarm LEDs.
8.3 Ater Interface

The ASMB has four Ater Interfaces. An Ater Interface link is a G.703 and G.704
compatible 2 048 kbit/s PCM link.
The input and output ports provide either 75 coaxial or 120 balanced-pair
termination. The type of termination depends on the PBA variant.
Each Ater Interface comprises a G.703 Clock Extraction circuit and a TTC
(Trunk Controller Chip). These two circuits operate in conjunction to perform
the Ater Interface functions.
Ater To/from Time Space
Interface G.703 Switch
Clock TCC
NRZ
Extraction To/From Sub−rate
HDB3
Switch
Figure 32: Ater Interface
8.3.1 Clock Extraction

The G.703 Clock Extraction circuit extracts a 2.048 Mhz clock signal from the
received PCM signal data marks for clock regeneration purposes. This local
clock signal is used to re-time the incoming PCM signals.
8.3.2 HDB3 to NRZ Conversion

The Ater Interface converts the received HDB3 signal to a binary NRZ
(Non-Return to Zero) signal. Conversely, the interface converts the NRZ
signals from the Switch to HDB3.
8.3.3 Re-timing
The Ater Interface adapts the frequency and bit alignment of the incoming
PCM data stream to the local clock signal. The G.703 Clock Extraction circuit
generates the clock signal. The frame alignment circuit tolerates jitter and
wander in the incoming data without loss of data, as specified in CCITT G.823.
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8.3.4 Frame Alignment Supervision

Using the data received in TS0, the Ater Interface checks the frame alignment.
It performs frame realignment if a loss of frame alignment occurs.
8.3.5 CRC4 Monitoring and Generation

The Ater Interface checks for correct synchronization. It also counts the CRC4
errors in the received signal (according to G.704 and G.706). The firmware
uses the CRC4 error count to calculate the performance parameters as
specified in G.821.
8.3.6 Fault Detection

The Ater Interface monitors the incoming 2 048 kbit/s signal to detect faults
and generate error signals.
The following error signals can be detected or generated:
LFA (Loss of Frame Alignment)
Remote Alarm Indication
Bit Error Ratio

LIS (Loss of Incoming Signal)
2 048 kbit/s AIS Detection
LMFA (Loss of CRC4 Multiframe Alignment)
Slip Detection.
8.3.7 Fault Indications Sent to Remote End

The Ater Interface sends AIS and RAI to the remote end according to G.732.
8.3.8 TCC Configuration

As the TCCs do not have a direct interface with the OBC, they are configured
by Time Space Switch 2 of the Switch.
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8.4 Ater Mux Interface

The Ater Mux Interface is similar to the Ater Interface. It performs similar
functions for the Ater Mux link. An Ater Mux Interface link is a G.703 and G.704
Microbreaks on the Ater Mux Interface do not result in the release of calls.
Microbreaks are short disturbances which can result in the generation of:
LIS
LFA
AIS
LMFA (if CRC4 is active).
Microbreak detection is initiated if there is no valid input data signal. Microbreak

control is enabled and disabled by the OBC writing to the RINVR, see Onboard
Registers (Section 8.15.1) .
8.5 Switch
The Switch performs the multiplexing and demultiplexing, and switching
functions. The Switch comprises two Sub-rate Switches and two TSSWs
(Time Space Switches).
The Switch also sends and detects redundant AISs in the TS which carries
the information from the Ater Interfaces. This is done when 1:4 multiplexing is
performed. The OBC software controls this function.
8.5.1 Sub-rate Switch

The SRSs perform the multiplexing and demultiplexing of channels between
the four Ater Interface links to/from the Ater Mux link. They also perform the
insertion/extraction of the embedded Qmux channels. This switching function is
performed at the bit level.
At the bit level, the SRSs provide:
Mapping, on a bit basis, of the multiplexing/demultiplexing function

performed, i.e., 1:4 or 1:3
A non-blocking cross-connection between the Ater Interfaces and the

Ater Mux Interface
A synchronous sub-rate matrix
Software transparency for the hardware relationship of TS0 with respect

to the frame pulse
The addition and dropping of the Qmux channels (in 16 kbit/s by over
sampling) via a matrix function
Insertion of tributary information bits to the outgoing Ater Mux signal.
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SRS1 also performs some clock selection functions.
SRS1 PLL
Ater Mux Clock
Ater 1 Clock Clock
Ater 2 Clock Selection
Ater 3 Clock and
Ater 4 Clock Detection
On−board
Oscillator
Timing to Timing Divider

PBA circuits Generator
8.192 MHz
16.384 MHz
Voltage Filter Phase
Divider 1/2 Controlled Comparator
Oscillator
Divider
Figure 33: Clock Selection and Synchronization Circuits
All the extracted clocks are applied to the clock selection and detection circuit in
SRS1. A clock signal generated by a Crystal Oscillator is also applied to the
clock selection and detection circuit.
The clock selection and detection circuit selects one of the inputs on a priority
basis as follows:
Ater Mux clock (highest priority)
Ater 1 clock
Ater 2 clock
Ater 3 clock
Ater 4 clock
Onboard Oscillator clock (lowest priority).
The selected clock is applied to a phase comparator. The other input to the
phase comparator is the output from the 16 MHz VCO applied via a Divider
Circuit. The phase comparator output controls the VCO.
The 8.192 MHz synchronized clock is applied to the Timing Generator. This
generates a 2.048 MHz clock signal, which synchronizes the timing of the PBA.
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8.5.2 Time Space Switch

The TSSWs perform 2 Mbit/s frame or TS-based switching. This provides
simultaneous connections for up to 256 x 64 kbit/s channels.
The switch:
Routes the TSs between the Ater Mux Interface and SRS2
Provides the OBC with read and write access to the TSs
Scans the tributary information bits, AIS, and RAI
Configures the TCCs (part of the Ater and Ater Mux Interfaces) to perform
the required functions.
8.6 TS0 Logic

The TS0 Logic inserts and extracts the Qmux information and the FEA (Far
End Alarm) information. It does this by writing to, or reading from, the spare bits
of the TS0 NFAS (Non Frame Alignment Signal) of the Ater Mux Interface. The
OBC writes the FEA bit into a register which the TS0 Logic accesses.
On the transmit side, the TS0 Logic receives the Qmux information from SRS2.
If necessary, it adapts the speed of the signal. Then the TS0 logic combines
the Qmux information with the FEA bit. It sends the combined signal to TSSW1
for onward transmission on the Ater Mux link.
On the receive side, the TS0 Logic receives the TS0 NFAS from the TCC of the
Ater Mux Interface. It extracts the Qmux information and sends it to SRS2.
The TS0 Logic ensures compatibility with Nokia Network Elements which
use TS0 for the Qmux information.
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Modes of Operation
The TS0 Logic operates in one of four modes, as described in the following
table.
Mode Description
0 No insertion/extraction of the Qmux information in TS0.

The output of the TS0 logic is set to the tri-state (high
impedance).
1 Qmux sampling rate is 4 kHz. Bit 8 corresponds to the

Qmux data.
2 Qmux sampling rate is 8 kHz. Bits 7 and 8 correspond to

the Qmux data.
3 Qmux sampling rate is 16 kHz. Bits 5 to 8 correspond to

the Qmux data.
Table 20: TS0 Logic - Modes of Operation
1 2 3 4 5 6 7 8
Mode 0: No Qmux
TS0 NFAS 1 1 1 1 1 1 1 1 insertion/extraction in TS0
TS0 NFAS 1 1 A 1 1 1 1 Q0 Mode 1: Qmux sampling rate = 4 kHz
TS0 NFAS 1 1 A 1 1 1 Q1 Q0 Mode 2: Qmux sampling rate = 8 kHz
TS0 NFAS 1 1 A 1 Q3 Q2 Q1 Q0 Mode 3: Qmux sampling rate = 16 kHz
Figure 34: TS0 Logic - Operating Modes
Bit 3 (A) is the RAI, which is set to 0 during error-free operations. It is set to 1
when an RAI is sent to the remote end. The unused national bits are set to 1.
8.7 Serial Communication Controller

The SCC is a dual channel, multi-protocol communication controller. It
Two independent full-duplex channels are programmed for asynchronous
data communication.
Channels The two channels are:
Channel A, which provides the local Qmux Interface link
Channel B, which provides the MMI link.
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8.8 Clock Circuits

The clock circuits, together with the PLL and SRS1, generate the timing signals
for the PBA. The following table describes the clock circuits.
Circuit Description
VCO Generates the 16 MHz clock signal which drives the PLL.
Out of Range Sends an alarm to the OBC if the control voltage of the
Detector VCO exceeds a predefined high or low limit.
Crystal Generates an 8 MHz clock signal. This signal is applied

Oscillator to SRS1.
Table 21: ASMB Clock Circuits
8.9 Memory
The following table describes the three types of memory on the ASMB PBA.
Circuit Description
EPROM The 512 kbytes EPROM stores all the software required
for operational and test tasks.
RAM The OBC stores volatile information in the RAM during

normal operations. The static RAM has 256 kbytes of
memory.
EEPROM The EEPROM stores PBA settings such as system

configuration and error counters. It provides 64 kbytes
of non-volatile memory. Write protection prevents the
information in the EEPROM being overwritten if an OBC
malfunction occurs.
Table 22: ASMB Memories
8.10 Remote Inventory EEPROM

The Remote Inventory EEPROM stores PBA inventory information. The PBA
inventory information includes items such as PBA manufacturing information,
PBA identification and PBA history. Access to the Remote Inventory EEPROM
is via the Remote Inventory Register (see Onboard Registers (Section 8.15.1)).
8.11 Local Qmux Interface

The local Qmux Interface provides local communication with the TSC. It
comprises a number of buffers and drivers. The interface conforms to the
requirements of RS-485. The local Qmux Interface is connected to Channel
A of the SCC.
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8.12 Remote Qmux Interface

The remote Qmux Interface provides point-to-point communication with the
TSCA PBA. The interface conforms to the requirements of RS-485. The
maximum operating speed is 2400 baud.
The remote Qmux information is inserted into, and extracted from, the Ater
Mux data stream. The SRS performs this function. This mechanism provides
communication with a remote submultiplexer at the Transcoder site for the
transfer of Qmux information.
8.13 Qmux Address Interface

This interface determines the address of the ASMB on the local Qmux bus
via a plug on the BPA. The software can reprogram this address to match the
network configuration requirements.
8.14 Man-Machine Interface

The MMI provides communication with a local maintenance device such as a
PC (TSC Terminal). The MMI is connected to one channel of the SCC.
The MMI provides serial asynchronous communication at a speed of up to
19200 baud. The baud rate is programmable from 50 to 19200 baud. An
I/O port bit detects the presence of TSC terminal. The interface conforms
to RS-232.
8.15 Control and Status Registers

The control and status registers comprise:
Onboard Registers
TS0 Logic Registers

SCC Registers
TSSW Registers
SRS Registers.
8.15.1 Onboard Registers

There are three onboard registers:
GPR (General Purpose Register)

RINVR
QAR (Qmux Address Register).
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8.15.1.1 GPR
The GPR is an 8-bit register that allows software control of the local Qmux
Interface and the LEDs. It also allows the software to reset the ASMB PBA.
The used read/write bits of the GPR are:
LEDs 1 to 4, which each control one of the four LEDs mounted on the
front of the PBA
SW-Reset, which allows the software to reset the PBA
LQmux-EN, which disables or enables the local Qmux Interface
PITMSK, which is the enable signal for the watchdog timer.
8.15.1.2 RINVR
The RINVR is an 8-bit register that controls access to the Remote Inventory
EEPROM. The following table describes the used bits of the RINVR.
OBC-SK RW Drives the clock signal of the Remote Inventory EEPROM.
OBC-CS RW Enables the Remote Inventory EEPROM when set (1).
OBC-PRE RW Enables the protected register when it is set (1).
OBC-DO RO Enables the Remote Inventory EEPROM data outputs.
OBC-IAE RO Indicates whether the Remote Inventory EEPROM can be accessed by the OBC.
MBE RO Enables and disables the microbreak control of the Ater Mux Interface.
REEN RW Controls the remote Qmux Interface transmitter.
TIMEN RW Enables the long range timer.
Table 23: RINVR Bits
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8.15.1.3 QAR
The QAR is an 8-bit register that indicates the Qmux address and the status
of a number of alarms and signals. The following table describes the used
bits of the QAR.
QMA0 - 4 RO Indicate the local Qmux address.
MTPR RO Indicates the status of the PBA, i.e., Test Mode or operational.
OUTRNG RO Indicates that a synchronization alarm (out of range detected) has occurred.
DSR RO Indicates the status of the MMI, i.e., terminal connected/not connected to the PBA.
Table 24: QAR Bits
8.15.2 TS0 Logic Registers

The TS0 Logic Registers control the operations of the TS0 Logic.
They comprise the:
Link Register, which indicates the FEA bit corresponding to the Ater Mux
Interface to the TS0 Logic
Mode Register, which indicates the rate at which the Qmux information is
sampled:
No sampling
4 kHz sampling
8 kHz sampling
16 kHz sampling.
8.15.3 SCC Registers

There are four registers via which the OBC controls the SCC:
B Channel Control
A Channel Control
B Channel Data
A Channel Data.
Each register controls the associated channel or data.
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8.15.4 TSSW Registers

There are four registers via which the OBC controls the TSSWs:
TSSW1 Control Register
TSSW1 Channel Register
TSSW2 Control Register

TSSW2 Channel Register.
Each registers controls the associated TSSW.
8.15.5 SRS Registers

There are two groups of registers via which the OBC controls the SRSs, SRS1
registers and SRS2 registers. Each group of registers controls the operation of
the associated SRS and the functions it performs.
8.16 Watchdog Reset Circuit

A reset signal is generated:
If the voltage decreases below +4.75 V
At power-on
Whenever the watchdog timer expires

When the reset button on the front of the PBA is pressed
When a reset signal is applied to the reset pin on the BPA
By a reset command given by software.
The reset is a general PBA reset, including the OBC.

Timer 0 of a Programmable Internal Timer provides the Watchdog function.
The Watchdog timeout can be programmed from 4.096 ms to approximately
4.5 minutes in steps of 4.096 ms.
8.17 Long Range Timer

Timers 1 and 2 of the timer circuit are connected in cascade to provide a long
range timer. When this timer expires, it generates an OBC interrupt.
8.18 O&M
This section describes the O&M facilities provided on the ASMB.
It comprises:
LEDs
Push Button
Replacement.
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8.18.1 LEDs
LED Description
4 Indicates a Prompt Maintenance Alarm, and is lit when:

A PMA is generated.
1 and 2 When flashing (normal condition), indicate that the OBC

is active.
Table 25: ASMB LED Description
8.18.2 Push Button

The push button on the front edge of the PBA generates a reset when it is
pressed.
8.18.3 Replacement
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Dimensions
Power Supply
The ASMB operates from a +5 V +/-5% supply.
Front Panel
Turn−button
Latch
LED 4
(Red)
Push−button
9−pin
Connector
PBA Identifying
Label
LED 3
(Red)
LED 2
(Red)
LED 1
(Red)
Turn−button
Latch
Figure 35: ASMB Front Panel
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9 BIUA
This section describes the hardware architecture of the BIUA PBA.
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9.1 Introduction
the BIU PBA.
BIUA Clock A
Clock
Circuits Clock B
Remote Remote Qmux

Qmux
Interface
LAPD
LAPD
Interface
Abis 1 BSI 1
Abis BSI
Interface
Time Space Sub−rate
Switch 1 Switch 1 BSI 2
Abis 2 BSI
Abis
Interface
BSI 3
BSI
Abis 3 Time Space Sub−rate
Abis Switch 2 Switch 2 BSI 4
Interface
BSI
BSI 5
Abis 4
Abis BSI
Interface Time Space Sub−rate
Switch 3 Switch 3 BSI 6
BSI
Abis 5
Abis
Interface
BSI 7
BSI
Time Space Sub−rate
Abis 6 Switch 4 Switch 4
Abis BSI 8
Interface
BSI
Alarm Alarms
Watchdog TS0 Logic
Reset Interface
LEDs
Selected Clock
On−board Control
and Status
Controller Registers
Local Local Qmux

Qmux
Remote Inventory Remote Serial Interface
Inventory Memory Communication RS−232
EEPROM Controller Man−Machine Interface
Interface
Figure 36: BIUA PBA Simplified Hardware Architecture
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The OBC manages the local operations and maintenance of the BIUA PBA.
The OBC:
Configures and reconfigures the BIUA PBA
Monitors the alarms and status of the BIUA PBA
Sets up the mapping of the multiplex/demultiplex function
Monitors the performance of the Ater and Ater Mux Interfaces

Controls the insertion and extraction of the embedded Qmux information
Runs self-tests
Controls the BIUA PBA alarm LEDs.
9.3 Abis Interface

The BIUA has six Abis Interfaces. An Abis Interface link is a G.703 and G.704
The input and output ports provide either 75 coaxial or 120 balanced-pair
termination. The type of termination depends on the PBA variant.
Each Abis Interface comprises a G.703 Clock Extraction circuit and a TCC.
These two circuits operate in conjunction to perform the Abis Interface functions.
Abis To/from Time Space
Interface G.703 Switch
Clock TCC
Extraction To/From Sub−rate
HDB3
Switch
Figure 37: Abis Interface
9.3.1 Clock Extraction

The G.703 Clock Extraction circuit extracts a 2.048 Mhz clock signal from
the received PCM signal data marks for clock regeneration purposes. This
local clock signal is used by the TCC.
9.3.2 HDB3 to NRZ Conversion

The Abis Interface converts the received HDB3 signal to a binary NRZ signal.
Conversely, the interface converts the NRZ signals from the Switch to HDB3.
9.3.3 Re-timing
The Abis Interface adapts the frequency and bit alignment of the incoming PCM
data stream to the local clock signal. This signal is generated by the G.703
Clock Extraction circuit. The frame alignment circuit tolerates jitter and wander
in the incoming data without loss of data, as specified in CCITT G.823.
9.3.4 Frame Alignment Supervision

Using the data received in TS0, the Abis Interface checks the frame alignment.
It performs frame realignment if a loss of frame alignment occurs.
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9 BIUA
9.3.5 CRC4 Monitoring and Generation

The Abis Interface checks for correct synchronization. It also counts the
CRC4 errors in the received signal (according to G.704 and G.706). The
firmware uses the CRC4 error count to calculate the performance parameters
as specified in G.821.
9.3.6 Fault Detection

The Abis Interface monitors the incoming 2 048 kbit/s signal to detect faults
and generate error signals.
The following error signals can be detected or generated:
LFA
RAI
BER
LIS
AIS Detection
LCRCMFA
Slip Detection.
9.3.7 Fault Indications Sent to Remote End

The Abis Interface sends AIS and RAI to the remote end according to G.732.
9.3.8 TCC Configuration

As the TCCs do not have a direct interface with the OBC, they are configured
by TSSWs.
9.4 BSI
As shown in the following figure, the BIUA has eight BSIs. Each BSI is a local
V.11 type interface. The drivers and receivers of these interfaces conform to the
RS-422 standard. The receivers have onboard polarization and termination
resistors.
Clock true
Clock
Clock false
Frame true
Frame
Frame false
Transmit data true

Transmit data
Transmit data false
Receive data Receive data false

Receive data true
Figure 38: BSI Drivers and Receivers
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9.5 Sub-rate Switch

There are four SRSs. These perform the multiplexing and demultiplexing of
channels between the Abis Interface links to/from the BSI links.
They also perform the insertion/extraction of the:
Embedded Qmux channels
LAPD channels.
This switching function is performed at the bit level.

At the bit level, the SRSs provide:
A non-blocking cross connection between the Abis Interfaces and the BSIs
A synchronous sub-rate matrix
Software transparency for the hardware relationship of TS0 with respect

to the frame pulse
The addition and dropping of the Qmux channels (in 16 kbit/s by over
sampling) via a matrix function
The addition and dropping of LAPD channels (64 kbit/s) via a matrix function
Activity failure detection on the BSIs

The addition of the:
Two-bit channels
Backward Ring Control channel
Ring Control channel.
The insertion, in any TS except TS0, of:

FEA
LCB (Local Clock Bit)
Master Clock Bit.
The SRSs perform mapping on a bit basis from point-to-multipoint and vice
versa.
Each SRS is divided into two main functional blocks:
Multiplexer part
Demultiplexer part.
The multiplexer part has 12 inputs, only two of which are used. These inputs
can be mapped onto one output. In the demultiplexer part, one input can be
mapped onto 12 outputs. Only two outputs of each SRS are used.
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9 BIUA
SRS1 also performs some clock synchronization functions.
SRS1 PLL
8 MHz Clock A
8 MHz Clock B Clock
Selection Phase
and Comparator
Detection
On−board
Oscillator
Timing to Timing Divider

PBA circuits Generator
8 MHz
Divider 16 MHz
1/2 Voltage Filter
Controlled
Oscillator
Figure 39: Clock Synchronization Circuits
Two clock signals from the BSC Clock and Alarm System (BCLA PBAs) are
applied to the clock selection and detection circuit in SRS1. A clock signal
generated by a Crystal Oscillator is also applied to the clock selection and
detection circuit.
The clock selection and detection circuit selects one of the inputs on a priority
basis as follows:
8 MHz clock A (highest priority)
8 MHz clock B
Onboard Oscillator clock (lowest priority).
The selected clock is applied to a phase comparator. The other input to the
phase comparator is the output from the 16 MHz VCO applied via a Divider
Circuit. The phase comparator output controls the VCO.
The output of the Divider Circuit is applied to the Timing Generator. This
generates a 2.048 Mhz clock signal, which synchronizes the timing of the PBA.
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9.6 Time Space Switch

The TSSWs perform 2 Mbit/s frame or TS-based switching. This provides
simultaneous connections for up to 256, 64 kbit/s channels.
The TSSWs:
Switch the dedicated Traffic Channels (TCHs) in any TS of the Abis Interface
to the SRSs. TSSW2 performs this function
Switch the dedicated TCHs in any TS of the SRS to the Abis Interfaces.
TSSW3 performs this function
Provide the OBC with read and write access to the TSs. TSSW3 performs
this function
Scan the TB, BRC and RNGC bits received from the TCCs (part of the Abis
Interfaces). TSSW2 performs this function
Scan the FEA, MCB and LCB bits. TSSW2 performs this function
Configure the TCCs to perform the required functions. TSSW1 and TSSW4
perform this function.
9.7 TS0 Logic

The TS0 Logic inserts and extracts the:
Qmux information
FEA information
MCB
LCB.
The TS0 Logic does this is by writing to, or reading from, the spare bits of the
TS0 NFAS of each Abis Interface. The OBC writes the FEA, MCB and LCB bits
into a register (one for each Abis Interface) which is accessed by the TS0 Logic.
On the transmit side, the TS0 Logic receives the Qmux information from SRS2.
If necessary, it adapts the speed of the signal. Then the TS0 logic combines
the Qmux information with the FEA, MCB and LCB bits. It sends the combined
signal to TSSW1 and TSSW4 for onward transmission on the Abis link.
On the receive side, the TS0 Logic receives the TS0 NFAS from the TCC of the
Ater Mux Interface. It extracts the Qmux information and sends it to SRS2.
The TS0 Logic ensures compatibility with Nokia Network Elements which
use TS0 for the Qmux information.
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Modes of Operation
The TS0 Logic operates in one of four modes, as described in the following
table.
Mode Description
0 No insertion/extraction of the Qmux information or MCB

and LCB bits in TS0. The output of the TS0 logic is set to
the tri-state (high impedance).
1 Qmux sampling rate is set at 4 kHz. Bits 4 and 5

respectively correspond to the MCB and LCB bits
(multidrop ring configuration). Bits 6 and 7 are set to 1. Bit
8 corresponds to the Qmux data.
2 Qmux sampling rate is set to 8 kHz. Bits 4 and 5

respectively correspond to the MCB and LCB bits
(multidrop ring configuration). Bit 6 is set to 1. Bit 7 and
Bit 8 correspond to the Qmux data.
3 Qmux sampling rate is set to 16 kHz. Bit 4 is set to 1. Bits

5 to 8 correspond to the Qmux data.
Table 26: TS0 Logic - Modes of Operation
1 2 3 4 5 6 7 8
Mode 0: No Qmux
TS0 NFAS 1 1 A MCB LCB 1 1 1 insertion/extraction in TS0
TS0 NFAS 1 1 A MCB LCB 1 1 Q0 Mode 1: Qmux sampling rate = 4 kHz
TS0 NFAS 1 1 A MCB LCB 1 Q1 Q0 Mode 2: Qmux sampling rate = 8 kHz
TS0 NFAS 1 1 A 1 Q3 Q2 Q1 Q0 Mode 3: Qmux sampling rate = 16 kHz
Figure 40: TS0 Logic - Operating Modes
Bit 3 (A) is the RAI, which is set to 0 during error free operations. It is set to 1
when an RAI is sent to the remote end. The unused national bits are set to 1.
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9.8 Serial Communication Controller

The SCC is a dual channel, multi-protocol communication controller. It
Two independent full-duplex channels are programmed for asynchronous
data communication.
Channels
The two channels are:
Channel A, which provides the Local Qmux Interface link
9.9 Clock Circuits

The clock circuits, together with the PLL of SRS1 generate the timing signals
for the PBA. The following table describes the clock circuits.
Circuit Description
VCO Generates the 16 MHz clock signal which drives the PLL.
Out of Range Sends an alarm to the OBC, if the control voltage of the
Detector VCO exceeds a predefined high or low limit.
Crystal Generates an 8 MHz clock signal. This signal is applied

Oscillator to SRS1.
Table 27: BIUA Clock Circuits
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9.10 Memory
The following table describes the three types of memory on the BIUA PBA.
Circuit Description
EPROM The 512 kbytes EPROM stores all the software required
for operational and test tasks.
RAM The OBC stores volatile information in the RAM during

normal operations. The static RAM has 256 kbytes of
memory.

configuration and error counters. It provides 64 kbytes
of non-volatile memory. Write protection prevents the
information in the EEPROM being overwritten if an OBC
malfunction occurs.
Table 28: BIUA Memories

The Remote Inventory EEPROM stores PBA inventory information. The PBA
inventory information includes items such as PBA manufacturing information,
PBA identification and PBA history. Access to the Remote Inventory EEPROM
is via the Remote Inventory Register (see Onboard Registers (Section 9.18.1)).
9.12 Local Qmux Interface

The local Qmux Interface provides local communication with the TSC. It
comprises a number of buffers and drivers. The interface conforms to the
requirements of RS-485. The local Qmux Interface is connected to channel
A of the SCC.
9.13 Remote Qmux Interface

The remote Qmux Interface provides point-to-point communication with the
TSCA PBA. The interface conforms to the requirements of RS-485. The
maximum operating speed is 2400 baud.
The remote Qmux information is inserted into, and extracted from, the Abis
data stream. The SRS performs this function. This mechanism provides
communication with a remote submultiplexer at the BTS site for the transfer of
Qmux information.
9.14 Qmux Address Interface

This interface determines the address of the BIUA on the local Qmux bus via a
plug on the BPA. The software can reprogram this address to match the
network configuration requirements.
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PC (TSC Terminal). The MMI is connected to one channel of the SCC.
19200 baud. The baud rate is programmable from 50 to 19200 baud. An
to RS-232.
9.16 LAPD Interface

The LAPD Interface provides O&M communication between the BIUA PBA
and the TSCA PBA. The interface comprises a line driver and line receivers
which connect the LAPD signal to and from SRS1.
The BIUA PBA inserts, and extracts, the LAPD information from one of the
BSIs with a TCUC PBA.
9.17 Alarm Interface

The Alarm Interface provides for the connection of four external alarm signals.
Each alarm input is connected to a local V.11 receiver. The receivers have
onboard polarization and termination resistors.
9.18 Control and Status Registers

The control and status registers comprise:
Onboard Registers
TS0 Logic Registers
SCC Registers
TSSW Registers
SRS Registers.
9.18.1 Onboard Registers

There are five onboard registers:
GPR
ALR (Alarm Register)
RINVR
QAR
LAPD Register.
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9.18.1.1 GPR
The GPR is an 8-bit register that allows software control of the local Qmux
Interface and the LEDs. It also allows the software to reset the BIUA PBA. The
used read/write bits of the GPR are:
LEDs 1 to 4, which each control one of the four LEDs mounted on the
front of the PBA
SW-Reset, which allows the software to reset the PBA
LQmux-EN, which disables or enables the local Qmux Interface.
9.18.1.2 ALR
The 8-bit ALR indicates the status of the external alarms.
9.18.1.3 RINVR
The RINVR is an 8-bit register that controls access to the Remote Inventory
EEPROM. The following table describes the used bits of the RINVR.
OBC-SK RW Drives the clock signal of the Remote Inventory EEPROM.
OBC-CS RW Enables the Remote Inventory EEPROM when set (1).
OBC-PRE RW Enables the protected register when it is set (1).
OBC-DO RO Enables the Remote Inventory EEPROM data outputs.
OBC-IAE RO Indicates whether the Remote Inventory EEPROM can be accessed by the OBC.
CLKS2 RO Indicate the status of the selected clock.

and
CLKS1
Table 29: RINVR Bits BIUA PBA
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9.18.1.4 QAR
The QAR is an 8-bit register that indicates the Qmux address and the status
of a number of alarms and signals. The following table describes the used
bits of the QAR.
QMA0 - 4 RO Indicate the local Qmux address.
MTPR RO Indicates whether the status of the PBA, i.e., test mode or operational.
OUTRNG RO Indicates that a synchronization alarm (out-of-range detected) has occurred.
DSR RO Indicates the status of the MMI, i.e., terminal connected/not connected to the PBA.
Table 30: QAR Bits
9.18.1.5 LAPD Register

The LAPD Register controls the LAPD information flow and some local PBA
functions. The following table describes the used bits of the LAPD register.
LAPDC0, RW Controls the LAPD data extraction and insertion functions performed by the SRSs.
LAPDC1
REEN RW Controls the remote Qmux interface transmitter.
TEEN RW Enables the long range timer.
PITMSK RW Enables the watchdog timer.
Table 31: LAPD Register Bits
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9.18.2 TS0 Logic Registers

The TS0 Logic Registers control the operations of the TS0 Logic.
They comprise:
Link Register, which indicates the FEA bit corresponding to the Ater Mux
Interface to the TS0 Logic.
Mode Register, which indicates the rate at which the Qmux information is
sampled:
No sampling
4 kHz sampling
8 kHz sampling
16 kHz sampling.
Selection Register, which indicates the SRS that is connected to TSSW3 to

allow switching of the TCHs
Mask Register, which selects the TCC output that is connected to the
TSSWs.

There are four registers via which the OBC controls the SCC:
B Channel Control
A Channel Control
B Channel Data
A Channel Data.
Each register controls the associated channel or data.
9.18.4 TSSW Registers

There are eight registers via which the OBC controls the TSSWs:
TSSWx Control Register (x = 1 to 4)
TSSWx Channel Register.
9.18.5 SRS Registers

There are four groups of registers via which the OBC controls the SRSs.
Each group of registers controls the operation of the associated SRS and
the functions it performs.
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At power-on


Timer 0 of a PIT provides the Watchdog function. The Watchdog timeout can be
programmed from 4.096 ms to approximately 4.5 minutes in steps of 4.096 ms.

Timers 1 and 2 of the timer circuit, connected in cascade, provide a long range
timer. When this timer expires, it generates an OBC interrupt.
9.21 O&M
This section describes the O&M facilities provided on the BIUA.
It comprises:
LEDs
Push Button
Replacement.
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9.21.1 LEDs
LED Description
4 Indicates a Prompt Maintenance Alarm, and is lit

when:
A PMA is generated.
1 and 2 When flashing (normal condition), indicate that the

OBC is active.
Table 32: BIUA LED Description
9.21.2 Push Button

pressed.
9.21.3 Replacement
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Dimensions
Power Supply
The BIUA operates from a +5 V +/-5% supply.
Front Panel
Turn−button
Latch
LED 4
(Red)
Push Button
9−pin
Connector
PBA Identifying
Label
LED 3
(Red)
LED 2
(Red)
LED 1
(Red)
Turn−button
Latch
Figure 41: BIUA Front Panel
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10 TSCA
This section describes the hardware architecture of the TSCA PBA.
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10 TSCA
10.1 Introduction
of the TSCA PBA.
TSCA
Local Qmux
Interface 4A
LAPD
Local ChA ChA LAPD
Qmux Interface Interface
Local Qmux
Interface 4B
SCC1 SCC2
Remote Qmux
Interface 3A
ChB MMI RS−232
ChB Interface
Remote Qmux
Interface 3B
Remote Qmux
Remote Interface 2A Remote
Qmux ChA Inventory Remote
EEPROM Inventory
Remote Qmux
Interface 2B
SCC3
Remote Qmux
Interface 1A
ChB
On−Board Watchdog
Remote Qmux Controller Reset
Interface 1B
Memory
Memory Controller and Watchdog
Register Unit Reset Unit
Memory
LEDs
Figure 42: TSCA PBA Simplified Hardware Architecture

The OBC manages the local operation and maintenance of the TSCA PBA.
The OBC:
Provides local control of the TSCA PBA

Initializes the PBA
Runs the self-test.
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10.3 Memory
The following table describes the four types of memory on the TSCA PBA.
Circuit Description
FLASH EPROM The FLASH EPROM comprises 2.048 Mbytes organized

into 32 pages, each of 64 kbytes. An FEPROM, known as
the Boot FEPROM, stores:
Booting routines
Elementary routines to provide communication with the

TSC Terminal
Programming routines to reprogram the FLASH
EPROMs of the TSCA PBA.
All the operational software can be download and stored
in the FEPROMs
DRAM The 2 Mbytes DRAM stores volatile information such as

variables and buffers used in the firmware. The DRAM is
organized into 32 x 64 kbytes banks.
SRAM The 128 kbytes SRAM stores the interrupt vectors.

configuration and error counters. It provides 32 kbytes of
non-volatile memory.
Table 33: TSCA Memories
10.4 Memory Controller and Register Unit

The Memory Controller and Register Unit is an Erasable Programmable
Logic Device.
This device performs:
DRAM control functions
Parity checks on the DRAM
Selects the FLASH EPROM and DRAM banks.
In addition, the device provides the onboard registers. Onboard Registers

(Section 10.14) describes these registers.
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10 TSCA
10.5 Serial Communication Controllers

There are three SCCs on the TSCA PBA. The SCC is a dual channel,
multi-protocol communication controller. It functions as a serial-to-parallel
and as a parallel-to-serial converter/controller. Two independent full-duplex
channels (A and B) are programmed for asynchronous data communication.
10.5.1 SCC1
The two channels of SCC1 are:
Channel A, which provides the Local Qmux Interface links
Channel B, which provides connections to Remote Qmux Interfaces 3A

and 3B.
10.5.2 SCC2
Channel A, which provides the LAPD link

10.5.3 SCC3
Channel A, which provides connection to Remote Qmux Interfaces 2A

and 2B
Channel B, which provides connections to Remote Qmux Interfaces 1A

and 1B.
10.6 Local Qmux Interfaces

There are two local Qmux Interfaces. These interfaces provide local
communication with the transmission elements on the same site. Each
interface comprises a number of buffers and drivers. The interfaces conform to
the requirements of RS-485. Each interface is polled alternately.
The local Qmux Interfaces are connected to channel A of SCC1. The baud rate
is programmable at 1 200 or 2 400 bauds.
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10 TSCA
10.7 Remote Qmux Interfaces

There are six remote Qmux Interfaces. These interfaces provide communication
with the transmission elements at remote sites. Each Interface comprises a
number of buffers and drivers. The interfaces conform to the requirements of
RS-485. Only three interfaces are active at a time.
Remote Qmux Interfaces 3A and 3B are connected to channel B of SCC1.
The other Remote Qmux Interfaces are connected to SCC3 as follows:
2A and 2B are connected to channel A
1A and 1B are connected to channel B.
The baud rate is programmable at 1 200 or 2 400 bauds.

PC (TSC Terminal). The MMI is connected to channel B of SCC2.
19 200 bauds. The baud rate is programmable from 50 to 19 200 bauds. An
to RS-232.
10.9 LAPD Interface

The LAPD interface provides O&M communication between the TSCA PBA
and the TCUC PBAs. This communication is via the BIUA PBA. The LAPD
interface comprises a line driver and line receivers which connect the LAPD
signal to and from channel A of SCC2. Channel A of SCC2 operates in the
HDLC-oriented synchronous mode.
Data is transferred between channel A of SCC2 and the memory by two DMA
channels. These channels are an integral part of the OBC. DMA channel 1
transfers transmit data. DMA channel 0 transfers receive data. The received
LAPD signal is monitored to detect the presence of the LAPD clock.

The Remote Inventory EEPROM stores PBA inventory information. The
PBA inventory information includes items such as PBA manufacturing, PBA
identification and PBA history. Access to the Remote Inventory EEPROM is
via the Remote Inventory Register (see Remote Inventory Register (Section
10.14.7)).
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10 TSCA

At power-on


Timer 0 of a PIT provides the Watchdog function. The Watchdog timeout can be
programmed from 4.096 ms to approximately 4.5 minutes in steps of 4.096 ms.

Timers 1 and 2 of the timer circuit, connected in cascade, provide a long range
timer. When this timer expires, it generates an OBC interrupt.
10.13 Test Loops

Two test loops are provided to allow the PBA to be tested in the system:
Self-test
Extended Test.
10.13.1 Self-test
The self-test allows testing of the PBA without the external interfaces, e.g.,
memory testing and SCC testing.
Disabling the drivers of the external interfaces during testing prevents data
being transmitted on these interfaces. Individual serial channels of each SCC
can be disabled. All the serial channels can be looped back internally on the
PBA by activating the internal loopback of the SCCs.
10.13.2 Extended Test

The extended test provides testing of the external interfaces. Loop cables must
be connected to the external interfaces before the extended test is performed.
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10 TSCA
10.14 Onboard Registers

The onboard registers comprise:
SCC Registers
DRAM Bank Select Register
FLASH EPROM Bank Select Register
Control and Status Register
Wait State Register

Parity Location Registers
Remote Inventory Register
LED Register.

There are three groups of registers via which the OBC controls the SCCs. Each
group controls the operations of an associated SCC.
Each group comprises:
B Channel Control
A Channel Control
B Channel Data
A Channel Data.
10.14.2 DRAM Bank Select Register

Six read/write bits of the 8-bit DRAM Bank Select Register determine which of
the DRAM banks is selected.
10.14.3 FLASH EPROM Bank Select Register

Five read/write bits of the 8-bit FLASH EPROM Bank Select Register determine
which of the FLASH EPROM banks is selected.
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10 TSCA
10.14.4 Control and Status Register

The Control and Status Register allows the OBC to:
Read the status of the LAPD signal
Read the status of the MMI, i.e., terminal connected/not connected to

the PBA
Read the status of the PBA, i.e., test mode or operational
Reset the PBA
Control access to the FLASH EPROM banks
Enable and disable parity checking during memory accesses

Enable and disable the LAPD link
Read the status of the DRAM during an access, i.e., parity error or parity OK.
10.14.5 Wait State Register

The Wait State Register allows the OBC to:
Control the number of DRAM wait states

Control the number of FEPROM wait states.
10.14.6 Parity Location Registers

The Parity Location Registers store the address where a parity error has
been detected.
10.14.7 Remote Inventory Register

The RINVR:
Drives the clock signal of the Remote Inventory EEPROM
Enables and disables the Remote Inventory EEPROM
Enables and disables the protected register

Enables and disables the Remote Inventory EEPROM data outputs
Indicates whether the Remote Inventory EEPROM can be accessed by

the OBC
Enables and disables the OBC Interface.
10.14.8 LED Register

The LED Register controls the four LEDs on the front panel. In addition,
it indicates the highest nibble of the address where a parity error has been
detected.
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10 TSCA
10.15 O&M
This section describes the O&M facilities provided on the TSCA.
It comprises:
LEDs
Push Button
Replacement.
10.15.1 LEDs
LED Description
4 Indicates a Prompt Maintenance Alarm, and is lit

when:

A PMA is generated.
1 and 2 When flashing (normal condition), indicate that the

OBC is active.
Table 34: TSCA LED Description
10.15.2 Push Button

pressed.
10.15.3 Replacement
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10 TSCA

Dimensions Refer to Common Information (Section 1.2) .
Power Supply The TSCA operates from a +5 V +/-5% supply.
Front Panel
Turn−button
Latch
LED 4
(Red)
Push Button
9−pin
Connector
PBA Identifying
Label
LED 3
(Red)
LED 2
(Red)
LED 1
(Red)
Turn−button
Latch
Figure 43: TSCA Front Panel
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9120 BSC Hardware Description

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3BK 21239 AAAA TQZZA Ed.04

Short title BSC HW Descr.

2 / 142 3BK 21239 AAAA TQZZA Ed.04

3BK 21239 AAAA TQZZA Ed.04 3 / 142

3.3.3 External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4 / 142 3BK 21239 AAAA TQZZA Ed.04

6.2.1 Reference Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3BK 21239 AAAA TQZZA Ed.04 5 / 142

8.11 Local Qmux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6 / 142 3BK 21239 AAAA TQZZA Ed.04

3BK 21239 AAAA TQZZA Ed.04 7 / 142

8 / 142 3BK 21239 AAAA TQZZA Ed.04

Figure 40: TS0 Logic - Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

3BK 21239 AAAA TQZZA Ed.04 9 / 142

10 / 142 3BK 21239 AAAA TQZZA Ed.04

What’s New In Edition 04

Audience This document is intended for:

System support engineers

Any other personnel interested in the structure of the BSC hardware.

3BK 21239 AAAA TQZZA Ed.04 11 / 142

12 / 142 3BK 21239 AAAA TQZZA Ed.04

This document provides an introduction to the hardware of the functional units

3BK 21239 AAAA TQZZA Ed.04 13 / 142

1.1 Functional Units

Abis TSU 1 Ater TSU 1

TSC Terminal OMC−R BSC Terminal External Alarms

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1.2 Common Information

All except DC/DC Converter 221 mm 254 mm 1.6 mm (1)

DC/DC Converter 221 mm 254 mm 3.2 mm (2)

Table 1: PBA Dimensions

1.2.2 Temperature Range

3BK 21239 AAAA TQZZA Ed.04 15 / 142

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This section describes the hardware architecture of the CPRC PBA.

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CEPK (Control Element Processor Kernel)

CENK (Control Element Network Kernel)

CEBK (Control Element Broadcast Kernel).

Network Communication X.25 Link

*= Common Parts with other Control Element PBAs

Figure 2: Simplified CPRC PBA Hardware Architecture

There are three main types of CPRC PBA:

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Control Element Processor Kernel

To/From Other Circuits on PBA

Figure 3: CEPK Functional Diagram

2.2.1 Onboard Controller

Very large address range

Memory management unit.

2.2.2 OBC Peripherals

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Counter/Timer 1 operates as a Watchdog Timer (or Sanity Timer)

Counter/Timer 2 operates as a Software Timer. It generates cyclic interrupts

2.2.2.2 Interrupt Controllers

2.2.2.3 Bus Arbitration Logic

2.2.3 Common RAM

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2.2.5 FLASH Memory

Read access to the FLASH memory can be in byte, word or double-word