DESIGN AND ANALYSIS OF HYBRID ADDER
USING ASYNCHRONOUS FINE-GRAIN
POWER-GATED LOGIC
Sushmitha.V1, Roselin Ramya. J2 ,Kiruba Bethesthal Elizabeth.E3 ,
1
PG Scholar – VLSI design, 2PG Scholar – VLSI design,3PG Scholar – VLSI design,
Dr.Sivanthi Aditanar College of Engineering,
1
mithavsush@gmail,2roselinramya04@gmail.com,3 kirubaelizabeth8@gmail.com.
Abstract:
The objective of this project is to design and
analyses of Hybrid adder using Asynchronous Fine-
Grain Power-Gated Logic. Hybrid adder, here uses the
common Boolean logic (CBL) on the available Square
root carry select adder (SQRT CSLA).In any VLSI system
design, there is a need to analyses parameters called
power, area of the circuit. Using AFPL technique the
speed is enhanced and the power dissipation is reduced.
The hybrid adder is designed and simulated using the
standard T-SPICE tool. The main feature of the proposed
system is to design an ultralow-power CMOS logic
circuits for implementing hybrid adder. As the feature
size continues to shrink and additionally the
corresponding semiconductor density can increase,
power dissipation has become an important concern in
Nano scale CMOS VLSI vogue. Relying upon the
appliance, there are numerous ways in which is also
accustomed trim the power consumption of VLSI circuits.
These can vary from low-level measures based upon
elementary physics, like using a lower power offer voltage
or victimization high threshold voltage transistors; to
high-level measures like clock-gating or power-down
modes. The two that meant this investigation were
asynchronous logic and adiabatic logic.
Keywords: CMOS, AFPL, Leakage Power, Sub-
threshold Leakage, Adiabatic logic.
I. INTRODUCTION
As the feature size continues to shrink and the
corresponding transistor density increases, power
dissipation has become an important concern in Nano scale
CMOS VLSI design. Power dissipation in CMOS circuits
can be categorized into dynamic dissipation and static
dissipation. Dynamic power is the power dissipated when
the device is active, and static power is the power
dissipated when the device is powered up but no signals are
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changing their values. Dynamic power consists of the
switching power, caused by charging and discharging of
load capacitance, and the internal power, caused by short-
circuit current and the currents needed to charge the
internal capacitance of the cell. Static dissipation results
from leakage currents and the main sources of leakage
include sub-threshold leakage, gate leakage, gate-induced
drain leakage, and junction leakage. As threshold voltage,
channel length, and gate oxide thickness continue to shrink,
leakage dissipation is becoming a significant contributor to
the total power dissipation. In a nanometer CMOS circuit,
leakage power can constitute as much as a third of total
power. International technology roadmaps for
semiconductors have recognized leakage power
consumption as a clear long-term threat for design
technology in the next fifteen years.
Various techniques for reducing leakage loss in CMOS
circuits have been proposed both at the circuit and process
technology levels. At the circuit level, leakage reduction
techniques include transistor stacking, reverse body
biasing, dual threshold CMOS, and power gating. Among
these techniques, power gating is one of the most effective
techniques for leakage reduction. In general, power gating
techniques increase the effective resistance of leakage
paths by inserting sleep transistors (power gating
transistors) between power supply rails and transistor
stacks. In the idle (sleep) mode, the sleep transistors are
turned off, cutting the pull-up and pull-down networks off
from one or both power rails, and thus the leakage current
is suppressed; In the active mode, the sleep transistors are
turned on, reconnecting the pull-up and pull-down
networks to power supply rails.
II. ASYNCHRONOUS FINE- GRAIN POWER-
GATED LOGIC
In this section, the proposed AFPL is presented. AFPL can
be combined with the PCR mechanism [1]. When AFPL
incorporates the PCR mechanism, it is denoted by AFPL-
PCR, otherwise, it is denoted by AFPLw/o PCR. Fig 1
shows the structure of the AFPL pipelines. In AFPL w/o
PCR[see Fig.1(a)], a pipeline stage, denoted by Si, is 4) The receiver de-asserts the acknowledge signal to
comprised of an efficient charge recovery logic (ECRL) complete the communication cycle.
gate Gi, which implements the logic function of the stage,
and a handshake controller HCi, which handles
Thus, the data stream flowing through the AFPL
handshaking with the neighboring stages and provides
power to ECRL logic gate Gi. pipeline is a sequence of alternating valid tokens and empty
In AFPL-PCR [see Fig.1 (b)], a pipeline stage, denoted by tokens. That is, there is always an empty token between two
Si+1, has an additional unit, the PCR unit PCRi+1, which consecutive valid tokens in the data stream, advice versa.
controls charge reuse between pipeline stages Si and
Si+1.An asynchronous system is made up of many
autonomous modules, each of which operates at its own
rate and communicates with its neighboring modules only
when it needs to exchange information. The
synchronization between those autonomous modules is not
achieved by a global clock but rather by local handshake
signals, request and acknowledge. The handshake protocol
used in the AFPL pipeline is the four phase dual-rail
protocol, in which the request signal is encoded into the
data signals (i.e., there is no separate request signal) and n
pairs of wires are required to encode n-bit data.

(b) AFPL-PCR pipeline

A.FUNCTIONAL BLOCKS IN AFPL

Several logic families, including ECRL, IPGL, PFAL

and DTGAL, have been validated to construct the function
blocks of AFPL. Out of the five logic families, ECRL has
the simplest structure and the best energy efficiency
according to our experiments. Hence, in this work, ECRL
was chosen to implement the function blocks of AFPL. Fig
Fig1, AFPL pipelines. (a) AFPL w/o PCR pipeline 2. (a) Shows the structure of an ECRL AND/NAND gate.
ECRL adopts dual-rail data encoding; that is, each input to
For example, one-bit information, denoted by d, an ECRL gate requires both polarities to be represented [3],
can be encoded with a pair of wires d.t and d.f. If and each ECRL gate computes both a logic function and its
(d.t,d.f)=(1, 0), the code word (d.t,d.f) is a valid token and complement. As shown in Fig2. (a), an ECRL gate acquires
represents a logic 1;if (d.t,d.f)=(0, 1), the code power from the power node, denoted by Vp. In the AFPL
word(d.t,d.f)is a valid token and represents a logic 0; if pipeline, the power node Vpi in stage Si is connected to the
(d.t,d.f)=(0, 0), the code word (d.t,d.f) is an empty token output of the handshake controller HCi.
and represents no data. In the four-phase dual-rail protocol,
the transferring of data from the sender to the receiver
involves the following four actions:
1) The sender issues a valid code word on the
communication channel;
2) The receiver acquires the valid code word from the
communication channel, and then asserts the
acknowledge signal;
3) The sender responds by issuing an empty code
word(i.e., taking all data wires LOW) to indicate that
Fig2, ECRL logic. (a) ECRL AND/NAND gate. (b) Operation
the data on the communication channel is no longer
phases for ECRL
valid; and

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 The handshake controllers instead of the
conventional fixed dc power supply. The operation cycle
of an ECRL gate comprises four phases, wait, evaluate,
hold, and discharge. The current operation phase of an
ECRL gate GI is determined by the voltage of the
associated power node Vpi.

For the sake of simplicity, we will assume that power node

Vpi has an ideal trapezoidal voltage waveform as shown in
Fig2. (b). during the wait phase, power node Vpi is kept at
0 V, and gate Gi cannot draw any current from Vpi. Thus,
the corresponding gate outputs, Oi.t and Oi.f, are both kept
LOW (i.e., the outputs represent an empty token),
irrespective of the current input values. In the evaluate
phase, the voltage of Vpi ramps up from 0 V to Vdd, and gate
Gi can draw current from Vpi and begin to evaluate its Fig 3. Structure of the C-elements used in AFPL. (a) Traditional
outputs.
C-element used in APFL w/o PCR. (b) Enhanced C*-element

Let us take the ECRL AND/NAND gate in Fig 2. (a) as an
example, and assume that both inputs X and Y are HIGH.
In this case, NMOS M3 and M4 turn on, output node out.
Being clamped to the ground and PMOS M2 turns on, the
current from Vp beginning to charge output node out.t. As
the voltage of Vp ramps up, the voltage of node out.t
follows the voltage of Vp.
B.HANDSHAKE CONTROLLERS:
In the AFPL pipeline, the handshake controller HCi in
stage Si performs the following tasks: 1) detecting the
validity of the inputs to the ECRL logic [2] gates in stage
Si; 2) offering power to the ECRL logic gates in stage Si;
3) detecting whether the outputs of stage Si have been
received by the downstream stage Si+2; and 4) informing
the upstream stage Si-2 when Si-2 can remove its outputs.
used in AFPL-PCR.
III.PROPOSED METHOD:
In this work, the reduced carry select adder and
ripple carry adder are designed by using CBL logic instead
of static CMOS logic based Kogge-stone in the existing
system [7][8]. The optimization of power and area in
digital circuits is very important to improve their
performance. In RCA, the sum for each bit position in basic
adder is generated sequentially only after the preceding bit
position has been summed & a carry propagates into the
next location.
The regular CSLA contains two sets of Ripple
carry adders for cin = 0 & cin = 1. The CSLA is used in
many systems to reduce the propagation delay of carry by
separately producing the multiple carries and then decide a
carry to produce the sum.

As illustrated in Fig 3.4.1(a), a handshake
controller is comprised of a CD, a C-element; the input to
stage Si represents a valid code word or an empty code
word. The output of the CD transits from LOW to HIGH
when the input to stage Si becomes a valid code word, and
transits from HIGH to LOW when the input to stage Si
becomes an empty code word. If the input consists of n-bit
data, n pairs of wires are required to encode the input, and
the associated CD can be implemented with a n-input C-
element gate and n two-input OR gates.
The output of the C-element in HCi is connected to Vpi, the
power node of the ECRL gates in stage Si.
The SQRT CSLA is used for various multiplier
circuits in order to reduce the carry propagation delay.
There are various combinations of CSLA available for
achieving low area and low power. In two set of RCAs,
One RCA can be replaced by either D-Latch or Binary to
Excess1 code Converter (BEC) for providing efficient low
computation and low area.
In this work, the design of SQRT CSLA is
performed by using reduced half adder instead of full
adders with optimized AND, OR and XOR gates. Hence,
the area occupancy is reduced in proposed SQRT CSLA.

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 transistors based on static CMOS logic. In the static CMOS
logic, the transistor reduction is very difficult when
compared to the PTL (Pass Transistor logic),
Complementary logic, CBL logic etc… The structure of
reduced full adder is shown in fig4.1. This full adder
structure is used to design reduced ripple carry adder.

Fig 4. Block diagram of reduced carry select adder

The block diagram of reduced CSLA is shown in

fig4. The reduced CSLA consists of half adder (HA), And
Or logic and XOR circuits. The internal diagram of half
adder, XOR gate, And Or logic is shown in Fig4.2. The
reduced AND gate is constructed using only 4 transistors
instead of 6transistors; OR gate is designed using 4
transistors instead of 6 transistors; and the reduced XOR
gate is applied in the Reduced CSLA. The optimized half
adder is constructed by using only 6 transistors based on
static CMOS technology [5]. All these gates and half adder
are incorporated into reduced Carry Select Adder as shown
Fig4.2 Circuit diagram of reduced half adder, AND &OR gates
in Fig4. Comparison between reduced CSLA and reduced
ripple carry adder structure with optimized AND, OR, using CBL logic.
XOR and half adder structures is performed to analyze
these working principle and power utilization [9]. Finally, the reduced ripple carry adder and
compact carry select adder are combined to make 8-bit
hybrid adder. This hybrid adder is compared with the
existing Kogge-stone adder. The proposed hybrid adder is
designed with asynchronous fine grain pipelined with
partial charge reuse (PCR) technique and without PCR
circuits.
IV. RESULTS AND DISCUSSION
In this work, the hybrid adder with reduced SQRT
CSLA and reduced RCA, full adder as well as half adder is
presented to reduce the area and power utilization. Tanner
Tool 14.11 is used to design Adder units. Power
consumption is calculated by using T-SPICE in Tanner.
The area reduction is performed by calculating the number
of NMOS and PMOS utilization. The comparison between
existing and proposed adder are carried out to analyse the
performance.
Fig4.1Circuit diagram of reduced full adder using CBL logic

The reduced full adder structure is designed by

using reduced half adder and XOR gate based on static
CMOS logic. Till now there is no full adder design with 16

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 Fig5.1 Schematic of CBL based CSLA

Fig.5.5 Schematic of Hybrid Adder using AFPL

Fig.5.2 Simulation output of CSLA

Fig.5.6 Power Output of Hybrid adder using AFPL

Fig.5.3 Schematic of Ripple Carry Adder

Fig.5.7 Power report of Hybrid adder using AFPL

NAME OF THE TRANSISTOR POWER

ADDER COUNT

HYBRID 188 124468 (nWatt)

ADDER
Fig.5.4 Simulation output of RCA
Table 1 shows the report of area and power

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 V. CONCLUSION [7] Heung JunJeon, Yong-Bin Kim, Senior Member,
IEEE, and Minsu Choi, Senior Member, IEEE ,
In this work, a new 8-bit hybrid adder with
“Standby Leakage Power Reduction Technique for
compact carry select adder (CSLA) and reduced ripple
Nano scale CMOS VLSI Systems”, IEEE
carry adder (RCA) is designed by using asynchronous fine
transaction on instrumentation and measurement,
grain pipelined (AFPL) technique with partial charge reuse
vol. 59, no. 5, may 2010
technique. The reduced full adder, half adder, AND, OR
[8] Carlos Ortega, Jonathan Tse, and Rajit Manohar,
and XOR gates based on gate diffusion input logic (GDI)
“Static Power Reduction Techniques for
is applied in the hybrid adder units. In the existing
Asynchronous Circuits” 2010
technique, Kogge-stone adder is designed by using
[9] T. Lin, K.-S. Chong, B.-H.Gwee, and J. S. Chang,
asynchronous fine grain pipelined technique with partial
“Fine-grained power gating for leakage and short-
charge reuse technique. These two adders are designed and
circuit power reduction by using asynchronous-
the results are analyzed. From the obtained results, it is
logic,” in Proc. IEEE Int. Symp. Circuits Syst., May
shows that the proposed hybrid adder with CSLA and RCA
2009, pp. 3162–3165.
offers low area and low power than the existing adder
[10] Dr.J.Karpagam, A.Arunadevi, “High performance
circuits. The 45nm CMOS technology is used to design the
ripple carry adder using domino logic”,
adder
International research journal of engineering and
technology (IRJET) e-ISSN: 2395-
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