Simple As Possible Computer

Simple As Possible
Computer
Md. Ayaz Masud

EEE 315: MICROPROCESSOR & INTERFACING
3/14/2016 Lecturer, Dept of EEE, BUET
Block Diagram
Md. Ayaz Masud

Instruction Set
1. LDA <memory address>
accumulator=content of memory address
2. ADD <memory address>
accumulator<=acc. + content of mem.
3. SUB <memory address>
accumulator<=acc. - content of mem.
1,2,3: Memory Reference Instruction

Md. Ayaz Masud
Instruction Set
4. OUT
out register = accumator
5. HLT
-stops clock
Md. Ayaz Masud

Example
25-9+10-18=?
-Load 25 in accumulator
-Subtract 9 from 25
-Add 10 with the result
-Subtract 18
-Show output
Md. Ayaz Masud

Example
25-9+10-18=?
F 00010010 7 XXXXXXXX
Source Machine
E 00001010 6 XXXXXXXX
Code Code
D 00001001 5 1111XXXX
LDA CH 00001100
C 00011001 4 1110XXXX
SUB DH 00101101
B XXXXXXXX 3 00101111
ADD EH 00011110
A XXXXXXXX 2 00011110
SUB FH 00101111
9 XXXXXXXX 1 00101101
OUT 1110XXXX
8 XXXXXXXX 0 00001100
HLT 1111XXXX
Md. Ayaz Masud
Control Word
CON=
= 00 1 1 1 1 1 0 0011
=3E3 H
Md. Ayaz Masud

Timing (T) States
• Controller/Sequencer controls all the
operations. Each instruction is executed
through a series of step. Each such step
is called a Timing state (T state)
• The 6 bit Ring Counter produces 6 T
states for SAP-1
• Different CON words are produced in
different T states
Md. Ayaz Masud
T states
Md. Ayaz Masud

Fetch Cycle : T1
CON= 0101 1110 0011

=5E3 H
T1: Address State
Md. Ayaz Masud

Fetch Cycle : T2
CON= 1011 1110 0011

=BE3 H
T2:Increment State
Md. Ayaz Masud

Fetch Cycle : T3
CON= 0010 0110 0011

= 26 3 H
T3: Memory State
Md. Ayaz Masud

Execution Cycle : T4 <LDA>
CON= 0001 1010 0011

= 1A3 H
Md. Ayaz Masud

CON= 0010 1100 0011

= 2C3 H
Md. Ayaz Masud

3/14/2016 EEE 315: MICROPROCESSOR & INTERFACING Lecturer, DeptMd. AyazBUET
of EEE, Masud
CON= 0011 1110 0011

= 3E3 H
NOP
Md. Ayaz Masud

3/14/2016 EEE 315: MICROPROCESSOR & INTERFACING Lecturer, DeptMd. AyazBUET
of EEE, Masud
Microprogramming
• Each control word is called a microinstruction
• Microprogramming is an alternate way of

building controller-sequencer by storing
every microinstruction in a ROM sequentially.
-starting address of routine

-stepping through the routine addresses
-applying them to control ROM
Md. Ayaz Masud

ADDRESS CONTENT ROUTINE
0 5E3 FETCH
1 BE3 Microprogramming
2 263
3 1A3 LDA
4 2C3 Control ROM
5 3E3
6 1A3 ADD
7 2E1 Address ROM
8 3C7
ADDRESS CONTENT
9 1A3 SUB
0000 3
A 2E1
0001 6
B 3CF
0010 9
C 3F2 OUT
……
D 3E3
1110 c
E 3E3
F X
Md. Ayaz Masud
Microprogramming
Md. Ayaz Masud

3/14/2016 EEE 315: MICROPROCESSOR & INTERFACING
Lecturer, Dept of EEE, BUET
3/14/2016
Simple As Possible
Computer
(SAP-2)
Reference: Malvino . Brown

Chapter 11
Md. Shafiqul Islam

Block Diagram
Md. Shafiqul Islam

1
3/14/2016
Input Port
Two input ports, numbered 1 & 2
Hexadecimal keyboard encoder is
connected to port 1 and also sends READY
signal to bit 0 of port 2 and SERIAL_IN to bit
7 of port 2
Md. Shafiqul Islam

Program Counter
PC has 16 bits
Can count from
PC=0000 0000 0000 0000 (0000H)
to
PC=1111 1111 1111 1111 (FFFFH)
Md. Shafiqul Islam

2
3/14/2016
MAR and Memory

During fetch cycle MAR receives 16-bit
addresses from PC
64K (2^16) memory (Address: 16 bits,
Data: 8 bits)
Memory has 2K ROM with address of
0000H to 07FFH
Rest of the memory is 62K RAM with
address 0800H to FFFFH
Md. Shafiqul Islam
Memory Data Register

MDR is an 8 bit buffer register
Receives data from the W bus during a
write operation
Sends data to the W bus during a read
operation
Md. Shafiqul Islam

3
3/14/2016
Instruction Register
• SAP-2 has total 42 (101010) instructions.
So we will use 8 bit op-codes
Md. Shafiqul Islam

Controller/Sequencer
Will produce the CON words or

microinstructions
Md. Shafiqul Islam

4
3/14/2016
Accumulator
Two state output goes to ALU and three state
output to W bus
Md. Shafiqul Islam

ALU and Flags

ALU has 4 or more control bits those
determine which arithmetic or logic
instruction has to be performed
Flag is a flip-flop that keeps track of
changing condition. SAP-2 has two flags
Sign flag (is set when the accumulator
content becomes -ve) & Zero flag (is set
when the accumulator content becomes
zero)
Md. Shafiqul Islam
5
3/14/2016
TMP, B & C Registers

Instead of B, TMP (temporary) register is
used to add or subtract from accumulator
Besides B & TMP, SAP-2 also has C
register
Md. Shafiqul Islam

Output Port
Two output ports, numbered 3 & 4
Contents of accumulator is loaded into
port 3, which drives a hexadecimal
display
Port 4 has SERIAL_OUT signal to its 0 bit
and ACKNOWLEDGE signat to its 7 bit
Md. Shafiqul Islam

6
3/14/2016
Mnemonics and Op-code

Mnemonics Op code Mnemonics Op code
ADD B 80H HLT 76H
ADD C 81H IN byte DBH
ANA B A0H INR A 3CH
ANA C A1H INR B 04H
ANI byte E6H INR C 0CH
CALL address CDH JM address FAH
CMA 2FH JMP address C3H
DRC A 3DH JNZ address C2H
DCR B 05H JZ address CAH
DCR C 0DH LDA address 3AH
Md. Shafiqul Islam

EEE 315: MICROPROCESSOR & INTERFACING Lecturer, Dept of EEE, BUET
3/14/2016
Mnemonics and Op-code

Mnemonics Op code Mnemonics Op code
MOV A,B 78H ORA C B1H
MOV A,C 79H ORI byte F6H
MOV B,A 47H OUT byte D3H
MOV B,C 41H RAL 17H
MOV C,A 4FH RAR 1FH
MOV C,B 48H RET C9H
MOV A,byte 3EH STA address 32H
MOV B,byte 06H SUB B 90H
MOV C,byte 0EH SUB C 91H
NOP 00H XRA B A8H
ORA B B0H XRA C A9HH
Md. Shafiqul Islam
7
3/14/2016
LDA address
LDA 8000H : Load the accumulator with the
content of address 8000H
RAM address Content

2000H 3A H
2001H 00 H
2002H 80 H
Md. Shafiqul Islam

LDA 8000H
T1 State: Address State
 Output of PC is
2000H
 2000H is sent to the
W bus
 MAR loads 2000H
 The content of
address 2000H of
RAM is available
Md. Shafiqul Islam
8
3/14/2016
LDA 8000H
T2 state: Increment
State
 PC has increased its
value to 2001H
 2001H is now
available at PC’s
output
Md. Shafiqul Islam

LDA 8000H
T3 State: Memory State
 MDR enables the
content of RAM
address to W bus
 IR loads the content
Md. Shafiqul Islam

9
3/14/2016
LDA 8000H
Execution Cycle: T4
 PC’s output 2001H is

enabled to W bus
 Content of W bus is
loaded to MAR
Md. Shafiqul Islam

LDA 8000H
Execution Cycle: T5
 PC increases its
output to 2002H
 Content of address
2001H is enabled to
W bus and loaded to
B register
Md. Shafiqul Islam

10
3/14/2016
LDA 8000H
Execution Cycle: T6
 PC’s output 2002H is
enabled to W bus
loaded to MAR
Md. Shafiqul Islam

LDA 8000H
Execution Cycle: T7
 PC increases its
value to 2003H
 Content of 2002H is
enabled to W bus
and loaded to C
register
Md. Shafiqul Islam

11
3/14/2016
LDA 8000H
Execution Cycle: T8
 Contents of B & C
registers are enabled
to W bus to create
the 16 bit address
8000H
 16 bit address is then
loaded to MAR
Md. Shafiqul Islam

LDA 8000H
Execution Cycle: T9
 Content of memory
address 8000H is
enabled to W bus
loaded to the
Accumulator
Md. Shafiqul Islam

12
3/14/2016
JUMP Instruction
 Instead of fetching
the next instruction
in the usual way,
jumps to another part
of program, e.g.
JMP 3000H
 Unconditional Jump
Md. Shafiqul Islam

JUMP Instruction
 JM 3000H : Jump to
address 3000H if the
sign flag is 1 (content
of accumulator is -ve)
 Otherewise fetch the
next instruction at
2006H
 Conditional Jump
Md. Shafiqul Islam

13
3/14/2016
CALL and RET

 CALL 5000H : Call the
subroutine starting
from 5000H
 RET : return, Have to
return to the address
next to the address
where CALL 5000H
was stored
 CALL is
unconditional
Md. Shafiqul Islam

CALL and RET

 When CALL is
executed, the content
of PC is automatically
saved in memory
locations FFFEH and
FFFFH
 Infinite Loop?
Md. Shafiqul Islam

14
3/14/2016
Thank You
Md. Shafiqul Islam

15
3/15/2016
Simple As Possible
Computer
(SAP-3)
Reference: Malvino . Brown

Chapter 12
Md. Shafiqul Islam

CALL and RET of SAP-2

 When a CALL is
executed, the
contents of PC are
automatically saved
in memory locations
FFFE H & FFFF H
Md. Shafiqul Islam

1
3/15/2016
SAP-2 Stack
Stack is a portion of
memory set assigned
primarily for saving
return address
Md. Shafiqul Islam

The Stack of SPA-3

 SAP-3 has a stack
between 20E0 H and
20FF H, 32 memory
locations for saving
return addresses
 Can be anywhere and
of any size depending
on the program
 Can’t be use for data &
instruction anymore
Md. Shafiqul Islam

2
3/15/2016
Stack Instructions
Instructions that are read and write into the stack
are called stack instruction
 CALL address and RET
 PUSH register: Contents of the register have to
be stored in the stack
 POP register: Contents of a specific stack
memory have to be restored in the register
Stack: First in Last out

Md. Shafiqul Islam
Stack Pointer
 16-bit register that
holds the desired
memory location of
20FC H stack which is
20FD H available is called
20FE H
SP Stack pointer (SP)
20FF H
 SP points 20FF H,
means we can write
address at that
location
Md. Shafiqul Islam
3
3/15/2016
Stack Pointer
 00H is stored in 20FF
H memory
20FC H
20FD H
20FE H
SP
20FF H 00 H
Md. Shafiqul Islam

Stack Pointer
 SP now points 20FE
H, means 20FE H is
available to store a
20FC H new value
20FD H
SP
20FE H
20FF H 00 H
Md. Shafiqul Islam

4
3/15/2016
Stack Pointer
 20H is then stored in
20FE H address
20FC H
20FD H
SP
20FE H 20 H
20FF H 00 H
Md. Shafiqul Islam

Stack Pointer
20FC H
SP
20FD H
20FE H 20 H
20FF H 00 H
Md. Shafiqul Islam

5
3/15/2016
20FC H
20FD H
SP
20FE H 20 H
20FF H 00 H
Md. Shafiqul Islam

Stack Pointer
20FC H
20FD H
SP
20FE H
20FF H 00 H
Md. Shafiqul Islam

6
3/15/2016
Stack Pointer
20FC H
20FD H
20FE H
SP
20FF H 00 H
Md. Shafiqul Islam

Stack Pointer
20FC H
20FD H
20FE H
SP
20FF H
Md. Shafiqul Islam

7
3/15/2016
Thank You
Md. Shafiqul Islam

8
Intel 8086
Architecture
Md. Ayaz Masud

Fifth Generation Pentium
Fourth Generation
During 1980s
Third Generation Low power version of HMOS technology
During 1978 (HCMOS)
HMOS technology  Faster speed, Higher 32 bit processors
packing density Physical memory space 224 bytes = 16 Mb
16 bit processors  40/ 48/ 64 pins Virtual memory space 240 bytes = 1 Tb
Easier to program Floating point hardware
Dynamically relatable programs Supports increased number of addressing
Processor has multiply/ divide arithmetic modes
hardware
More powerful interrupt handling Intel 80386
capabilities
Flexible I/O port addressing Second Generation
During 1973
Intel 8086 (16 bit processor) NMOS technology  Faster speed, Higher
density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are
multiplexed Intel 8085 (8 bit processor)
2
Md. Ayaz Masud
Key Features
• First introduced in 1978
• 16 bit microprocessor with 16 bit bus
• Main memory of 1 MB
• 5 MHz
• 6 Byte instruction cache
• 117 instructions
• 64kB i/o ports
Md. Ayaz Masud

Pin Diagram
Md. Ayaz Masud

Functional Blocks
Register array or Data Bus
internal memory
ALU
Instruction decoding
unit
Flag Register
Timing and
control unit PC/ IP
Control Bus Address Bus
Md. Ayaz Masud

Execution Unit (EU)
EU executes instructions that

have already been fetched by
the BIU. Architecture
BIU and EU functions
separately.
Bus Interface Unit (BIU)
BIU fetches instructions, reads data

from memory and I/O Md.ports, writes
Ayaz Masud
data to memory
4/4/2016 Lecturer,and
DeptI/ O ports.
of EEE, BUET
Architecture
BIU performs the following actions
• Sends out address
• Fetches instruction from memory
• Read data from port and memory
• Write data to port and memory
EU performs the following actions
• Tells BIU where to fetch instruction from
• Decode instructions to determine operations
• Execute operations and store the results in general
operators
Md. Ayaz Masud
Architecture
EU has no connection to system buses. It

receives and outputs all its data through
BIU
Md. Ayaz Masud

Flags
• 8086 has 9 flag registers- status flags(6) and
control flags(3)
• Status flags are
1. Carry flag (CF)
2. Parity flag (PF)
3. Overflow flag (OF)
4. Zero flag (ZF)
5. Sign flag(SF)
6. Auxiliary flag(AF)
Md. Ayaz Masud
Flags
Control flags are
1. Trace flag(TF)
2. Interrupt flag (IF)
3. Direction flag (DF)
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
U U U U OF DF IF TF SF ZF CF AF U PF U CF
Md. Ayaz Masud

REGISTERS
• 8086 has 14 general purpose registers,
each of which are 16 bits in size
• DATA Registers
-AX (Accumulator Register)
-BX (Base Register)
-CX (Count Register)
-DX(Data Register)
• The high and low byte of data registers
can be accessed separately
Md. Ayaz Masud
REGISTERS
• Index Registers
-SI (Source Index)
-DI (Destination Index)
• Point Registers
-IP (Instruction Pointer); usually inaccessible
-BP (Base Pointer)
-SP (Stack Pointer)
BP,SI,DI are mostly used as pointers
Md. Ayaz Masud
REGISTERS
• Segment Registers
-CS (Code Segment)
-DS (Data Segment)
-SS (Stack Segment)
-ES (Extra Segment)
Md. Ayaz Masud

Program Segments
• CS:IP –points to the physical address of
the next instruction to be executed
• SS:SP –points to the stack
• DS:DI – points to the physical address in
memory where data is to be stored next
• DS:SI - points to the physical address in
memory where data is to be read from
Md. Ayaz Masud

ASSEMBLY for8086
Md. Ayaz Masud

Types of Programming Language
• Machine Language
• Assembly Language
• High-Level Language
Md. Ayaz Masud

Assembly vs HLL
Advantages of HLL Advgs of Assembly
• Easier to write • Closer to Machine
• Easier to code
understand • Access to specific
• Better control memory location
• Doesn’t depend on • Helps understand
particular machine how computer
actually works
Md. Ayaz Masud

Remember
• ASSEMBLY language program is machine
specific
• ASSEMBLER converts it into machine
code
• Not case-sensitive
Md. Ayaz Masud

Syntax
• Each line of an ASSEMBLY program
contains a statement
• A statement can either be an instruction
or an assembler directive
• Instruction: MOV, SHL, JMP etc
• Assembler Directive: ORG, ASSUME, END
etc (Pseudo Op-Code)
Md. Ayaz Masud

Synatx
General syntax for a statement is
Name: Instruction Operand(s) ; Comment
Example:
MYLABEL : MOV AX,BX ; abrakadabra
Md. Ayaz Masud

Name Field
• Used for instruction labels, procedure
names and variable names
• 1 to 31 characters long
• Can contain letters, digits and following
special characters
. ? _ @ $ %
• Period must be used at the beginning
Md. Ayaz Masud

Syntax
• Operand : There can be 1,2 or no operand
at all. For two operands, generally, they are
Destination, Source
• Comment : Anything after (;)
• One of the operands can be a data
MOV AX,10 MOV AX,10D

MOV AX, 1010B MOV AX,0AH
Md. Ayaz Masud
Syntax
• Hex number cant start with an alphabet
• +/- sign is allowed
• String or character is allowed as data
MOV AX, ‘AB’

MOV AX,0ABCDH
MOV AX, ABCD
MOV AX, ABCDH
Md. Ayaz Masud
Variables
Byte 8 DB
Word 16 DW
Double Word 32 DD
Quad Word 64 DQ
Ten Bytes 80 DT
MYBYTE DB 15
MYWORD DW ?
MYARRAY DB 4,5,6,?,?,?
MYSTRING DB ‘abrakadabra’
Md. Ayaz Masud
Named Constant
• Name EQU constant
MYCONSTANT EQU 5
• EQU is a pseudo-opcode
• Constant can be a string as well
Md. Ayaz Masud

MOV
MOV destination, source
Source Destination Operand
Operand General Segment Memory Constant
Register Register Location
General X
Register
Segment X X
Register
Memory X X
Location
Constant X X
-no change in flag

Md. Ayaz Masud
XCHG
XCHG destination, source
Source Destination
Operand Operand
General Memory
Register Location
General
Register
Memory X
Location
-no change in flag

Md. Ayaz Masud
ADD/SUB
ADD destination, source
Source Destination
Operand Operand
General Memory
Register Location
General
Register
Memory X
Location
Constant
-all flags are updated

Md. Ayaz Masud
INC/DEC
• Single operand instruction
• INC destination
• Destination is either a register or a
memory location.
• Updates all flags but CF
INC AX ; ax++
DEC MYBYTE; mybyte - -
Md. Ayaz Masud
NEG
• Single operand instruction
• NEG destination
• Destination is either a register or a
memory location.
• Updates all flags
CF=1 unless result is 0
OF=1 if word destination is 8000h or
byte destination is 80h
Md. Ayaz Masud
Type Agreement of Operands
• The operands of preceding two operand
instructions must be of the same type
MOV AX, MYBYTE ; illegal
MOV AH, ‘A’ ; ah=41H

MOV AX, ‘A’ ; ax =0041H
Md. Ayaz Masud

ORG
• ORG stands for origin
• Assembler directive
• Displacement from the start of a segment
ORG 1000H
ORG $+1000H
Md. Ayaz Masud

Arrays
Addressing Modes
Md. Ayaz Masud

Array
ORG 1600H
MYARRAY DB 1,2,3,-3,-2,-1,?
DS:1600 1600 1 MYARRAY

1601 2 MYARRAY+1
1602 3 MYARRAY+2
1603 -3 MYARRAY+3
1604 -2 MYARRAY+4
1605 -1 MYARRAY+5
1606 x MYARRAY+6
Md. Ayaz Masud

Array
ORG 1600H
MYWARRAY DW 1,2,0ABCDH,?
DS:1600 1600 01 MYWARRAY

1601 00 MYARRAY+1
1602 02 MYARRAY+2
1603 00 MYARRAY+3
1604 CD MYARRAY+4
1605 AB MYARRAY+5
1606 X MYARRAY+6
Md. Ayaz Masud

Array
• Lower byte of the word is stored in the
lower address while the higher byte will
be stored in the next address
• For an array named MYARRAY, address
of the k-th element,
MYARRAY + (k-1)*S
Where S is the size of each element (1 for
byte, 2 for word)
Md. Ayaz Masud
DUP
MYARRAY DB 10 DUP (0)
0,0,0,0,0,0,0,0,0,0
MYARRAY DB 1,2,3, 7 DUP(4)

1,2,3,4,4,4,4,4,4,4
MYARRAY DB 3, 2 DUP (5,6, 2 DUP(4),5),8

3, 5,6,4,4,5,5,6,4,5,5,8
Md. Ayaz Masud
Addressing Modes
• The way an operand is specified is known as
its addressing mode.
• Register Mode- when operand is a register
• Immediate Mode- when operand is a constant
• Direct Mode-when operand is a variable
• MOV AX, BX
• SUB AX, 12
• MOV DATA1,AX
Md. Ayaz Masud
Register Indirect Mode
• The offset address of a memory content is
contained in a register. The register acts as
a pointer to that memory.
• Format : [register]
• Allowed Registers: BX,SI,DI,BP
• For BX,SI & DI, DS contains the segment
address and for BP, SS is the segment.
Md. Ayaz Masud

Register Indirect Mode
MOV BX, 1000H
MOV DX,BX
MOV AX, [BX] DS: 1000H 1000H 5E H
HLT 1001H 12 H
1002H AB
1003H 34
;DX=1000H
1004H 22
;AX=125E H
Md. Ayaz Masud

Based & Index Modes
• The operand’s offset is obtained by adding
a ‘displacement’ with the content of a
register.
• Format:
[Register + Displacement] MOV AX, [BX+2]
[Displacement + Register] MOV AX,[2+BX]
AX=34ABH
[Register] +Displacement MOV AX,[BX]+2
Displacement+ [Register] MOV AX, 2+[BX]
Displacement[Register] MOV AX, 2[BX]
Md. Ayaz Masud
Based & Index Modes
• The addressing mode is based for BX,BP
• The addressing mode is index for SI,DI
• Displacement can be negative:
MOV AX,-2[BX]
• Displacement can be a numerical value
or name of a variable/array
Md. Ayaz Masud

Based & Index Modes
ORG 1000H
MYWARRAY DW 1,2,0ABCDH
[Register + Displacement] MOV AX, [BX+MYWARRAY]

[Displacement + Register] MOV AX,[MYWARRAY+BX]
[Register] +Displacement MOV AX,[BX]+MYWARRAY
Displacement+ [Register] MOV AX, MYWARRAY+[BX]
Displacement[Register] MOV AX, MYWARRAY[BX]
Md. Ayaz Masud

LEA
• LEA=Load Effective Address
• Loads the offset of a variable in a register
LEA BP, MYWARRAY; bp=1000h
ORG 1000H
MYWARRAY DW 1,2,0ABCDH
Md. Ayaz Masud

PTR
MOV BX,10H; bx=0010h
MOV [BX],1 ; ????
-creates ambiguity
-PTR assembler directive is used to solve it
MOV BYTE PTR BX,1; [1000]=1

MOV WORD PTR BX, 1; [1000]=1;[1001]=0
Md. Ayaz Masud
2D Array
Row Major Format
MY2DARRAY DB 1,2,3
DB 4,5,6
DB 7,8,9
MY2DARRAY DB 1,2,3,4,5,6,7,8,9
Column Major Format

MY2DARRAY DB 1,4,7
DB 2,5,8
DB 3,6,9
MY2DARRAY DB 1,4,7,2,5,8,3,6,9
Md. Ayaz Masud
2D Array
For a M x N array A declared in Row Major Format,
Location of A(i , j)=A+{(i-1)N + (j-1)} S
When declared in Column Major Format,
Location of A(i , j)=A+{(j-1) + (i-1)M} S
Md. Ayaz Masud

Based Indexed Addressing Mode
• Array_Name [Base Register] [Index Register]

MOV AX, W [BX][SI]
• [Array_Name +Base Register + Index Register+ Constant]
MOV AX, [W+BS+SI+3]
MOV AX,[W+BX+SI]
• Array_Name [Base Register+Index Register+Constant]
MOV AX, W[BX+SI+3]
• Constant [Array_Name +Base Register+Index Register]
MOV AX, 3[W+BX+SI]
 The order of terms within bracket is arbitrary
Md. Ayaz Masud
Label
ORG 1500H
CGPA LABEL WORD
INT DB 3
FRAC DB 50
MOV AX, WORD PTR INT ;ah=50, al=3
MOV AX, CGPA
Md. Ayaz Masud

XLAT
• No operand instruction used to translate
/code/decode
• AL<= [BX+AL]
• BX will have the address of conversion
table
• The byte to be converted will be in AL
• XLAT adds AL with the address in BX,
goes to the address and copies that ‘byte’
in AL
Md. Ayaz Masud
Md. Ayaz Masud
Overflow, Shift , Rotate
Md. Ayaz Masud

Overflow
Decimal Decimal Decimal Decimal
Range of Range of Range of Range of
Signed Unsigned Signed Unsigned
Numbers in a Numbers in a Numbers in a Numbers in a
Word Word Byte Byte
-32768 to 32767 0 to 65535 -128 to 127 0 to 255
When the result of an operation falls beyond this range, an overflow occurs
Md. Ayaz Masud

Overflow
• Signed Overflow
• Unsigned Overflow
In an arithmetic operation both signed

and unsigned overflow can occur
simultaneously.
Md. Ayaz Masud

Unsigned Overflow
8086 Operation:
Unsigned Signed
Interpretation Interpretation
Md. Ayaz Masud

Signed Overflow
8086 Operation:
Unsigned Signed
Interpretation Interpretation
Md. Ayaz Masud

Overflow vs Carry
• CF=1 for unsigned overflow
• OF=1 for signed overflow
• Processor doesnot interpret the result as
either signed or unsigned
• Its up to the programmer to interpret the
result and depending upon the convention
he is following, he will use a flag and
overlook the other
Md. Ayaz Masud
Flags for Logic Instructions
• SF,ZF,PF are updated after each logical

instruction
• CF=0 and OF=0
• NOT doesnot affect any status flags
Md. Ayaz Masud

Shift Instruction
• Opcode destination, 1
• Opcode destination, CL ; cl>1
• Shifts destination bit pattern at specified
direction
• Handy alternative of mul/div
CF=last bit shiftet out

OF=1; if sign changes
Md. Ayaz Masud
SHL
Shift Left
CF 1 1 0 1 1 0 1 1 0
1 1 0 1 1 0 1 1 0 0
1 0 1 1 0 1 1 0 0
0 1 1 0 1 1 0 0 0
Md. Ayaz Masud

SAL
Shift Arithmetic Left

CF 1 1 0 1 1 0 1 1 0
1 1 0 1 1 0 1 1 0 0
1 0 1 1 0 1 1 0 0
0 1 1 0 1 1 0 0 0
Md. Ayaz Masud

SHR
Shift Right
CF
0 1 1 0 1 1 0 1 1
0 1 1 0 1 1 0 1 1
0 0 0 1 1 0 1 1 0 1
0 0 0 1 1 0 1 1 0
Md. Ayaz Masud

SAR
Shift Arithmetic Right

1 0 1 1 0 1 1 CF
1/0
MSB 1 1 1 0 1 1 0 1 1
Retains 1 1 1 1 0 1 1 0 1
Value 1 1 1 1 1 0 1 1 0
Md. Ayaz Masud

ROTATE
• Opcode destination, 1
• Opcode destination, CL ; cl>1
• Rotates destination bit pattern at specified
direction
CF=last bit shiftet out

OF=1; if sign changes
Md. Ayaz Masud

ROL
Rotate Left
CF 1 1 0 1 1 0 1 1
1 1 0 1 1 0 1 1 1
1 0 1 1 0 1 1 1 1
0 1 1 0 1 1 1 1 0
Md. Ayaz Masud

ROR
Rotate Right
1 1 0 1 1 0 1 1 CF
1 1 1 0 1 1 0 1 1
1 1 1 1 0 1 1 0 1
0 1 1 1 1 0 1 1 0
Md. Ayaz Masud

RCL
Rotate Carry Left
CF 1 1 0 1 1 0 1 1
0
1 1 0 1 1 0 1 1 0
1 0 1 1 0 1 1 0 1
0 1 1 0 1 1 0 1 1
Md. Ayaz Masud

RCR
Rotate Carry Right

CF
1 1 0 1 1 0 1 1 0
0 1 1 0 1 1 0 1 1
1 0 1 1 0 1 1 0 1
1 1 0 1 1 0 1 1 0
Md. Ayaz Masud

Procedure,
Multiplication & Division
Md. Ayaz Masud

Procedures
 Decompose the original problem into a
series of sub-problems that are easier to
solve
 Main procedure contains the entry to the
program
 Main procedure calls one of the other
procedures
 These procedures can call each other and a
procedure can also call itself
 When one procedure calls another, control
transfers to the called procedure
Md. Ayaz Masud
Procedures
 Syntax:
name PROC type
;body of the procedure
RET
name ENDP
 Type (near or far) is optional
 Near: the statement that calls the procedure is in
the same segment as the procedure itself. NEAR
is assumed if type is omitted.
 Far: the statement that calls the procedure is in a
different segment.
Md. Ayaz Masud
Procedures
Main PROC
CALL PROC1
next instruction
PROC1 PROC
first instruction
RET
Md. Ayaz Masud

Procedures
The RET instruction causes control to
transfer back to the calling procedure.
Every procedure should have a RET
someplace (except the main procedure)
Usually it is the last statement in the
procedure
Md. Ayaz Masud

CALL and RET
 To invoke a procedure, the CALL instruction
is used.
 There are two kinds of procedure calls,
direct and indirect.
 Direct: CALL name
 Indirect: CALL address_expression
 address_expression specifies a register or
memory location containing the address of
a procedure.
Md. Ayaz Masud
EEE 315: MICROPROCESSOR & INTERFACING Lecturer, Dept of EEE, BUET
4/11/2016
Executing CALL instruction
The return address of the calling
program is saved on the stack. This is the
offset of the next instruction after the
CALL statement. CS:IP has segment:
offset of this instruction at the time when
the call is executed
 IP gets the offset address of the first
instruction of the procedure. This
transfers control to the procedure.
Md. Ayaz Masud
Before CALL
CODE SEGMENT STACK SEGMENT
OFFSET Content OFFSET Content
address address
Main PROC
IP 0010H CALL PROC1 00FCH

0012H next instruction 00FDH
……. 00FE H
PROC PROC1 00FF H
0200H first instruction SP 0100 H
……..
0300H RET
Md. Ayaz Masud
After CALL
address address
Main PROC
0010H CALL PROC1 00FCH

……. SP 00FE H 12H
PROC PROC1 00FF H 00H
IP 0200H first instruction 0100 H
……..
0300H RET
Md. Ayaz Masud
Executing RET instruction
 Syntax: RET pop_value
 The integer argument pop_value is
optional.
 For a NEAR procedure, execution of RET
causes the stack to be popped into IP.
 If a pop value N is specified, it is added to
SP and thus has the effect of removing N
additional bytes from the stack.
 CS:IP now contains the segment:offset of the
return address and control returns to the
calling program.
Md. Ayaz Masud
Before RET
address address
Main PROC

……. SP 00FE H 12H
PROC PROC1 00FF H 00H
0200H first instruction 0100 H
……..
IP 0300H RET
Md. Ayaz Masud
After RET
address address
Main PROC

IP 0012H next instruction 00FDH
……. 00FE H XX
PROC PROC1 00FF H XX
0200H first instruction SP 0100 H
……..
0300H RET
Md. Ayaz Masud
Multiplication Instruction
 Syntax:
MUL source (for unsigned multiplication)
IMUL source (for signed multiplication)
 If two bytes are multiplied, the product is a
word (16 bits).
 If two words are multiplied, the product is a
doubleword (32 bits).
 For multiplication of positive numbers both
MUL and IMUL give the same result.
Md. Ayaz Masud

Multiplication Instruction:
BYTE form
Multiplier in source byte
Multiplicand in AL
16 bit product in AX
The source may be a byte register, a
memory byte, but not a constant
MUL BL
MUL MYBYTE
Md. Ayaz Masud

WORD form
Multiplier in source word
Multiplicand in AX
Most significant 16 bits of product in DX
Least significant 16 bits of product in AX
The source may be a 16 bit register, a
memory word but not a constant
MUL BX
MUL MYWORD
Md. Ayaz Masud
Effect on Flags
SF, ZF, AF, PF : Undefined
CF/ OF:
Instruction CF/OF
0, if the upper half of the result is zero
MUL 1, otherwise
0, if the upper half of the result is the sign
IMUL extension of the lower half
1, otherwise
Md. Ayaz Masud

Examples
AX=FFFF H, BX=FFFF H
Instruction Decimal Hex DX AX CF/OF
Product Product
MUL BX 4294836225 FFFE0001 FFFE 0001 1
IMUL BX 1 00000001 0000 0001 0
AL=80 H, BL=FF H
Instruction Decimal Hex AH AL CF/OF
Product Product
MUL BL 32640 7F80 7F 80 1
IMUL BL 128 0080 00 80 1
Md. Ayaz Masud

Division Instruction
 Syntax:
DIV divisor (for unsigned multiplication)
IDIV divisor (for signed multiplication)
 The quotient and the remainder have the same
size as the divisor.
 All the flags are undefined
 Divide Overflow: If the quotient is too long to fit
in the destination, program terminates and the
system displays the message “Divide Overflow”
Md. Ayaz Masud

Division Instruction:
BYTE form
Divisor is an 8 bit register or memory
byte
16 bit dividend is in AX
8 bit quotient is in AL
8 bit remainder is in AH
Md. Ayaz Masud

Division Instruction:
WORD form
Divisor is a 16 bit register or memory
word
32 bit dividend is in DX:AX
16 bit quotient is in AX
16 bit remainder is in DX
Md. Ayaz Masud

Sign Extension of the Dividend
 Word division: If the dividend fits in AX only
– For DIV, DX should be cleared
– For IDIV, DX should be made sign extension of
AX. The instruction CWD (Convert Word to
Doubleword)will do the extension
 Word division: If the dividend fits in AL only
– For DIV, AH should be cleared
– For IDIV, AH should be made sign extension
of AL. The instruction CBW (Convert Byte to
Word) will do the extension
 CBW and CWD has no operands and has no effect
on flags
Md. Ayaz Masud

Advanced Arithmetic

5/2/2016
Double Precision Number
 Numbers stored in the 8086 based
microprocessors can be 8 or 16-bit numbers.
 Even for 16-bit numbers, the range is limited to 0
to 65535 for unsigned numbers and -32768 to
+327678 for signed numbers.
 To extend this range, a common technique is to
use 2 words for each number. Such numbers are
called double-precision numbers
 The range here is 0 to 2^(32)-1 or 4,294,967,295
for unsigned and -2,147,483,648 to 2,147,483,647
for signed numbers.
5/2/2016
Double Precision Number
• A double-precision number may occupy
two registers or two memory words.
• For example, if a 32-bit number is stored
in the two memory words A and A+2,
written A+2:A, then the upper 16 bits are
in A+2 and the lower 16 bits are in A.
• If the number is signed, then the MSB of
A+3 is the sign bit.

5/2/2016
Double Precision Addition
To add two 32 bit numbers, we first add
or subtract the lower 16 bits and then
add or subtract the higher 16 bits.
In case of addition, carry generated in
the addition of the lower 16 bit numbers
must be added to the sum of the higher
16 bit, which can be done by ADC
instruction (Add with Carry).
Syntax: ADC destination, source
5/2/2016
Double Precision Addition:
Example
Write instructions to add the 32 bit
number in A+2:A to the number in B+2:B
MOV AX, A; AX gets lower 16 bits of A

MOV DX, A+2; DX gets upper 16 bits of A
ADD B, AX; add the lower 16 bits to B
ADC B+2, DX ; add DX and CF to B+2

5/2/2016
Double Precision Subtraction
 To subtract two 32 bit numbers, we first
subtract the lower 16 bits and then subtract
the higher 16 bits.
 Borrow generated in the subtraction of the
lower 16 bit numbers must be subtracted
from the subtracted result of the higher 16
bit, which can be done by SBB instruction
(Subtract with Borrow).
 Syntax: SBB destination, source
5/2/2016
Double Precision Negation
Write instructions to form the negation of
A+2:A
NOT A+2
NOT A
ADD A, 1
ADC A+2, 0

5/2/2016
Double Precision Multiplication
1. AX ← A
2. DX:AX ← AX×BX
3. C ← AX
4. TEMP ← DX
5. AX ← A+2
6. DX:AX ← AX×BX
7. AX ← AX+TEMP
8. C+2 ← AX
9. DX ← DX+C (Carry)
10. C+4 ← DX

5/2/2016
Double Precision Division
 Division of a 48-bit number by a 16-bit
number
1. DX:AX ← A+4:A+2
2. Quotient AX, Remainder DX← DX:AX÷BX
3. Q+2 ← AX
4. AX ← A
5. Quotient AX, Remainder DX← DX:AX÷BX
6. Q ← AX, R ← DX
5/2/2016
Binary-Coded Decimal Numbers
 The BCD (binary coded decimal) number
system uses four bits to code each decimal
digit, from 0000 to 1001. The combinations
1010 to 1111 are illegal in BCD.
 Since only 4 bits are required to represent a
BCD, two digits can be placed in a byte. This
is known as packed BCD form(59=
01011001).
 In unpacked BCD form, only one digit is
contained in a byte(59=
0000010100001001).
5/2/2016
BCD Addition
 In BCD addition, we perform the addition on one
digit at a time.
 When addition performed using ADD
instruction, it is possible to obtain a non-BCD
result.
 For example if AL= 6d and BL=7d, the sum of 13
is in AL which is no longer a valid BCD digit.
 To adjust it is required to subtract 10 from AL and
place 1 in AH, then AX will contain the correct
sum.
 We can get the same result by adding 6 to AL
and clearing the high nibble.
5/2/2016
BCD Addition
 This adjustment is performed in 8086 if we add
the instruction AAA (ASCII Adjust for addition).
 AAA checks the lower nibble of AL. If it is greater
than 9 or the AF is set, then AAA adds 6 to AL,
clears the high nibble and adds 1 to AH.
 The following assembly code performs decimal
addition on the unpacked BCD numbers in AL
and BL.
MOV AH, 0
ADD AL, BL
AAA

5/2/2016
BCD subtraction
 BCD subtraction is also performed on one digit at a
time.
 When subtraction performed using SUB instruction,
it is possible to obtain a non-BCD result.
 For example to subtract 26 from 7, we put AH=2, AL=
6, BL = 7.
 After subtracting BL from AL, we obtain an incorrect
result in AL.
 To adjust it is required to subtract 6 from AL, clear
high nibble (most significant 4 bits) and subtract 1
from AH, then AX will contain the correct result.

5/2/2016
BCD subtraction
 This adjustment is performed in 8086 if we add the
instruction AAS (ASCII Adjust for subtraction) after
subtraction
 AAS checks the lower nibble of AL. If it is greater
than 9 or the AF is set, then AAS subtracts 6 to AL,
clears the high nibble and adds 1 to AH.
 The following assembly code performs decimal
subtraction on the unpacked BCD numbers in AL
and BL.
MOV AH, 0
SUB AL, BL
AAS
5/2/2016
BCD Multiplication
Two BCD digits can be multiplied to
produce one or two-digit product.
The product may not be a BCD digit.
AAM (ASCII Adjust for multiplication)
converts the result into BCD digits.
We put multiplicand in AL and multiplier
in BL, after multiplication AX contains the
product.
5/2/2016
BCD Multiplication
AAM divides the contents of AL by 10,
the quotient is placed in AH and
remainder is placed in AL
MOV AL, 9D
MOV BL, 8D
MUL BL ; AX=72D
AAM ; AH=07D and AL=02D
5/2/2016
BCD division
Convert the dividend in AX from to BCD
digits to their binary equivalent.
Do ordinary division, which puts quotient
in AL and remainder in AH.
Convert the binary quotient in AL to its
two digit equivalent in AX

5/2/2016
BCD division
 To divide 97 and 9, we put 0907 in AX and 9 in BL.
Before dividing using DIV, the contents in AH is
changed from 0907 to 97d=61h by AAD (ASCII adjust
for division).
 After ordinary binary division, AAM instruction must
follow to convert the contents to BCD format.
AAD
DIV BL
MOV R, AH ; Remainder
AAM ; CONVERTING THE QUOTIENT TO BCD FOR

5/2/2016
Floating-Point Numbers
In floating representation, each number
is represented in two parts, a mantissa,
which contains the loading significant
bits in a numbers and an exponent,
which is used to adjust the position of the
binary point.

5/2/2016
Floating-Point Numbers :
Example
 Multiplication of two numbers in Floating point representation
;A = 8000 0000 0000h = 8x16^(C) , B = 0.0000 0000 00F0h = Fx16^(-B)

;C=AxB
MOV AX, A
MUL B
MOV C, AX
MOV AX, A+2
ADD AX, B+2
MOV C+2, AX
HLT
A DW 8H, 0CH ;A = MANTISSA, A+2 = EXPONENT
B DW 0FH, -0BH ;B = MANTISSA, B+2 = EXPONENT
C DW ?, ? ;C = MANTISSA, C+2 = EXPONENT

5/2/2016
Thank You

5/2/2016
STACK
Md. Ayaz Masud

STACK MANAGEMENT
• A declared ‘1-D Data Array’

• Memory block in the RAM
• Last In First Out
• Used for temporary storage
DECLARATION
PUSH
• Saves a ‘WORD’ in stack
• PUSH source
• Lower Byte -> Lower Address of Stack
• Higher Byte -> Higher Address of Stack
• PUSH CX will save the current value of
CX in the address pointed by SP
POP
• Retrieves a ‘WORD’ from the stack
• POP destination
• POP CX gets the word from the address
pointed by SP
• Neither PUSH , nor POP works on byte
type registers.
USE OF BP
• SS:BP allows us to save SP value in BP
• Thus stack operation can be done
without perturbing stack
ILLUSTRATION
ILLUSTRATION OF PUSH AX
ILLUSTRATION OF PUSH BX
ILLUSTRATION OF POP CX
ILLUSTRATION OF POP AX
Intel 8086
Based Microcomputer
Md. Ayaz Masud

8086 Based Microcomputer
Md. Ayaz Masud

Read Cycle
Md. Ayaz Masud

Write Cycle
Md. Ayaz Masud

Address Decoder
• Produces a signal which enables a
particular RAM, ROM or PORT for a
particular address
• Ensures that only one device is active to
interact with data bus
Md. Ayaz Masud

Address Decoder
Md. Ayaz Masud

8255A
Md. Ayaz Masud

Methods of Parallel Data Transfer
a) Simple Output
b) Simple Strobe I/O
c) Single handshake
I/O
d) Double handshake
I/O
Introduction to 8255A
• The 8255A programmable peripheral
interface (PPI) implements a general-
purpose I/O interface
• Connects peripheral equipment to a
microcomputer system bus.
• External logic is not required to
interface peripheral devices.
Features
• Three 8-bit Peripheral Ports - Ports A, B, and C
• Three programming modes for Peripheral Ports: Mode 0
(Basic Input/Output), Mode 1 (Strobed Input/Output),
and Mode 2 (Bidirectional)
• Total 24 programmable I/O lines
• 8-bit bidirectional system data bus with standard
microprocessor interface controls
Block Diagram
Control Pin Connection
• 8255A has 8 data pins. They can be either connected to
the higher or lower bus of 8086.
• Depending on this architecture we have to fix the LSB
of 8086 data bus i.e. A0 (of 8086) for further operation
in this particular 8255 IC
• Thus A0 goes to address decoder and cannot be
connected to the control pins of 8255
• Rather A2 and A1 are connected to the control pins.
• Left pins from address bus then go to address decoder.
Modes
Mode 0
• Simple I/O
• Port C bits can be
individually set or reset.
• No handshaking
Mode 1
• Some of the Port C pins
are used as handshaking
bits
• If B is set as input in mode
1,
PC0-2 works as handshake
signal.
Modes
Mode1
• If A is set as input in mode 1, PC3-5 works as
handshake signal.
• PC6,PC7 is left as i/o
• If Port A is declared as output in mode 1, PC3, PC6 and
PC7 are used as handshake signals.
• If Port B is declared as output in mode 1, again PC0-2
are used as handshake signals.
• So if A is output in mode-1, PC4-5 are left for i/o
Modes
Mode 2
• Bidirectional handshake
• Only port A can be initialized in this mode
• PC3-7 are handshaking pins
• PC0-2 could be used as handshaking pins for Port B if
it is working in Mode 1.
• Or it could be used as i/o if Group B is working in
Mode 0.
Mode Definition Control Word
Example:
Initialize 8255 as follows:
PortB as Mode 1 Input

Port A as Mode 0 output
Port C upper as input
Port C bit 3 as output
Bit Set/Reset Control Word
Example:
Set Bit 3 of PORT C

IN and OUT instruction
• IN is used to READ data from a • OUT is used to WRITE data in a port
port • Fixed Port Format
• Fixed Port Format
OUT ADDRESS_PORT, AL; 8 bit
IN AL, ADDRESS_PORT; 8 bit OUT ADDRESS_PORT, AX; 16 bit
IN AX, ADDRESS_PORT; 16 bit
• Variable Port Format • Variable Port Format

MOV DX, ADDRESS_PORT MOV DX, ADDRESS_PORT
IN AL, DX; 8 bit OUT DX,AL; 8 bit
IN AX, DX; 16 bit OUT DX, AX; 16 bit
Code for SSD
Appendix
• ~STB : The strobe input loads data into the port latch
on a 0-to-1 transition.
• IBF : Input buffer full is an output indicating that the
input latch contain information.
• INTR : Interrupt request is an output that requests an
interrupts.
• ~OBF : Output buffer full is an output that goes low when

data is latched in either port A or port B. Goes low on ~ACK.
• ~ACK : The acknowledge signal causes the ~OBF pin
return to 0. This is a response from an external device.
Interrupt
Md. Ayaz Masud

Interrupt
An interrupt is a condition that causes
the microprocessor to temporarily work on a
different task, and then later return to its
previous task. Interrupts can be internal or
external.
Software Interrupt (INT)

Hardware Interrupt
-Non-maskable Interrupt (NMI)
-Interrupt Input (INTR)
Response to an Interrupt
i. PUSH FLAGS
ii. Disables the 8086 INTR interrupt
input by clearing the interrupt
(IF) in the flag register
iii. It resets the trap flag (TF) in the
flag register
iv. PUSH CS
v. PUSH IP
vi. It does an indirect far jump to the
start of the procedure written to
respond to the interrupt
Return from an Interrupt (IRET)
• IRET restores the flags by popping in the flag register.
This also reenables INTR.
• If INTR is still high, the program will again enter ISP.
• External hardware must be used to make sure that the
signal is made low before you reenable INTR.
• You can reenable INTR within your ISP using the
instruction : STI . Otherwise it will be active after
reaching IRET of your ISP.
Interrupt Vector Table
• You need a dedicated memory space to store the
staring CS-IP values of your ISPs.
• Each ISP requires a 2 Byte CS and a 2 Byte IP for its
starting address.
• First 1 kB memory (00000H-003FFH) of 8086 is
dedicated for storing CS and IP of ISPs.
• We can store 256 ISP in a single 8086
• Since the starting address of an ISP is called Interrupt
Vector (or Interrupt Pointer) , this address table is
called Interrupt Vector Table.
STI and CLI
• The 8086 INTR input allows some external signal to
interrupt the execution of a program
• If the interrupt flag (IF) is cleared, then the INTR input is
disabled (masked).
CLI = Clear Interrupt -> IF = 0
STI = Set Interrupt -> IF = 1
• These two instructions can be used anywhere in the
program.
• When the 8086 is reset, IF is automatically cleared . This
feature ensures that you will have the time necessary for
initializations before any interrupt occurs.
• For INTR interrupts, the interrupt type is sent to the 8086 from
an external device, Priority Interrupt Controller (8259A)
Interrupt Flag (IF)
• IF is automatically cleared when you enter
an ISP and set when you leave. However you
can still manually set IF with STI instruction
anywhere within the ISP.
• It is important to clear IF upon entering ISP
- Prevents a low priority interrupt while
processing one with higher priority.
-Does not allow same interrupt signal to
incur multiple ISP operation.
Priority of Interrupts
Interrupt Priority
Divide Error, INT n, Highest
INTO
NMI
INTR
Single Step Lowest
Priority Interrupt Controller
8259: Programmable Interrupt
Controller
8259 Block Diagram
Multiple Interrupts
8259 System Connection
Initialization Command
Word(ICW)
Word(ICW)
Word(ICW)
Word(ICW)
Initialization Sequence
Operation Command Word
(OCW)
(OCW)
(OCW)
Sample Program
Sample Program
Sample Program

Simple As Possible Computer

Încărcat de

Informații document

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Simple As Possible Computer

Încărcat de

Drepturi de autor:

Formate disponibile

Simple As Possible

Md. Ayaz Masud

Md. Ayaz Masud

1,2,3: Memory Reference Instruction

Md. Ayaz Masud

Md. Ayaz Masud

Md. Ayaz Masud

Md. Ayaz Masud

CON= 0101 1110 0011

T1: Address State

Md. Ayaz Masud

CON= 1011 1110 0011

Md. Ayaz Masud

CON= 0010 0110 0011

T3: Memory State

Md. Ayaz Masud

CON= 0001 1010 0011

Md. Ayaz Masud

CON= 0010 1100 0011

Md. Ayaz Masud

CON= 0011 1110 0011

Md. Ayaz Masud

• Microprogramming is an alternate way of

-starting address of routine

Md. Ayaz Masud

Md. Ayaz Masud

Reference: Malvino . Brown

Md. Shafiqul Islam

Md. Shafiqul Islam

Md. Shafiqul Islam

Md. Shafiqul Islam

MAR and Memory

Memory Data Register

Md. Shafiqul Islam

Md. Shafiqul Islam

Will produce the CON words or

Md. Shafiqul Islam

Md. Shafiqul Islam

ALU and Flags

TMP, B & C Registers

Md. Shafiqul Islam

Md. Shafiqul Islam

Mnemonics and Op-code

Md. Shafiqul Islam

Mnemonics and Op-code

RAM address Content

Md. Shafiqul Islam

Md. Shafiqul Islam

Md. Shafiqul Islam

 PC’s output 2001H is

Md. Shafiqul Islam

Md. Shafiqul Islam

Md. Shafiqul Islam

Md. Shafiqul Islam

Md. Shafiqul Islam

Md. Shafiqul Islam

Md. Shafiqul Islam

Md. Shafiqul Islam

CALL and RET

Md. Shafiqul Islam

CALL and RET

Md. Shafiqul Islam

Md. Shafiqul Islam