VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

CONTENTS

DATE OF DATE OF
S.NO NAME OF EXPERIMENT REMARKS
EXPERIMENT SUBMISSION
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

EXPERIMENT: - 1

AIM: - STUDY OF VHDL LANGUAGE

Introduction to VHDL

VHDL stands for VHSIC Hardware Description Language VHSIC is acronym for very high
speed integrated circuit. VHDL is hardware description language used to model any digital
system. In this language we can check the functionality of any digital system from gate level to
chip level.

VHDL is amalgation of 5 languages:

Sequential language
Concurrent language
Net list language
Timing specification
Waveform generation language

By this language we can express behavior of any digital system. We can also model any digital
system as interconnection of its component. Model written in this language can be verified using
VHDL simulator.

Main Features of VHDL

1. The language is used as an exchange medium between chip vendor and CAD tool users .
2. The language support hierarchy. Digital system can be model in term of its components.
3. Language support top down and bottom up approach.
4. Language support both synchronous and asynchronous model.
5. It is an IEEE and ANSI standard, so model described in this language are portable.
6. Faculty to define new data types model retaining this language can be verified by
simulation.
7. Propagation delay set up holding time can also be described in this language.
8. Language is technology independent but it is capable of support technology specific
features.
9. Model written in this language can be verified by simulation.
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

Design units or primary constructs

A hardwre abstraction is called entity. when an entity A is used in entity B ,it is called
component. Hence a component is also an entity.

To dscribe any hardwre system or entity VHDL has 5 design units or primary constructs.

Entity declaration
Architecture Body
Configuration
Package Declaration
Package Body

Entity Declaration

Entity declaration describes external view of an entity. It specifies name of entity and list of
interfacing ports. Interfacing ports are input and output signals ,through wich entity
communicates with other entite.

For example, consider the AND gate AG.

So we declare the entity as below:

Entity AG is
Port (a,b: in bit;
Z:out bit);
end AG;

thus the entity name is AG has two input a and b, ‘in’ specifies the ports a and b are input ports.
While mode ‘out’ specifies output port.

Architecture Body architecture bodey contain internal description of entity. Internal details can
be described by following ways:

1) As a set of interconnected components (structural modeling)

2) As a set of concurrent assignment statement( data flow modeling)
3) As a set of sequential assignment statement(Behavioral modeling)
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

1 ) Structural Modeling: In this modeling entity is described as a set of interconnected

Components.

Let us consider a half adder. It consists of XOR gate and AND gate. NOW we declare the entity.

Half adder ( structure modeling)

entity half_adder is
port (a,b : in std_logic;

s,c : out std_logic);

end half_adder;

architecture structure of half_adder is

component xor
port(x,y :in std_logic;
z :out std_logic);
end component;

component and
port(p,q :in std_logic;
r:out std_logic);
end component;
begin
x1: xor port map (a,b,s);
A1: and port map (a,b,c);
end structure;
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

Name of the architecture bodey is HA2 .architecture body has two parts:Declarative part( before
the keybord ‘begin’) statement part after the keyword ‘begin’).

There are two components declared in declarative part,first is XOR2 and second is AND2.These
component are used in architecture bodey. They may be predefined components in library or
may be bound to other components.

Dataflow modeling :

In this modeling flow of data through entity is described primarily usin concurrent signal
assignment statements.
Concurrent statements are statements that are executed parallely.Structure of entity is not
explicitly specified in this modeling style but it can be deduced.

Architecture HA2 of HA is

Begin
S<= a xor b;
C<= a and b;
end HA2;

The symbol <= implies an assignment of value to a signal . The value of expression on the right
hand side is computed and assigned to the signal on left hand side. A concurrent signal is
executed only when any signal used in the expression changes its value. Concurerent statement
execute concurrently . so order of statement is not importanent.

Behavioural Style of Modeliing.

In this type of modeling the behavior of entity is defined as a set of sequential statements.
Sequential statement are specified inside process statements . Consider the VHDL code for D
flip-flop.
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

library ieee ;
use ieee.std_logic_1164.all;
use work.all;

---------------------------------------------
entity dff is
port ( data_in : in std_logic;
clock : in std_logic;
data_out : out std_logic );

end dff;
----------------------------------------------
architecture D_behave of dff is
begin
process(data_in, clock)
begin
-- clock rising edge

if (clock='1' and clock'event) then

data_out <= data_in;
end if;
end process;
end D_behave;
----------------------------------------------

WAVEFORM
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

EXPERIMANT: 2

AIM:-VHDL CODE FOR AND GATE & OR GATE

library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------
entity AND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end AND_ent;
-------------------------------------------------
architecture behav1 of AND_ent is
begin
process(x, y)
begin
-- compare to truth table
if ((x='1') and (y='1')) then
F <= '1';
else
F <= '0';
end if;
end process;
end behav1;
architecture behav2 of AND_ent is
begin
F <= x and y;
end behav2;
--------------------------------------------------
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

AIM:- VHDL CODE FOR OR-GATE:-

library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity OR_G is
port ( x: in std_logic;
y: in std_logic;
F: out std_logic );
end OR_G;
---------------------------------------
architecture OR_BEHAVE of OR_G is
begin
process(x, y)
begin
-- compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;

end process;
end OR_BEHAVE;

architecture OR_DATA of OR_ent is

begin
F <= x or y;
end OR_DATA;
-------------------------------------
WAVEFORMS
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

EXPERIMANT: 3

AIM: - HALF ADDER (structure modeling)

library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------
entity half_adder is
port (a,b : in std_logic;
s,c : out std_logic);
end half_adder;
---------------------------------------
architecture structure of half_adder is
component xor
port(x,y :in std_logic;
z :out std_logic);
end component;
component and
port(p,q :in std_logic;
r:out std_logic);
end component;
begin
x1: xor port map (a,b,s);
A1: and port map (a,b,c);
end structure;

AIM: - FULL ADDER (data flow)

------------------------------------------
entity full_adder is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end full_adder;
-----------------------------------------------
architecture dataflow of full_adder is
begin
sum <= (a xor b) xor cin;
cout <= (a and b) or (cin and a) or (cin and b);
end dataflow ;
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

EXPERIMANT: 4

AIM :- FULL SUBTRACTOR ( using data flow)

Library IEEE;
use IEEE.std_logic_1164.all;
---------------------------------------

entity full_sub is
port (x,y,z :in std_logic;
d,b : out std_logic);
end full_sub;
---------------------------------------
architecture dataflow of full_sub is
begin
d<=x xor y xor z;
b<=(not x and y)or(not x and z)or(y and z);
end dataflow;

Full subtractor ( using behavioral modeling)

library ieee;
use ieee.std_logic_1164.all;
entity full_sub is
port(x,y,z:in std_logic;
d,b:out std_logic);
end full_sub;
architecture full_sub of full_sub is begin
process (x,y,z)
variable temp1,temp2,temp3,temp4:std_logic;
begin
temp1:= z xor y;
temp2 := z and y;
temp3 := not x;
temp4 := temp3 and temp1;
d <= temp1 xor x;
b <= temp2 and temp4;
end process;
end full_sub;
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

EXPERIMANT: 5

AIM :- VHDL CODE FOR D FLIP-FLOP:-

library ieee ;
use ieee.std_logic_1164.all;
use work.all;

---------------------------------------------
entity dff is
port ( data_in: in std_logic;
clock: in std_logic;
data_out: out std_logic );
end dff;
----------------------------------------------
architecture D_behave of dff is
begin
process(data_in, clock)
begin
-- clock rising edge

if (clock='1' and clock'event) then

data_out <= data_in;
end if;
end process;
end D_behave;
----------------------------------------------

WAVEFORM
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

EXPERIMANT: 6

AIM :- VHDL CODE FOR 4 x 1 MULTIPLEXER-

library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity Mux_41 is
port (I3 : in std_logic_vector(2 downto 0);
I2 : in std_logic_vector(2 downto 0);
I1 : in std_logic_vector(2 downto 0);
I0 : in std_logic_vector(2 downto 0);
S : in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0));
end Mux_41;
-------------------------------------------------
architecture behv1 of Mux_41 is
begin
process(I3,I2,I1,I0,S)
begin
-- use case statement
case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= "ZZZ";
end case;
end process;
end behv1;
architecture behv2 of Mux is
begin
-- use when.. else statement
O <= I0 when S="00" else
I1 when S="01" else
I2 when S="10" else
I3 when S="11" else
"ZZZ";
end behv2;
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

WAVEFORM

HARDWARE FOR 4*1 MULTIPLEXER

 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

4 * 1 MULTIPLEXER ( BEHAVIORAL MODELING) USING IF ELSE

library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (a,b,c,d: in std_logic_vector(3 downto 0);
s:in std_logic_vector(1 downto 0);
x:out std_logic_vector(3 downto 0));
end mux;
architecture archmux of mux is
begin
process(a,b,c,d,s)
begin
if s ="00" then
x <= a;
elsif s = "01" then
x <= b;
elsif s= "10" then
x <= c;
else x <= d;
end if;
end process;
end archmux;
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

EXPERIMANT: 7

AIM :- VHDL CODE FOR 2 x 4 DECODER:-

library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity DECODER is
port (I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0));
end DECODER;
-------------------------------------------------
architecture DEC_24 of DECODER is
begin

-- process statement

process (I)
begin
case I is
when "00" => O <= "0001";
when "01" => O <= "0010";
when "10" => O <= "0100";
when "11" => O <= "1000";
when others => O <= "XXXX";
end case;
end process;
end DEC24;

architecture DEC of DECODER is

begin
-- use when..else statement

O <= "0001" when I = "00" else

"0010" when I = "01" else
"0100" when I = "10" else
"1000" when I = "11" else
"XXXX";
end DEC;
--------------------------------------------------
 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)

WAVEFORM

HARDWARE GENERATED FOR 2*4 DECODER

 VINDHYAINSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

Software are Lab-II- Hardware Description Languages (EC-506)