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Daubechies Filters
K-l K-l
HL' (m,n ) = h(i) .l(i)- LL'-' (2m - i,2n - k ) (3)
i=O k=O
In this paper, two high-speed and ultra low-power [6] Model ModelSim Products: http://www.
architectures for 2-D DWT and IDWT with single model.com/products.
transform modules have been proposed. Both
[7] Synopsys FPGA Express, http://www.
architectures perform analysis in 2 . (1 - 2-2i). N~ I 3 synopsys.com/products.
processing time and synthesis in 2 . (1 - 2-2i). N~ I 3 .
[8] Xilinx FPGA products, http://www. xilinx.com/products.
They are significantly faster than conventional
architectures proposed by Wu and Chen [lo]-[l I], and [9] S. Masud, J. V. McCanny, "Reusable Silicon IP Cores for
Marino [12]. Table 1 depicts the comparison with Discrete Wavelet Transform Application," IEEE
previous works. In this table, AT^ represents the Transactions on Circuits and Systems-I, Vol. 5 1, No. 6, June
system performance [Ill-[15], where A denotes area 2004, pp.1114-1124.
and T denotes time or latency (clock cycles). As can be [lo] P. -C. Wu, L. -G. Chen, "An Efficient Architecture for
seen, the system performances of the two proposed Two-Dimensional Discrete Wavelet Transform," IEEE
architectures are significantly better than that of Transactions on Circuits and Systems for Video Technology,
previous works. Vol. 11, NO.4, April 2001, pp. 536-545.
Filter coefficients are quantized before
implementation using 4-tap Daubechies filters. Both [ I l l P. -C. Wu, C. -T. Liu, L. -G. Chen, "An Efficient
hardwares are cost-effective and the systems have Architecture for Two-Dimensional Inverse Discrete Wavelet
high-speed. The architectures reduce power dissipation Transform," IEEE International Symposium on Circuits and
by m compared with conventional architectures in Systems, Vol. 2, May 2002, pp. 11-312-11-315.
m-bit operand (low-power utilization). [12] F. Marino, "Two Fast Architectures for the Direct 2-D
The proposed architectures have been verified by Discrete Wavelet Transform," IEEE Transactions on Signal
Verilog-HDL and implemented on FPGA. The Processing, Vol. 49, No. 6, June 2001, pp. 1248-1259.
advantages of the proposed architectures are 100%
hardware utilization and ultra low-power. The [I31 S. Y. Kung, VLSI Array Processors, Prentice-Hall, New
architectures have regular structure, simple control Jersey, USA, 1989.
flow, high throughput and high scalability. Thus, they
are very suitable for new-generation image [I41 T. Y. Sung, C. S. Chen, "A Parallel-Pipelined Processor
codingldecoding systems, such as PEG-2000. for Fast Fourier Transform," The Fourth IEEE Asia-Pacz$c
Conference on Advanced System Integrated Circuits
(AP-ASIC-2004), Fukuoka, Japan, August 3-5, 2004,
pp. 194-197.
1
input -
Figure 1. The vertical filter for I-D DWT
(a) Ib)
Figure 8. (a) Original image and @)
Reconstructed image