Study of low drop-out voltage regulator

Amit Kumar (2013VLSI-01)

ABV-Indian Institute of Information Technology and Management Gwalior,

Morena Link Road, Gwalior, MadhyaPradesh, INDIA - 474015.

November 27, 2014

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Contents

1 Introduction

2 Different techniques used to design LDRs with high PSR

3 Conclusion

4 References

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Introduction

Voltage regulator is a circuit which is used to automatically maintain

a constant voltage.
A voltage regulator may be feed forward or feedback circuit.
Voltage regulators are used to provide a stable power supply voltage
independent of load impedance, input-voltage variations,
temperature, and time.
A low-dropout regulator (LDR) is used to maintain its specified
output voltage, down to a very small difference between input and
output voltages.
This difference is known as the dropout voltage.

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Introduction (Contd...)

An LDR consists of a voltage reference, an error amplifier, a feedback

voltage divider, and a pass transistor. As shown in the figure-

Fig1.-Conventional LDO

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Introduction (Contd...)

Output current is delivered via the pass transistor. whose gate voltage
is controlled by the error amplifier.
Error amplifier is used to -
compare reference voltage with feedback voltage.
amplifies the difference to reduce the error voltage.
If the feedback voltage is lower than the reference voltage, the gate of
the pass transistor is become lower which allowes more current to
pass and increasing the output voltage.
If the feedback voltage is higher than the reference voltage, the gate
of the pass transistor is become higher which restrictes the current
flow and decreases the output voltage.

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Different techniques used to design LDRs
with high PSR
There are different techniques have been introduced for designing the
voltage regulator circuit with higher Power Supply rejection(PSR).
Every technique have there own advantages and disadvantages.
FIRST TECHNIQUE-

Fig2.-Technique introduced with RC filter

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First technique(Contd....)

In this technique, RC filter was used to suppress the ripple of VDD

before reaching at LDRs.So it achieves high PSR.
The drawback of these technique was that, It has very low corner
frequency which achieve large attenuation at higher frequencies.
To improve that low corner frequencies, the capacitance value of RC
filter has to be increased.
It takes too much area.

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SECOND TECHNIQUE-
In this technique two LDRs was cascaded in series.
It increases the total drop-out voltage and constant current
consumption.

Fig3.-Technique introduced with cascaded LDRs

This technique gives the improvement in PSR at low frequencies but

normal PSR at high frequencies.
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THIRD TECHNIQUE-
In this technique source-gate voltage of PMOS set constant for ripple
cancellation.
When the change in VDD takes place, it makes the small change in
drain current of PMOS. thus achieves high PSR.

Fig4.-Ripple feed-forward methode

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Third technique(Contd...)

This technique has two parts.

In first part a diode connected PMOS was used.
Due to this diode PMOS, It was difficult to control the feed-forward
gain as well as fully turn on/off LDR.
Second part has the better control in feed-forward gain.
The drawback of these technique was that, When pass high frequency
VDD ripple to the PMOS gate, It required high band-width for both
feed-forward amplifier and summing amplifier.
To get this high band-width a large bias current is necessary.
Hence both design in this technique required a capacitor of few range
which is not practically integrated on-chip.

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 FOURTH TECHNIQUE-
This technique has three different technique to improve high PSRs which
is based on supply ripple isolation.

Fig5.-Ripple isolation Topologies

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Fourth technique(Contd...)

In the first technique LDR uses NMOS transistor cascode with the
NMOS transistor so that It can isolate LDR from power supply noise.
A charge pump:low dropout voltage,biasing to the cascode NMOS as
well as error amplifier and delivered large current so that it increases
the area.
In the second technique LDRs uses the NMOS which in cascode with
PMOS pass transistor which gives low efficiency.
The third technique same as the second, But in this technique NMOS
has biased by a step-up charge pump and a reference voltage
generator is used which consume much current which leads to power
and area consumption of the charge pump.

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FIFTH TECHNIQUE-
2T LQC-HPSR LDR 3T LQC-HPSR LDR

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Fifth technique(Contd....)

2T LQC-HPSR LDR technique has two LDRs(one is auxiliary LDR

and second is core LDR) which have low constant current and high
PSR.
The auxiliary LDRs takes low current from step-up charge pump so
power consumption is very small.
For getting better PSR as compare to 2T LQC-HPSR LDR,Another
technique has been proposed that is called 3T LQC-HPSR TDR.
3T LQC-HPSR LDR has one more cascode NMOS transistor and also
have an additional auxiliary LDR2.

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Conclusion

1 There is so many technique was introduced for high PSRs.Every

technique has there advantages and disadvantages.
2 In the proposed technique NMOS power transistor cascode with the
PMOS pass transistor of the core regulator.
3 NMOS power transistor is biased by auxiliary LDRs.The LDRs is used
to get isolation from the noise of supply and there is no need of
off-chip capacitor.
4 A on-chip 2X charge pump are used in the proposed technique which
is quite power and area efficient.This is effective design of power
management application for system on chip.

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References

[1] Chenchang Zhan; Wing-Hung Ki

”Analysis and Design of Output-Capacitor-Free Low-Dropout
Regulators With Low Quiescent Current and High Power Supply
Rejection,” Circuits and Systems I: Regular Papers, IEEE Transactions
on , vol.61, no.2, pp.625,636, Feb. 2014.
[2] Leo, C.J.; Raja, M.K.; Je Minkyu
”An ultra low-power capacitor-less LDO with high PSR,” Microwave
Workshop Series on RF and Wireless Technologies for Biomedical and
Healthcare Applications (IMWS-BIO), 2013 IEEE MTT-S
International , vol., no., pp.1,3, 9-11 Dec. 2013

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 THANK YOU

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