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Lecture 18
OUTLINE
• Basic MOSFET amplifier
• MOSFET biasing
• MOSFET current sources
• Common‐source amplifier
• Reading: Chap. 7.1
Reading: Chap. 7.1‐7.2
7.2
Common‐Source Stage
λ =0
Av = −g m RD
W
Av = − 2μnCox I D RD
L
EE105 Spring 2008 Lecture 18, Slide 2 Prof. Wu, UC Berkeley
EE105 Fall 2007 1
4/3/2008
Operation in Saturation
• In order to maintain operation in saturation, Vout
cannot fall below Vin by more than one threshold
voltage.
• The condition above ensures operation in saturation.
EE105 Spring 2008 Lecture 18, Slide 3 Prof. Wu, UC Berkeley
CS Stage with λ=0
Av = − g m RL
Rin = ∞
Rout = RL
EE105 Spring 2008 Lecture 18, Slide 4 Prof. Wu, UC Berkeley
EE105 Fall 2007 2
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CS Stage with λ ≠ 0
Av = −gm ( RL || rO )
Rin = ∞
Rout = RL || rO
• However, channel length modulation leads to finite
output resistance, ro, which is in parallel with the load
resistance, RL
EE105 Spring 2008 Lecture 18, Slide 5 Prof. Wu, UC Berkeley
CS Gain Variation with Channel Length
W
2μnCox
Av = L ∝ 2μnCoxWL
λ ID ID
• Since λ is inversely proportional to L, the intrinsic
voltage gain actually becomes proportional to the
square root of L.
EE105 Spring 2008 Lecture 18, Slide 6 Prof. Wu, UC Berkeley
EE105 Fall 2007 3
4/3/2008
MOS Biasing
R1
VDD = VGS + I D RS
R1 + R2
1 W
I D = μ nCox (VGS − VTH )
2
2 L
⎛ RV ⎞
VGS = − (V1 − VTH ) + V12 + 2V1 ⎜ 2 DD − VTH ⎟
⎝ 1
R + R2 ⎠
1
V1 =
W
μnCox RS
L
• Voltage at X is determined by VDD, R1, and R2.
• VGS can be found using the equation above, and ID can be
found by using the NMOS current equation.
EE105 Spring 2008 Lecture 18, Slide 7 Prof. Wu, UC Berkeley
Self‐Biased MOS Stage
I D RD + VGS + RS I D = VDD
1 W
I D = μnCox (VGS −VTH )
2
2 L
• The circuit above is analyzed by noting M1 is in
saturation and no potential drop appears across RG.
EE105 Spring 2008 Lecture 18, Slide 8 Prof. Wu, UC Berkeley
EE105 Fall 2007 4
4/3/2008
Current Sources
• When in saturation region, a MOSFET behaves as a current source.
• NMOS draws current from a point to ground (sinks current),
whereas PMOS draws current from VDD to a point (sources
current).
EE105 Spring 2008 Lecture 18, Slide 9 Prof. Wu, UC Berkeley
CS Stage with Current‐Source Load
Av = − g m1 (rO1 || rO 2 )
Rout = rO1 || rO 2
• To alleviate the headroom problem, an active current‐source load
is used.
• This is advantageous because a current‐source has a high output
resistance and can tolerate a small voltage drop across it.
EE105 Spring 2008 Lecture 18, Slide 10 Prof. Wu, UC Berkeley
EE105 Fall 2007 5
4/3/2008
PMOS CS Stage with NMOS as Load
Av = − g m 2 (rO1 || rO 2 )
• Similarly, with PMOS as input stage and NMOS as the
load, the voltage gain is the same as before.
EE105 Spring 2008 Lecture 18, Slide 11 Prof. Wu, UC Berkeley
CS Stage with Diode‐Connected Load
⎛ 1 ⎞
Av = − g m1 ⎜ || rO 2 || rO1 ⎟
⎝ gm2 ⎠
1 (W / L )1
Av = − g m1 ⋅ =−
gm2 (W / L )2
• Lower gain, but less dependent on process parameters.
EE105 Spring 2008 Lecture 18, Slide 12 Prof. Wu, UC Berkeley
EE105 Fall 2007 6
4/3/2008
CS Stage with Diode‐Connected PMOS Device
⎛ 1 ⎞
Av = − g m 2 ⎜⎜ || ro1 || ro 2 ⎟⎟
⎝ g m1 ⎠
• Note that PMOS circuit symbol is usually drawn with
the source on top of the drain.
EE105 Spring 2008 Lecture 18, Slide 13 Prof. Wu, UC Berkeley
CS Stage with Degeneration
RD
Av = −
1
+ RS
gm
λ =0
• Similar to bipolar counterpart, when a CS stage is degenerated,
its gain, I/O impedances, and linearity change.
EE105 Spring 2008 Lecture 18, Slide 14 Prof. Wu, UC Berkeley
EE105 Fall 2007 7
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Example of CS Stage with Degeneration
RD
Av = −
1 1
+
g m1 g m 2
• A diode‐connected device degenerates a CS stage.
EE105 Spring 2008 Lecture 18, Slide 15 Prof. Wu, UC Berkeley
CS Stage with Gate Resistance
VRG = 0
• Since at low frequencies, the gate conducts no
current, gate resistance does not affect the gain or I/O
impedances.
EE105 Spring 2008 Lecture 18, Slide 16 Prof. Wu, UC Berkeley
EE105 Fall 2007 8
4/3/2008
Output Impedance of CS Stage with
Degeneration
rout ≈ gmrO RS + rO
• Similar to the bipolar counterpart, degeneration
boosts output impedance.
Output Impedance Example (I)
⎛ 1 ⎞
Rout = rO1 ⎜1 + g m1 ⎟
⎝ gm2 ⎠
• When 1/gm is parallel with rO2, we often just consider 1/gm
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Output Impedance Example (II)
CS Core with Biasing
R1 || R2 − RD
Av = ⋅ , Av = − g m R D
RG + R1 || R2 1 + R
S
gm
• Degeneration is used to stabilize bias point, and a bypass
capacitor can be used to obtain a larger small‐signal voltage
gain at the frequency of interest.
EE105 Spring 2008 Lecture 18, Slide 20 Prof. Wu, UC Berkeley
EE105 Fall 2007 10