Chapter 4 : Circuit Characterization

Before the actual fabrication of transistors and interconnects, it is advantageous if we could predict to a fair degree
whether the circuit is going to function, how much time it take to perform the operations, how much power it is going to
dissipate etc. One can use simulation tools to characterize a particular circuit. The simulations are based on
circuit/system models. In this chapter, the focus is to develop simple models that enable one to understand the system
performance. To develop models, one should have physical insights of circuit behavior and the fabrication and this
knowledge will help the designer to change the circuit to function it better. A fully-fledged model takes into account the
parasitic capacitance, resistance, and the inductance effects of the devices and interconnects.

In the previous chapter, we have discussed the fabrication of passive components like resistors, capacitors and active
transistors and wires that connect them in CMOS technology. Though the basic properties of transistors are important
for logic design; a high performance design requires the consideration of parasitic circuit elements - capacitance and
resistance. These parasitics are created as necessary by-products of the fabrication process. With the introduction of
deep submicron semiconductor technologies, these parasitics start to dominate the speed, energy consumption and
reliability considerations of the ICs. In the following sections, we discus the estimation of resistance and capacitance of
interconnects.

4.1 Resistance Estimation:

The resistance of a wire is proportional to its length L, and inversely proportional to its cross section A. The resistance
of a rectangular conductor (wire) of Fig 4.1 can be expressed as

where is the resistivity of the material in -cm, L is the length of the wire, H is the thickness of the wire and W is the
wire width.
 Fig. 4.1: Parallel plate capacitance model of a wire

Since H is a constant for a given technology, the above equation can be rewritten as

where is the sheet resistance of the material having units (known as “ohms per square”). This expresses
that the resistance of a square conductor is independent of its absolute size. The ratio L/W is refered as the number of
squares of wire and to obtain the resistance of a wire simply multiply the sheet resistance with the number of squares.

Using the above concepts can calculate the resistance of transistors and inverters. Consider the following n-type
transistor in Fig 4.2 with channel length . and channel width . This channel has three squares

in series and thus the resistance of the channel will be 3 .

Fig 4.2 : Resistance calculation for transistor channel

We have considered the resistance linear and constant, however, at high frequencies skin effect comes to play, and
resistance becomes frequency dependent. The increased resistance at high frequencies may cause extra attenuation
and thus distortion of the signals being transmitted over the wire.

Aluminum is the interconnect material mostly used in ICs because of its low cost and compatibility with
the standard CMOS process. Present technology uses copper increasingly because of its low resistivity and better
immunity against electro migration. Polysilicon should only be used for local interconnect. Although the sheet resistance
of diffusion layer (n+, p+) is comparable to that of polysilicon, the use of diffusion wires should be avoided due its large
capacitance and the associated RC delay.

4.2 Capacitance Estimation :

Consider the simple rectangular wire placed above the semiconductor substrate as shown in Fig 4.1. The capacitance
between the parallel plates is proportional to its proportional to its cross section A (length L multiplied by width W) and
inversely proportional to the separation t between the plates. The capacitance can be expressed as

Where is the permittivity of free space, k is the relative dielectric constant of the insulator and t is the thickness of the
insulating material.

4.3 Switching characteristics

In the first chapter, we have already studied the configuration, static characteristics, and noise margins of a CMOS
inverter circuit. The switching characteristics of MOS circuits (e.g. the inverter) depend on the charging and discharging
of the load capacitance CL through the PMOS and NMOS transistors respectively. The finite time taken for this charging
and discharging is the reason for the delay in circuits. Once we have the estimation of capacitance and resistances
associated with a circuit, we can calculate the delays.

Manual analysis of MOS circuits where each capacitor is considered individually is almost impossible because many
nonlinear capacitors are associated with a MOS transistor. The capacitance depends on the voltage applied and is
distributed among the gate, source, drain, and body regions. To make the analysis possible, once assume that all
capacitances are lumped together into one single capacitance CL , located between V out and ground. Fig 4.4 shows
the schematic of a cascaded inverter pair and with the parasitic capacitances associated. The components of CL are as
follows:

Gate Drain capacitance Cgd12

Diffusion capacitances Cdb1 and Cdb2
Wiring capacitance Cw
Gate capacitance of fan out Cg3 and Cg4
 Fig 4.4 : Parasitic capacitances associated a cascaded inverter pair

Digital logic circuits exhibit finite rise and fall delays as well as finite propagation times due to capacitances and
resistances associated with the gates. The following section discusses simple models to estimate the delays.

4.3.1 Analytic delay models

The CMOS inverter switching characteristics can be studied by the switch model given in Fig 4.5. The transistor can be
considered as a switch with an infinite off-resistance for | VGS | < | VT | and a finite on-resistance for | VGS | > | VT |. When
the input when the input makes a step change from low to high, the pull-down transistor is turned on and the pull-up
transistor turns off. This situation is shown in Fig 4.5a, and the resulting high resistance of an off PMOS device modeled
as a switch open. The NMOS transistor is on and the finite on resistance is modeled as R n . The time required for Vout
to change from VOL to the 50% point can be calculated by the capacitance charging through the pull-up device. When
the input makes a step change from high to low, the pull-down transistor is turned off and the pull-up transistor turns on.
This situation is shown in Fig 4.5b. The off NMOS transistor is shown as a switch open. The PMOS is on and is
modeled by as Rp , its on resistance. The time required for Vout to discharge from VOH to the 50 % point can be calculated
by the capacitance discharging through the pull-down device.

Fig 4.5 (a) : Static CMOS inverter and switch models for (b) in = VDD and (b) in = 0

The propagation delay of the circuit in above situations can be analyzed using a first order RC network shown in Fig
4.6. When applying a step input (with V in going from 0 to VDD ), the capacitor charges exponentially and is given by,

Fig 4.6 : Simple RC circuit to illustrate the delay calculations

where is the time constant of the network. The time to reach the 50% point is . And it takes

is to get from 10% to the 90% point.

Fig 4.7: Definitions of transition and delay times

Standard definitions of delay times are illustrated in Fig 4.7. Rise and fall times are defined between 10 and 90% points
of the total voltage transition at the input of an inverter or gate. The total voltage range at both input as well as output is
taken to be V OL and V OH. Propagation delay times input to output, denoted t PLH (for the high to low transition of output
waveform) and t PHL (for the low to high transition of output waveform) are defined between 50% points of input and
output pulse waveforms.
The overall propagation delay of the inverter is defined as the average of the two values:

Cycle time t cycle is the time between identical points of successive cycles in the signal waveform as seen at any single
node. Often cycle time is specified in terms of its reciprocal, clock frequency f clk .

4.3.2 Gate delay

The delay of simple gates may be approximated by constructing an “equivalent inverter”. The size of NMOS and PMOS
of this inverter reflect the effective strength of the real pull-down and pull-up path in the gate. Thus the propagation
delay can be calculated by modeling each transistor of the gate as a resistor in series with the ideal switch. The value of
the resistance depends on the power supply voltage and the device width over length ratio. The logic is transformed
into an equivalent RC network that includes the effect of internal node capacitances. Fig 4.8 shows the two input NAND
gate implementation and the equivalent RC model. It can also be seen that the delay depends on the input patterns. For
the case in which both the inputs go from one to zero, results in a smaller delay compared to the case in which only one
input goes low. The worst case low to high delay depends for the case in which A = 1 and B changes from 1 to 0. This is
because the internal node capacitance also needs to be charged and it slows down the transistor.

4.4 CMOS-gate transistor sizing

First up all, let us consider the sizing of an inverter. We have already seen that the propagation delay of the gate is
proportional to (Rp + Rp)C L . The delay of an inverter can be minimized by keeping the output capacitance small or by
decreasing the on resistance of the transistor. The C L consists of the diffusion capacitance of the transistors, the
interconnect capacitance and the fan-out capacitance. Careful layout helps to reduce the diffusion n and interconnect
capacitances. The on-resistance of the transistor is inversely proportional to the W/L ratio of the device. It is known that
the mobility of holes are approximately 2.5 times lower than that of electrons in Silicon. Thus, a 2.5 time wider PMOS
transistor is needed to match its on-resistance to that of pull-down NMOS device. With such a sizing of NMOS and
PMOS width, we can design an inverter with a symmetrical VTC (Voltage Transfer Characteristics) and equal high-to-
low and low-to-high propagation delays. The diffusion capacitance is also increased with increasing widths and careful
optimization is required.
 Fig 4.8 : Two input NAND gate implementation and the equivalent RC model

Now let us consider the sizing of 2 input NAND gate shown in Fig. 4.7. For this gate to have the same pull-down delay (t
PHL) as a minimum sized inverter, the NMOS devices must be made twice as wide so that the equivalent resistance of
the pull-down network is the same as the inverter. Since the PMOS devices are in parallel, its size can remain
unchanged. In other words, adding devices in series slows down the circuit and devices must be made wider to avoid
performance penalty. 4.5 Power Dissipation

The power level of some chips has approached 100 watts these days and power dissipation is a major design
consideration. The basic power equation is

where I is the current flowing from VDD to ground. The power dissipation of a logic gate can be categorized into static
and dynamic power. The static power involves power dissipation when the gate is not switching and the dynamic power
involves the power dissipation during switching. So

The main sources of leakage currents are :

1. Reverse biased junction leakage current

This occurs from source or drain to the substrate through reverse biased diodes when transistor is off.

2. Sub threshold leakage

This is the drain to source current of transistor operating in the weak inversion region. Unlike the strong
inversion region in which the drift current dominates, the sub threshold conduction is due to the diffusion current
of minority carriers in the channel.

3. Gate direct tunneling leakage

Reduction of gate oxide thickness results in an increase in the field across the oxide. This results in tunneling of
electrons from substrate to gate and from gate to substrate through the gate oxide, resulting in gate oxide
tunneling current.

Each time the capacitance C gets charged through the PMOS transistor, certain amount of energy is drawn from the
power supply. Part of this energy is dissipated in PMOS device and remainder is stored on the load capacitor. During
the high to low transition, the capacitor is discharged and the stored energy is dissipated in the NMOS transistor.
Dynamic power is associated with this switching from high to low and low to high.
where f is the switching frequency of the gate and C is the output capacitance driven by the gate.

Another source of dynamic power dissipation is due to short-circuit current. Due to the finite slope of the high to low
transition or low to high transition of the input signals, both the PMOS and NMOS transistors are partially on for a short
duration and there exist a direct path between V DD and Ground.

4.6 Scaling of MOS transistor dimensions

The steady downscaling of transistor dimensions over the past two decades has been the main motivation to the growth
of silicon integrated circuits. Channel lengths of 0.25 µum down to 0.09 µm are now the norm. The more an IC is
scaled, the higher becomes its packing density, the higher its circuit speed, and the lower its power dissipation.
However, reducing the source-to-drain spacing (channel length) of a MOSFET has led to undesirable short channel
effects. The most undesirable short-channel effect is the reduction in the gate threshold voltage at which device turns
on. In constant-field scaling, it was proposed that one could keep short-channel effects under control by scaling down
the vertical dimensions and along with the horizontal dimensions, while also proportionately decreasing the applied
voltages and increasing the substrate doping concentrations. Since both the device dimensions and device voltages are
scaled down by the same factor k, the electric field remains unchanged. Consequently, the currents also are reduced by
a factor of k as well. Since the power dissipation is the product of the current and voltage, the power consumption drops
by a factor of k 2 for this scaling. Because the time factor is reduced by a factor of k, the frequency of operation
increases by a factor of k.

By keeping the same electric fields in the scaled devices, the reliability is not compromised. However, in actual
technology evolution, voltages have not been reduced with the same scaling factor. There has been lack of enthusiasm,
for example to change standardized power supply levels that have been used in preceding circuits. In addition, other
non-scaled factors such as threshold voltages and sub threshold currents have made reduction in applied voltages less
desirable. Consequently, electric fields in MOS devices have increased as the device dimensions shrink. Whatever
clever techniques one build to make one more step towards smaller devices, there are some ultimate limits.

Fig 4.1: Cross section of (a) original NMOS transistor and (b) scaled NMOS transistor
 Property Scaling
1/ k
All lateral and vertical dimensions
k
Doping concentration
Packing density (No. transistor/cm 2 ) k2 k2
Current densities K k3
Field strengths 1 k
Power loss density 1 k3
Power loss per transistor 1/k 2 k
Time delay per transistor 1/k 1/k 2

Table 4.1: Scaling laws and their effect on device and Circuit parameters