Metastability/Overview

– Metastability of flip-flops (FFs) and latches

(D-FF, JK-FF, T-FF…)
• Basics
• Small-signal gain of gates
• Gain and transient behavior of clocked flip-flops
• Timing requirements of clocked flip-flops
• Observation of metastability
• Problem analysis and characterisation
• Synchronisers

State 0 State 1
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 Metastability/Latches and Flip-Flops
Data Latches:
•Output follows input when latch input is asserted (level-triggered)
•Data is held while latch input is de-asserted
Data Flip-Flops:
•Output follows input when clocked (positive or negative edge)
•Data is held between clock events

•Commonly: Latches and FF’s also provide asynchronous reset (and/or preset)
•Example synchronous FF: MM74HC74A (see below)

D Q

Clr

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Metastability/Gain of Logic Gates
Digital Logic Gates:
•For small signals around their logic thresholds logic gates act like linear amplifiers
•Gates do provide high gains around the threshold (but note that the gain is not infinite!)
•TTL gates/unbuffered CMOS gates provide a relatively low gain (10..100)
•Buffered CMOS gates provide high gains (>1e3)
•In a few specific applications gate maybe used in their linear region (e.g. oscillators)

HCMOS TTL (LS)

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 Metastability/Transient Response of Gates
Digital Logic Gates:
•In the linear region the voltage transfer function of
~vin ~vo
digital gates is approximately first order... (here, inverter
is behaving like an inverting amplifier)
Vo ( p ) gain
H ( p) = =
Vin ( p ) 1 + pTgate Vcc

In the linear region the step response is approximately... ~vin

~vo
 −
t

vo (t ) = (Vstep − Vth ) ⋅ gain ⋅ 1 − e 
Tgate

  Vth
 

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 Metastability/FF & Latch Model
Model of FF’s (and latches):
In contrast to gates, FF’s (and latches) behave like sampling amplifiers with positive feedback. At clock
event, input is sampled (S1 closed). After clock event (S1’ closed), the FF amplifier, once slewed into
the correct position, merely holds the circuit in one state.

clk
R
Vin Vo
S1 S1' At the clocking moment S1’
opens for a short period. While
Vcc
open, S1 briefly pulses closed,
charging capacitor C to the input
voltage. When S1’ closes again,
C ending the cycle, positive
feedback through resistor R
forces the FF amplifier to saturate
Vth either at the high or low state, and
holding the output.

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 Metastability/Timing Requirements of D-FF
Clk

Data

t
Tsetup Timing Characteristics of Data Flip-Flops:
Thold •Data input has to stabilise before the clock event (data setup
time Tsetup)
Tpd •Data input has to remain stable for some time after the clock
event (data hold time Thold)
•Clock-to-output propagation delay Tpd

Data flip-flops work as expected as long as setup and hold time requirements are met...
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 Metastability/Timing Requirements of D-FF
AC Specification Data Flip-Flops:
•Example: MM74HC74A

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 Metastability/Timing Requirements of D-FF
However: There are situations where there is no guarantee that setup and hold specs
are complied with...
Asynchronous Inputs Synchronous System
Potential violation of setup and hold D Q
requirements whenever asynchronous
inputs1 are clocked into synchronous
systems. D Q

Asynchronous inputs may change at any

time without regard to internal synchronous
clocks. D Q

Is there a way to clock async signals into

sync systems without violating flip-flop
timing requirements? No, there isn’t... central clock

What happens to a flip-flop if setup and hold requirements are not met?
1A signal is considered asynchronous if it is not controlled by a clock, or if it is synchronised by a clock in a different
clock domain
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 Metastability/Observation of Metastability
Tsetup Thold
Clk

t
Tcrit

Observation:
•Let the data input change state (low-to-high) during the “illegal” interval
•Relative to the clock edge there is a time Tcrit
•If data arrives before Tcrit the output follows the input
•If data arrives after Tcrit the output stays low.
•(note that Tcrit may fall into Tsetup or Thold depending on FF technology)

A closer look reveals...

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 Metastability/Observation of Metastability
Tsetup Thold
Clk

t
Tcrit
Observation of Metastability:
•As the data transition approaches the critical time Tcrit the clock-to-output delay increases
•For data transitions very close to Tcrit the clock-to-output delay is proportional to the
logarithm of the time difference between data transition and Tcrit

Metastability = Increase of the clock-to-output delay due to violation of setup and hold
timing requirements.
Metastability can cause excessive propagation delays and subsequent system failures.
ALL FFs (and latches) exhibit metastability. The problem cannot be eliminated. But it is
possible to make metastability less likely to occur.

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 Metastability/Analysis of Metastability
Metastability
•Occurs if the input voltage is close to threshold voltage Vth when switch S1’ is clocked
•Voltage difference at input of amplifier is small (ie there is no signal to be amplified)
•Because of limited gain of amplifier, its output assumes an intermediate (bias) level
•It may take a long time till amplifier saturates
•The hesitation of the output to saturate is called the metastable state

clk
R
Vin Vo
S1 S1'
Vcc

Vth

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 Metastability/Analysis of Metastability
Metastability clk
•Amplifier is exponentially “unstable”... R
Vin Vo
S1 S1'
 Vcc 
 = (Vin − Vth ) ⋅ e FF
K ⋅t
Vo − Vcc
 2 
For a complete transition output needs to C
swing up to Vcc (or down to GND)...
Vth
How close to Vth must the input be to cause a
metastable delay of T seconds?
Vcc Vin − Vth
Vin − Vth = Convert input signal into time offset: Tw = Tr
2e K FF ⋅T Vcc
Tr − K FF ⋅T If an input signal arrives within a metastable window Tw within
Tw = e Tcrit, the output remains in a metastable state for more than T
2 seconds...

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 Metastability/Analysis of Metastability
Metastability
•Example: Actel ACT-1 gate array
•Clock-to-output delay vs time difference Tw=Ttransition-Tcrit
40
34.328

30

Tclkd( T diff( nd) )

20
n ⋅s

10

9.3 0
1 .10 1 .10 1 .10
3 3 4
0.01 0.1 1 10 100
0.005 T diff( nd) 5000
pico ⋅s
Note: Clock-to-output delay is proportional to the logarithm of Tw
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Metastability/General Recommendations
Metastability cannot be avoided at the boundary between asynchronous and
synchronous systems.
However - the propability that metastable states are encountered can be significantly
reduced:
•Use synchronisers
•Use faster flip-flops (narrower metastable window Tw)
•Use metastable-hardened flip-flops (designed for very high bandwidth and reduced sampling
times – optimised for clock domain input circuitry)
•Cascade flip-flops in synchronisers (two or more). A chain of N flip-flops has a propability
of PN where P is the chance of metastable failure for one flip-flop
•Reduce sampling rate
•Avoid input signals with low dV/dt

Special completion detection circuits can detect metastable states… (however circuitry
following the completion detection circuits must be asynchronous…)

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 Metastability/Synchronisers
Synchronisers
We have shown: Mean time between failures of a circuit with an asynchronous input is exponentially
related to the time available for recovery from a metastable condition. Use synchronisers to create a
time buffer for recovering from a metastable event!
BUT: An async. Signal should never be synchronised by more than one synchroniser! (to do so would risk
having the outputs of multiple synchronisers produce different signals)

Synchroniser A
•Use synchroniser A if expected pulse width of async. input is larger than the clock period
Synchroniser (Tsignal>Tclk)

q1
Async_in D Q D Q Sync_out
clk

Clr Clr

Reset

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 Metastability/Synchronisers
Synchroniser A Operation
•If the async. Input reaches a stable condition outside the setup interval, it will be clocked
through with a latency of two clock cycles
•Otherwise, FF1 may enter metastability
•If metastability is resolved in less than one clock cycle, FF2 will have a stable input
•Price paid: Latency
•Scheme can be improved by deeper cascadation (3..)
clk
t
Synchroniser (Tsignal>Tclk)
Timing violation

q1
Async_in D Q D Q Sync_out Async_in
clk t

Clr Clr
q1 Metastable
Reset t

Sync_out
t

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 Metastability/Synchronisers
Synchroniser B
•Use synchroniser B if expected pulse width of async. input is smaller than the clock period

Synchroniser (Tsignal<Tclk)

Vcc
q1 q2
D Q D Q D Q Sync_out
Async_in

Clr Clr Clr

clk

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 Metastability/Synchronisers
Synchroniser B Operation
•Note that D input of first FF is connected to Vcc, while async input clocks the FF
•Remaining two FF’s are clocked by system clock (clk)
•A short pulse will drive q1 high
•High will propagate to Sync_out after two clk edges
clk
•Asynchronous reset of FF1 t
Timing violation

Async_in
t

Synchroniser (Tsignal<Tclk)

Vcc
q1 Metastable

q1 q2
t
D Q D Q D Q Sync_out
Async_in

Clr Clr Clr q2

t

Sync_out
clk
t

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 Metastability/Synchronisers
Synchronisers at boundaries of clock domains
•Use synchronisers when a signal must cross a boundary between clock domains
•If clk1<clk2 use synchroniser A at the input of clock domain #2
•Otherwise use synchroniser B

Clock Domain #1 Clock Domain #2

Data_in D Q D Q Data_out

Clr Clr

clk1 clk2

Reset

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