Hemal Shahporia

Midterm Exam 1
1.

The relation between mask dimension (D) etch depth (h) and floor width(d) is given by:

D = 280 um wide
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2.
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3.
Total Thickness = 300 um
Required Thickness = 25 um
Thickness to be etched = 275 um
Etch rate = 10 um/hr
Time required = 27.5 hours
Etch Selectivity = 200
Etch rate over SiO2 = 0.005 A/min = 0.3 A/hour
Thickness of Sio2 mask = 8.25 A/min

As (111) attacks crystal plane (100)plane 100 times slower undercut =

Undercut = 6.73 um = 3.365 um on both sides

Hence the pattern on mask would be 603.365um*603.365um.
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4.
Silicon dioxide (silica) layer is formed on the surface of a silicon wafer by thermal oxidation at
high temperatures in a stream of oxygen.
Si+02 = SiO2 (solid)
The oxidation furnace used for this reaction is similar to the diffusion furnace. The thickness of
the oxide layer depends on the temperature of the furnace, the length of time that the wafers
are in it, and the flow rate of oxygen. The rate of oxidation can be significantly increased by
adding water vapour to the oxygen supply to the oxidizing furnace.
Si + 2H2O = SiO2 + 2H2
The time and temperature required to produce a particular layer thickness arc obtained from
empirically determined design curves, of the type shown in the figures given below
corresponding to dry- oxygen atmosphere and also corresponding to steam atmosphere.
The process of silicon oxidation takes place many times during the fabrication of an IC. Once
silicon has been oxidized the further growth of oxide is controlled by the thickness of the initial
or existing oxide layer.

MOS VLSI technology requires silicon dioxide thickness in the 50 to 500 A range in a repeatable
manner. This section is devoted to the growth and properties of such thin oxide. This oxide must
exhibit good electrical properties and provide long-term reliability. As an example, the dielectric
material for MOS devices can be thin thermal oxide. This dielectric is an active component of the
storage capacitor in dynamic RAMs, and its thickness determines the amount of charge that can
be stored.
a) Gate oxide;
The gate oxide is the dielectric layer that separates the gate terminal of a MOSFET from the
underlying source and drain terminals as well as the conductive channel that connects
source and drain when the transistor is turned on. Gate oxide is formed by oxidizing the
silicon of the channel to form a thin (5 - 200 nm) insulating layer of silicon dioxide.
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b) Sacrificial layer in surface micromachining;

Surface micromachining builds microstructures by deposition and etching of different
structural layers on top of the substrate.[1] Generally polysilicon is commonly used as one of
the layers and silicon dioxide is used as a sacrificial layer which is removed or etched out to
create the necessary void in the thickness direction. Added layers are generally very thin
with their size varying from 2-5 Micro meters.

c) IC surface passivation and protection

The other function of Si02 in IC fabrication is the surface passivation. This is nothing but
creating protective Si02 layer on the wafer surface. The figure below shows a cross-sectional
view of a p-n junction produced by diffusion through an oxide window. There are lateral
diffusion effects, that is, the diffusion not only proceeds in the downward direction, but also
sideways as well, since diffusion is an isotropic process. The distance from the edge of the
oxide window to the junction in the lateral direction underneath die oxide is indicated as yj.

5.
a) Draw the top and cross-section view of the process for fabrication of a silicon piezoresistive
pressure sensor. What CMOS compatible chemical can be used as diaphragm wet etchants?
What materials (thin films) can be used as etching mask in the etching process?
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The chemical used as diaphragm wet etchants is “HNA”: HF, Nitric Acid (HNO3) and Acetic Acid
(CH3 COOH).

The materials used as etching mask is “TMAH”: Tetramethylammonium Hydroxide

b) What are the advantages of silicon Deep Reactive Ion Etch (DRIE) over anisotropic wet etch?
How to get a more directional etch in DRIE?

When a material is attacked by a liquid or vapor etchant, it is removed isotropically

(uniformly in all directions) or anisotropic etching (uniformity in vertical direction). The
difference between isotropic etching and anisotropic etching is shown in the figure below.
Material removal rate for wet etching is usually faster than the rates for many dry etching
processes and can easily be changed by varying temperature or the concentration of active
species.

a) Completely anisotropic b) Partially anisotropic c) Isotropic etching of silicon

c) Illustrate process flow for the “SCREAM – Single Crystal Reactive Etching And Metalization”
process by MacDonald.

SCREAM’03 process flow is shown in figure below. We start witha SOI wafer with highly doped
device layer (ρ~0.01ohm-cm), as shown is step 1. After standard optical photolithography (step
2) the patterned wafer is deep etched using BOSCH process to the desired depth (Step 3),
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followed by deposition of a thick layer of polymer (fluorocarbon) (Step 4), which is used in
BOSCH process for sidewall passivation. This polymer layer protects the structure from later
isotropic release etch. An extension etch (another BOSCH process) is performed to etch
the polymer on the floor and silicon left in the device layer (Step 5 and 6). The device is released
by isotropic etch of the unprotected silicon (Step 7) using SF6 ICP, the same step as
in SCREAM. The polymer on the sidewall and photo resist left are finally removed using oxygen
plasma etch (Step 8).

6.
Ultrathin Semiconductors-on-Insulators (SOI) are engineered silicon wafers designed for logic
and memory chip applications, particularly those of 45nm thickness and below. Ultrathin SOIs
are two very thin silicon wafers separated by a silicon dioxide insulator—also known as a Buried
Oxide layer (BOx). The BOx is effectively a non-conducting layer that separates the two silicon
conductors. Ultrathin SOIs are critical to the semiconductor industry’s 22nm roadmap for
increasingly thin devices such as partially depleted (PD) and fully depleted (FD) logic devices,
advanced memory devices such as ZRAM, a number of advanced MOSFET devices and
potentially a number of other system-on-chip applications.

Ultrathin SOI substrates are engineered to have top layer thicknesses ranging from a few
microns down to 20nm thick, depending on customer demands. Manufacturers can engineer
the BOx layer to be as thin as 10nm. The Smart Cut process used to make Ultrathin SOI wafers
can control the uniformity and thickness down to 10 Å (Angstroms) or ±5%.

The fabrication process for manufacturing Ultrathin SOI chips via Soitec’s Smart Cut technology
involves a number of steps simplified as follows. Two initial silicon wafers are used in the
process—A and B. One wafer (A) is oxidized in a high temperature high oxygen environment to
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create the silicon dioxide insulating layer. An implantation process using hydrogen ions creates
a weakened layer just below the surface of the oxidized coating. Wafer A is flipped onto the
non-oxidized wafer B, and is cleaved at the weakened later by the Smart Cut process. The
remainder of wafer A is recycled as a new wafer A or is polished to be recycled as a new Wafer
B. Finally, the Ultrathin SOI wafer (Wafer A, B, and the insulating later) is annealed and polished
using Chemical Mechanical Polishing (CMP) and touch polishing techniques.

7.

Time(t)= 25 min

H = 50 um

Initial Capacitance = 0.0177pF

Hemal Shahporia

Reference:

- https://nice.asu.edu/nano/fabrication-ultrathin-silicon-insulator-soi-using-soitec-smart-
cut%C2%AE-technology
- http://www.me.berkeley.edu/~lwlin/papers/MEC-1998.pdf
- http://web.ece.ucdavis.edu/~anayakpr/Papers/Wet%20and%20Dry%20Etching_submitted.pdf
- http://www.mems.ece.ufl.edu/EEL5225/Fall03/Lectures_pdf/Lecture09.pdf
- https://pdfs.semanticscholar.org/6ff1/b7c46b1c1431dff49189aba8b6f687db1046.pdf