Int. J. Electron. Commun.

(AEÜ) 79 (2017) 184–191

Contents lists available at ScienceDirect

International Journal of Electronics and

Communications (AEÜ)
journal homepage: www.elsevier.com/locate/aeue

Regular paper

A 5 Gbps serial link pre-emphasis transmitter with a novel-designed

register based multiplexer
Xiaoran Li, Shunan Zhong, Fei Shi, Weijiang Wang ⇑
School of Information and Electronics, Beijing Institute of Technology, No.5, Zhong Guancun South Street, Haidian District, Beijing 100081, China

a r t i c l e i n f o a b s t r a c t

Article history: A serial link transmitter with 4-tap pre-emphasis is presented in this manuscript. The system consists of
Received 2 December 2016 two 5:1 multiplexers, a 2:1CML multiplexer, and a driver with 4-tap pre-emphasis. A new 5:1 multi-
Accepted 20 May 2017 plexer structure is proposed to prevent sampling on the data edge, which shows a lower power consump-
tion and chip size. Implement in standard 180 nm CMOS 1P6M process with 1.8 V power supply, the
newly designed transmitter can be able to work with bit error rate (BER) as 10
14. The transmitter output
Keywords: jitter is 0.09UI while the amplitude can reach from 540 mV to 750 mV.
Register based multiplexer
Ó 2017 Elsevier GmbH. All rights reserved.
Transmitter
Pre-emphasis
Jitter
BER
CMOS

1. Introduction pre-emphasis and equalization have been performed to reduce the

With the growing demand for information, traditional designed
parallel interfaces are more and more difficult to satisfy the trans-
mission bandwidth and other systematic requirements. The point-
to-point serial transmission will reduce the complexity of inter-
connect between each system and within the system module.
Therefore, reducing size and power consumption while improving
the reliability have become the key elements to solve the problem.
High speed serial interface SerDes (Serializer/Deserializer) technol-
ogy has been used extensively as a common chip to chip I/O inter-
face standard [1,2].
As data rate increase, various non-ideal factors such as reflec-
tion, crosstalk, skew, electromagnetic interference (EMI) noise, jit-
ter, will seriously affect the quality of signal transmission in high-
speed data transmission systems [3]. Transmission line losses such
as group-delay distortion and amplitude attenuation will cause
intersymbol interference (ISI), which is the major limitation for
the data rate and transmission distance [4].To compensate the
transmission losses, the pre-emphasis filter in the transmitter and
equalization in the receiver can be employed. Common approaches
for the transmitter and receiver are feed-forward equalization (FFE)
and decision feedback equalizer (DFE), respectively [5–7]. Data will
be disordered before transmission, and then will be recovered at
the receiver as a desired shape [8]. Previously, several studies about
ISI and the results showed that an outcome of improving data trans-
mission had been achieved reliably [9–16].
Multiplexers (MUX) are the major parts for serial link transmit-
ter to convert parallel data to serial data, which will highly affect
the output jitter. Several researches are reported about the tree-
type MUX [17–19]. The conventional tree structure is shown in
Fig. 1(a) and comprised of single 2:1 MUX cells. This type of
MUX requires a half data rate clock for the final stage and divided
to each stage. Usually tree-type MUX consumes extra chip area and
power consumption. As is shown in Fig. 1(b), single stage MUX is
another type of MUX, which employs a multi-phase low-speed
clock. Although lower power consumption and smaller chip size,
it suffers from speed limitation [20]. The multi-phase clock gener-
ator is required. Also some hybrid architectures are introduced
[21]. For these structures, there are risks that the clock may not
sample on the center of input data.
A shift register-based multiplexer is proposed in this paper. This
novel designed MUX will prevent the clock sampling on the input
data edge by using 20% and 40% duty cycle clock, which also
employs a smaller chip size and lower power consumption. This
multiplexer is employed in transmitter design and test results
show a lower output jitter and lower BER.
2 5:1 shift register based multiplexer

⇑ Corresponding author. The proposed transmitter is comprised of two 5:1 CMOS logic
E-mail address: wangweijiang_bit@hotmail.com (W. Wang). multiplexers, a 2:1 CML logic multiplexer, and a driver with

http://dx.doi.org/10.1016/j.aeue.2017.05.033
1434-8411/Ó 2017 Elsevier GmbH. All rights reserved.
 X. Li et al. / Int. J. Electron. Commun. (AEÜ) 79 (2017) 184–191 185

0 OUT
5
D0

1
6
D1

...

...

...
7
4
/2 /2 ... /2 CLK D7

(a) (b)
Fig. 1. Conventional multiplexer type shown in Ref. [7]: (a) Tree type; (b) Single-stage MUX.

Fig. 2. Block diagram of proposed 5:1 multiplexer.

Fig. 3. The structure of the divide-by-5 divider.

186 X. Li et al. / Int. J. Electron. Commun. (AEÜ) 79 (2017) 184–191

4-tap pre-emphasis. First, 10-channel parallel 500 Mbps data are

serialized to 2-channel 2.5 Gbps data with two 5:1 multiplexers.
Then these 2-channel data are serialized to 5 Gbps data by CML
multiplexer and output by the pre-emphasis driver.
10-channel parallel 500 Mbps data are divided into two groups,
D0–D4 and D5–D9, respectively. Each group includes one 5:1 mul-
tiplexer. In this paper, a novel design of multiplexer is proposed.
As is shown in Fig. 2, the 5:1 multiplexer consists of divide-by-5
divider, D flip-flop (DFF) and a decision circuit. Two 500 MHz
clocks, of which the duty cycle is 20% and 40%, respectively, are
provided by 2.5 GHz clock by a divide-by-5 divider. This method
requires only one frequency divider to produce two clocks, and
thus does not require multi-phase clock generator.
The structure of the divide-by-5 divider is shown in Fig. 3,
which can provide 40% and 20% duty cycle clock. The divider con-
sists of three D-flip-flops and two AND gates. The timing margin
was taken into consideration during the divider design. The
Fig. 4. Functional sequence diagram of proposed 5:1 multiplexer.
divide-by-5 divider only uses the rising edge of the input clock

Fig. 5. Measured S21 of transmission line.

1.2
Amplitude (V)

0.8

0.4

0.0
0 1 2 3 4 5 6 7 8 9 10
Time (ns)
(a)
1.2
Amplitude (V)

0.8

0.4

0.0
0 1 2 3 4 5 6 7 8 9 10
Time (ns)
(b)
Fig. 6. Pulse response: (a) Before channel, (b) After channel.
 X. Li et al. / Int. J. Electron. Commun. (AEÜ) 79 (2017) 184–191 187

Fig. 7. Block diagram of the transmitter with 4-tap pre-emphasis.

low-speed parallel data, and keep the synchronous sampling

Table 1
Feature of the pre-emphasis taps.
between the clock and data. Then the 500 MHz 20% duty cycle
clock is used to load the synchronous parallel data, and output data
Pre-emphasis Taps Full Scale DAC bits Polarity to DFF2. After 20% duty cycle clock completed the load on the
Pre-cursor 25% 2 ±1 low-speed parallel data, the data are serialized by a high-speed
Main-cursor 100% 4 +1 clock. Five DFF2, connected as a shift register, read data from the
1st Post-cursor 50% 3 ±1
decision circuit and output 5-channel data sequentially. Each
2nd Post-cursor 25% 2 ±1
module will produce a gate level circuit delay for data compared
with the original clock. The same numbers of inverters are
for sampling. Therefore, the divide-by-5 divider is not sensitive to added into the clock path to ensure the clock sample data signal
the duty cycle of the input clock. correctly.
Fig. 4 shows timing sequences of the proposed 5:1 multiplexer. The proposed 5:1 shift register-based multiplexer consume only
First, the 500 MHz 40% duty cycle clock is employed to sample 100nW static power consumption and 0.1  0.12 mm2 chip area.

(a) (b)
Fig. 8. Output eye diagram after channel: (a) Without pre-emphasis, (b) With pre-emphasis.
188 X. Li et al. / Int. J. Electron. Commun. (AEÜ) 79 (2017) 184–191

Fig. 9. Chip microphotograph and layout.

Table 2
Performances summary and comparison of the proposed MUX.

[13] [14] [15] This work

Technology 350 nm 180 nm 180 nm 180 nm
Supply voltage 3.3 V 1.8 V 1.8 V 1.8 V
Structure Tree Type Tree Type Tree Type Register-based
Data rate 3.6 Gbps 2 Gbps 5 Gbps 5 Gbps
N:1 4:1 16:1 8:1 10:1
Power Consumption 60 mW 36.2 mW 30.06 mW 18 mW
Area 0.36 mm2 0.78 mm2 0.03 mm2 0.03 mm2

3. Driver with 4-tap Pre-emphasis
According to the transmission medium attenuation, the trans-
mitter uses pre-emphasis and equalizer pre-set functions. By con-
trolling the amplitude of pre-emphasis driver, the dielectric loss
and high frequency attenuation on the transmission link will be
compensated effectively, so that the ISI was reduced significantly.
Transmitting electrical parameter measurements are usually
carried out under certain application. Typically the eye-diagram
signal quality test is required in the near-end and far-end of the
transmission line, respectively, to make sure that the receiver has
the tolerance of the signal quality. Also, the corresponding eye pat-
tern templates are given for each node in each protocol.
The transmission channel model is applied for the simulation as
the load. By observing eye diagram, the signal distortion caused by
the channel attenuation before equalization can be found. There-
fore we can improve the data signal by the proper equalization.
In order to accurately estimate the attenuation characteristics of
transmission line, the vector network analyzer is used to measure
the transmission line S-parameters, and then output SP files. The S-
parameter was extracted as load and imported into Cadence for
simulation. The S21 was measured with 0.5 m SMA RF coaxial
cable by the vector network analyzer. The measured S21 of this
transmission line is shown in Fig. 5.
As is shown in Fig. 6, the pulse response of the 0.5 m SMA RF
coaxial cable was stimulated. The pulse before and after the cable
are shown in Fig. 6(a) and (b), respectively.
Fig. 7 shows the block diagram of the driving circuit using 4-tap
pre-emphasis. The pre-driver and main driver circuits are all based
on current mode logic (CML) circuit structure. The pre-driver con-
sists of 2:1 multiplexer and D flip-flop. Following two 5:1 multi-
plexer, 10-channel of data serialize to 2-channel, Data1 and
Data2. The 2:1 CML multiplexer is employed to serialize Data1
and Data2 to 5 Gbps. The main driver uses four groups of CML buf-
fer with different weight. Each CML unit shares the same standard
structure so that the current proportion of each path will be more
accurate.
As is shown in Table 1, the pre-emphasis amplitude is adjusted
by 4-tap control, pre-cursor, main cursor, first post-cursor and sec-
ond post-cursor respectively, the corresponding control digits are
2bit, 4bit, 3bit, 2bit, respectively. The DAC controls the CML unit
tail current to change the current that flow through the 50X load
resistor, to adjust the pre-emphasis amplitude. Except for the main
cursor, each cursor can be adjusted positively or negatively by con-
trolling the XOR gate before the current driver. The amplitude of
the output data is shown in (1).
 
RLOAD
V out ð0Þ ¼ ½I
1 Dð1Þ þ I0 Dð0Þ þ I1 Dð
1Þ þ I2 Dð
2Þ ð1Þ
2
D(1)–D(
2) is the polarity of 4 cursors.
The above two SMA RF coaxial cables were in series connection
for simulation and measurement, in order to increase the channel
attenuation and show the effect of pre-emphasis compensation.
The eye diagram of the output signal after transmission channel
attenuation is shown in Fig. 8. Fig. 8(a) shows the eye diagram
without pre-emphasis, while Fig. 8(b) shows the eye diagram with
pre-emphasis. It can be observed in the eye diagrams that the eye
opening becomes larger and the jitter becomes smaller after equal-
ization, indicating that the transmitter equalization can make com-
 X. Li et al. / Int. J. Electron. Commun. (AEÜ) 79 (2017) 184–191 189

DC Source PC

Power Supply Digital Control

LDO PCB

Data
PRBS

DUT Oscilloscope
Reference
Signal Clock
PLL
Generator Clock On-chip

(a)

DC Source PC

Power Supply Digital Control

LDO PCB

RX DUT BERT
...

Clock Reference
Clock Signal
PLL
Generator
SPI On-chip

(b)
Fig. 10. Block diagram of the measurement setup for the experiments: (a) Transmitter output test, (b) Loopback test.

(a) (b)
Fig. 11. Test Result of Pre-emphasis: (a) Pre-emphasis is set a high mode; (b) Pre-emphasis is low mode.
190 X. Li et al. / Int. J. Electron. Commun. (AEÜ) 79 (2017) 184–191

This work

0.09 mm2
Internal
180 nm

5 Gbps

<10
14
0.09UI
1.8 V

0.14UI @1.62 Gbps

0.26UI @2.7 Gbps
1.62–2.7 Gbps

0.94 mm2
Internal
130 nm

<10
12
1.2 V
[25]

**
Fig. 12. Test result of eye diagram.

pensation of the channel attenuation in order to reduce the effect

of ISI.

4. Measurement results

The chip is fabricated in 180 nm standard CMOS 1P6M process.

The microphotograph of the transmitter shown in Fig. 9, the trans-

2.72mm2
130 nm
mitter core occupies a chip area of 0.09 mm2.

8 Gbps

0.36UI
1.2 V
[24]
The whole 10:1 multiplexer is comprised by two 5:1 MUX and

–
*
one CML 2:1 MUX. Some performances and comparisons of the
MUX are shown in Table 2.
The measurement was carried out under room temperature,
with a power supply voltage of 1.8V. Low dropout voltage regula-
tor (LDO) chip on printed circuit board (PCB) provided stable
power supply voltage. Serial peripheral interface (SPI) provided
digital control signal from the host computer to control the work-
ing mode and the code of each module. The proposed transmitter
was tested with on-chip pseudorandom binary-sequence (PRBS) 0.08 mm2
4.8 Gbps

generator. On-chip phase locked loop (PLL) is used as the clock -

65 nm

0.2UI
1.2 V

source for the transmitter measurement.

[23]

The block diagram of the measurement setup is shown in

Fig. 10. As is shown in Fig. 10(a), the transmitter output was mea-
sured by Agilent oscilloscope. Agilent E3646A DC source was used
for power supply. On-chip PRBS generator and PLL provided paral-
lel input data and clock for the transmitter, respectively. As is
shown in Fig. 10(b), loopback test was used to measure the BER
by Tektronix BSA286CL BERT. BERT provided serial data to on-
chip receiver. The receiver generated parallel data for the input
of the transmitter. The transmitter outputted the serial data to
Performances summary and comparison of the transmitter.

3.125 Gbps

0.045 mm2
1.8 V/3.3 V

BERT and compared with the initial data. The BER can reach to
Internal

10
14 with 27-1 PRBS input.

180 nm

0.31UI
[22]

The performance of 4-tap pre-emphasis is measured. Without

–

pre-emphasis, the output amplitude is 540 mV. As is shown in

Fig. 11(a), when PREM is set at a high mode (Pre: 00, Main:
1010, Post: 01000), differential output amplitude is 741 mV. As is
shown in Fig. 11(b), when PREM is set at a low mode (Pre: 00,
Including the whole transceiver.

Main: 1010, Post: 10000), output amplitude is 660 mV.

The eye diagram is shown in Fig. 12. If the jitter is too large in
the serial link, the receiver clock recovery circuit (CDR) will not
be able to track such data. Therefore, the bit errors in the transmis-
Including the pad.

sion can degrade the performance of the overall link and, and in the
Supply voltage

worst case will invalidate the transmission link. As is shown in the

Clock Source
Output Jitter
Technology

eye diagram, the transmitter output jitter is measured about

Data rate

0.09UI.
Table 3

Area
BER

As is shown in Table 3, some performances of the whole trans-

**
*

mitter are summarized and compared with the state-of-the-art.

 X. Li et al. / Int. J. Electron. Commun. (AEÜ) 79 (2017) 184–191
5. Conclusion
A wireline transmitter with a newly-designed multiplexer is
proposed in this manuscript. The 10:1 MUX is comprised of two
5:1 CMOS logic multiplexers, a 2:1 CML logic multiplexer. This
approach avoids the limitations of digital circuits limit the trans-
mission rate, and enhances the reliability of high-speed data trans-
mission systems. A shift register-based 5:1 multiplexer is proposed
to prevent the clock sampling on the input data edge. The multi-
plexer shows a lower power consumption and smaller chip area.
The transmitter employs a 4-tap pre-emphasis. The whole circuits
have been implemented in 180 nm standard CMOS process. By
using this multiplexer, the eye diagram of the whole transmitter
shows that the jitter is 0.09UI with on-chip PLL, and a lower BER
as 10
14.
Acknowledgments
This work was supported in part by National Natural Science
Foundation of China under Grant 61301006 and National Natural
Science Foundation of China under Grant 61271113, in part by
111 Project of China under Grant B14010.
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