EE326 Embedded Systems 2016

lab 2 : Four-Bit Adder Design and

Implementation
Particle members
ELECTRICAL & ELECTRONICS
Aneesh Amitesh Chand
Kushal Aniket Prasad
s11107891
s11108638
ENGINEERING DISCIPLINETHE
Semester 2 UNIVERSITY LAB REPORT WRITING
Lab Time Wednesday 2-5pm

Aim
This tutorial provides instruction for using the Xilinx ISE Web PACK toolset for basic
development on Digilent system boards. This tutorial covers the following steps:

 Use a Xilinx ISE project.

 Using schematic capture to create logic circuits and symbol elements
 how to implement and in cooperate a logic circuit and generate a bitstream representation
of the program and test the logic onto Spartan-6 Development Board.

Introduction
Throughout this course we will use the ISE integrated design environment from Xilinx Tools is a
“

suite of software tools used for the design of digital circuits implemented using Xilinx Field
Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD). ”

The design procedure consists of:

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Theory

Xilinx ISE (“Integrated Synthesis Environment”) is a software tool produced by Xilinx for
“

synthesis and analysis of “HDL” designs, enabling the developer to "compile" their designs,
perform timing analysing, examine “RTL” diagrams, simulate a design's reaction to different
stimuli, and configure the target device with the programmer. [1]
Xilinx ISE is a design environment for FPGA products from Xilinx, and is tightly-coupled to the
architecture of such chips, and cannot be used with FPGA products from other vendors. The
Xilinx ISE is primarily used for circuit synthesis and design, [1] while ISIM or the Model- Sim
logic simulator is used for system-level testing. Other components shipped with the Xilinx ISE
include the Embedded Development Kit (EDK), a Software Development Kit (SDK) and Chip
Scope Pro. [2]
Since 2012, Xilinx ISE has been discontinued in favor of Vivado design Suitev, that serves the
same roles as ISE with additional features for system on a chip development. Xilinx released the
last version of ISE in October 2013 (version 14.7).[3]
The software has many options and at the beginning it might be quite frustrating to work with it.
There will be many little quirks that need some time to get used to. Although we will try to
explain the steps required to finish the exercises as clearly as possible, there will be times when
you will get lost.[4] Do not be intimidated by the many options as we will only use a small subset
of them, and have some patience.

ISE allows us to describe our circuit (design entry), convert our design idea from a description
into an actual circuit that can be implemented on the FPGA (synthesis), allocate resources on the
actual FPGA, connect these to implement our circuit (placement and routing) and downloads the
final configuration to the FPGA itself (programming). [5]
”

Methodology

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Results and Analysis
Step1: A new project and name it “fourbit_adder” was create.

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Step 2: Select Projection was done.

Step 3: Add Source was selected.

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Step 4: Copy files “full_adder.vhd” and “fourbit_adder.vhd” in working directory.

Step 5: Select files “full_adder.vhd” and “fourbit_adder.vhd”

-> click Open. Explain the two VHDL codes “full_adder.vhd”
and “fourbit_adder.vhd”.

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Step 6: Notice added VHDL files.

Step 7: Draw the 1-bit Full Adder and the 4-bit Adder
circuit diagrams. Double click Implement Design.

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Step 8: Expand (+) User Constraints -> Double-click on I/O Pin Planning
(PlanAhead) - Post- Synthesis.

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Step 9: Plan Ahead software is launched.

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Step 10: Expand a(4)

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Step 11: Select desired pin number (Site) -> check the pin number
(Fixed).

Step 12: Repeat for the rest of the signals a, b, z, and cout using the pin numbers
as shown the figure below that shows the connection of the pushbuttons, slide
switches, and LEDs to the Spartan-6 (FPGA’s) pins:

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Step 13: The PlanAhead window should look like

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Step 14: In the Package window zoom-in to pin A10 and verify that it is
assigned to a[0]. You should see a[0] written inside the cell at location row A
column 10.

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Step: 15 Verify the correct assignment of the other pins (a[1], a[3], a[3], b[0], b[1], b[2], b[3],
b[4], z[0], z[1], z[2], z[3], and cout) as well.

Select File -> Save Constraints.

Select File -> Exit.
Select OK.

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Step:16 Re-implement design by double-clicking on “Implement Design”

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Step 17: Double-click on Generate Programming File.

Step: 18 Select Tools -> Schematic Viewer -> RTL

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Click Ok.

Step: 19 Expand the (+) sign of the

Signals area, select all of the signals, and
click the “Add ->” button

Click “Create Schematic

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Step: 20 Describe in details the generated
schematic. Click on “Generate Programming
file”.

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Step: 21 Power on Spartan-6 board and connect USB cable to
“PROG” port and to PC. Open Diligent Adept software.

Step: 22 Select Browse and locate the generated bit file

(fourbit_adder.bit). What does a (.bit) file represent?

Click Program

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Step: 23 After the programming is complete, the Adept software should print the message
“Programming Successful” and LED (DONE) is lit on the board.
 To verify that the four-bit adder works correctly, use the slide switches to set inputs “a”
and “b” and watch the LEDs. Try different

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For example
 if we wanted to test a = 2, b = 5, a + b = 7 we would set input a = 0010 and b = 0101
via the slide switches and the output should turn ON the LEDs (LD2, LD1, and LD0)
as shown in the figure below:

Discussion:
A new project was created and saved to local folder and named as “fourbit_adder”. The
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device family was selected as Spartan 6 (XC6SLX4S) along with the other details as in the
manual. The circuit diagram and design for “fourbit_adder” was then implemented and was
the design verification by static timing analysis, functional simulation and controlled timing.

As the design was implemented than PlanAhead software launched initially. The signal a[0]
the corresponding pin A10 was entered in the box which was present in input/output port
properties tab. All input pin were implemented accordingly with the help of the manual. This
was the defining of slide switches and output LED’s on the development board.

After this verification, the file was saved. For assigning the pins to our design, “implement
design” was clicked again and re-implemented. The program file was then generated
(fourbit_adder.bit) with same notes the schematic was also made to represent the design.

Once the generation of program file is completed, the development board was then interfaced
to pc using an USB cable. The power switch of the board was switched on. Adept was then
launched. As communication and recognition of board, the bit stream file was downloaded to
the board using the software after which the analysis and testing was done as outlined in
results. ”
”
Discussion Questions:
1. Explain the two VHDL codes “full_adder.vhd” & “fourbit_adder.vhd”?

Full adder.vhd- It is a virtual file format used for implementing logic circuits in low leverl
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computer language that is machine language. It carries out simple operations on 3 bit binary
numbers. A sum and a carry bit is also produced in a full adder. ”

Fourbit_added.vhd-“ virtual file format for implementing logic combinational circuit in

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assembly. This has an input of 3 bits and results in output of two bit. I.e. carry out and carry
in bit. ”

One bit adder

Four bit

2. The design constraint allowed the observation and comprehension of the input and output
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pins. It allows the project of the input and output pins of the circuit.
”

3. PlanAhead allows planning and investigation of a design on FPGA boards. The software
“

allows the choice of input and output pins of the signals. The software is integrated with
Simulation switching and Robust Design Rule Checks. ”

4. RTL- Register Transfer level.

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The diagram above displays the accurate potential input and output pin
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structures with interfacing configuration to the board of the four bit adder suite. ”

The cin of the input connects to ground and the x pin of the input connects to signal
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a(3,0) the y pin of the input connects to signal b(3,0). The cout pin of the output connects
to cout and the sum pin of the output connects to signal z (3, 0).”

7. The program buttons in used to send the designed program to the bit stream file onto
the xlinix board for testing.

Notes:
Once the programme has completed running and the results were tested for program and
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the design was sent programmed onto the Xlinix board via the Adept software. ”

 A 4 bits and b has four bits different combinations were tested for,
 Like in the above picture b represents 5 in binary which is 0101 and a represents 2
“

which is 0010 in binary the output shows the first 3 LED’s lit up which indicate 7
which is 111 in binary, this verifies that the program is working successfully as
a+b=2+5=7. ”

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The above picture shows for a +b where a =1, b=1. In binary, 0001 + 0001 = 00000010.
(LED 1)

The above picture shows for a +b where a =4, b=4. In binary, 0100 + 0100 = 00001000.
(LED 3)

The above picture shows for a +b where a =15, b=15. In binary, 1111 + 1111 = 00011110.
(LED 1, 2, 3, 4)

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Conclusion:
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Upon the completion of the lab it can be concluded that that Xilinx ISE tools can be used to
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design and do real time analysis of the created project logic. The logic “fourbit_adder” was
then represented as a bit stream file. The bit stream file was done to the FPGA board which
was loaded first, but the slide switching along the LED’s on the Xiline development board
was used to verify the results. After implementation, you can analyse your design for
performance against constraints, device resource utilization, timing performance, and power
utilization. You can view results in static report files and by looking at actual device
implementation in graphical layout tools, such as the PlanAhead software and Editor. It also
more features like, based on the analysis of your design results, you can make changes to
design sources, process properties, or design constraints and then, rerun synthesis,
implementation, or both to achieve design closure.
”

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References
[1] INTRODUCTION TO XILINX ISE DESIGN SUITE 14.5 (2014) Available at:
https://www.google.com/search?q=INTRODUCTION+TO+XILINX+ISE+DESIGN+SUITE
+14.5&oq=INTRODUCTION+TO+XILINX+ISE+DESIGN+SUITE+14.5&aqs=chrome..69i
57.1475j0j7&sourceid=chrome&ie=UTF8#q=theory+on+introduction+to+xilinx+ise+design
+suite+14.5 (Accessed: 25 July 2016).

[2] Pullman, "Xiilliinx® IISE WebPACK™ Verilog Tutorial," 27 February 2010. [Online].
Available: www.digilentinc.com.

[3] Xilinx Design Tools: Installation and Licensing Guide (UG798):

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/iil.pdf

[4] Xilinx Design Tools: Release Notes Guide (UG631):

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/irn.pdf

[5] ISE Design Suite 13: Release Notes Guide . Chapter 3: Architecture Support and
Requirements: Xilinx, Inc. 2012-01-25. p. 50.

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