15ECL58 CBCS VTU Verilog HDL Manual KIT, Tiptur 2018

NAME:
USN:
Department of
Electronics & Communication Engineering
Kalpataru Institute Of Technology
Tiptur-572202
KALPATARU VIDYA SAMSTHE®
KALPATARU INSTITUTE OF TECHNOLOGY
TIPTUR
Department Of Electronics and Communication

Engineering
HDL LAB MANUAL
15ECL58 2018
For 5THsemester E&C Engineering as per

VTU Syllabus
Compiled by,
Prof. Prashanth N R Prof. Prathibha C

Associate Professor, Dept. of ECE, Assistant Professor, Dept. of ECE,
K.I.T, Tiptur K.I.T, Tiptur
Prof. PramodKumar S Prof. PradeepKumar S K

Assistant Professor, Dept. of ECE, Assistant Professor, Dept. of ECE,
K.I.T, Tiptur K.I.T, Tiptur
SYLLABUS
HDL Lab
B.E., V Semester, Electronics & Communication Engineering/
Telecommunication Engineering
[As per Choice Based Credit System (CBCS) scheme]
Subject Code 15ECL58 IA Marks 20
Number of Lecture 01 Hr Tutorial (Instructions) Exam Marks 80
Hours/Week + 02 Hours Laboratory = 03
Exam Hours 03
CREDITS – 02
Laboratory Experiments
Part–A (Using Xilinx Tool)
1. Write Verilog code to realize all the logic gates
2. Write a Verilog program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer.
d. 4 bit binary to gray converter
e. Multiplexer, de-multiplexer, comparator.
3. Write a VHDL and Verilog code to describe the functions of a Full Adder using
three modeling styles.
4. Write a Verilog code to model 32 bit ALU using the schematic diagram shown
below
ALU should use combinational logic to calculate an output based on the four bit
op-code input.
ALU should pass the result to the out bus when enable line in high, and tri-state
the out bus when the enable line is low.
ALU should decode the 4 bit op-code according to the example given below.
OPCODE ALU Operation
1. A+B
2. A-B
3. A Complement
4. A*B
5. A AND B
6. A OR B
7. A NAND B
8. A XOR B
5. Develop the Verilog code for the following flip-flops, SR, D, JK and T.
6. Design a 4 bit binary, BCD counters (Synchronous reset and Asynchronous
reset) and “any sequence” counters, using Verilog code.
Part – B
INTERFACING (at least four of the following must be covered using
VHDL/Verilog
1. Write HDL code to display messages on an alpha numeric LCD display.

2. Write HDL code to interface Hex key pad and display the key code on seven
segment display.
3. Write HDL code to control speed, direction of DC and Stepper motor.
4. Write HDL code to accept Analog signal, Temperature sensor and display the
data on LCD or Seven segment display.
5. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp
etc.,) using DAC - change the frequency.
6. Write HDL code to simulate Elevator operation.
Conduct of Practical Examination:

1. All laboratory experiments are to be included for practical examination.
2. Strictly follow the instructions as printed on the cover page of answer script
for breakup of marks.
3. Change of experiment is allowed only once and Marks allotted to the
procedure part to be made zero.
HDL LAB (15ECL58) 2018
Additional programs
1) Write HDL code for full adder using structural design
2) Write HDL code for a carry look ahead adder
3) Write HDL code for 9bit parity generator using structural design
4) Design a ripple counter for given sequence 0-1-3-5-7-9-11-13-15-0 using JK flip flop
5) Write HDL code for the given mealy FSM state table
0 1
Entries in table are
ST0 ST0 ST3
next state, input A
and output Z
0 1
ST1 ST1 ST0
1 0
ST2 ST2 ST1
0 1
ST3 ST2 ST1
0 0
6) Write a HDL program for the given more FSM state diagram
A=‟1‟
Z<=‟1‟ ST1
A=‟0‟ ST1
A=‟1‟
A=‟1‟
A=‟0‟
Z<=‟1‟
ST1 A=‟0‟
ST1
Z<=‟0‟ A=‟1‟
Department of Electronics & Communication Engineering , K.I.T, Tiptur.

LAB INSTRUCTIONS
Do’s Don’ts
Be regular to the lab. Do not come late to the lab.
Follow proper Dress Code. Don't interchange any part of one computer
with another.
Maintain Silence. Avoid loose connections and short
circuits.
Know the theory behind the experiment and Do not attempt to open any machines, and do
understand how to carry out an activity not touch the backs of machines when they
thoroughly before coming to the laboratory. are switched on.
Avoid unnecessary talking while doing the Do not personalize the computers, for
experiment. example: installing screen savers, changing
the desktop background, or changing the
video and audio settings.
Keep the LAB as clean as possible. Call the Do not open the system unit casing or
attender, if necessary to clean the LAB. monitor casing particularly when the power
is turned on. Some internal components hold
electric voltages of up to 300 volts, which
can be fatal.
Report any broken plugs or exposed electrical Don‟t do the experiments in the hurry.
wires to your lecturer/laboratory technician
immediately
Handle the FPGA Kit properly and Make FRC Do not spill water or any other liquid on the
connections properly. machines, in order to maintain electrical
safety.
While doing the Interfacing, connect proper Do not remove or carry anything from the
voltages to the interfacing kit. computer laboratory without permission
Keep the table clean. Do not touch, connect or disconnect any plug
or cable without your lecturer/laboratory
technician‟s permission.
Take a signature of the incharge before taking Do not plug in external devices without
the kit/components. scanning them for computer viruses.
After the completion of the experiments switch Don't do anything that can make the LAB
off the power supply and return the apparatus. dirty (like, eating, throwing waste papers
etc).
Arrange the chairs/stools and equipment Try not to touch any of the circuit boards and
properly before leaving the lab. Don't leave the power sockets when a device is connected to
computers of the LAB turned on while leaving them and switched on.
the LAB.
The computers of the LAB are responsibility of
the LAB users. Keep your computer clean and
take a good care of them.
In case of any hardware related problem, ask
LAB in charge for solution
Look away from the screen once in a while to
give your eyes a rest.
Turn off the machine once you are done using
it.
Quick Start to Xilinx ISE Software for Digital Logic Design

It is one of most popular software tool used to synthesize HDL code. This tool Includes many
steps for synthesize and FPGA implementation. To make user feel comfortable with the tool
the steps are given below:-
 Double click on Project navigator. (Assumed icon is present on desktop).
 Select New Project in File Menu.
Enter following details as per your convenience
Project Name: sample
Project Location: D:\example
Top Level Module: HDL
 In New Project dropdown Dialog box, Choose your appropriate device specification.
Example is given below:
Device Family: Spartan3
Device: xc3s400
Package: TQ144
Speed Grade:-4
TOP Level Module: HDL
Synthesis Tool: XST
Simulation: Modelsim
Preferred Language: VHDL / Verilog
 In source window right click on specification, select new source
Enter the following details
Select VHDL/ Verilog Module and enter the file name: sample
Enter the input and output port and modes. This will create sample VHDL / Verilog
source file. Click Next and Finish the initial Project preparation.
 Edit the code and double click on synthesis. If error occurs edit and correct the code.
 Double click on Launch modelsim for functional simulation of your design.
 Expand the User Constraints in processes window and double click on Edit constraint
(Text)/Assign Package Pins in process window. This will create sample. UCF constraints
file. Edit and enter pin constraints with syntax:
NET “NETNAME” LOC = “PIN NAME”
 Double click on Implement, which will carry out translate, mapping, place and route of
your design. Also generate program file by double clicking on it, intern which will create
.bit file.
 Connect JTAG cable between your kit and parallel port of your computer.
 Double click on configure device and select mode in which you want to configure your
device. For ex: Choose Configure Device using Boundary-Scan and finish your
configuration.
 Right click on device and select „program’. Verify your design giving appropriate inputs
and check for the output.

EXPERIMENT NO. 1
Aim: Simulation and realization of all logic
gates.
a_in not_op
and_op
ALL LOGIC nand_op
GATES or_op
nor_op
b_in xor_op
xnor_op
Block Diagram
Truth Table For logic gates: Logic Diagram
Inputs Outputs
not_op
a_in b_in and_op nand_op or_op nor_op xor_op xnor_op
(a_in)
0 0 1 0 1 0 1 0 1
0 1 1 0 1 1 0 1 0
1 0 0 0 1 1 0 1 0
1 1 0 1 0 1 0 0 1
VERILOG CODE
module gates (a_in, b_in, not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op);
input a_in;
input b_in;
output not_op;
output and_op;
output nand_op;
output or_op;
output nor_op;
output xor_op;
output xnor_op;
assign not_op= ~a_in;

assign and_op= a_in&b_in;
assign nand_op= ~(a_in&b_in);
assign or_op= a_in|b_in;
assign nor_op=~(a_in|b_in);
assign xor_op= a_in^b_in;
assign xnor_op= ~(a_in^b_in);
endmodule
1 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Waveform for verilog code:
Result: The logic gates design has been realized, simulated and implemented using FPGA/CPLD using
HDL codes.
Date of Completion of Exp. Staff Signature Remarks

EXPERIMENT NO. 2
Aim: Write HDL codes for the following combinational circuits. ENABLE
2. a) 2 to 4 Decoder.
D_OUT (0)
Sel (0)
2-4 D_OUT (1)
DECODER
D_OUT (2)
Sel (1)
D_OUT (3)
Truth Table For 2 to 4 Decoder:

Enable Select Outputs
Lines
e s1 s0 d_out(3) d_out(2) d_out(1) d_out(0)
0 X X z z z z
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0
1 X X 0 0 0 0
VERILOG CODE
module decoder (sel,en,d_out);
input [1:0] sel;
input en;
output [3:0] d_out;
reg [3:0] d_out;
always @(sel , en)
if (en==1)
d_out=4’b0000;
else
begin
case (sel)
2'b00: d_out = 4'b0001;
2'b01: d_out = 4'b0010;
2'b10:d_out = 4'b0100;
2'b11: d_out = 4'b1000;
default: d_out =4'bzzzz;
endcase
end
endmodule

2. b) 8 to 3 Encoder Without Priority

ENABLE
SEL(0)
SEL(1)
D_OUT(0)
SEL(2)
8:3
SEL(3) Encoder D_OUT(1)
SEL(4) Without
D_OUT(2)
SEL(5) Priority
SEL(6)
SEL(7)
Truth Table for 8 to 3 Encoder without Priority:
INPUTS OUTPUTS
enable sel(7) sel(6) sel(5) sel(4) sel(3) sel(2) sel(1) sel(0) d_out(2) d_out(1) d_out(0)
1 X X X X X X X X Z Z Z
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 0 1 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 1 0 1
0 0 1 0 0 0 0 0 0 1 1 0
0 1 0 0 0 0 0 0 0 1 1 1
VERILOG CODE
module encoder8_3(en, sel, d_out);
input en;
input [7:0] sel;
output [2:0] d_out;
reg [2:0] d_out;
always @ (sel,en)
begin
if(en==1)
d_out=3’bzzz;
else
begin
case(sel)
8’b00000001: d_out=3'b000;
8’b00000010: d_out =3'b001;
8’b 00000100: d_out =3'b010;
8’b00001000: d_out =3'b011;
8’b00010000: d_out =3'b100;
8’b00100000: d_out =3'b101;
8’b01000000: d_out =3'b110;
8’b10000000:d_out =3'b111;
default: d_out=3’bzzz;
endcase
end
end
endmodule

Waveform for Verilog code:
ENABLE
2. c) 8 to 3 Encoder With Priority
SEL(0)
SEL(1) D_OUT(0)
SEL(2)
8: 3
D_OUT(1)
SEL(3) Encoder
SEL(4) With Priority D_OUT(2)
SEL(5)
SEL(6)
SEL(7)
Truth Table for 8 to 3 Encoder with Priority:
INPUTS OUTPUTS
D_OUT D_OUT D_OUT
ENABLE SEL(7) SEL(6) SEL(5) SEL(4) SEL(3) SEL(2) SEL(1) SEL(0)
(2) (1) (0)
1 X X X X X X X X 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 0 1 X X 0 1 0
0 0 0 0 0 1 X X X 0 1 1
0 0 0 0 1 X X X X 1 0 0
0 0 0 1 X X X X X 1 0 1
0 0 1 X X X X X X 1 1 0
0 1 X X X X X X X 1 1 1
VERILOG CODE
module encoder8_3p(en, sel, d_out);
input en;
input [7:0] sel;
output [2:0] d_out;
reg [2:0] d_out;
always @ (sel,en)
begin
if(en==1)
d_out=3’b000;
else
begin
case(sel)
8’b00000001: d_out=3'b000;
8'b0000001x: d_out =3'b001;
8'b000001xx: d_out =3'b010;
8'b00001xxx: d_out =3'b011;
8'b0001xxxx: d_out =3'b100;
8'b001xxxxx: d_out =3'b101;
8'b01xxxxxx: d_out =3'b110;

8’b1xxxxxxx:d_out =3'b111;
default: d_out=3’bzzz;
endcase
end
end
endmodule
2.d)8 to 1 Multiplexer
Truth Table for 8:1 Multiplexer

INPUTS OUTPUT A(0)
SEL[0] SEL[1] SEL[2] MUX_OUT A(1)
0 0 0 A(0) A(2)
8:1
0 0 1 A(1) A(3) MUX_OUT
0 1 0 A(2) A(4) MUX

0 1 1 A(3) A(5)
1 0 0 A(4) A(6)
1 0 1 A(5) A(7)
1 1 0 A(6)
1 1 1 A(7) SEL SELSEL
(0) (1) (2)
INPUTS SELECT LINES OUTPUT

A(7) A(6) A(5) A(4) A(3) A(2) A(1) A(0) SEL[2] SEL[1] SEL[0] MUX_OUT
X X X X X X X 0 0 0 0 0
X X X X X X X 1 0 0 0 1
X X X X X X 0 X 0 0 1 0
X X X X X X 1 X 0 0 1 1
X X X X X 0 X X 0 1 0 0
X X X X X 1 X X 0 1 0 1
X X X X 0 X X X 0 1 1 0
X X X X 1 X X X 0 1 1 1
X X X 0 X X X X 1 0 0 0
X X X 1 X X X X 1 0 0 1
X X 0 X X X X X 1 0 1 0
X X 1 X X X X X 1 0 1 1
X 0 X X X X X X 1 1 0 0
X 1 X X X X X X 1 1 0 1
0 X X X X X X X 1 1 1 0
1 X X X X X X X 1 1 1 1

VERILOG CODE
module mux8_1(a, sel, mux_out);
input[7:0]a;
input [2:0] sel;
output mux_out;
reg mux_out;
always @ (a , sel )
case (sel)
3'b000: mux_out = a[0];
3'b001: mux_out = a[1];
3'b010: mux_out = a[2];
3'b011: mux_out = a[3];
3'b100: mux_out = a[4];
3'b101: mux_out = a[5];
3'b110: mux_out = a[6];
3'b111: mux_out = a[7];
default: mux_out =0;
endcase
endmodule
2.e)1 to 8 Demultiplexer SEL SELSEL

(0) (1) (2)
D_OUT (0)
D_OUT (1)
D_OUT (2)
1:8
D_OUT (3)
D_IN Demultiplexer D_OUT (4)
D_OUT (5)
D_OUT (6)
D_OUT (7)

Truth Table For 1:8 Demultiplexer

SELECT LINES INPUT OUTPUT
SEL[2] SEL[1] SEL[0] D_IN D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT
(7) (6) (5) (4) (3) (2) (1) (0)
0 0 0 0 X X X X X X X 0
0 0 0 1 X X X X X X X 1
0 0 1 0 X X X X X X 0 X
0 0 1 1 X X X X X X 1 X
0 1 0 0 X X X X X 0 X X
0 1 0 1 X X X X X 1 X X
0 1 1 0 X X X X 0 X X X
0 1 1 1 X X X X 1 X X X
1 0 0 0 X X X 0 X X X X
1 0 0 1 X X X 1 X X X X
1 0 1 0 X X 0 X X X X X
1 0 1 1 X X 1 X X X X X
1 1 0 0 X 0 X X X X X X
1 1 0 1 X 1 X X X X X X
1 1 1 0 0 X X X X X X X
1 1 1 1 1 X X X X X X X
VERILOG CODE
module d_mux1_8(sel, d_out,d_in);
input d_in;
input [2:0] sel;
output [7:0]d_out;
reg [7:0]d_out;
always @ (d_in, sel )
case (sel)
3'b000: d_out[0] = d_in;
3'b001: d_out[1] = d_in;
3'b010: d_out [2]= d_in;
3'b011: d_out [3]= d_in;
3'b100: d_out [4]= d_in;
3'b101: d_out [5]= d_in;
3'b110: d_out [6]= d_in;
3'b111: d_out [7]= d_in;
default: d_out =0;
endcase
endmodule

2. f) 1:4 De-multiplexer. D_OUT[0]

1:4 D_OUT[1]
D_IN
D_OUT[2]
DEMUX
D_OUT[3]
SEL[0] SEL[1]
Truth TableFor1:4 De-multiplexer:

SELECT INPUT OUTPUT
SEL[1] SEL[0] D_IN D_OUT[3] D_OUT[2] D_OUT[1] D_OUT[0]
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0
VERILOG CODE
module demux1_4(d_in, sel, d_out);
input d_in;
input [1:0] sel;
output [3:0] d_out;
reg[3:0] d_out;
always @(d_in ,sel)
case (sel)
2'b00:
begin
d_out [0]= d_in;
d_out [1]=1’b0;
d_out [2]=1’b0;
d_out [3]=1’b0;
end
2'b01:
begin
d_out [0]=1’b0;
d_out [1]= d_in;
d_out [2]=1’b0;
d_out [3]=1’b0;
end
2'b10:
begin
d_out [0]=1’b0;
d_out [1]=1’b0;
d_out [2]= d_in;
d_out [3]=1’b0;
end
2'b11:
begin
d_out [0]=1’b0;
d_out [1]=1’b0;
d_out [2]=1’b0;
d_out [3]= d_in;
end
default d_out =4'b0000;
endcase
endmodule

2.g)4 bit Binary to Gray converter
Truth TableFor4 bit Binary to Gray converter:

Binary inputs Gray Outputs
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 B(3) G(3)
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
B(2) G(2)
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
G(1)
1 0 0 1 1 1 0 1
B(1)
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0 B(0) G(0)
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
G2 G1 G0
B1 B0 B1 B0 B1 B0
B3 B2 00 01 11 10 B3 B2 00 01 11 10 B3 B2 00 01 11 10
00 00 1 1 00 1 1
01 1 1 1 1 01 1 1 01 1 1
11 11 1 1 11 1 1
10 1 1 1 1 10 1 1 10 1 1
G3 = B3 G2 = B3 B2’ + B3 B2’ G1 = B2 B1’ + B1 B2’ G0 = B1’B0 + B1 B0’

G2 = B3 B2 G1 = B1  B2 G0 = B1  B0
VERILOG CODE
module binary_gray(g, b);
input [3:0] b;
output [3:0] g;
reg[3:0] g;
always @ (b)
begin
g[3] = b[3];

g[2] = b[3] ^ b[2];

g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
end
endmodule
2.g)N bit comparator
Truth Table For 2 bit comparator: A<B

A 2-BIT
A B A=B A>B A<B A>B
00 00 1 0 0 COMPARATER
00 01 0 0 1 B
01 00 0 1 0 A=B
VERILOG CODE
module comparator(a, b, alb,agb,aeb);
parameter n = 1;
input [n:0] a;
input [n:0] b;
output alb;
output agb;
output aeb;
reg alb,agb,aeb;
always @ (a , b)
begin
if (a<b)
begin
alb=1'b1;
agb=1'b0;
aeb=1'b0;
end
else if (a>b)
begin
agb=1'b1;
alb=1'b0;
aeb=1'b0;
end
else if (a==b)
begin
aeb=1'b1;
alb=1'b0;
agb=1'b0;
end
end
endmodule

Result: All combinational design has been realized , simulated and implemented using FPGA/CPLD using
HDL code

EXPERIMENT NO.3
Aim: Write a VHDL and verilog code to describe the functions of a full adder using three modeling styles.
3. a)Half Adder.
Truth Table For Half Adder: Boolean expressions: Sum=A  B, Carry=A*B

Inputs Outputs
A B Sum(S) Carry(C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
VHDL CODE VERILOG CODE

LIBRARY IEEE; module halfadder(a, b, sum, carry);
USE IEEE.STD_LOGIC_1164.ALL; input a;
USE IEEE.STD_LOGIC_ARITH.ALL; input b;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; output sum;
ENTITY HALFADDER IS output carry;
PORT ( A, B: IN STD_LOGIC; reg sum;
SUM, CARRY : OUT STD_LOGIC); reg carry;
END HALFADDER; always @ (a , b)
ARCHITECTURE BEHAVIORAL OF begin
HALFADDER IS sum = a^b;
BEGIN carry = a & b;
SUM <= A XOR B; end
CARRY<= A AND B; endmodule
END BEHAVIORAL;
Waveform for VHDL code:

3.b) FULL ADDER
Inputs Outputs
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Block Diagram For VHDL Code
Logic Diagram For VHDL Code Logic Diagram For Verilog Code
VHDL CODE FOR FULL ADDER USING COMPONENT VERILOG CODE FOR FULL ADDER
INSTANTIATION METHOD (STRUCTURAL STYLE) USING TWO HALF
ADDER.(STRUCTURAL STYLE)
LIBRARY IEEE; module FULL_2HA(A, B, C, SUM,
USE IEEE.STD_LOGIC_1164.ALL; CARRY);
USE IEEE.STD_LOGIC_ARITH.ALL; input A;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input B;
ENTITY FULLADDER IS input C;
PORT ( A,B,C : IN STD_LOGIC; output SUM;
CARRY : OUT STD_LOGIC; output CARRY;
SUM : OUT STD_LOGIC); wire S1,T1,T2;
END FULLADDER; xor
X1(S1,A,B),
ARCHITECTURE BEHAVIORAL OF FULLADDER IS X2(SUM,S1,C);
COMPONENT HALFADDER and
PORT ( A : IN STD_LOGIC; A1(T1,S1,C),
B : IN STD_LOGIC; A2(T2,A,B);
SUM : OUT STD_LOGIC; or
CARRY : OUT STD_LOGIC); O1(CARRY,T1,T2);
END COMPONENT; endmodule
SIGNAL TEMP1,TEMP2, TEMP3: STD_LOGIC;

BEGIN
L1: HALFADDER PORT MAP( A, B,TEMP1,TEMP2);
L2: HALFADDER PORT MAP( TEMP1,C,SUM,TEMP3);
CARRY <= TEMP2 OR TEMP3;
END BEHAVIORAL;

VHDL CODE USING DATA FLOW VERILOG CODE USING DATA FLOW
LIBRARY IEEE; module FULLADDER(A, B, C, SUM,
USE IEEE.STD_LOGIC_1164.ALL; CARRY);
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input A;
input B;
ENTITY FA IS input C;
PORT (A,B,C:IN BIT; output SUM;
SUM,CARRY:OUT BIT); output CARRY;
END FA;
wire T1, T2, T3;
ARCHITECTURE FA_ARCH OF FA IS
BEGIN assign SUM=A^B^C;
assign T1=A&B;
SUM <= AXOR B XOR C; assign T2=B&C;
assign T3=C&A;
CARRY<=(A AND B )OR (B AND C) OR (C assign CARRY=(T1| T2) | T3;
AND A);
endmodule
END FA_ARCH;

VHDL CODE (BEHAVIORAL STYLE) VERILOG CODE (BEHAVIORAL

STYLE)
LIBRARY IEEE; module fulladd(cin,x,y,s,co);

USE IEEE.STD_LOGIC_1164.ALL; input cin,x,y;
USE IEEE.STD_LOGIC_ARITH.ALL; output s,co;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; reg s,co;
ENTITY FULLADDER IS always@(cin or x or y)

PORT ( A,B,C : IN STD_LOGIC; begin
SUM,CARRY : OUT STD_LOGIC);
END FULLADDER ; case ({cin,x,y})
3'b000:{co,s}=2'b00;
ARCHITECTURE BEHAVIORAL OF FULLADDER IS 3'b001:{co,s}=2'b01;
BEGIN 3'b010:{co,s}=2'b01;
PROCESS( A,B,C) 3'b011:{co,s}=2'b10;
BEGIN 3'b100:{co,s}=2'b01;
IF(A='0' AND B='0' AND C='0') THEN SUM<='0'; 3'b101:{co,s}=2'b10;
CARRY<='0'; 3'b110:{co,s}=2'b10;
ELSIF(A='0' AND B='0' AND C='1') THEN SUM<='1'; 3'b111:{co,s}=2'b11;
CARRY<='0'; endcase
ELSIF(A='0' AND B='1' AND C='0') THEN SUM<='1'; end
CARRY<='0'; endmodule
ELSIF(A='0' AND B='1' AND C='1') THEN SUM<='0';
CARRY<='1';
CARRY<='0';
CARRY<='1';
CARRY<='1';
ELSE
SUM<='1'; CARRY<='1';
END IF;
END PROCESS;
END BEHAVIORAL;

Result: Three modeling styles of full adder have been realized simulated and implemented using
FPGA/CPLD using HDL Codes.

EXPERIMENT NO. 4
Aim: Write a model for 32 bit ALU using the schematic diagram shown below
OPCODE OPCODE ALU OPERATION

1 A+B
2 A-B
3 A Complement
4 A*B
5 A or B
6 A and B
7 A nand B
8 A xor B
Truth table For 32bits ALU:
EN OPC A B Y OPM OPERATION

xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx zzzzzzzzzzzzzzzz
0 xxxx - -
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx zzzzzzzzzzzzzzzz
0000000000000000 0000000000000000 000000000000000
1 0001 - A+B
0000000000001111 0000000000000000 000000000001111
0000000000000000 0000000000000000 000000000000000
1 0010 - A-B
0000000000001110 0000000000000010 000000000001100
0000000000000000 000000000000000 111111111111111
1 0011 - not A
0000000000001111 000000000001111 111111111110000
0000000000000000 0000000000000000 00000000000000000000000000000000
1 0100 - A*B
0000000000001001 0000000000001000 00000000000000000000000001001000
0000000000000000 0000000000000000 000000000000000
1 0101 - A or B
0000000000001111 0000000000000000 000000000001111
0000000000000000 0000000000000000 000000000000000
1 0110 - A and B
0000000000001111 0000000000001011 000000000001011
0000000000000000 0000000000000000 000000000000000
1 0111 - A nand B
0000000000001111 0000000000000010 000000000001101
0000000000000000 0000000000000000 000000000000000
1 1000 - A xor B
0000000000000000 0000000000000100 000000000000100

VERILOG CODE FOR 4 BIT ALU

MODEL
module alu (a, b, opc, en, y, opm);
input [31:0] a, b;
input en;
input [3:0] opc;
output [31:0] y;
output [63:0] opm;
reg [31:0]y;
reg [63:0]opm;
always @(a ,b , opc, en)
begin
if (en==1)
begin
case (opc)
4'b0001:y=a+b;
4'b0010:y=a-b;
4'b0011:y=~a;
4'b0100: opm=a*b;
4'b0101:y=a|b;
4'b0110:y=a&b;
4'b0111:y=~(a|b);
4'b1000:y=a^b;
endcase
end
else
begin
y = 32’bz;
opm = 32’bz;
end
end
endmodule
Result: 32 bit ALU operations have been realized, simulated and implemented on FPGA/CPLD using HDL
codes.

EXPERIMENT NO.5
Aim: Develop the HDL code for the following flip-flop, SR, D, JK, T.
5.a). SR Flip-flop RST
Truth Table For SR Flip-flop:

INPUTS OUTPUTS
RST S R Q QBAR S Q
S-R
1 X X 0 1
0 0 0 0 1 CLK
0 0 1 0 1 FLIP-FLOP
0 1 0 1 0 R QBAR
0 1 1 ?
VERILOG CODE
module sr_ff(s ,r ,clk , rst , q , qbar);
input s,r,clk,rst;
output q,qbar;
reg q,qbar;
always@(posedge clk , rst , s , r)
begin
if(rst==1)
begin
q=0;
qbar=1;
end
else
begin
if(s==0&&r==0)
begin
q=q;
qbar=qbar;
end
if(s==1&&r==0)
begin
q=1;
qbar=0;
end
if(s==0&&r==1)
begin
q=0;
qbar=1;
end
if (s==1&&r==1)
begin
q=1'bx;
qbar=1'bx;
end
end
end
endmodule

5. b). D Flip-flop
D Q
Truth Table For D Flip-flop: D
RESET D Q QBAR CLK
0 0 1 FLIP-FLOP
1 0 0 1 RST QBAR
1 1 1 0
VERILOG CODE
module D_FF(D, RESET, CLK, Q, QBAR);
input D;
input RESET;
input CLK;
output Q,QBAR;
reg Q,QBAR;
always@(posedge CLK , posedge RESET)
begin
if (RESET==0)
begin
Q=0;
QBAR=1;
end
else
begin
Q=D;
QBAR=~D;
end
end
endmodule

5.c). JK Flip-flop RST
Truth Table For JK Flip-flop:

RESET J K Q QBAR
J Q
1 0 1 J-K
0 0 0 0 1 CLK
0 0 1 0 1
0 1 0 1 0 K FLIP-FLOP QBAR
0 1 1 Toggle
VERILOG CODE
module JK_FF(J, K, CLK, RESET, Q,
QBAR);
input J;
input K;
input CLK;
input RESET;
output Q, QBAR;
reg Q, QBAR;
always @ (posedge CLK , posedge RESET)
begin
if(RESET==1)
begin
Q=0;
QBAR=1;
end
else if (J==0 && K==0)
begin
Q=Q;
QBAR=QBAR;
end
else if (J==0 && K==1)
begin
Q=0;
QBAR=1;
end
else if (J==1 && K==0)
begin
Q=1;
QBAR=0;
end
else
begin
Q=~Q;
QBAR=~QBAR;
end end
endmodule

5. d).T Flip-flop
Truth Table For T Flip-flop:

RESET T Q QBAR T Q
T
1 X 0 1
CLK
0 0 0 1 FLIP-FLOP
0 1 Toggle RST QBAR
VERILOG CODE
module T_FF(T, CLK, RESET, Q, QBAR);
input T, CLK,RESET;
output Q, QBAR;
reg Q,QBAR;
always @ (posedge CLK or RESET)

begin
if (RESET==1)
begin
Q=0;
QBAR=1;
end
else if (T==0)
begin
Q=Q;
QBAR=QBAR;
end
else
begin
Q=~Q;
QBAR=~QBAR;
end
end
endmodule
Result: Flip-flop operations have been realized, simulated and implemented on FPGA /CPLD using HDL
codes.

EXPERIMENT NO.6
Aim: Design 4 bits Binary, BCD counter, Any sequence (Synchronous reset and Asynchronous reset and
any sequence counters.
6.a).4-Bit Synchronous Counter

Truth Table For 4-Bit Synchronous Counter:
Reset Clock Q3 Q2 Q1 Q0
1 1 0 0 0 0
0 1 0 0 0 0
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 0 1 1
0 1 0 1 0 0
0 1 0 1 0 1
0 1 0 1 1 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 0 1
0 1 1 0 1 0
0 1 1 0 1 1
0 1 1 1 0 0
0 1 1 1 0 1
0 1 1 1 1 0
0 1 1 1 1 1
VERILOG CODE FOR 4 BIT BINARY

COUNTER ( Synchronous Reset )
module sync2(clk, reset, count);
input clk;
input reset;
output [3:0] count;
reg[3:0]count;
always@(posedge clk)
begin
if(reset==1)
count=4'b0000;
else
count=count+1;
end
endmodule

6. b). 4-Bit Asynchronous Counter
VERILOG CODE FOR 4 BIT BINARY

COUNTER ( Asynchronous Reset )
module synk(clk, reset, count);
input clk;
input reset;
output [3:0] count;
reg [3:0]count;
always@(posedge clk , posedge reset)

begin
if(reset==1)
count=4'b0000;
else
count=count+1;
end
endmodule
6.c). BCD Counter Truth Table For BCD Counter:
Clock Q3 Q2 Q1 Q0
VERILOG CODE for 4-bit 0 0 0 0 0
synchronous BCD counter. 1 0 0 0 1
module bcd (clk, reset, count); 1 0 0 1 0
1 0 0 1 1
input clk, reset; 1 0 1 0 0
output [3:0] count; 1 0 1 0 1
1 0 1 1 0
reg[3:0]count; 1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
always@(posedge clk , posedge reset) 1 0 0 0 0
begin
if(reset==1 | count==4'b1001)
begin
count=4'b0000;
end
else
count=count+1;
end
endmodule

6.d). Binary Any Sequence up down 4bit Counter

4
d_in /
VERILOG CODEfor Binary Any Sequence
up down 4bit Counter load
Binary Any 4
module seq_counter(clk,rst,load,updown, updown Sequence up / Bin_out
d_in,bin_out); down 4bit
rst Counter
input clk,rst,load,updown;
input [3:0] d_in;
output [3:0] bin_out;
clk
reg[3:0] bin_out;
always@ (posedgeclk)
begin
if(rst)
bin_out =4'b0000;
else if (load)
bin_out= d_in;
else if (updown)
bin_out = bin_out + 4'b0001;
else
bin_out = bin_out - 4'b0001;
end
endmodule
Result: Asynchronous and synchronous counters have been realized, simulated and implemented
on FPGA/CPLD using HDL codes.

INTERFACING PROGRAMS
EXPERIMENT NO.7
Aim: Write HDL code to display messages on the given seven segment display and LCD and accepting Hex
key pad input data.
7.a).LCD Display
Procedure:
1. Make the connection between FRC5 of the FPGA board to the LCD display Connector of the VTU card1.
2. Make the connection between FRC 4 of the FPGA board to the keyboard Connector of the VTU card1.
3. Make the connection between FRC 6 of the FPGA board to the dipswitch Connector of the VTU card1.
4. Connect the downloading cable and power supply to the FPGA board
5. Then open the xilinx impact software (refer ISE flow) select the slave Serial mode and select the
respective bit file and click program.
6. Make the reset switch on (active low).
7. Press the hex keys and analyze the data.
VHDL Code for LCD Display Package

--Package for LCD Display (This Package must be added to display all the messages on LCD)
-- Package File Template
-- Purpose: This package defines supplemental types, subtypes, constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package LCD_GRAP is
-- THE NUMBERS
constant ONE : std_logic_vector(7 downto 0) := "00110001";
constant TWO : std_logic_vector(7 downto 0) := "00110010";
constant THREE : std_logic_vector(7 downto 0) := "00110011";
constant FOUR : std_logic_vector(7 downto 0) := "00110100";
constant FIVE : std_logic_vector(7 downto 0) := "00110101";
constant SIX : std_logic_vector(7 downto 0) := "00110110";
constant SEVEN : std_logic_vector(7 downto 0) := "00110111";
constant EIGHT : std_logic_vector(7 downto 0) := "00111000";
constant NINE : std_logic_vector(7 downto 0) := "00111001";
constant ZERO : std_logic_vector(7 downto 0) := "00110000";
-- THE CHARACTERS
constant A : std_logic_vector(7 downto 0) := "01000001";
constant B : std_logic_vector(7 downto 0) := "01000010";
constant C : std_logic_vector(7 downto 0) := "01000011";
constant D : std_logic_vector(7 downto 0) := "01000100";
constant E : std_logic_vector(7 downto 0) := "01000101";
constant F : std_logic_vector(7 downto 0) := "01000110";
constant G : std_logic_vector(7 downto 0) := "01000111";
constant H : std_logic_vector(7 downto 0) := "01001000";
constant I : std_logic_vector(7 downto 0) := "01001001";
constant J : std_logic_vector(7 downto 0) := "01001010";
constant K : std_logic_vector(7 downto 0) := "01001011";
constant L : std_logic_vector(7 downto 0) := "01001100";
constant M : std_logic_vector(7 downto 0) := "01001101";
constant N : std_logic_vector(7 downto 0) := "01001110";
constant O : std_logic_vector(7 downto 0) := "01001111";
constant P : std_logic_vector(7 downto 0) := "01010000";
constant Q: std_logic_vector(7 downto 0) := "01010001";
constant R : std_logic_vector(7 downto 0) := "01010010";
constant S : std_logic_vector(7 downto 0) := "01010011";
constant T : std_logic_vector(7 downto 0) := "01010100";
constant U : std_logic_vector(7 downto 0) := "01010101";
constant V : std_logic_vector(7 downto 0) := "01010110";

constant W : std_logic_vector(7 downto 0) := "01010111";

constant X : std_logic_vector(7 downto 0) := "01011000";
constant Y : std_logic_vector(7 downto 0) := "01011001";
constant Z : std_logic_vector(7 downto 0) := "01011010";
-- SMAL LETTERS
constant SA : std_logic_vector(7 downto 0) := "01100001";
constant SB : std_logic_vector(7 downto 0) := "01100010";
constant SC : std_logic_vector(7 downto 0) := "01100011";
constant SD : std_logic_vector(7 downto 0) := "01100100";
constant SE : std_logic_vector(7 downto 0) := "01100101";
constant SF : std_logic_vector(7 downto 0) := "01100110";
constant SG : std_logic_vector(7 downto 0) := "01100111";
constant SH : std_logic_vector(7 downto 0) := "01101000";
constant SI : std_logic_vector(7 downto 0) := "01101001";
constant SJ : std_logic_vector(7 downto 0) := "01101010";
constant SK : std_logic_vector(7 downto 0) := "01101011";
constant SL : std_logic_vector(7 downto 0) := "01101100";
constant SM : std_logic_vector(7 downto 0) := "01101101";
constant SN : std_logic_vector(7 downto 0) := "01101110";
constant SO : std_logic_vector(7 downto 0) := "01101111";
constant SP : std_logic_vector(7 downto 0) := "01110000";
constant SQ : std_logic_vector(7 downto 0) := "01110001";
constant SR : std_logic_vector(7 downto 0) := "01110010";
constant SS : std_logic_vector(7 downto 0) := "01110011";
constant ST : std_logic_vector(7 downto 0) := "01110100";
constant SU : std_logic_vector(7 downto 0) := "01110101";
constant SV : std_logic_vector(7 downto 0) := "01110110";
constant SW : std_logic_vector(7 downto 0) := "01110111";
constant SX : std_logic_vector(7 downto 0) := "01111000";
constant SY : std_logic_vector(7 downto 0) := "01111001";
constant SZ : std_logic_vector(7 downto 0) := "01111010";
---THE SYMBOLS
constant SPACE: std_logic_vector(7 downto 0) := "00100000";
constant SLASH: std_logic_vector(7 downto 0) := "00101111";
constant MINUS: std_logic_vector(7 downto 0) := "00101101";
constant EQUAL: std_logic_vector(7 downto 0) := "00111101";
constant PLUS : std_logic_vector(7 downto 0) := "00101011";
constant STAR : std_logic_vector(7 downto 0) := "00101010";
constant DOT : std_logic_vector(7 downto 0) := "00101110";
end LCD_GRAP;
VHDL CODE for LCD Display

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.LCD_GRAP.ALL;
ENTITY HEXKEY_LCD IS
PORT (
CLK: IN STD_LOGIC; -- 16 MHZ CLOCK
RESET: IN STD_LOGIC; -- MASTER RESET PIN
LCD_RW : OUT STD_LOGIC;
LCD_SELECT : OUT STD_LOGIC;
LCD_ENABLE : OUT STD_LOGIC;
ROW: IN STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES
LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- GIVES REGISTERED DATA OUTPUT
COL: INOUT STD_LOGIC_VECTOR(0 TO 3));
END HEXKEY_LCD;
ARCHITECTURE HEXKEY_BEH OF HEXKEY_LCD IS

TYPE KEYPAD_STATE_TYPE IS (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1); --
STATE NAMES
TYPE STATE_TYPE IS (INITIAL,DISPLAY,CLEAR,LOCATION,PUTCHAR);
SIGNALSTATE,NEXT_STATE: STATE_TYPE;
-- CLEAR SCREEN.
CONSTANT CLR: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001";
-- DISPLAY ON, WITHOUT CURSOR.
CONSTANT DON: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00001100";
-- FUNCTION SET FOR 8-BIT DATA TRANSFER AND 2-LINE DISPLAY
CONSTANT SET: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00111000";
--FREQUENCY DIVIDER
CONSTANT BIG_DELAY: INTEGER :=16;
CONSTANT SMALL_DELAY: INTEGER :=2;
CONSTANT REG_SETUP: INTEGER :=1;
SIGNAL CS, NS: KEYPAD_STATE_TYPE; -- SIGNALS FOR CURRENT AND NEXTSTATES
SIGNAL DIV_REG: STD_LOGIC_VECTOR (16 DOWNTO 0); -- CLOCK DIVIDE REGISTER
SIGNAL DCLK,DDCLK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.
SIGNAL COL_REG_VALUE: STD_LOGIC_VECTOR (0 TO 3);
SIGNAL R1: STD_LOGIC; -- ROW DETECTION SIGNAL
SIGNAL KEY_VALUE: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL DATA: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
R1 <= ROW(3) OR ROW(2) OR ROW(1) OR ROW(0);
---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) -------------------------------
SYNC_PROC: PROCESS (DCLK, RESET, KEY_VALUE) -- THIS IS THE SYNCHRONOUS PART
BEGIN
IF (RESET = '0') THEN -- YOU MUST HAVE A RESET FOR FSM TO SYNTHESIZE PROPERLY
CS <= WAIT_R_0;
ELSIF (DCLK'EVENT AND DCLK = '1') THEN
CS <= NS;
END IF;
END PROCESS;
COMB_PROC: PROCESS (CS, R1, COL_REG_VALUE) -- THIS IS THE COMBINATIONAL PART
BEGIN
CASE CS IS
---------------------------------------------------------------------------------------------------
WHEN WAIT_R_0 => -- WAITS TILL A BUTTON IS PRESSED
COL<= "1111"; -- KEEP ALL COLUMNS ACTIVATED
IF R1 = '1' THEN -- A BUTTON WAS PRESSED. BUT WHICH ONE?
NS <= C3; -- LET'S FIND OUT
ELSE
NS <= WAIT_R_0;
END IF;
---------------------------------------------------------------------------------------------------
WHEN C3 => --
COL<= "0001"; -- ACTIVATE COLUMN 3
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 3
NS <= C2; -- SO CHECK IF IT WAS IN COLUMN 2
ELSE NS <= FOUND; -- BUTTON WAS IN COLUMN 3
END IF;
---------------------------------------------------------------------------------------------------
WHEN C2 => --
ELSE
NS <= FOUND; -- BUTTON WAS IN COLUMN 2
END IF;
---------------------------------------------------------------------------------------------------
WHEN C1 => --


ELSE
END IF;
---------------------------------------------------------------------------------------------------
WHEN C0 => --
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 0 ??
NS <= WAIT_R_0; -- SO THE BUTTON MUST HAVE BEEN DEPRESSED FAST
ELSE
END IF;
---------------------------------------------------------------------------------------------------
WHEN FOUND => --
COL<= COL_REG_VALUE;
IF R1 = '0' THEN -- THIS MEANS BUTTON IS DEPRESSED
NS <= WAIT_R_0; -- SO GO BACK TO INITIALSTATE
ELSE
NS <= SAMPLE; -- OTHERWISE WRITE THE KEY VALUE TO DATA REGISTER
END IF;
---------------------------------------------------------------------------------------------------
WHEN SAMPLE => -- THIS STATE WILL GENERATE A SIGNAL WITH ONE CLOCK PERIOD FOR
SAMPLING
NS <= WAIT_R_1; -- OTHERWISE WAIT TILL BUTTON IS PRESSED
---------------------------------------------------------------------------------------------------
WHEN WAIT_R_1 => --
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS DEPRESSED
NS <= WAIT_R_0; -- SO GO BACK TO INITIALSTATE
ELSE
END IF;
---------------------------------------------------------------------------------------------------
END CASE;
END PROCESS;
---------------------------------------------------------------------------------------------------
WRITE_DATA: PROCESS (DCLK, CS, KEY_VALUE) -- WRITE VALID DATA TO REGISTER
BEGIN
IF DCLK'EVENT AND DCLK = '0' THEN -- ON THE FALLING EDGE
IF CS = FOUND THEN
DATA <= KEY_VALUE;
END IF;
END IF;
END PROCESS; -- WRITE_DATA
---------------------------------------------------------------------------------------------------
COL_REG: PROCESS (DCLK, CS, COL) -- THIS IS THE COLUMN VALUE REGISTER
BEGIN
IF (DCLK'EVENT AND DCLK = '0') THEN -- REGISTER THE COL VALUE ON THE FALLING EDGE
IF (CS = C3 OR CS = C2 OR CS = C1 OR CS = C0) THEN -- PROVIDED WE'RE IN STATES C3 THRU
C0 ONLY
COL_REG_VALUE <= COL; -- OTHERWISE THE COLUMN VALUE IS NOT VALID
END IF;
END IF;
END PROCESS; -- COL_REG
---------------------------------------------------------------------------------------------------
DECODER: PROCESS(ROW, COL_REG_VALUE) -- DECODES BINARY VALUE OF PRESSED KEY
FROM ROW AND
COLUMN
VARIABLE CODE: STD_LOGIC_VECTOR (0 TO 7);

BEGIN
CODE := (ROW & COL_REG_VALUE);
CASE CODE IS
-- COL
-- ROW 0 0123
WHEN "00010001" => KEY_VALUE <= ZERO;--KEY 0
WHEN "00010010" => KEY_VALUE <= ONE;--KEY 1
WHEN "00010100" => KEY_VALUE <= TWO;--KEY 2
WHEN "00011000" => KEY_VALUE <= THREE;--KEY 3
-- ROW 1
WHEN "00100001" => KEY_VALUE <= FOUR;--KEY 4
WHEN "00100010" => KEY_VALUE <= FIVE;--KEY 5
WHEN "00100100" => KEY_VALUE <= SIX;--KEY 6
WHEN "00101000" => KEY_VALUE <= SEVEN;--KEY 7
-- ROW 2
WHEN "01000001" => KEY_VALUE <= EIGHT;--KEY 8
WHEN "01000010" => KEY_VALUE <= NINE;--KEY 9
WHEN "01000100" => KEY_VALUE <= A;--KEY A
WHEN "01001000" => KEY_VALUE <= B;--KEY B
-- ROW 3
WHEN "10000001" => KEY_VALUE <= C;--KEY C
WHEN "10000010" => KEY_VALUE <= D;--KEY D
WHEN "10000100" => KEY_VALUE <= E;--KEY E
WHEN "10001000" => KEY_VALUE <= F;--KEY F
WHEN OTHERS => KEY_VALUE <= SPACE; -- JUST IN CASE
END CASE;
END PROCESS; -- DECODER
---------------------------- END OF FSM1 (KEYPAD SCANNER) ---------------------------------------
-- SELECT THE APPROPRIATE LINES FOR SETTING FREQUENCY
CLK_DIV: PROCESS (CLK, DIV_REG) -- CLOCK DIVIDER
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
DIV_REG <= DIV_REG + 1;
END IF;
END PROCESS;
DCLK <= DIV_REG(8);
DDCLK<=DIV_REG(10);
---------------------------- END OF CLOCK DIVIDER -------------------------------------------------
LCD_RW<='0';
PROCESS (DDCLK,RESET)
VARIABLE COUNT: INTEGERRANGE 0 TO BIG_DELAY;
VARIABLE C1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF RESET = '0' THEN
STATE<=INITIAL;
COUNT:=0;
LCD_ENABLE<='0';
LCD_SELECT<='0';
C1 := "01111111";
ELSIF DDCLK'EVENT AND DDCLK = '1' THEN
CASESTATE IS
WHEN INITIAL => -- TO SET THE FUNCTION
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=SET;
LCD_SELECT<='0';
IF COUNT=SMALL_DELAY THEN
STATE<=DISPLAY;

COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN DISPLAY => -- TO SET DISPLAY ON
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=DON;
LCD_SELECT<='0';
STATE<=CLEAR;COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN CLEAR => -- CLEAR THE SCREEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=CLR;
LCD_SELECT<='0';
IF COUNT=BIG_DELAY THEN
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN LOCATION => -- CLEAR THE SCREEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
IF COUNT=0 THEN
IF C1="10001111" THEN
C1:="11000000";
ELSIF C1="11001111" THEN
C1:="10000000";
ELSE
C1:=C1+'1';
END IF;
END IF;
LCD_DATA <= C1 ;
LCD_SELECT<='0';
STATE<=PUTCHAR;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN PUTCHAR=> -- DISPLAY THE CHARACTER ON THE LCD
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
CASE C1 IS

WHEN "10000000" => LCD_DATA<= H ;--SIGLE LINE

WHEN "10000001" => LCD_DATA<= E ;--SIGLE LINE
WHEN "10000010" => LCD_DATA<= X ;--SIGLE LINE
WHEN "10000011" => LCD_DATA<= SPACE ;--SIGLE LINE
WHEN "10000101" => LCD_DATA<= K ;--SIGLE LINE
WHEN "10000111" => LCD_DATA<= Y ;--SIGLE LINE
WHEN "10001000" => LCD_DATA<= B ;
WHEN "10001001" => LCD_DATA<= O ;
WHEN "10001010" => LCD_DATA<= A ;
WHEN "10001011" => LCD_DATA<= R ;
WHEN "10001100" => LCD_DATA<= D ;
WHEN "10001101" => LCD_DATA<= SPACE ;
WHEN "10001111" => LCD_DATA<= SPACE;
WHEN "11000000" => LCD_DATA<= K ;--SIGLE LINE
WHEN "11000010" => LCD_DATA<= Y ;--SIGLE LINE
WHEN "11000011" => LCD_DATA<= P ;--SIGLE LINE
WHEN "11000100" => LCD_DATA<= R ;--SIGLE LINE
WHEN "11000110" => LCD_DATA<= S ;--SIGLE LINE
WHEN "11001000" => LCD_DATA<= E ;
WHEN "11001001" => LCD_DATA<= D ;
-- WHEN "11001011" => LCD_DATA<= RIGHT_ARROW ;
WHEN "11001101" => LCD_DATA<= DATA ;
WHEN OTHERS => NULL;
END CASE ;
LCD_SELECT<='1';
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
END CASE;
END IF;
END PROCESS;
END HEXKEY_BEH;
===============================================================
UCF FILE(USER CONSTRAINT FILE)
NET "CLK" LOC = "P52" ;
NET "COL<0>" LOC = "P139" ;
NET "COL<1>" LOC = "P134" ;
NET "COL<2>" LOC = "P136" ;
NET "COL<3>" LOC = "P132" ;
NET "LCD_DATA<0>" LOC = "P21" ;

NET "LCD_ENABLE" LOC = "P19" ;

NET "LCD_RW" LOC = "P20" ;
NET "LCD_SELECT" LOC = "P4" ;
NET "RESET" LOC = "P41" ;
NET "ROW<0>" LOC = "P126" ;
NET "ROW<1>" LOC = "P129" ;
NET "ROW<2>" LOC = "P124" ;
NET "ROW<3>" LOC = "P122" ;
===============================================================
7)b. SEVEN SEGMENT DISPLAY
Procedure:
1. Make the connection between FRC5 of the FPGA board to the seven-segment connector of the
VTUcard1.
2. Make the connection between FRC 1 of the FPGA board to the keyboard connector of the VTU card.
3. Make the connection between FRC 5 of the FPGA board to the 7segment connector of the VTU card.
4. Connect the downloading cable and power supply to the fpga board.
5. Then open the xilinx impact software (refer ISE flow) select the slave serial mode and select the
VHDL CODE FOR SEVEN DISPLAY

------------------------------------
--CODE FOR SIMULATING 16 KEYS USING
--KEYBOARD PROVIDED ON SPARTAN BOARD
------------------------------------
LIBRARY IEEE;
ENTITY KEY IS
PORT ( COLUMN : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0):=”0001”;
ROW_READ : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK : IN STD_LOGIC;
DISP_SELECT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SEVEN_SEG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END KEY;

ARCHITECTURE BEHAVIORAL OF KEY IS

BEGIN
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN

COLUMN <=COLUMN(2 DOWNTO 0)& COLUMN (3); --SHIFTING
END IF;
END PROCESS;
DISP_SELECT <=”1110”; ----TO SELECT DISPLAY
PROCESS(ROW_READ,COLUMN)
BEGIN
CASE COLUMN IS
WHEN "0001" => CASE ROW_READ IS

WHEN "0001" => SEVEN_SEG <= "1111110";
WHEN "0010" => SEVEN_SEG <= "0110011";
WHEN "0100" => SEVEN_SEG <= "1111111";
WHEN "1000" => SEVEN_SEG <= "1001110";
WHEN OTHERS=> SEVEN_SEG <= "0000000";
END CASE;

WHEN "0001" => SEVEN_SEG <= "0110000";
WHEN "0010" => SEVEN_SEG <= "1011011";
WHEN "0100" => SEVEN_SEG <= "1111011";
WHEN "1000" => SEVEN_SEG <= "0111101";
END CASE;
WHEN "0001" => SEVEN_SEG <= "1101101";
WHEN "0010" => SEVEN_SEG <= "1011111";
WHEN "0100" => SEVEN_SEG <= "1110111";
WHEN "1000" => SEVEN_SEG <= "1001111";
END CASE;
WHEN "0001" => SEVEN_SEG <= "1111001";
WHEN "0010" => SEVEN_SEG <= "1110000";
WHEN "0100" => SEVEN_SEG <= "0011111";
WHEN "1000" => SEVEN_SEG <= "1000111";
END CASE;
WHEN OTHERS=> NULL;
END CASE;
END PROCESS;
END BEHAVIORAL;

===============================================================
NET "CLK" LOC = "P52";
NET "COLUMN <0>" LOC = "P78";
NET "DISP_SELECT<0>" LOC = "P23";
NET "DISP_SELECT <1>" LOC = "P24";
NET "ROW_READ <0>" LOC = "P74";
NET "SEVEN_SEG<0>" LOC = "P18";
NET "SEVEN_SEG <1>" LOC = "P17";
===============================================================

EXPERIMENT NO.8
Aim: To control speed and direction of DC motor and Stepper motor.
8.a). DC Motor
Procedure:
1. Make the connection between FRC9 of the fpga board to the dc motor connector of the vtu card2.
2. Make the connection between FRC7 of the fpga board to the keyboard connector of the vtucard2.
3. Make the connection between FRC1 of the fpga board to the dip switch connector of the vtu card2.
5. Then open the xilinx impact software (refer ise flow) select the slave serial mode and select the
7. Press the hex keys and analyze the speed changes.
VHDL CODE FOR DC MOTOR CONTROL

LIBRARY IEEE;
ENTITY DCMOTOR IS
PORT ( CLK: IN STD_LOGIC; -- 4 MHZ CLOCK

RESET,DIR: IN STD_LOGIC; -- MASTER RESET PIN
PWM : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
RLY: OUT STD_LOGIC;
ROW: IN STD_LOGIC_VECTOR(0 TO 3) ); -- THIS ARE THE ROW LINES
END DCMOTOR;
ARCHITECTURE DCMOTOR1 OF DCMOTOR IS

SIGNAL COUNTER : STD_LOGIC_VECTOR(7 DOWNTO 0):="11111110";
SIGNAL DDCLK,TICK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.
SIGNAL DUTY_CYCLE: INTEGER RANGE 0 TO 255;
BEGIN


BEGIN
END IF;
END PROCESS;
DDCLK<=DIV_REG(12);
TICK <= ROW(0) AND ROW(1) AND ROW(2) AND ROW(3);
PROCESS(TICK)
BEGIN
IF FALLING_EDGE(TICK) THEN
CASE ROW IS
WHEN "1110" => DUTY_CYCLE <= 255 ; --MOTOR SPEED 1
WHEN OTHERS => DUTY_CYCLE <= 100;
END CASE;
END IF;
END PROCESS;
PROCESS(DDCLK, RESET)
BEGIN
IF RESET = '0' THEN
COUNTER <= (OTHERS => '0');
PWM<="01";
ELSIF (DDCLK'EVENT AND DDCLK = '1') THEN
COUNTER <= COUNTER + 1;
IF COUNTER >= DUTY_CYCLE THEN
PWM(1) <= '0';
ELSE
PWM(1) <= '1';
END IF; END IF;
END PROCESS;
-- RLY<='1'; --MOTOR DIRECTION CONTROL- CLOCK WISE
RLY<=DIR;--MOTOR DIRECTION CONTROL- COUNTER CLOCK WISE
END DCMOTOR1;
==============================================================
UCF FILE (USER CONSTRAINT FILE)
NET "PWM<0>" LOC = "P141" ;
NET "PWM<1>" LOC = "P4" ;
NET "RLY" LOC = "P2" ;
NET "DIR" LOC = "P74" ;
NET "ROW<0>" LOC = "P69" ;
NET "ROW<1>" LOC = "P63" ;
NET "ROW<2>" LOC = "P59" ;
NET "ROW<3>" LOC = "P57" ;
===============================================================
8.b). Stepper Motor

Procedure:
1. Make the connection between FRC9 of the FPGA board to the stepper motor connector of the VTUcard2.
2. Make the connection between FRC1 of the FPGA board to the dip switch connector of the VTUcard2.
3. Connect the downloading cable and power supply to the FPGA board.
6. Press the hex keys and analyze the speed changes.
S(3) S(2) S(1) S(0)

1 0 0 1
1 1 0 0
0 1 1 0
0 0 1 1
1 0 0 1
VHDL CODE FOR STEPPER MOTOR CONTROL

LIBRARY IEEE;
ENTITY STEPPER IS
PORT ( DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ROW: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK,RESET : IN STD_LOGIC;
DIRE: IN STD_LOGIC);
END STEPPER;
ARCHITECTURE BEHAVIORAL OF STEPPER IS

SIGNAL CLK_DIV : STD_LOGIC_VECTOR(25 DOWNTO 0);
SIGNAL CLK_INT: STD_LOGIC;
SIGNAL SHIFT_REG : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN

IF RISING_EDGE (CLK) THEN

CLK_DIV <= CLK_DIV + '1';
CASE ROW IS
WHEN ”00” =>CLK_INT <= CLK_DIV(19);
WHEN ”01”=> CLK_INT<= CLK_DIV(18);
WHEN”10”=> CLK_INT<= CLK_DIV(15);
WHEN OTHERS => CLK_INT<= CLK_DIV(13);
END CASE;
END IF;
END PROCESS;
PROCESS(RESET,CLK_INT)
BEGIN
IF RESET='0' THEN
SHIFT_REG <= "1001";
ELSIF RISING_EDGE(CLK_INT) THEN
CASE DIRE IS
WHEN ‘0’ =>SHIFT_REG <= SHIFT_REG(2 DOWNTO 0) & SHIFT_REG(3);
WHEN ‘1’ =>SHIFT_REG <= SHIFT_REG(0) & SHIFT_REG(3 DOWNTO 1);
END CASE;END IF;
END PROCESS;
DOUT <= SHIFT_REG;
END BEHAVIORAL;
============================================================================
NET "CLK" LOC = "P52";
NET "DIRE " LOC = "P74";
NET "DOUT<0>" LOC = "P141";
NET "RESET" LOC = "P76";
NET "ROW<0>" LOC = "P77";
NET "ROW<1>" LOC = "P79";

EXPERIMENT NO.9
Aim: To generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using DAC change the
frequency and amplitude.
Procedure:
1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2.
2. Make the connection between FRC1 of the FPGA board to the dip switch connector of the VTU card2.
5. Make the reset switch on (active low) and analyze the data.
9.a) SINE WAVE
Max amplitude(5v)=127 sinθ +127

where θ =0,15,30,45………..345
Resolution of the DAC :8 Bit (2pow8=256 steps)
VHDL CODE FOR SINE WAVE

LIBRARY IEEE;
ENTITY DIGITAL_SINE_WAVE IS
PORT ( CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DAC_OUT : OUT STD_LOGIC_VECTOR(0 TO 7));
END DIGITAL_SINE_WAVE ;
ARCHITECTURE BEHAVIORAL OF DIGITAL_SINE_WAVE IS

SIGNAL I: INTEGER RANGE 0 TO 23;
TYPE LOOK_UP IS ARRAY(0 TO 23) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
CONSTANT SINE_LOOKUP:LOOK_UP:=(“01111111”,”10100000”,10111110”,”11011001”,
”11101101”,”11111001”,”11111110”, --0 TO 90
“11111001”,”11101101”,”11011001”,”10111110”,”10100000”,”01111111”, --TILL 180
“01011110”,”00111111”,”00100101”,”00010001”,”00000100”,”00000000”, --TILL 270
“00000100”,”00010001”,”00100101”,”00111111”,”01011110”);
SIGNAL TEMP : STD_LOGIC_VECTOR(2 DOWNTO 0):=”000”;
BEGIN

PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
TEMP <= TEMP + '1' ;
END IF;
END PROCESS;
PROCESS(TEMP(2))
BEGIN
IF TEMP(2)= '1' AND TEMP(2)’EVENT THEN
IF RST='1' THEN
DAC_OUT<= "00000000";
ELSE
I <= I +1;
DAC_OUT<=SINE_LOOKUP(I);
IF I=23 THEN
I<=0;
END IF;
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;
===========================================================================
NET "DAC_OUT<0>" LOC = "P21" ;
NET "RST" LOC = "P74" ;

9.b) SQUARE WAVE
VHDL CODE FOR SQUARE WAVE

LIBRARY IEEE;
ENTITY SQUARE_WAVE IS
RST : IN STD_LOGIC;
END SQUARE_WAVE;
ARCHITECTURE BEHAVIORAL OF SQUARE_WAVE IS

SIGNAL TEMP : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUNTER : STD_LOGIC_VECTOR(0 TO 7);
SIGNAL EN :STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
END IF;
END PROCESS;
PROCESS(TEMP(3))
BEGIN
IF RST='1' THEN
COUNTER <= "00000000";
ELSIF RISING_EDGE(TEMP(3)) THEN
IF COUNTER<255 AND EN='0' THEN
COUNTER <= COUNTER + 1 ;
EN<='0';
DAC_OUT <="00000000"; --DAC_OUT<=COUNTER;(FOR TRIANGULAR WAVE)
ELSIF COUNTER=0 THEN
EN<='0';
ELSE
EN<='1';
COUNTER <= COUNTER-1;
DAC_OUT <="11111111"; --DAC_OUT<=COUNTER;(FOR TRIANGULAR WAVE)
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;
===============================================================
===============================================================

9.c) TRIANGULAR WAVE
VHDL CODE FOR TRIANGULAR WAVE

LIBRARY IEEE;
ENTITY TRIANGULAR_WAVE IS
RST : IN STD_LOGIC;
END TRIANGULAR_WAVE ;
ARCHITECTURE BEHAVIORAL OF TRIANGULAR_WAVE IS
BEGIN
PROCESS(CLK)
BEGIN
END IF;
END PROCESS;
PROCESS(TEMP(3))
BEGIN
IF RST='1' THEN
COUNTER <= "000000000";
IF COUNTER(0)='1' THEN
DAC_OUT <=COUNTER(1 TO 8);
ELSE
DAC_OUT <=NOT(COUNTER(1 TO 8));
END IF;END IF;
END PROCESS;
END BEHAVIORAL;
================================================
================================================

9.d). RAMP WAVE
VHDL CODE FOR RAMP WAVE

LIBRARY IEEE;
ENTITY RAMP_WAVE IS
RST : IN STD_LOGIC;
END RAMP_WAVE;
ARCHITECTURE BEHAVIORAL OF RAMP_WAVE IS

BEGIN
PROCESS(CLK)
BEGIN
END IF;
END PROCESS;
PROCESS(TEMP(3))
BEGIN
IF RST='1' THEN
COUNTER <= "00000000";
END IF;
END PROCESS;
DAC_OUT <=COUNTER;
END BEHAVIORAL;


9.e). SAWTOOTH WAVE
VHDL CODE FOR SAWTOOTH WAVE

LIBRARY IEEE;
ENTITY SWATOOTH_WAVE IS
RST : IN STD_LOGIC;
END SWATOOTH_WAVE;
ARCHITECTURE BEHAVIORAL OF SWATOOTH_WAVE IS

BEGIN
PROCESS(CLK)
BEGIN
END IF;
END PROCESS;
PROCESS(TEMP(3))
BEGIN
IF RST='1' THEN
COUNTER <= "00000000";
END IF;
END PROCESS;
DAC_OUT <=COUNTER;
END BEHAVIORAL;
===============================================================
===============================================================

EXPERIMENT NO.10
Aim: To accept 8 channel analog signal, and display the data on LCD panel or seven segment display.
PROCEDURE:
1. Make the connection between frc5 of the FPGA board to the LCD display connector of the VTU card1.
2. Make the connection between frc10 of the FPGA board to the ADC connector of the VTU card1.
3. Make the connection between frc6 of the FPGA board to the dip switch connector of the VTU card1.
4. Short the jumper j1 to the vin to get the analog signal.
VHDL CODING
LIBRARY IEEE;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
ENTITY ADC_LCD IS
RESET: IN STD_LOGIC; -- MASTER RESET PIN
INTR: IN STD_LOGIC;
ADC_OUT: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CS,RD,WR:OUT STD_LOGIC;
LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); -- GIVES REGISTERED DATA OUTPUT
END ADC_LCD;
ARCHITECTURE ADC_BEH OF ADC_LCD IS
SIGNAL STATE,NEXT_STATE: STATE_TYPE;
-- CLEAR SCREEN.
--FREQUENCY DIVIDER
SIGNAL COUNTER : STD_LOGIC_VECTOR(18 DOWNTO 0);
SIGNAL CLK_DIV :STD_LOGIC;
SIGNAL DIGITAL_DATA1,DATA1,DATA2: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DIGITAL_DATA : INTEGER RANGE 0 TO 255;
SIGNAL NTR :STD_LOGIC;
BEGIN
IBUF_INST : IBUF
-- EDIT THE FOLLOWING GENERIC TO SPECIFY THE I/O STANDARD FOR THIS PORT.
GENERIC MAP (
IOSTANDARD => "LVCMOS25")
PORT MAP (
O => NTR, -- BUFFER OUTPUT
I => INTR -- BUFFER INPUT (CONNECT DIRECTLY TO TOP-LEVEL PORT));
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNTER<=COUNTER+'1';
END IF;
END PROCESS;
CLK_DIV<=COUNTER(7);

CS <='0';
WR <=NTR;
DIGITAL_DATA1 <= ADC_OUT ;
RD <='0';
DIGITAL_DATA<=CONV_INTEGER(DIGITAL_DATA1) ;
PROCESS(DIGITAL_DATA)
BEGIN
CASE (DIGITAL_DATA) IS
WHEN 0 TO 100 => DATA1 <= ONE ; DATA2 <= NINE ;
WHEN 101 TO 110 => DATA1 <= TWO ; DATA2 <= ZERO ;
WHEN 111 TO 120 => DATA1 <= TWO ; DATA2 <= ONE ;
WHEN 121 TO 130 => DATA1 <= TWO ; DATA2 <= TWO ;
WHEN 131 TO 140 => DATA1 <= TWO ; DATA2 <= THREE ;
WHEN 141 TO 150 => DATA1 <= TWO ; DATA2 <= FOUR ;
WHEN 151 TO 160 => DATA1 <= TWO ; DATA2 <= FIVE ;
WHEN 161 TO 170 => DATA1 <= TWO ; DATA2 <= SIX ;
WHEN 171 TO 180 => DATA1 <= TWO ; DATA2 <= SEVEN ;
WHEN 181 TO 190 => DATA1 <= TWO ; DATA2 <= EIGHT ;
WHEN 191 TO 200 => DATA1 <= TWO ; DATA2 <= NINE ;
WHEN 201 TO 205 => DATA1 <= THREE ; DATA2 <= ZERO ;
WHEN 206 TO 210 => DATA1 <= THREE ; DATA2 <= ONE ;
WHEN 211 TO 215 => DATA1 <= THREE ; DATA2 <= TWO ;
WHEN 216 TO 220 => DATA1 <= THREE ; DATA2 <= THREE ;
WHEN 221 TO 225 => DATA1 <= THREE ; DATA2 <= FOUR ;
WHEN 226 TO 230 => DATA1 <= THREE ; DATA2 <= FIVE ;
WHEN 231 TO 235 => DATA1 <= THREE ; DATA2 <= SIX ;
WHEN 236 TO 240 => DATA1 <= THREE ; DATA2 <= SEVEN ;
WHEN 241 TO 245 => DATA1 <= THREE ; DATA2 <= EIGHT ;
WHEN 246 TO 250 => DATA1 <= THREE ; DATA2 <= NINE ;
WHEN OTHERS => DATA1 <= FOUR ; DATA2 <= ZERO ;
END CASE;
END PROCESS;
LCD_RW<='0';
PROCESS (CLK_DIV,RESET)
VARIABLE COUNT: INTEGER RANGE 0 TO BIG_DELAY;
BEGIN
IF RESET = '1' THEN
STATE<=INITIAL;
COUNT:=0;
LCD_ENABLE<='0';
LCD_SELECT<='0';
C1 := "01111111";
ELSIF CLK_DIV'EVENT AND CLK_DIV = '1' THEN
CASE STATE IS
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=SET;
LCD_SELECT<='0';
STATE<=DISPLAY;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=DON;
LCD_SELECT<='0';

STATE<=CLEAR;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=CLR;
LCD_SELECT<='0';
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
IF COUNT=0 THEN
IF C1="10001111" THEN
C1:="10000000";
ELSE
C1:=C1+'1';
END IF;
END IF;
LCD_DATA <= C1 ;
LCD_SELECT<='0';
STATE<=PUTCHAR;
COUNT:=0; ELSE
COUNT:=COUNT+1;
END IF;
LCD_ENABLE<='1';
ELSE LCD_ENABLE<='0';
END IF;
CASE C1 IS
WHEN "10000000" => LCD_DATA<= A ;
WHEN "10000001" => LCD_DATA<= D ;
WHEN "10000010" => LCD_DATA<= C ;
WHEN "10000100" => LCD_DATA<= V ;
WHEN "10000101" => LCD_DATA<= O ;
WHEN "10000110" => LCD_DATA<= L ;
WHEN "10000111" => LCD_DATA<= T ;
WHEN "10001000" => LCD_DATA<= A ;
WHEN "10001001" => LCD_DATA<= G ;
WHEN "10001010" => LCD_DATA<= E ;
WHEN "10001100" => LCD_DATA<= EQUAL ;
WHEN "10001101" => LCD_DATA<= DATA1 ;
WHEN "10001110" => LCD_DATA<= DOT ;
WHEN "10001111" => LCD_DATA<= DATA2;


END CASE ;
LCD_SELECT<='1';
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
END CASE;
END IF;
END PROCESS;
END ADC_BEH;
===============================================================
NET "CS" LOC = "P6" ;
NET "INTR" LOC = "P12" ;
NET "ADC_OUT<0>" LOC = "P13" ;
NET "WR" LOC = "P11";
NET "RD" LOC = "P10";
NET "LCD_RW" LOC = "P20";
NET "LCD_SELECT" LOC = "P4";
===============================================================

EXPERIMENT NO.11
Aim: To operate elevator and observe the simulation results on LCD.
Procedure:
1. Make the connection between FRC5 of the FPGA board to the LCD display connector of the VTU card1.
2. Make the connection between FRC1 of the FPGA board to the keyboard connector of the VTUcard1.
3. make the connection between FRC6 of the FPGA board to the dip switch connector of the VTU card1.
VHDL CODE
LIBRARY IEEE;
ENTITY ELEVATOR IS
GENERIC(BITS : INTEGER := 8 ); -- NUMBER OF BITS USED FOR DUTY CYCLE.
-- ALSO DETERMINES PWM PERIOD.
RESET,EN: IN STD_LOGIC; -- MASTER RESET PIN
PWM : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ROW: IN STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES
LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- GIVES REGISTERED DATA OUTPUT
COL: INOUT STD_LOGIC_VECTOR(0 TO 3));
END ELEVATOR;
ARCHITECTURE RTL OF ELEVATOR IS
SIGNAL COUNTER : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0):="00000000";
TYPE KEYPAD_STATE_TYPE IS (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1);
-- STATE NAMES
SIGNAL STATE,NEXT_STATE: STATE_TYPE;
-- CLEAR SCREEN.
--FREQUENCY DIVIDER
SIGNAL CS, NS: KEYPAD_STATE_TYPE; -- SIGNALS FOR CURRENT AND NEXT STATES
SIGNAL DUTY_CYCLE,DUTY_CYCLE1 : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0);
SIGNAL DCLK,DDCLK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.
SIGNAL COL_REG_VALUE: STD_LOGIC_VECTOR (0 TO 3);
SIGNAL R1,CLK_D,START,STOP: STD_LOGIC; -- ROW DETECTION SIGNAL
SIGNAL KEY_VALUE1,FLOOR,KEY_VALUE: INTEGER RANGE 0 TO 15;
SIGNAL DATA,DATA1,FLOOR_NUM: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL TEMP1,TEMP2,TEMP3,TEMP4: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL TEMP5,TEMP6,TEMP7,TEMP8: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
--CLK_OUT <= DCLK;
R1 <= ROW(3) OR ROW(2) OR ROW(1) OR ROW(0);
---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) -------------------------------
SYNC_PROC: PROCESS (DCLK, RESET, KEY_VALUE) -- THIS IS THE SYNCHRONOUS PART
BEGIN
IF (RESET = '0') THEN -- YOU MUST HAVE A RESET FOR FSM TO SYNTHESIZE PROPERLY
CS <= WAIT_R_0;

ELSIF (DCLK'EVENT AND DCLK = '1') THEN

CS <= NS;
END IF; END PROCESS;
COMB_PROC: PROCESS (CS, R1, COL_REG_VALUE) -- THIS IS THE COMBINATIONAL PART
BEGIN
CASE CS IS
WHEN WAIT_R_0 => -- WAITS TILL A BUTTON IS PRESSED
COL <= "1111"; -- KEEP ALL COLUMNS ACTIVATED
IF R1 = '1' THEN -- A BUTTON WAS PRESSED. BUT WHICH ONE?
NS <= C3; -- LET'S FIND OUT
ELSE
NS <= WAIT_R_0;
END IF;
---------------------------------------------------------------------------------------------------
WHEN C3 => --
COL <= "0001"; -- ACTIVATE COLUMN 3
ELSE NS <= FOUND; -- BUTTON WAS IN COLUMN 3
END IF;
---------------------------------------------------------------------------------------------------
WHEN C2 => --
ELSE
END IF;
---------------------------------------------------------------------------------------------------
WHEN C1 => --
ELSE
END IF;
---------------------------------------------------------------------------------------------------
WHEN C0 => --
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 0 ??
NS <= WAIT_R_0; -- SO THE BUTTON MUST HAVE BEEN DEPRESSED FAST
ELSE
END IF;
---------------------------------------------------------------------------------------------------
WHEN FOUND => --
COL <= COL_REG_VALUE;
IF R1 = '0' THEN -- THIS MEANS BUTTON IS DEPRESSED
NS <= WAIT_R_0; -- SO GO BACK TO INITIAL STATE
ELSE
NS <= SAMPLE; -- OTHERWISE WRITE THE KEY VALUE TO DATA REGISTER
END IF;
---------------------------------------------------------------------------------------------------
WHEN SAMPLE => -- THIS STATE WILL GENERATE A SIGNAL WITH ONE CLOCK PERIOD FOR
SAMPLING
---------------------------------------------------------------------------------------------------
WHEN WAIT_R_1 => --
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS DEPRESSED
NS <= WAIT_R_0; -- SO GO BACK TO INITIAL STATE
ELSE
END IF;
---------------------------------------------------------------------------------------------------
END CASE;
END PROCESS;

---------------------------------------------------------------------------------------------------
WRITE_DATA: PROCESS (DCLK, CS, KEY_VALUE) -- WRITE VALID DATA TO REGISTER
BEGIN
IF DCLK'EVENT AND DCLK = '0' THEN -- ON THE FALLING EDGE
IF CS = FOUND THEN
KEY_VALUE <= KEY_VALUE1;
END IF;
END IF;
END PROCESS; -- WRITE_DATA
---------------------------------------------------------------------------------------------------
COL_REG: PROCESS (DCLK, CS, COL) -- THIS IS THE COLUMN VALUE REGISTER
BEGIN
IF (DCLK'EVENT AND DCLK = '0') THEN -- REGISTER THE COL VALUE ON THE FALLING EDGE
IF (CS = C3 OR CS = C2 OR CS = C1 OR CS = C0) THEN -- PROVIDED WE'RE IN STATES C3 THRU C0 ONLY
COL_REG_VALUE <= COL; -- OTHERWISE THE COLUMN VALUE IS NOT VALID
END IF;
END IF;
END PROCESS; -- COL_REG
---------------------------------------------------------------------------------------------------
DECODER: PROCESS(ROW, COL_REG_VALUE) -- DECODES BINARY VALUE OF PRESSED KEY FROM
ROW AND
COLUMN
VARIABLE CODE: STD_LOGIC_VECTOR (0 TO 7);
BEGIN
CODE := (ROW & COL_REG_VALUE);
CASE CODE IS
-- COL
-- ROW 0 0123
WHEN "00010001" => KEY_VALUE1 <= 0;
WHEN "00010010" => KEY_VALUE1 <= 1;
WHEN "00010100" => KEY_VALUE1 <= 2;
WHEN "00011000" => KEY_VALUE1 <= 3;
-- ROW 1
WHEN "00100001" => KEY_VALUE1 <= 4;
WHEN "00100010" => KEY_VALUE1 <= 5;
WHEN "00100100" => KEY_VALUE1 <= 6;
WHEN "00101000" => KEY_VALUE1 <= 7;
-- ROW 2
WHEN "01000001" => KEY_VALUE1 <= 8;
WHEN "01000010" => KEY_VALUE1 <= 9;
WHEN "01000100" => KEY_VALUE1 <= 10;
WHEN "01001000" => KEY_VALUE1 <= 11;
-- ROW 3
WHEN "10000001" => KEY_VALUE1 <= 12;
WHEN "10000010" => KEY_VALUE1 <= 13;
WHEN "10000100" => KEY_VALUE1 <= 14;
WHEN "10001000" => KEY_VALUE1 <= 15;
WHEN OTHERS => KEY_VALUE1 <= 0;
END CASE;
END PROCESS; -- DECODER
---------------------------- END OF FSM1 (KEYPAD SCANNER) ---------------------------------------
BEGIN
END IF;
END PROCESS;
DCLK <= DIV_REG(8);
DDCLK<=DIV_REG(10);
CLK_D<=DIV_REG(22);
LCD_RW<='0';
PROCESS (DDCLK,RESET)
VARIABLE COUNT: INTEGER RANGE 0 TO BIG_DELAY;
BEGIN
IF RESET = '0' THEN

STATE<=INITIAL;
COUNT:=0;
LCD_ENABLE<='0';
LCD_SELECT<='0';
C1 := "01111111";
ELSIF DDCLK'EVENT AND DDCLK = '1' THEN
CASE STATE IS
LCD_ENABLE<='1';
END IF;
LCD_DATA<=SET;
LCD_SELECT<='0';
STATE<=DISPLAY;
COUNT:=0;
ELSE COUNT:=COUNT+1;
END IF;
LCD_ENABLE<='1';
END IF;
LCD_DATA<=DON;
LCD_SELECT<='0';
STATE<=CLEAR;
COUNT:=0;
END IF;
LCD_ENABLE<='1';
END IF;
LCD_DATA<=CLR;
LCD_SELECT<='0';
STATE<=LOCATION;
COUNT:=0;
END IF;
LCD_ENABLE<='1';
END IF;
IF COUNT=0 THEN
IF C1="10001111" THEN
C1:="11000000";
ELSIF C1="11001111" THEN
C1:="10000000";
ELSE C1:=C1+'1';
END IF;
END IF;
LCD_DATA <= C1;
LCD_SELECT<='0';
STATE<=PUTCHAR;
COUNT:=0;
END IF;
LCD_ENABLE<='1';
END IF;

CASE C1 IS
WHEN "10000000" => LCD_DATA<= F ;--SIGLE LINE
WHEN "10000001" => LCD_DATA<= L ;--SIGLE LINE
WHEN "10000010" => LCD_DATA<= O ;--SIGLE LINE
WHEN "10000011" => LCD_DATA<= O ;--SIGLE LINE
WHEN "10000100" => LCD_DATA<= R ;--SIGLE LINE
WHEN "10000110" => LCD_DATA<= N ;--SIGLE LINE
WHEN "10000111" => LCD_DATA<= U ;--SIGLE LINE
WHEN "10001000" => LCD_DATA<= M ;
WHEN "10001001" => LCD_DATA<= B ;
WHEN "10001010" => LCD_DATA<= E ;
WHEN "10001011" => LCD_DATA<= R ;
WHEN "10001101" => LCD_DATA<= EQUAL ;
WHEN "10001110" => LCD_DATA<= FLOOR_NUM ;
WHEN "11000001" => LCD_DATA<= T ;--SIGLE LINE
WHEN "11000010" => LCD_DATA<= A ;--SIGLE LINE
WHEN "11000011" => LCD_DATA<= T ;--SIGLE LINE
WHEN "11000100" => LCD_DATA<= U ;--SIGLE LINE
WHEN "11000111" => LCD_DATA<= TEMP1 ;--SIGLE LINE
WHEN "11001000" => LCD_DATA<= TEMP2 ;
END CASE ;
LCD_SELECT<='1';
STATE<=LOCATION;
COUNT:=0;
END IF; END CASE; END IF; END PROCESS;
PROCESS(CLK_D,RESET)
VARIABLE COU : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE START,STOP: STD_LOGIC; -- ROW DETECTION SIGNAL
BEGIN
IF RESET='0' THEN
COU:="00";
TEMP1 <= L ;
TEMP2 <= I ;
TEMP3 <= F ;
TEMP4 <= T ;
TEMP5 <= I ;
TEMP6 <= D ;
TEMP7 <= L ;
TEMP8 <= E ;
FLOOR_NUM <= ZERO ;
ELSIF RISING_EDGE(CLK_D) THEN
CASE KEY_VALUE IS
WHEN 0 => FLOOR_NUM <= ZERO ;
FLOOR <=0;
WHEN 1 => FLOOR_NUM <= ONE ;
FLOOR <=1;
WHEN 2 => FLOOR_NUM <= TWO ;
FLOOR <=2;
WHEN 3 => FLOOR_NUM <= THREE ;
FLOOR <=3;
WHEN 4 =>
TEMP1 <= D ;

TEMP2 <= O ;
TEMP3 <= O ;
TEMP4 <= R ;
TEMP5 <= O ;
TEMP6 <= P ;
TEMP7 <= E ;
TEMP8 <= N ;
WHEN 5 =>
TEMP1 <= D ;
TEMP2 <= O ;
TEMP3 <= O ;
TEMP4 <= R ;
TEMP5 <= C ;
TEMP6 <= L ;
TEMP7 <= O ;
TEMP8 <= S ;
WHEN 6 =>
START:='1';
STOP:='0';
WHEN 7 =>
STOP:='1';
START:='0';
==========================================================
WHEN OTHERS =>
TEMP1 <= I ;
TEMP2 <= D ;
TEMP3 <= L ;
NET "COL<0>" LOC = "P83" ;
TEMP4 <= E ;
NET "COL<1>" LOC = "P79" ;
TEMP5 <= K ;
NET "COL<2>" LOC = "P80" ;
TEMP6 <= E ;
NET "COL<3>" LOC = "P77" ;
TEMP7 <= Y ;
NET "ROW<0>" LOC = "P78" ;
TEMP8 <= SPACE ;
NET "ROW<1>" LOC = "P76" ;
END CASE;
NET "ROW<2>" LOC = "P75" ;
IF START='1' THEN
NET "ROW<3>" LOC = "P74" ;
IF COU=FLOOR THEN
START := '0';
NET "LCD_RW" LOC = "P20" ;
COU:=COU;
NET "LCD_SELECT" LOC = "P4" ;
TEMP7 <= "001100" & COU ;
ELSIF COU<=FLOOR THEN
COU:=COU + '1';
TEMP1 <= U ;
TEMP2 <= P ;
TEMP3 <= SPACE ;
TEMP4 <= SPACE ;
TEMP5 <= SPACE ;
TEMP6 <= "01111110" ;
========================================================
TEMP7 <= "001100" & COU ;
TEMP8 <= SPACE ;
ELSIF COU>=FLOOR THEN
COU:=COU-'1';
TEMP1 <= D ;
TEMP2 <= O ;
TEMP3 <= W ;
TEMP4 <= N ;
TEMP5 <= SPACE ;
TEMP6 <= "01111111" ;
TEMP7 <= "001100" & COU ;
TEMP8 <= SPACE ;
END IF; END IF; END IF;
END PROCESS;
END RTL;

Additional Code apart from syllabus


VIVA QUESTIONS
1) Differences between D-Latch and D flip-flop?
2) What is setup time and hold time?
3) What is racing condition?
4) What do you mean by comparator and write the truth table?
5) What is decoder and write the truth table?
6) What is encoder and write the truth table?
7) What is priority encoder, and what is the difference between encoder and priority
encoder?
8) What is the difference between decoder and encoder?
9) What is multiplexer and write the truth table?
10) Give the applications of mux?
11) What is the difference between decoder and multiplexer?
12) What do you mean by sequential circuits and combinational circuits?
13) Give the comparison between combinational and sequential circuits.
14) Give the comparison between synchronous and asynchronous circuits.
15) Draw and explain the working of basic bistable element.
16) Draw and explain the working of a) SR latch b) gated SR latch c) Gated D latch.
17) Draw and explain the working of all flip-flops.
18) Explain the working of 4-bit asynchronous counter.
19) What is the difference between synchronous and asynchronous counters?
20) Explain Synchronous and Asynchronous reset.
21) How can you convert a JK flip-flop to a D flip-flop?
22) Define Clock skew , Negative Clock Skew, Positive Clock Skew.
23) Define Metastability.
24) Give the characteristic tables of RS, JK, D and T flip-flops
25) Mention and explain fundamental VHDL units
26) Comparison between VHDL and Verilog
27) Explain compilation, Simulation and synthesis
28) Explain design flow or design process for implementation of hardware
29) Why is it called VHDL code rather than VHDL program
30) Explain all the library packages in VHDL
31) Mention the design units of VHDL
32) Explain VHDL and Verilog codes
33) Explain difference between signal and variable with an example
34) Classify and explain data types in HDL
35) Explain syntax of generic statement
36) Explain structure of data type description
37) Write the syntax of sequential stamens in HDL
38) Explain CASEX and CASEZ statement
39) Explain the highlight of structural description
40) Explain
(a) Binding between entity and architecture in VHDL
(b) Binding between library and module in VHDL
(c) Binding between library and component in VHDL
(d) Binding between two modules in Verilog
41) Explain procedure, task and function in HDL with an Example
42) Difference between task and function?

43) Differences between Functions and Procedures in VHDL?

44) What is delta simulation time?
45) What is sensitivity list?
46) What is the difference between wire and reg data type?
47) What is the difference between = = = and = =?
48) What is the difference between unary and logical operators?
49) Difference between blocking and non-blocking?
50) Explain VHDL file processing
51) Explain highlight of mixed language description
52) How to invoke one language from the other
53) Mention the limitation of mixed language disruption
54) Expand the following: PLA, PAL, CPLD, and FPGA.
55) Mention difference between FPGA and CPLD
56) What is LUT?
57) What is the significance of FPGAs in modern day electronics?
58) Give True or False.
(a) CPLD consumes less power per gate when compared to FPGA.
(b) CPLD has more complexity than FPGA
(c) FPGA design is slower than corresponding ASIC design.
(d) FPGA can be used to verify the design before making an ASIC.
(e) PALs have programmable OR plane.
(f) FPGA designs are cheaper than corresponding ASIC, irrespective of design
complexity.
59) What are different types of FPGA? What are you currently using and what is its
clock frequency?
60) Can you draw general structure of FPGA?
61) Why cannot initial statement be synthesizable?
62) Explain the Various steps in Synthesis?
63) Give detail about pattern generator and logic analyzer?
64) Expand XST, ISE, IDE, RTL,xc3s400-5tq144.

PIN DETAIL OF SPATRON3 XC3S400
FRC1 FRC2 FRC3 FRC4 FRC6 FRC7

FRC XF400 FRC XF400 FRC XF400 FRC XF400 FRC XF400 FRC XF400
1 74 1 84 1 100 1 112 1 28 1 57
2 76 2 85 2 102 2 116 2 31 2 59
3 77 3 86 3 124 3 119 3 33 3 63
4 79 4 87 4 103 4 118 4 44 4 69
5 78 5 89 5 105 5 123 5 46 5 68
6 82 6 90 6 107 6 131 6 47 6 73
7 80 7 92 7 108 7 130 7 50 7 70
8 83 8 96 8 113 8 137 8 51 8 20
9 VCC 9 VCC 9 VCC 9 VCC 9 VCC 9 VCC
10 GND 10 GND 10 GND 10 GND 10 GND 10 GND
FRC5 FRC8 FRC10 FRC9

FRC XF400 FRC XF400 FRC XF400 FRC XF400
1 1 1 93 1 60 1 5
2 12 2 95 2 56 2 4
3 13 3 97 3 41 3 2
4 14 4 98 4 40 4 141
5 15 5 99 5 36 5 VCC
6 17 6 104 6 35 6 GND
7 18 7 125 7 32
8 21 8 122 8 10
9 23 9 129 9 11
10 24 10 132 10 8
11 26 11 135 11 7
12 27 12 140 12 6
13 5V 13 5V 13 5V
14 -5 14 -5 14 -5
15 VCC 15 VCC 15 VCC CLK
16 GND 16 GND 16 GND 52
*USE FRC 9 FOR DC AND STEPPER MOTOR
*USE FRC 5 FOR DAC

15ECL58 CBCS VTU Verilog HDL Manual KIT, Tiptur 2018

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15ECL58 CBCS VTU Verilog HDL Manual KIT, Tiptur 2018

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NAME:

Department Of Electronics and Communication

For 5THsemester E&C Engineering as per

Prof. Prashanth N R Prof. Prathibha C

Prof. PramodKumar S Prof. PradeepKumar S K

1. Write HDL code to display messages on an alpha numeric LCD display.

Conduct of Practical Examination:

Department of Electronics & Communication Engineering , K.I.T, Tiptur.

Quick Start to Xilinx ISE Software for Digital Logic Design

Department of Electronics & Communication Engineering , K.I.T, Tiptur.

Truth Table For logic gates: Logic Diagram

assign not_op= ~a_in;

1 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Waveform for verilog code:

Date of Completion of Exp. Staff Signature Remarks

2 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Truth Table For 2 to 4 Decoder:

3 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

2. b) 8 to 3 Encoder Without Priority

4 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Waveform for Verilog code:

5 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Waveform for Verilog code:

Truth Table for 8:1 Multiplexer

0 1 0 A(2) A(4) MUX

INPUTS SELECT LINES OUTPUT

6 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Waveform for verilog code:

2.e)1 to 8 Demultiplexer SEL SELSEL

7 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Truth Table For 1:8 Demultiplexer

Waveform for Verilog code:

8 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

2. f) 1:4 De-multiplexer. D_OUT[0]

Truth TableFor1:4 De-multiplexer:

9 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Waveform for verilog code:

2.g)4 bit Binary to Gray converter

Truth TableFor4 bit Binary to Gray converter:

G3 = B3 G2 = B3 B2’ + B3 B2’ G1 = B2 B1’ + B1 B2’ G0 = B1’B0 + B1 B0’

10 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

g[2] = b[3] ^ b[2];

Waveform for verilog code:

2.g)N bit comparator

Truth Table For 2 bit comparator: A<B

11 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Waveform for verilog code:

Date of Completion of Exp. Staff Signature Remarks

12 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Truth Table For Half Adder: Boolean expressions: Sum=A  B, Carry=A*B

VHDL CODE VERILOG CODE

Waveform for VHDL code:

Waveform for verilog code:

13 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

3.b) FULL ADDER

SIGNAL TEMP1,TEMP2, TEMP3: STD_LOGIC;

14 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Waveform for VHDL code:

Waveform for Verilog code:

Waveform for VHDL code:

15 Department of Electronics & Communication Engineering, K.I.T, Tiptur.

Waveform for verilog code:

VHDL CODE (BEHAVIORAL STYLE) VERILOG CODE (BEHAVIORAL

LIBRARY IEEE; module fulladd(cin,x,y,s,co);