1CY 7C10 6A

PRELIMINARY CY7C106A

256K x 4 Static RAM

Features output enable (OE), and three-state drivers. The device has
an automatic power-down feature that reduces power con-
• High speed sumption by more than 65% when deselected.
— tAA = 12 ns
Writing to the device is accomplished by taking chip enable
• CMOS for optimum speed/power (CE) and write enable (WE) inputs LOW. Data on the four I/O
• Low active power pins (I/O0 through I/O3) is then written into the location speci-
— 910 mW fied on the address pins (A0 through A17).
• Low standby power Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write
— 275 mW
enable (WE) HIGH. Under these conditions, the contents of
• 2.0V data retention (optional) the memory location specified by the address pins will appear
— 100 µW on the four I/O pins.
• Automatic power-down when deselected The four input/output pins (I/O0 through I/O3) are placed in a
• TTL-compatible inputs and outputs high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
Functional Description operation (CE and WE LOW).
The CY7C106A is a high-performance CMOS static RAM or- The CY7C106A is available in standard 400-mil-wide DIPs
ganized as 262,144 words by 4 bits. Easy memory expansion and SOJs.
is provided by an active LOW chip enable (CE), an active LOW

Logic Block Diagram Pin Configuration

DIP/SOJ
Top View

A0 1 28 VCC
A1 2 27 A17
A2 3 26 A16
A3 4 25 A15
A4 5 24
A14
A5 6 23 A13
A6 7 22 A12
A7 8 21 A11
INPUT BUFFER
A8 9 20 NC
A9 10 19 I/O3
A1 A10 11 18 I/O2
A2 I/O3 CE 12 17
I/O1
A3 OE 13 16 I/O0
GND 14 15 WE
A4 I/O2
A5 512 x 512 x 4
A6 ARRAY C106A–2
A7 I/O1
A8
A9 I/O0

POWER
COLUMN DOWN
DECODER CE

WE
OE
C106A–1

Selection Guide
7C106A–12 7C106A–15 7C106A–20 7C106A–25 7C106A–35
Maximum Access Time (ns) 12 15 20 25 35
Maximum Operating Commercial 165 155 145 130 125
Current (mA) Military 165 150 140 135
Maximum Standby Commercial 50 30 30 30 25
Current (mA) Military 40 30 30 25
Shaded area contains advanced information.

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1992 – Revised February 1996
 PRELIMINARY CY7C106A

Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA

(Above which the useful life may be impaired. For user guide- Static Discharge Voltage .......................................... >2001V
lines, not tested.) (per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C Latch-Up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C Operating Range
Supply Voltage on VCC Relative to GND[1] .... –0.5V to +7.0V Ambient
DC Voltage Applied to Outputs Range Temperature[2] VCC
in High Z State[1] .....................................–0.5V to VCC +0.5V Commercial 0°C to +70°C 5V ± 10%
DC Input Voltage[1]..................................–0.5V to VCC +0.5V Military –55°C to +125°C 5V ± 10%

Electrical Characteristics Over the Operating Range[3]

7C106A–12 7C106A–15 7C106A–20
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC 2.2 VCC 2.2 VCC V
+0.3 +0.3 +0.3
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 –1 +1 µA
IOZ Output Leakage Current GND < VI < VCC, –5 +5 –5 +5 –5 +5 µA
Output Disabled
IOS Output Short VCC = Max., VOUT = GND –300 –300 –300 mA
Circuit Current[4]
ICC VCC Operating VCC = Max., Com’l 165 155 140 mA
Supply Current IOUT = 0 mA,
Mil 165 150
f = fMAX = 1/tRC
ISB1 Automatic CE Max. VCC, CE > VIH, Com’l 50 30 30 mA
Power-Down Current VIN > VIH or VIN < VIL,
Mil 40 30
—TTL Inputs f = fMAX
ISB2 Automatic CE Max. VCC, Com’l 10 10 10 mA
Power-Down Current CE > VCC –0.3V,
L 2 2 2
—CMOS Inputs VIN > VCC – 0.3V
or VIN < 0.3V, f=0 Mil 10 10
L 2 2
Shaded area contains advanced information.
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

2
 PRELIMINARY CY7C106A

Electrical Characteristics Over the Operating Range[3] (continued)

7C106A–25 7C106A–35
Parameter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V
[1]
VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 µA
IOZ Output Leakage Current GND < VI < VCC, –5 +5 –5 +5 µA
Output Disabled
IOS Output Short VCC = Max., VOUT = GND –300 –300 mA
Circuit Current[4]
ICC VCC Operating VCC = Max., Com’l 130 125 mA
Supply Current IOUT = 0 mA,
Mil 140 135
f = fMAX = 1/tRC
ISB1 Automatic CE Max. VCC, CE > VIH, Com’l 30 25 mA
Power-Down Current VIN > VIH or VIN < VIL,
Mil 30 25
— TTL Inputs f = fMAX
ISB2 Automatic CE Max. VCC, Com’l 10 10 mA
Power-Down Current CE > VCC –0.3V,
L 2 2
— CMOS Inputs VIN > VCC – 0.3V
or VIN < 0.3V, f=0 Mil 10 10
L 2 2

Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN: Addresses Input Capacitance TA = 25°C, f = 1 MHz, 7 pF
CIN: Controls VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms

R1 480Ω R1 480Ω ALL INPUT PULSES
5V 5V 3.0V
90% 90%
OUTPUT OUTPUT
10% 10%
30 pF R2 5 pF R2 GND
255Ω 255Ω
INCLUDING INCLUDING < 3 ns < 3 ns
JIG AND JIG AND
SCOPE SCOPE
(a) (b) C106A–3 C106A–4

Equivalent to: THÉVENIN EQUIVALENT

167Ω
OUTPUT 1.73V

3
 PRELIMINARY CY7C106A

Switching Characteristics Over the Operating Range[3,6]

7C106A–12 7C106A–15 7C106A–20 7C106A–25 7C106A–35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 12 15 20 25 35 ns
tAA Address to Data Valid 12 15 20 25 35 ns
tOHA Data Hold from Address Change 3 3 3 3 3 ns
tACE CE LOW to Data Valid 12 15 20 25 35 ns
tDOE OE LOW to Data Valid 6 7 8 10 10 ns
tLZOE OE LOW to Low Z 0 0 0 0 0 ns
[7,8]
tHZOE OE HIGH to High Z 6 7 8 10 10 ns
tLZCE CE LOW to Low Z[8] 3 3 3 3 3 ns
tHZCE CE HIGH to High Z[7,8] 6 7 8 10 10 ns
tPU CE LOW to Power-Up 0 0 0 0 0 ns
tPD CE HIGH to Power-Down 12 15 20 25 35 ns
WRITE CYCLE[9,10]
tWC Write Cycle Time 12 15 20 25 35 ns
tSCE CE LOW to Write End 10 12 15 20 25 ns
tAW Address Set-Up to Write End 10 12 15 20 25 ns
tHA Address Hold from Write End 0 0 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 0 0 ns
tPWE WE Pulse Width 10 12 15 20 25 ns
tSD Data Set-Up to Write End 7 8 10 15 20 ns
tHD Data Hold from Write End 0 0 0 0 0 ns
tLZWE WE HIGH to Low Z[8] 2 3 3 3 3 ns
tHZWE WE LOW to High Z[7,8] 6 7 8 10 10 ns
Shaded area contains advanced information.
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30–pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

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 PRELIMINARY CY7C106A

Data Retention Characteristics Over the Operating Range (L Version Only)

Commercial Military
[11]
Parameter Description Conditions Min. Max. Min. Max. Unit
VDR VCC for Data Retention 2.0 2.0 V
ICCDR Data Retention Current VCC = VDR = 2.0V, 50 70 µA
CE > VCC – 0.3V,
tCDR[5] Chip Deselect to Data Retention Time 0 0 ns
VIN > VCC – 0.3V or
tR[5] Operation Recovery Time VIN < 0.3V tRC tRC ns
Notes:
11. No input may exceed V CC +0.5V.

Data Retention Waveform

DATARETENTIONMODE

VCC 4.5V VDR > 2V 4.5V

tCDR tR

CE

C106A–5

Switching Waveforms
Read Cycle No.1[12, 13]
1
tRC

ADDRESS

tAA
tOHA

DATA OUT PREVIOUS DATA VALID DATA VALID

C106A–6

Read Cycle No. 2 (OE Controlled)[13, 14]

ADDRESS

tRC
CE

tACE

OE
tHZOE
tDOE
tHZCE
tLZOE HIGH
HIGH IMPEDANCE IMPEDANCE
DATA OUT DATA VALID
tLZCE
VCC tPD
tPU ICC
SUPPLY
50% 50%
CURRENT
ISB
C106A–7

Notes:
12. Device is continuously selected, OE and CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.

5
 PRELIMINARY CY7C106A

Switching Waveforms (continued)

Write Cycle No. 1 (CE Controlled)[15, 16]

tWC

ADDRESS

tSCE
CE
tSA
tAW tHA
tPWE
WE

tSD tHD

DATA I/O DATA VALID

C106A–8

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16]

tWC

ADDRESS

tSCE
CE

tAW tHA
tSA tPWE

WE

OE

tSD tHD

DATA I/O DATA VALID

tHZOE
C106A–9

Notes:
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
16. Data I/O is high impedance if OE = VIH.

6
 PRELIMINARY CY7C106A

Switching Waveforms (continued)

Write Cycle No. 3 (WE Controlled, OE LOW)[10, 16]

tWC

ADDRESS

tSCE
CE

tAW tHA
tSA tPWE

WE

tSD tHD

DATA I/O DATA VALID

tHZWE tLZWE
C106A–10

Truth Table
CE OE WE Input/Output Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)

Ordering Information
Speed Package Operating
(ns) Ordering Code Name Package Type Range
12 CY7C106A–12PC P41 28-Lead (400-Mil) Molded DIP Commercial
CY7C106A–12VC V28 28-Lead (400-Mil) Molded SOJ
15 CY7C106A–15PC P41 28-Lead (400-Mil) Molded DIP Commercial
CY7C106A–15VC V28 28-Lead (400-Mil) Molded SOJ
CY7C106A–15DMB D42 28-Lead (400-Mil) CerDIP Military
20 CY7C106A–20PC P41 28-Lead (400-Mil) Molded DIP Commercial
CY7C106A–20VC V28 28-Lead (400-Mil) Molded SOJ
CY7C106A–20DMB D42 28-Lead (400-Mil) CerDIP Military
25 CY7C106A–25PC P41 28-Lead (400-Mil) Molded DIP Commercial
CY7C106A–25VC V28 28-Lead (400-Mil) Molded SOJ
CY7C106A–25DMB D42 28-Lead (400-Mil) CerDIP Military
35 CY7C106A–35PC P41 28-Lead (400-Mil) Molded DIP Commercial
CY7C106A–35VC V28 28-Lead (400-Mil) Molded SOJ
CY7C106A–35DMB D42 28-Lead (400-Mil) CerDIP Military
Shaded area contains advanced information.
Contact factory for “L” version availability.

7
 PRELIMINARY CY7C106A

MILITARY SPECIFICATIONS
Group A Subgroup Testing

DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL Max. 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
ISB1 1, 2, 3
ISB2 1, 2, 3

Switching Characteristics
Parameter Subgroups
READ CYCLE
tRC 7, 8, 9, 10, 11
tAA 7, 8, 9, 10, 11
tOHA 7, 8, 9, 10, 11
tACE 7, 8, 9, 10, 11
tDOE 7, 8, 9, 10, 11
WRITE CYCLE
tWC 7, 8, 9, 10, 11
tSCE 7, 8, 9, 10, 11
tAW 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tSA 7, 8, 9, 10, 11
tPWE 7, 8, 9, 10, 11
tSD 7, 8, 9, 10, 11
tHD 7, 8, 9, 10, 11
Document #: 38–00230–B

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 PRELIMINARY CY7C106A

Package Diagrams
28-Lead (400-Mil) CerDIP D42

28-Lead (400-Mil) Molded DIP P41

9
 PRELIMINARY CY7C106A

Package Diagrams (continued)

28-Lead (400-Mil) Molded SOJ V28

© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.