Foxcom 945CMX PDF

5 4 3 2 1
Foxconn Precision Co. Inc.

D
945M09 Schematic D
Fab.1.0
Data: 2007/08/18
Page Index
01. Index Page 18. PCI Express x16(x1)Gfx Slot
C
02. Topology 19. VGA Connector C
03. Rest Map 20. ICH7-1

04. Clock Distribution 21. ICH7-2
05. Power Delivery Map 22. ICH7-3
06. Power Sequence 23. PCI Slots 1, 2
07. CK505 ClockGen 24. PCIE LAN
08. VRD11 ISL6312 25. USB
09. DDR2 1.8V/0.9V 5V_DUAL 26. AUDIO ALC662
10. Power 1.5V 1.2V 2.5V 1.05V 27. Super I/O ITE8718F/GX
11. LGA775-1 28. Keyboard / Mouse / Fan
B
12. LGA775-2 29. Serial / Parallel B
13. LAKEPORT-GMCH-1 30. Power / MISC Connectors

14. LAKEPORT-GMCH-2 31. GPIO / IRQ / IDSEL Map
15. LAKEPORT-GMCH-3 32. Modify List
16. DIMM D DDRII-A1,A2
17. DDRII A & B Term
A A
FOXCONN PCEG
Title
Page Map
Size Document Number Rev
C 945M09 1.0
Date: Monday, August 20, 2007 Sheet 1 of 32

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LGA775 Processor
VRD 11
D 3 Phase PWM Socket D
1333/1066/800/533 FSB
Intel ADD2/+ Card CK-505 Clock
or
PCI Express x 16 Channel A DDR2
PCI Express x16 Port DDR2 533/667
External Graphics
DIMM1
Card
GMCH DDR2 533/667 Channel B DDR2

VGA Connector
Lakeport DIMM1
C C
Back Panel
USB2.0 Port 1 PCIE Interface LAN
4 Lanes
USB2.0 Port 2 RTL8101E/8111B/8111C
Direct Media Interface (DMI)
USB2.0 Port 3
USB2.0 Port 4
uBTX Form Factor
PCI Slot 1
PCI Slot 2
Front Panel ICH7R/
USB2.0 Port 5 ICH7 PCI Express x1 port
PCI Express x1 Slot
USB2.0 Port 6
SPI
B
Header Serial ATA B
SATA Connector 1
USB2.0 Port 7 AHCI, RAID0,1,5,10
USB2.0 Port 8 SATA Connector 2

BIOS SATA Connector 3
SPI Flash 4Mb SATA Connector 4
ATA100
IDE CONN 1
LPC I/F
Super I/O
IT8718F
Intel HD Audio
Realtek ALC662
6 Channels W/ SPDIF I/O
PS2 Parallel Floppy
A Keyboard / Mouse Serial Drive Connector A
FOXCONN PCEG
Title
Topology
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
CPU
CPU_PWRGD
CPURST#
D
LGA775 processor D
ATX
Power
Translation PWRGD_3V
PWRGD_PS PWROK CPURST#
Circuitry PCI Express x16
PS_ON#
GMCH
Lakeport
C
RSTIN# PCI Express x1 C
ICH7
PCIE LAN
ICH_PWRGD
PCIRST#
PLTRST#
Front Panel PWROK AC_RST#
RST#
FR_RST SYS_RESET# PCI Slot 1
B
SW_ON PWRBTN# PCI Slot 2 B
RSMRST#
RCIN#
SLP_S3#
ATA100
IDE CONN 1
RST# PCIRST3# RST# Audio

Power on/off KBRST PCIRST2#
circuit RSMRST#
Super IO
SLP_S3#
PCIRST1#
PCIRST4#
PSIN
A A
PSOUT#
FOXCONN PCEG
Title
Reset Map
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
14.318MHz
CPU
D
CPU 133/200/266/333MHz Diff Pair D
MCH 133/200/266/333 MHz Diff Pair
DDR2 4 Slots 12 Diff CLKs

PCI Express 100 MHz Diff Pair
PCI Express x16 Gfx Channel A DDR2
GMCH DIMM1
DOT 96 MHz Diff Pair Lakeport DIMM2
Channel B DDR2
DIMM1
PCI Express/DMI 100 MHz Diff Pair
C C
CK-410
PCI Express/DMI 100 MHz Diff Pair
USB/SIO 48 MHz
ICH 33 MHz
REF 14 MHz
PCI Express 100 Mhz Diff Pair LAN

8101E/8111B/8111C ICH7
Azalia Bit Clock
B
PCI 33 MHz PCI Slot 1 B
PCI 33 MHz PCI Slot 2
32.768KHz
HD Audio
PCI Express 100 Mhz Diff Pair PCI Express x1 Slot
SIO 33 MHz Super I/O
SATA 100 MHz Diff Pair
A A
FOXCONN PCEG
Title
CLOCK Distribution
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
Super I/O
3.3V
Icc(Max)=50mA
Proceessor
Vccp (CPU Vcore) 3.3SBV
VRD 10.1 Voltage=0.8375~1.6V Icc(Max)=50mA(S0)
Switching Icc(Max)=119A
Four Phase 4-Phases Swithing 3.3SBV
D D
Icc(Max)=38mA(S3)
1.2V FSB
Vtt-tbdA
ATX P/S USB 8 Ports
+5V DUAL=4A(S0, S1)
12V +5V DUAL=20mA(S3)
Lakeport GMCH
5VSB
FSB_Vtt PS2
Linear 1.5V
3.3V 1.2V FSB Vtt +5V DUAL=345mA(S0, S1)
to 1.2V
CK410 5A
Icc(Max)=tbdA +5V DUAL=2mA(S3)
5V
Vdd (Core)
3.3V -12V FWH
Ivdd(Max)=560mA 1.8V DDR2 I/O=4.6A(S0,S1)
1.8V DDR2 I/O=250mA(S3) 3.3V=107mA(S0, S1)
Vcore (Core Logic) PCI Express

1.5V X16 slot (1)
Icc(Max)=9.6A(Integrated) +12V=5.5A
DDR2 Channel A Icc(Max)=7.5A(Discrete)
5VDUAL 3.3VSB
Vdd (Core)=1.8V Icc(Max)= *1.5V
C
Ivdd(Max)=4.7A(per channel)
Icc(Max)=0.375A(wake) C
4.345A(S0,S1) PCIexpress(X16)=1A Icc(Max)=0.02A(no wake)

22mA(S3) *1.5V
Vtt (Core) PCIexpress(X1)=0.06A
0.9V +3.3V=3A
*1.5V SDVO=tbdA
Ivterm(Max)=200mA *1.5V DMI=0.25A
(per channel) PCI Express
2.5V DAC
regulator *2.5V DAC=0.07A X1 slot (1)
Single Phase Switch
5V to 1.8V V_2p5_DAC 2.5V HV=tbdA
DDR2 Channel B +12V=0.5A
Ivdd(Max)=14A 100mA
Ivdd(Max)=650mA(S3) 3.3VSB
Vdd (Core)=1.8V LDO Icc(Max)=0.375A(wake)
Ivdd(Max)=4.7A(per channel) 1.8V to 0.9V Icc(Max)=0.02A(no wake)
Ivterm(Max)=1.2A
Vtt (Core)
0.9V +3.3V=3A
Ivterm(Max)=200mA
(per channel)
ICH7RW
Vin=12V
V_1p5_core 1.2V VCC_CPU-tbdmA
1.5V PCI Per Slot (2)
Switching=14A -12V
B 1.05V Core=tbdA Icc(Max)=0.1A B
1.5V PCI Express=tbdmA

1.5V DMI=tbdmA 5V
HDA Codec 1.5V SATA=tbdmA Icc(Max)=5A
Vcc LDO
1.5V USB=tbdmA
5V -12V
12V 3.3V
Icc(Max)=tbdA to 5V Icc(Max)=7.6A
3.3V=180mA
Vcc 12V
3.3V VccSus
3.3V Icc(Max)=0.5A
Icc(Max)=tbdA Icc(Max)=330mA
3.3VSB
5VRef=tbduA Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)
5VrefSus=tbduA
1.0V
LDO Lan Core Tekoa GbE Lan
5V_dual to 3.3SB RTC=5uA V_1p2_ctrl BJT
Icc(Max)=1.5A +1.2V=tbdA
1.8V +2.5V=tbdA BJT

Lan Phy
A V_2p5_ctrl A
RTC
Battery
*Power derived through filter FOXCONN PCEG

Title
Power Delivery Map
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
S0->S5
+12V_SYS +12V_SYS
S5->S0
D D
+5V_DUAL +5V_SYS +5V_SYS +5V_DUAL
+3D3V_DUAL +3D3V_SYS +3D3V_SYS +3D3V_DUAL

+1D8V_STR +1D8V_STR
VTT_DDR
VTT_DDR
VTT_VR VTT_VR
Vcc Vcc
1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD VIDPWRGD PS_ONJ
C
PS_ONJ C
S0->S3 S3->S0
+12V_SYS +12V_SYS
+5V_SYS +5V_DUAL +5V_DUAL +5V_SYS
+3D3V_SYS +3D3V_DUAL +3D3V_DUAL +3D3V_SYS

B B
+1D8V_STR +1D8V_STR +1D8V_STR +1D8V_STR
VTT_DDR
VTT_DDR
VTT_VR VTT_VR
Vcc Vcc
1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD PS_ONJ VIDPWRGD
PS_ONJ
A A
FOXCONN PCEG
Title
Power Sequence
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
3D3V_SYS
3D3V_SYS
+/-25% +/-25%
FB101 2FB 100 Ohm 3D3V_CLK FB111 2FB 100 Ohm
Dummy Dummy
CP2 CP7
1 2 1 2 3D3V_CLK_SATA_25M
C143 C140 C170 C207 C185

X_COPPER 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF X_COPPER C138 C139 C141
* * * * *
1
C133 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 4.7uF 0.1uF 0.1uF
D * 4.7uF CP16 Dummy * 10V, Y5V, +80%/-20% * *
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
D
10V, Y5V, +80%/-20% X_COPPER dummy
2
Place near to pin3,5,32,44,47 +/-25% Place near pin 61,62
3D3V_CLK_48M FB141 2FB 100 Ohm
Dummy
C180 C165
CP18
4.7uF 0.1uF
* 10V, Y5V, +80%/-20%* 16V, Y5V, +80%/-20% 1 2 3D3V_CLK_REF_A
Dummy Place near pin14
C196 C164
X_COPPER C187 0.1uF 0.1uF
* 4.7uF * *
16V, Y5V, +80%/-20%
10V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
3D3V_SYS
3D3V_CLK
3D3V_CLK Place near pin 42,53
*R135
1K R136
+/-5% * 4.7K
*R139
4.7K U15
+/-5%
Dummy Ce = 2 * CL - Cs - Cinx = 2 * 32pf - 2.8pf - 5pf = 57.2p
22 Ohm +/-5%
*
23
27
CK_33M_PCI2
CK_33M_SIO
CK_33M_PCI2 RN19
CK_33M_SIO
*1 2
+/-5%
9,20 SLP_S4J
R137
Dummy
0 +/-5% 1
2
**RLATCH 25Mhz_0F_2x
64
63
3 4 3 GND GND 62 3D3V_CLK_SATA_25M
5 6 3D3V_CLK VDD VDD25Mhz_STB
CK_33M_ICH 4 61 3D3V_CLK_SATA_25M
22 CK_33M_ICH 7 8 **GSEL/24.576Mhz VDDSATA_STB
3D3V_CLK 5 60 CK_SATA_100M_P_ICH 21 1 2
6 VDDPCI SATACLKT_LR 59 CK_SATA_100M_N_ICH 21
*
GND SATACLKC_LR
R142 4.7K +/-5% Dummy 7 58 C136 X1 C137
*
**DOC_1 GND R152 22 +/-5% CK_14M_ICH 56pF XTAL 14.31818MHz 56pF
8
9
PCICLK0
*Freerun/PCICLK1_2x
REF0_2x/FSLC
GND
57
56 ICS_FSBSEL2
CK_14M_ICH 20 * +/-5%+/-30ppm *
+/-5%
ICS_FSBSEL1 10 55
FSLB/PCICLK2_2x X1
11,20,30 ICH_SYS_RSTJ 11 54
*
CK_33M_PCI1 R161 33+/-5% SELRSET/RESET#/PCICLK32 X2 3D3V_CLK_REF_A

23 CK_33M_PCI1 12 53
**
C R171 4.7K +/-5% Dummy 13 PCICLK4 VDDREF_STB 52 R163 0 +/-5% SMB_DATA_MAIN C
**DOC0 SDATA SMB_DATA_MAIN 16,18,20,23 Place near Clock generator
ICS_FSBSEL0 3D3V_CLK_48M 14 51 R162 0 +/-5% SMB_CLK_MAIN
SMB_CLK_MAIN 16,18,20,23
**
CK_48M_ICH R179 22 +/-5% VDD48 SCLK
20 CK_48M_ICH 15 50
CK_48M_SIO R186 22 +/-5% 24/48M_SEL 16 FSLA/USB_48MHz GND 49
27 CK_48M_SIO *SEL24_48#/24_48Mhz CPUT_LR0 CK_200M_P_CPU 11
17 48
GND CPUC_LR0 CK_200M_N_CPU 11
CLK_VTT_PG 18 47 3D3V_CLK
Vtt_PwrGd/WOL_STOP# VDDCPU
13 CK_96M_P_GMCH 19 46 CK_200M_P_GMCH 13
DOT96T_LR/PCIeT_LR0 CPUT_LR1
20 45
13 CK_96M_N_GMCH DOT96C_LR/PCIeC_LR0 CPUC_LR1 CK_200M_N_GMCH 13
21 44 3D3V_CLK
GND VDDI/O
18 CK_PE_100M_P_1PORT 22 43
PCIeT_LR1 GNDA 3D3V_CLK_REF_A
18 CK_PE_100M_N_1PORT 23 42
24 PCIeC_LR1 VDDA_STB 41
24 CK_PE_100M_P_LAN PCIeT_LR2 PCIeT_LR8
24 CK_PE_100M_N_LAN 25 40
26 PCIeC_LR2 PCIeC_LR8 39
GND PCIeT_LR7 CK_PE_100M_P_GMCH 13
27 38
18 CK_PE_100M_P_16PORT PCIeT_LR3 PCIeC_LR7 CK_PE_100M_N_GMCH 13
18 CK_PE_100M_N_16PORT 28 37
29 PCIeC_LR3 GND 36
PCIeT_LR4 PCIeT_LR6
30 35
PCIeC_LR4 PCIeC_LR6
31 34 CK_PE_100M_P_ICH 20
32 GND PCIeT_LR5 33
3D3V_CLK VDDPCIEX PCIeC_LR5 CK_PE_100M_N_ICH 20
*internal pull-up resistor ICS9LPRS511EGLF-T

**internal pull-down resistor
RESET pin is 3.3V tolerant 3D3V_SYS
3D3V_SYS Integrated 33ohm series resistor on all differential outputs
3D3V_CLK SMBus Address :1101-0010
*R187
1K
+/-5%
*R185
4.7K R103 2.7K +/-5% SMB_DATA_MAIN
+/-5%
Dummy
*
ICS_FSBSEL0 R181 2.2K +/-5% R102 2.7K +/-5% SMB_CLK_MAIN
FSBSEL0 11,13
CLK_VTT_PG 24/48M_SEL
8,20 VRM_PWRGD
B B
* R182
4.7K
*
ICS_FSBSEL1 R154 2.2K +/-5%
+/-5% FSBSEL1 11,13
C174
1
0.1uF
* 16V, X7R, +/-10%
Dummy
2
*
ICS_FSBSEL2 R148 2.2K +/-5%
FSBSEL2 11,13
Dummy
* R145
2.2K
+/-5%
For support 1333Mhz CPU on 945GC platform
CK_48M_SIO
CK_48M_ICH
CK_33M_PCI1
CK_33M_SIO
CK_33M_ICH
BSEL TABLE
CK_14M_ICH
CK_33M_PCI2 FS_C FS_B FS_A FSB Frequency
0 0 1 133MHz(533)
C198 C171 C163 C146 C153 C154 C144 0 1 0 200MHz(800)
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
10pF 10pF 10pF 10pF 10pF 10pF 10pF

A
* * *
Dummy *
Dummy *
Dummy * * 0 0 0 266MHz(1066)
A
C0402 C0402 C0402 C0402 C0402 C0402 C0402

Dummy Dummy Dummy Dummy
1 0 0 333MHz(1333)
EMI CAPS. FOXCONN PCEG

Title
CK505 ClockGen
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
VCCP
EC19 EC17
PWR2
12V_VRM
* 1800uF
6.3V, +/-20%
* 1800uF
6.3V, +/-20%
Dummy Dummy
4
5 Input LC circuit
3
HM3502E-P1 VIN
D L12 D
1.2uH@100KHz
*
C219 EC13 EC11 EC20 EC14
1
* 0.1uF
16V, Y5V, +80%/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20% *
EC35
680uF *
EC24
680uF *
EC25
680uF *
EC26
680uF *
EC27
680uF
Dummy 4V,+/-20% 4V,+/-20% 4V,+/-20% 4V,+/-20% 4V,+/-20%
2
C250 R211
1nF 1K
*
* Dummy EC28 EC39 EC40 EC42
Dummy
* 680uF
4V,+/-20%
* 680uF
4V,+/-20%
* 680uF
4V,+/-20%
* 680uF
4V,+/-20%
R226
1
C257 50V, X7R, +/-10%

+/-1% 2.2K
* 4.7nF +/-1%
50V, X7R, +/-10%
2
*R227 *
*R216
0
0
+/-5% T RT2
10K *
TC2
100uF TC1
1
120pF
1
* C252
+/-5% +/-1%
Dummy VIN
2V,+30/-20%
ctxh15
* 100uF
2V,+30/-20%
*
R22550V, NPO, +/-5% R209 Dummy Dummy ctxh15
2
15K 2.43K +/-1% Dummy

14
15
16
+/-1%
U16 Q6 C80
1
2 AOD452 4.7uF
*
VDIFF
FB
IDROOP
13 16V, Y5V, +80%/-20% R191 6.2K +/-1%PHASE1

COMP
*
2
VCCP R205 100 +/-1% 31 R194 2.2 +/-5%
C2221 20.22uF 25V, X7R, +/-10% G C224
*
BOOT1
Dummy 0.1uF C168 C167 C206 C212 C184 C169
C241 R73 2.2+/-5% * R80 * 25V, X7R, +/-10% 10uF 10uF 10uF 10uF 10uF 10uF
11 VCC_SENSE 18 32
* * * * * *
S
1
10nF VSEN UGATE1 L14 Choke 400nH 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
* 25V, X7R, +/-10%
PHASE1
33
10K
+/-5% 2 1
*
Dummy 17
D
11 VSS_SENSE
2
1
C RGND C84 C
*
*
R206 100 +/-1% 30 Q9 Q11 1nF

LGATE1
Dummy 50V, X7R, +/-10%
2
5V_SYS R237 2.2 +/-5% C255 10 12V_VRM G G
1
0.1uF VCC PHASE1 AOD472 AOD472 R71

* 16V, X7R, +/-10% ISEN1-
34
2.2
S
*
35 R196 100 +/-1% C226 VCCP R189 +/-5%

*
R224 68K +/-1% ISEN1+ 0.1uF 2.2

5V_SYS 12
OFS * 16V, X7R, +/-10% +/-5% C200 C193 C182 C211 C202 C195
25V, Y5V, +80%/-20% VIN
* 10uF
* 10uF
* 10uF
* 10uF
* 10uF
* 10uF
2
R241 R212 100KOhm

+/-1% 45 29 1 C221 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
FS PVCC1_2
*
30K 1uF Dummy Dummy Dummy Dummy

+/-1% C2561 210nF25V, X7R,
11 +/-10% * Q14
D
*
REF
Dummy AOD452 C103
2
1
R192 2.2 +/-5%
C2291 20.22uF 4.7uF R198 6.2K +/-1% PHASE2
27
*
*
BOOT2 25V, X7R, +/-10% 16V, Y5V, +80%/-20% VCCP

26 R128 2.2+/-5% G C235
2
R223 100KOhm
+/-1% 9 UGATE2 0.1uF
SS * R129 *
*
25 25V, X7R, +/-10%
S
PHASE2 L19 Choke 400nH
10K
+/-5% 2 1
*
*
R222 0 +/-5% C205 C194 C201 C183 C210 C204
5V_SYS 8 28
*
D
D
OVPSEL LGATE2
1
C158 10uF 10uF 10uF 10uF 10uF 10uF
12V_VRM Q19 Q21 * 1nF 6.3V, X5R, +/-10% * 6.3V, X5R, +/-10% * 6.3V, X5R, +/-10%* 6.3V, X5R, +/-10% * 6.3V, X5R, +/-10% * 6.3V, X5R, +/-10%
50V, X7R, +/-10% Dummy Dummy Dummy Dummy Dummy Dummy
2
27 PVID7 46 G G
47 VID7 20 PHASE2 AOD472 AOD472 R157
27 PVID6
*
VID6 ISEN2-
27 PVID5 48 19 R200 49.9 +/-1% C223 VCCP R199 2.2
S
S
VID5 ISEN2+
1
0.1uF 2.2 +/-5%

27
27
PVID4
PVID3
1
2
VID4
VID3
* 16V, X7R, +/-10% +/-5%
27 PVID2 3 VIN
2
VID2 C236
27 PVID1 4 42
VID1 PVCC3
1
1uF Q5
5
*
D
27 PVID0 VID0 C228 0.22uF 25V, Y5V, +80%/-20% AOD452 C81 VTT_OUT_RIGHT
1
40 R197 2.2 +/-5% 225V, X7R, +/-10% 4.7uF R202 6.2K +/-1% PHASE3
1
*
2
*
VID_SELECT:VR10.1<0.6V; 0.6<VR11<3.0V BOOT3 16V, Y5V, +80%/-20%

11,27 VID_SELECT 6 39 R72 2.2+/-5% G C247 R306
2
VRSEL UGATE3 0.1uF 680

B
PGOOD is Open-Drain 38 * R79 * 25V, X7R, +/-10% VTT_OUT_RIGHT 5V_SB_SYS
* +/-5%
B
S
PHASE3 L13 Choke 400nH r0402h4

37 10K
7,20 VRM_PWRGD PGOOD
+/-5% 2 1 VTT_PWRGD 11
12V_VRM
*
*R302
D
D
1
C85 20K
R195 LGATE3
41
Q10 Q8 * 1nF R304 +/-1% Q28
9.1K 2 50V, X7R, +/-10% 4.7K
+/-5% 43 PHASE3 G G +/-5% G
*
1
R0603 ISEN3- 44 R210 100 +/-1% C239 AOD472 AOD472 R70 BOM need update 2N7002-7-F
VCCP
1
VRM_EN ISEN3+
Dummy 0.1uF 2.2 CP21
36
*
C
S
S
EN 16V, X7R, +/-10% +/-5% R307 X_COPPER
EN voltage must R193 Dummy 100K B Q29
*
2
2
higher than 0.850V 1K +/-1% MMBT3904_NL
+/-5% R0603 12V_VRM VTT_OUT_RIGHT
E
23 5V_SYS
EN_PH4
Dummy
R291 R290
C297
10K Dummy
680
7 24 1 2 +/-5% +/-5%
*
DRSEL PWM4 R0603
2.2uF
Dummy VRM_EN
22
ISEN4-
49
D
GND
21
ISEN4+
Dummy Q26 C285
0.1uF R292
ISL6312CRZ G * 4.7K
2N7002-7-F +/-5%
R0603
S
Dummy
A A
FOXCONN PCEG
Title VR11 ISL6312

C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
12V_SYS 5V_SYS 5V_SB_SYS
L
R332
* 4.7K H
1D8V_STR
A
+/-5%
G AP9T16GH D45
B120-13-F
EC64
1.8V Power requires
D
Q41
* 1000uF
C
17A maximum current Q33 +/-20%
D
D D
VCC_DUAL
G
C374 10 VCC_DUAL_SW
D40 2N7002-7-F
12V_SYS D39 A C LS4148-F A C 1 2 18V_PHASE
*
S
*
L31
R353 10+/-5% SD103AW 1uH@1KHz
0.1uF
16V, X7R, +/-10% VCC_DUAL
5V_SB_SYS D38 A C SD103AW
C368
1uF close to Q21Drain
*
5V_SB_SYS R361 25V, Y5V, +80%/-20% C423 EC61 C441
1
Open 14.3K
* 0.1uF * 470uF
* 10uF
D
5
+/-1% U18 +/-20% +-10%
R331 L 1 Q39 Dummy
*
VCC
2
L 4.7K Rocset BOOT
+/-5% Open 7 2 R379 2.2 +/-5% G
H COMP/OCSET UGATE AOD452 1D8V_STR
C
Open L30
*
S
L B Q30 6 8 18V_PHASE
MMBT3904_NL FB PHASE 2.5uH@100KHz
GND
L 4
E
LGATE R384
D
APW7120KE-TRL 2.2
3
Q40 +/-5% C259 EC56 EC58 EC59 EC53 EC52
1
G C407 * 0.1uF * 1000uF
6.3V, +/-20%
* 1000uF *
6.3V, +/-20%
1000uF
6.3V, +/-20%
* 220uF
6.3V, +/-20%
* 220uF
6.3V, +/-20%
1
AOD472 2.2nF
*
2
50V, X7R, +/-10%
S
First H Near MOSFET
*
2
R325 1K+/-5% B Q32
7,20 SLP_S4J MMBT3904_NL
S5 L VOUT= 0.8V(1+R638 / R658)
E
1
S0 H * C324
R638,R658 must less than 1k
Pull FB trace out after Cout
Between CHA dimm and CHB dimm
*
2.2uF R363 300
2
C S3 H C
C0603
6.3V, Y5V, +80%/-20%
Dummy R364 220 R0603 +/-1%C3731 2 18nF C0603 50V, Y5V, +80%/-20%
*
Dummy Dummy
R377 R362
2.4KOhm 1.2K
+/-1%
C401 C381
1
*R373 * 10uF
* 10uF
*
R385 1K+/-5% B Q38 240 +-10% 10V, Y5V, +80%/-20%
20 1D8V_GPIO27 MMBT3904_NL +/-1% Dummy
2
E
C
*
R381 1K+/-5% B Q37

20 1D8V_GPIO28 MMBT3904_NL
E
B B
VCC_DUAL
DDR_VTT
3D3V_DUAL
Vout
ADJ
Vin
U20
AZ1084D-ADJTRE1 Max. output current = 3A
1D8V_STR 3D3V_SYS
1
*R380
301 EC60
EC62 C406
+/-1% * 1000uF
6.3V, +/-20% U19
* 1000uF
+/-20% * 1uF
10V, Y5V, +80%/-20%
3D3VADJ
EC49 Dummy
1
VIN VCNTL
8
7
VTT_DDR
VCNTL
Dummy R378
* 1000uF
6.3V, +/-20% *R374
100KOhm VCNTL
6
5
*499 +/-1% VCNTL
+/-1% 4
VOUT
3 2
REFEN GND
RT9173 C396 EC57 C399
1
*R376 C380
* 0.1uF * 1000uF
* 4.7uF
1
100KOhm 0.1uF 6.3V, +/-20%

+/-1% *
2
2
A A
Vout=Vref(1+R2/R1)+IadjR2
R1 is Up Resistor.
Iadj=50uA
Vref=1.25V
FOXCONN PCEG
Title
3D3V_DUAL Size
DDR2 1.8V/0.9V 5VDUAL
Document Number Rev
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
VCC_DUAL_SW 9
VCC_DUAL 5V_SYS 12V_SYS

3D3V_DUAL 1D8V_STR
*R251
130 *R242
4.7K U17A 1D5V_CORE
4
+/-1% +/-5%
3 VCC_DUAL R245
+
1 24.9KOhm
2 +/-1%
- 12V_SYS C391
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

LM324DR2G 10uF
*
11
D D
5V_SYS 10V, Y5V, +80%/-20% C325 C372 C321 C326 C365 C317 C286 C390
1
R275
* * * * * * * * *
D
R249 C260 4.7K U17B
4
4.12K 0.1uF +/-5% Q34 Q31 2.2uF 2.2uF 2.2uF 1uF 1uF 1uF 10uF 10uF
*
2
+/-1% 5
+ Dummy Dummy Dummy Dummy Dummy
7 G G
D
R248
4.7K * *R247
4.7K
6 -
AOD452 AOD452
S
+/-5% +/-5% R243 C264 R234
LM324DR2G
*
11
1
2N7002-7-F
Dummy 8.06K 1uF 1K
G
C281 Q24 +/-1% * 10V, X5R, +/-10%
* +/-5% 1D5V_CORE
1
0.1uF Dummy
*
2
B Q27 16V, Y5V, +80%/-20%
D
MMBT3904_NL Dummy
*
2
R267 C271 R231 100 +/-1%
E
2.2K 0.1uF
27,30 PS_ONJ G
2N7002-7-F
+/-5% * 25V, X7R, +/-10%
Q25 Dummy R230
* 113Ohm
S
+/-1% C313 EC51 EC54 C369
1
* 0.1uF
16V, Y5V, +80%/-20%
* 680uF
4V,+/-20%
* 680uF
4V,+/-20% * 10uF
10V, Y5V, +80%/-20%
R236 R246
*
2
806 402
+/-1% +/-1%
Dummy Dummy
1D5V FOR CHIP
C
*
R207 1K+/-5% B Q22 3D3V_DUAL

C
20 1D5V_GPIO16
Dummy
MMBT3904_NL
Dummy
1D05V FOR ICH7 1D5V_CORE
C
E
R217 12V_SYS
470 Ohm
+/-1%
D
U17C
4
1D05V_REF 10 Q35 1D05V_ICH
C
+ AP15N03H
8 G
*
R221 1K+/-5% B Q23 9

20 1D5V_GPIO34 -
MMBT3904_NL C251
S
*
1
Dummy Dummy 12V_SYS 12V_SYS R218 0.1uF LM324DR2G R229 1K+/-5%Dummy 1.0524V
*
E
11
220 16V, Y5V, +80%/-20%
+/-5% Dummy
2
U14D U17D
4
C375 C371 C367 EC55
1
12 +
14
12 +
14
0.1uF 0.1uF 0.1uF 100uF
+/-20% * * * *
13 13 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
2
- -
LM324DR2G Dummy
LM324DR2G place close to ICH7
11
11
FSB_VTT
2D5V FOR GMCH
12V_SYS
3D3V_DUAL 3D3V_SYS
C122 12V_SYS 3D3V_SYS
B B
0.1uF
*
*R123 25V, X7R, +/-10%
D
1K U14A EC30 placed near the LM324M pin 8

4
+/-1% Q12 * 1000uF

6.3V, +/-20% 3D3V_DUAL
C265
0.1uF
3
*
1
+ AP15N03H 25V, X7R, +/-10% C149
C123 2 -
1 G
Dummy * 0.1uF
1
0.1uF R126 16V, Y5V, +80%/-20%

*
S
2
*
16V, Y5V, +80%/-20% LM324DR2G 1K R133

11
+/-5% 324Ohm
D
2
Dummy +/-1% U14C
4
Q18
10
+
R122 8 G
* 1K
* R134 9 -
2N7002-7-F
+/-1% 1K
S
3D3V_DUAL +/-1% LM324DR2G
11
*
12V_SYS R138 1K+/-5% Dummy 2D5V_MCH
* R131
D
1K
4
+/-5% U14B Q16

1D2V_REF 5
1D5V_CORE + AP15N03H
7 G
C142
6
*
C
-
R127 4.7uF
S
*
B Q15 LM324DR2G 1K
C
11
MMBT3904_NL +/-5%
R130 1K+/-5% B Q17 R121 C121 Dummy
2.5V for GMCH VGA function.
E
*
C126 MMBT3904_NL 1.13K 1uF

* 10uF +/-1% * 10V, Y5V, +80%/-20% FSB_VTT
E
6.3V, X5R, +/-20%

Dummy
C157 C173 EC33

1
A
* 4.7uF * 0.1uF
16V, Y5V, +80%/-20%
* 1000uF
6.3V, +/-20%
D24
BAT54A
A
1D5V_CORE 1 2D5V_MCH
2
10V, Y5V, +80%/-20% 3

2
FOXCONN PCEG
Title
Power 1.5V 1.2V 1.05V
C 945M09 A

5 4 3 2 1

5 4 3 2 1
HAJ[31..3]
13 HAJ[31..3]
HDJ[63..0]
HDJ[63..0] 13 U8A
HAJ3 L5 D2 3 OF 7
HAJ4 P6 A03# ADS# C2 HADSJ 13 U8C
2 OF 7 HAJ5 A04# BNR# HBNRJ 13 TESTHI_0
M5 D4 P2 F26
U8B A05# HIT# HITJ 13 21 SMIJ SMI# TESTHI00
HAJ6 L4 H4 TP_RSPJ K3 W3 TESTHI_1
A06# RSP# TP15 21 A20MJ A20M# TESTHI01
HAJ7 M4 G8 R3 P1 TESTHI_11
A07# BPRI# HBPRIJ 13 21 FERRJ FERR#/PBE# TESTHI11
HDJ0 B4 G16 HDJ32 HAJ8 R4 B2 K1 W2 TESTHI_12
D00# D32# A08# DBSY# HDBSYJ 13 21 INTR LINT0 TESTHI12
HDJ1 C5 E15 HDJ33 HAJ9 T5 C1 L1 F25
D01# D33# A09# DRDY# HDRDYJ 13 21 NMI LINT1 TESTHI02
HDJ2 A4 E16 HDJ34 HAJ10 U6 E4 N2 G25
D02# D34# A10# HITM# HITMJ 13 21 IGNNEJ IGNNE# TESTHI03
HDJ3 C6 G18 HDJ35 HAJ11 T4 AB2 HIERRJ M3 G27
D03# D35# A11# IERR# 21 STPCLKJ STPCLK# TESTHI04
HDJ4 A5 G17 HDJ36 HAJ12 U5 P3 G26
HDJ5 D04# D36# HDJ37 HAJ13 A12# INIT# INITJ 21 TESTHI05
D B6 F17 U4 C3 12 HVCCA A23 G24 D
HDJ6 D05# D37# HDJ38 HAJ14 A13# LOCK# HLOCKJ 13 VCCA TESTHI06 TESTHI_2_7
B7 F18 V5 E3 12 HVSSA B23 F24
HDJ7 A7 D06# D38# E18 HDJ39 HAJ15 V4 A14# TRDY# AD3 TP_BINITJ HTRDYJ 13
D23 VSSA TESTHI07 AK6
D07# D39# A15# BINIT# TP20 1D5V_CORE RSVD5 FORCEPH
HDJ8 A10 E19 HDJ40 HAJ16 W5 G7 C23 G6 RSVD_G6
D08# D40# A16# DEFER# HDEFERJ 13 12 HVCCIOPLL VCCIOPLL RSVD11
HDJ9 A11 F20 HDJ41 N4 F2 HGTLREF_3
HDJ10 B10 D09# D41# E21 HDJ42 P5 RSVD1 EDRDY# AB3 TP_MCERRJ L2 TP_CPUSLPJ
D10# D42# 13 HREQJ[4..0] RSVD2 MCERR# TP22 TESTHI13
HDJ11 C11 F21 HDJ43 HREQJ0 K4 VID0 AM2 AH2
D11# D43# REQ0# 27 VID0 VID0 RSVD12
HDJ12 D8 G21 HDJ44 HREQJ1 J5 U2 TP_APJ0 VID1 AL5 N1
D12# D44# REQ1# AP0# TP27 27 VID1 VID1 PWRGOOD CPU_PWRG 20
HDJ13 B12 E22 HDJ45 HREQJ2 M6 U3 TP_APJ1 VID2 AM3 AL2 PROCHOTJ
D13# D45# REQ2# AP1# TP25 27 VID2 VID2 PROCHOT#
HDJ14 C12 D22 HDJ46 HREQJ3 K6 VID3 AL6 M2
D14# D46# REQ3# 27 VID3 VID3 THERMTRIP# THERMTRIPJ 21
HDJ15 D11 G22 HDJ47 HREQJ4 J6 F3 HBR0J VID4 AK4
D15# D47# HAJ[31..3] REQ4# BR0# HBR0J 13 27 VID4 VID4
HDBIJ0 A8 D19 HDBIJ2 5/10 R6 G3 TESTHI_8 VID5 AL4
13 HDBIJ0 DBI0# DBI2# HDBIJ2 13 13 HAJ[31..3] 13 HADSTBJ0 ADSTB0# TESTHI08 27 VID5 VID5
C8 G20 G5 G4 TESTHI_9 VID6 AM5 A13 HCOMP0
13 HDSTBNJ0 DSTBN0# DSTBN2# HDSTBNJ2 13 27 PECI PCREQ# TESTHI09 27 VID6 FC11 COMP0
B9 G19 H5 TESTHI_10 VID7 AM7 T1 HCOMP1
13 HDSTBPJ0 DSTBP0# DSTBP2# HDSTBPJ2 13 TESTHI10 27 VID7 FC12 COMP1
HAJ17 AB6 VID_SELECT AN7 G2 HCOMP2
A17# 8,27 VID_SELECT FC16 COMP2
HDJ16 G9 D20 HDJ48 HAJ18 W6 J16 TP_DPJ0 F28 R1 HCOMP3 VTT_OUT_LEFT
D16# D48# A18# DP0# TP6 7 CK_200M_P_CPU BCLK0 COMP3
HDJ17 F8 D17 HDJ49 HAJ19 Y6 H15 TP_DPJ1 G28 J2 HCOMP4
D17# D49# A19# DP1# TP8 7 CK_200M_N_CPU BCLK1 COMP4
HDJ18 HDJ50 HAJ20 TP_DPJ2 HCOMP5
HDJ19
HDJ20
F9
E9
D18#
D19#
D50#
D51#
A14
C15 HDJ51
HDJ52
HAJ21
HAJ22
Y4
AA4
A20#
A21#
DP2#
DP3#
H16
J17 TP_DPJ3
TP7
TP4 AE8
SKTOCC#
COMP5
T2
TP_RSVD_CPU_N5
*R293
51 Ohm
D7 C14 AD6 N5 +/-5%
D20# D52# A22# 27 THERMDA RSVD13 TP14
HDJ21 E10 B15 HDJ53 HAJ23 AA5 H2 HGTLREF_1 AE6 TP_RSVD_CPU_AE6
D21# D53# A23# GTLREF1 27 THERMDC RSVD14 TP10
HDJ22 D10 C18 HDJ54 HAJ24 AB5 H1 HGTLREF_0 AL1 C9 TP_RSVD_CPU_C9
HDJ23 D22# D54# HDJ55 HAJ25 A24# GTLREF0 CPU_MCH_GTLREF THERMDA RSVD15 HGTLREF_2
F11 B16 AC5 E24 AK1 G10
HDJ24 D23# D55# HDJ56 HAJ26 A25# CS_GTLREF MCH_GTLREF_CPU 13 THERMDC RSVD16 TP_RSVD_CPU_D16
F12 A17 AB4 D16 TP5
HDJ25 D24# D56# HDJ57 HAJ27 A26# RSVD17
D13 B18 AF5 AN3 A20
HDJ26 D25# D57# HDJ58 HAJ28 A27# VCCSENSE RSVD18 TP_RSVD_CPU_E23
E13 C21 AF4 G23 AN4 E23 TP2
HDJ27 D26# D58# HDJ59 HAJ29 A28# RESET# HCPURSTJ 13 VSSSENSE RSVD19 TP_RSVD_CPU_F23
G13 B21 AG6 8 VCC_SENSE AN5 F23 TP3
HDJ28 D27# D59# HDJ60 HAJ30 A29# VCC_MB_REG RSVD21 TP_RSVD_CPU_J3
F14 B19 AG4 B3 8 VSS_SENSE AN6 J3 TP18
HDJ29 G14 D28# D60# A19 HDJ61 HAJ31 AG5 A30# RS0# F5 HRSJ0 13 VSS_MB_REG RSVD24
HDJ30 D29# D61# HDJ62 TP_LAG775_PIN_AH4 A31# RS1# HRSJ1 13 Changed pin name MS_ID1
F15 A22 AH4 A3 V1
D30# D62# TP23 A32# RS2# HRSJ2 13 MSID1
HDJ31 G15 B22 HDJ63 TP_LAG775_PIN_AH5 AH5 F29 from RSV W1 MS_ID0
D31# D63# TP21 A33# RSVD9 MSID0
HDBIJ1 G11 C20 HDBIJ3 TP_LAG775_PIN_AJ5 AJ5 Two Feedback Network:
13 HDBIJ1 DBI1# DBI3# HDBIJ3 13 TP17 A34#
G12 A16 TP_LAG775_PIN_AJ6 AJ6 1. socket feedback
13 HDSTBNJ1 DSTBN1# DSTBN3# HDSTBNJ3 13 TP19 A35#
E12 C17 AC4 2. die feedback Y1 CPU_BOOT
13 HDSTBPJ1 DSTBP1# DSTBP3# HDSTBPJ3 13 RSVD3 BOOTSELECT TP26
AE4 THERMDA/THERMDC V2
AD5 RSVD4 1. width=10 mils, spacing=10 mils. LL_ID0 AA2 LL_ID1
13 HADSTBJ1 ADSTB1# 2. route the lines in parallel LL_ID1
Socket-IntelPrescottCPU
C 1 OF 7 C
LL_ID1
R287
0
FSB routing guidelines: If under 5" OK (pin to pin) +/-5%
R0603
check DG 1.0 Dummy
Place at CPU end of route Loadline ID for Cedar Mill support

VTT_OUT_LEFT
VTT_OUT_LEFT VTT_OUT_RIGHT VTT_OUT_RIGHT
VTT_OUT_LEFT place TDO termination near XDP connector
**
Place at CPU end of route R279 62+/-5% HIERRJ place TCK/TDI/TMS terminations near CPU within 1.5 inch
place TRSTJ termination anywhere on route FSB_VTT
*
R294 62+/-5% HBR0J R303 62+/-5% HCPURSTJ C268 U8D 4 OF 7
*****
1
0.1uF R281 49.9 +/-1% Dummy HTDO HTCK
VTT_OUT_RIGHT * 16V, Y5V, +80%/-20% HTDI
AE1
AD1 TCK
TDI
VTT1
VTT2
A29
B25
R263 49.9 +/-1% Dummy HTDI HTDO AF1 B29
2 HTMS AC1 TDO VTT3 B30
TMS VTT4
R262 49.9 +/-1% Dummy HTMS HTRSTJ AG1 C29
TRST# VTT5 A26
TESTHI_9 HTCK VTT6
RN28
8 7
62+/-5% R264 49.9 +/-1% Dummy VTT7
B27
TESTHI_8 HBPM0J AJ2 C28
6 5 TESTHI_10 R298 130 +/-1% PROCHOTJ R266 49.9 +/-1% HTRSTJ HBPM1J AJ1 BPM0# VTT8 A25
4 3 TP_CPUSLPJ VTT_OUT_RIGHT HBPM2J BPM1# VTT9
* AD2 A28
2 1 C284 C270 HBPM3J BPM2# VTT10
AG2 A27
1
HBPM4J BPM3# VTT11

1uF
*
10V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% HBPM5J
AF2
AG3
BPM4# VTT12
C30
A30
1
C283 C269 BPM5# VTT13

* * C25
2
2
** **
R259 62+/-5% TESTHI_12 0.1uF 0.1uF VTT_OUT_RIGHT ICH_SYS_RSTJ VTT14

7,20,30 ICH_SYS_RSTJ AC2 C26
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% DBR# VTT15 C27
2
R256 62+/-5% TESTHI_11 VTT16

AK3 B26
ITPCLKOUT0 VTT17
AJ3 D27
VTT_OUT_LEFT ITPCLKOUT1 VTT18
D28
R255 60.4 +/-1% HCOMP4 RN26 62 +/-5% HBPM4J FSBSEL0 G29 VTT19 D25
B 8 7 7,13 FSBSEL0 BSEL0 VTT20 B
HBPM3J FSBSEL1 H30 D26
HCOMP5 6 5 HBPM5J 7,13 FSBSEL1 FSBSEL2 BSEL1 VTT21 VTT_OUT_RIGHT
R258 60.4 +/-1% G30 B28
1D5V_CORE 4 3 HBPM1J 7,13 FSBSEL2 BSEL2 VTT22
* D29
2 1 VTT23 VTT_OUT_LEFT
design guide 1.0 For VCCPLL D30
*
VTT24
10 mils width R254 62+/-5% Dummy RSVD_G6 AM6 VTT_PWRGD 8
* *
7 mils spacing R280 62+/-5% HBPM2J FSB_VTT VTTPWRGD
max. 1200mils AA1 VTT_OUT_RIGHT
VTT_OUT1
C119 C117 RN18
*1 470 +/-5% FSBSEL0 J1 VTT_OUT_LEFT
1
update in WW32 MOW FSB_VTT 10uF 10nF R282 62+/-5% HBPM0J 2 FSBSEL1 VTT_OUT2
* * F27 TP1
**
R252 60.4 +/-1% HCOMP2 25V, X7R, +/-10% 3 4 FSBSEL2 VTT_SEL

**
R124 62+/-5% TESTHI_0 5 6

2
R257 60.4 +/-1% HCOMP3 7 8

R125 62+/-5% TESTHI_2_7 Place BPM termination near CPU
VTT_OUT_RIGHT
VTT_OUT_LEFT
**
R183 60.4 +/-1% HCOMP0 near D23 R299 1K+/-5% VID_SELECT

*
R278 62+/-5% TESTHI_1

R276 60.4 +/-1% HCOMP1
Intel reply 60.4 Ohm is corrected
* *
MS_ID0 R260 62+/-5%
MS_ID1 R277 62+/-5%
VTT_OUT_RIGHT VTT_OUT_RIGHT
GTLREF voltage should be 0.667*VTT Note:

R295 12 mils width, 15 mils spacing R296
124 divider should be within 1.5" of the GTLREF pin 124
1.MS_ID0: indicate whether the platform
+/-1%0.22nF caps should be placed near CPU pin +/-1% support FMB 05B(05B:MSID0 must
place series resistor as close to divider be pull low)
*
*
HGTLREF_0 R283 0 +/-5%Dummy HGTLREF_2 HGTLREF_1 R286 0 +/-5%Dummy HGTLREF_3
2.MSID1 must be pull low.
A R284 10 +/-5% HGTLREF_0 R285 10 HGTLREF_1 A
+/-5%
C290 C288
C289 * *
* 1uF *R300
249 * C266
220pF * 1uF
10V, X5R, +/-10%
R301
210 * C267
220pF
220pF
50V, NPO, +/-5%
C282
220pF
10V, X5R, +/-10% +/-1% 50V, NPO, +/-5% +/-1% 50V, NPO, +/-5% Dummy 50V, NPO, +/-5%
Dummy Dummy
Dummy
FOXCONN PCEG
Title
LGA775 -1
P4EE GTLREF0 of 0.0986Vcc+0.6106Vtt is based on Vtt of 1.2V Vcc of 1.575V
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
FSB_VTT PLL Supply Filter
VCCP VCCP VCCP

U8G 7 OF 7
U8E 5 OF 7 U8F 6 OF 7
AG22 AK12 AF9 AL23 H22 D5
VCCP1 VCCP93 VCCP185 VSS41 VSS126 VSS211
K29 AH22 AF22 A12 H21 A9
1
AM26 T29 AH11 L25 H20 D3
VCCP3 VCCP95 VCCP187 VSS43 VSS128 VSS213 L15 L16
AL8 AM14 AJ14 J7 H19 B1
AE12 AM25 AH19 AE28 H18 B5 L0805 10uH L0805 10uH
VCCP5 VCCP97 VCCP189 VSS45 VSS130 VSS215 SRF: >=30MHz
AE11 AE9 AH29 AE29 AB7 B8
2
D VCCP6 VCCP98 VCCP190 VSS46 VSS131 VSS216 D
W23 Y29 AH27 K5 H17 AJ4 Rated I: >=120mA SRF: >=30MHz
W24 VCCP7 VCCP99 AK25 AG28 VCCP191 VSS47 J4 AJ24 VSS132 VSS217 AE26 DCR: <=0.36 ohm Rated I: >=120mA
W25 AK19 AL26 AE30 AM17 AH1 DCR: <=0.36 ohm
VCCP9 VCCP101 VCCP193 VSS49 VSS134 VSS219 HVCCIOPLL
T25 AG15 AM12 AN20 AC3 E29 11 HVCCIOPLL
Y28 VCCP10 VCCP102 J22 J24 VCCP194 VSS50 AF10 H14 VSS135 VSS220 V7
AL18 T24 J13 AE24 P28 C13
VCCP12 VCCP104 VCCP196 VSS52 VSS137 VSS222 HVCCA
AC25 AG21 T28 AM24 V6 AK24 11 HVCCA
W30 VCCP13 VCCP105 AM21 W28 VCCP197 VSS53 AN23 AK2 VSS138 VSS223 AB30
Y30 J25 J12 H9 P27 L6
VCCP15 VCCP107 VCCP199 VSS55 VSS140 VSS225 BC1
AN14 U30 J27 H8 P26 L7
AD28
Y26 VCCP17 VCCP109
AL21
AG25
AG19
AL9 VCCP201 VSS57
H13
AC6
AM28
AJ13 VSS142 VSS227
AB29
M1 * 22uF
6.3V,X5R,+/-10%
* EC32
VCCP18 VCCP110 VCCP202 VSS58 VSS143 VSS228 c1206h6
AC29 AJ18 AD30 AC7 W4 AB28 100uF
M29
VCCP20 VCCP112
J19 AF21
VCCP204 VSS60
AH6 P25
VSS145 VSS230
E8 Dummy +/-20%
ESL <= 9 nH, ESR < 0.3 ohm
U24 AH30 Y24 C16 AJ20 AG20
J23 J15 AK14 AM16 W7 AN17
AC27 VCCP22 VCCP114 AG12 J9 VCCP206 VSS62 AE25 P23 VSS147 VSS232 AB27 HVSSA check component requirements
VCCP23 VCCP115 VCCP207 VSS63 VSS148 VSS233 11 HVSSA
AM18 AJ22 M27 AE27 AG13 AB26 Notes:
AM19 J20 AF14 AJ28 AG16 AN16 1. Cap. should be within 1.5" mils of the VCCA and VSSA pins
AB8 AH18 J30 AJ7 AG17 M7 2. VCCA route should be parallel and next to VSSA route to minimize loop area
AC26 AH26 AG18 F19 C7 AB25 3. VCCIOPLL route should be parallel and next to VSSA route to minimize loop area
J8 W27 AA8 AH13 Y2 AB24 3. Min. 12 mils trace from the filter to the processor pins
J28 AL25 AG8 AD7 L30 AB23 4. The inductors should be close to the cap.
T30 AN8 AL29 AH16 L29 N3
AM9 AH14 AD29 AK17 D15 AA30
AF15 U27 W8 E17 AL27 F4
AC8 T23 AH8 AH17 Y7 AG10
AE14 VCCP33 VCCP125 R8 N24 VCCP217 VSS73 AH20 L27 VSS158 VSS243 AE13 VTT_OUT_LEFT
N23 AK22 AN22 AE5 AA29 AF30
W29
U29 VCCP36
VCCP37
VCCP128
VCCP129
AN29
AG11
J14
K26 VCCP220
VCCP221
VSS76
VSS77
AH23
AE7
N6
N7 VSS161
VSS162
VSS246
VSS247
H28
F7 *R253
51 Ohm
AC24 AK26 AF19 AM13 AA28 AF29 +/-5%
AC23 J10 N8 AH24 AN13 AF28
Y23 AJ15 AF12 AJ30 AA27 G1
AN26 VCCP40 VCCP132 AG26 M28 VCCP224 VSS80 AJ10 AA26 VSS165 VSS250 AF27 VTT_OUT_RIGHT
AN25 AN9 AK9 AF3 P4 AF26
AN11 AH15 AK5 AA25 AF25
C AN18 VCCP43 VCCP135 AF18 VSS83 AJ16 AA24 VSS168 VSS253 AN28 10 mils width C
VCCP44 VCCP136 VSS84 VSS169 VSS254
Y27 AL15 C10 AF6 P7 AN27 7 mils spacing
VCCP45 VCCP137 VSS1 VSS85 VSS170 VSS255
Y25 J26 D12 AK29 E26 AF24 max. 1200mils
AD24 VCCP46 VCCP138 J18 VSS2 VSS86 AJ17 V30 VSS171 VSS256 AF23
* **
VCCP47 VCCP139 VSS87 VSS172 VSS257 R261 60.4 +/-1% HCOMP6
AE23 J21 C24 F22 R2 AG24
AE22 AG27 K2 AH3 V29 AF17
VCCP49 VCCP141 VSS5 VSS89 VSS174 VSS259 R265 60.4 +/-1% HCOMP7
AN19 AK15 C22 AK10 V28 AN24
V8 AF11 AN1 AM10 R5 H3
K8 AD23 B14 F16 V27
VCCP52 VCCP144 VSS8 VSS92 VSS177 R184 24.9 +/-1% HCOMP8
AE21 AM15 K7 AJ23 R7 P24
AM30 AF8 AE16 F13 E20 AE20
AE19 VCCP54 VCCP146 AK21 B11 VSS10 VSS94 AG7 AN10 VSS179 VSS264 AE17
AC30 AG30 AL10 F10 V25 E27
AE15 VCCP56 VCCP148 AJ21 AK23 VSS12 VSS96 L26 T3 VSS181 VSS266 T7
VCCP57 VCCP149 VSS13 VSS97 VSS182 VSS267 15 mils width
M30 AM11 H12 AD4 V24 R30
VCCP58 VCCP150 VSS14 VSS98 VSS183 VSS268 7 mils spacing
K27 AL11 AF7 H11 V23 AJ27
M24 VCCP59 VCCP151 AJ11 AK7 VSS15 VSS99 L24 T6 VSS184 VSS269 AB1 max. 1200mils
AN21 K30 H7 L23 AL7 AM4
T8 AL14 E14 AM23 E25 V26
AC28 VCCP62 VCCP154 AN30 L28 VSS18 VSS102 A15 U1 VSS187 VSS272 AA23
N25 AH25 Y5 AH10 R29 AL28
AE18 VCCP64 VCCP156 AL12 E11 VSS20 VSS104 H29 R28 VSS189 VSS274 AF20
W26 AJ9 AL16 B24 R27 AG23
AD25 VCCP66 VCCP158 AK11 AL24 VSS22 VSS106 L3 R26 VSS191 VSS276
M8 AG14 AK13 H27 R25
N30 N29 TP24 AL3 A21 U7
AD26 VCCP69 VCCP161 AL30 D21 VSS25 VSS109 AE2 R24 VSS194
AJ26 AJ25 AL20 AJ29 R23
AM29 AH9 D18 A24 P30
M25 J29 AN2 AK27 V3
M26 J11 AK16 AK28 P29
L8 K25 AK20 B20 AF16 F6
VCCP75 VCCP167 VSS31 VSS115 VSS200 RSVD26
U25 P8 AM27 AM20 AE10
Y8 VCCP76 VCCP168 K23 AM1 VSS32 VSS116 H26 AF13 VSS201 Y3 HCOMP6
VCCP77 VCCP169 VSS33 VSS117 VSS202 RSVD28 HCOMP7
AJ12 AL19 AL13 B17 H6 AE3
AD27 AM8 AL17 H25 A18
U23 T26 C19 H24 A2 E7
M23 VCCP80 VCCP172 N28 E28 VSS36 VSS120 AA3 E2 VSS205 RSVD31 B13 HCOMP8
B VCCP81 VCCP173 VSS37 VSS121 VSS206 RSVD32 B
AG29 AH12 AH7 AA7 D9 D14
N27 AL22 AK30 H23 C4 E6
AM22 AN15 D24 AA6 A6 D1
U28 AJ8 H10 D6 E5
VCCP85 VCCP177 VSS125 VSS210 RSVD36
K28 U26
VCCP86 VCCP178
U8 AJ19 Socket-IntelPrescottCPU Socket-IntelPrescottCPU
VCCP87 VCCP179
AK18 T27
VCCP88 VCCP180
AD8 AK8
K24 VCCP89 VCCP181 AN12
VCCP90 VCCP182
AH28 AG9
VCCP91 VCCP183
AH21 N26
VCCP92 VCCP184
A A
FOXCONN PCEG
Title
LGA775 -2
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
U9A
* *
**
HDJ[63..0] FSBSEL2 R167 10K Dummy FSBSEL0 R147 10K
11 HAJ[31..3] HDJ[63..0] 11 7,11 FSBSEL2 7,11 FSBSEL0
HAJ3 J39 HA3* 1.0 HD0* P41 HDJ0
7,11 FSBSEL1
FSBSEL1 R143 10K U9D Place close to GMCH
HAJ4 K38 HA4* HD1* M39 HDJ1 R166 10K Within 500 mils
HAJ5 J42 HA5* HD2* P42 HDJ2
U9G 1.0
**
HAJ6 K35 HA6* HD3* M42 HDJ3 F21 BSEL0 HSYNC D17 HSYNC_P R172 39+/-5%
HSYNC 19
HAJ7 J37 HA7* HD4* N41 HDJ4 H21 BSEL1 VSYNC C17 VSYNC_P R173 39+/-5%
HAJ8
HAJ9
M34
N35
HA8*
HA9*
HA10*
FSB HD5*
HD6*
M40
L40
HDJ5
HDJ6 18
18
EXP_RXP0
EXP_RXN0
G12
F12
EXP_RX0
EXP_RX0*
EXP_RX1
1.0 EXP_TX0
EXP_TX0*
EXP_TX1
D14
C13
EXP_TXP0
EXP_TXN0
EXP_TXP0
EXP_TXN0
18
18
TP11 TP_ALLZTEST
L20
K18
BSEL2
ALLZTEST
XORTEST
RED
GREEN
F17 RED
RED
VSYNC
19
19
HAJ10 R33 HD7* M41 HDJ7

18 EXP_RXP1
D11 A13 EXP_TXP1
EXP_TXP1 18
TP9 TP_XORTEST H20 K17 GREEN
GREEN 19
VGA
HAJ11 N32 HA11* HD8* K42 HDJ8 D12 EXP_RX1* EXP_TX1* B12 EXP_TXN1
EXP_TXN1 18
TP13 TP_RSV_TP5 L18 RSV_TP5 BLUE H18 BLUE
BLUE 19
HAJ12 HA12* HDJ9 18 EXP_RXN1 EXP_RX2 EXP_TX2 EXP_TXP2 GMCH_EXP_SLR REDJ
N34 HD9* G39
18 EXP_RXP2
J13 A11 EXP_TXP2 18 K21 EXP_SLR RED* G17
HAJ13 M38 HA13* HD10* J41 HDJ10
18 EXP_RXN2
H13 EXP_RX2* EXP_TX2* B10 EXP_TXN2
EXP_TXN2 18
TP12 TP_RSV_TP4 L21 RSV_TP4 GREEN* J17 GREENJ
D
HAJ14 N42 HA14* HD11* G42 HDJ11 E10 EXP_RX3 EXP_TX3 C10 EXP_TXP3
EXP_TXP3 18
GMCH_EXP_EN F20 EXP_EN BLUE* J18 BLUEJ
D
HAJ15 HA15* HD12* HDJ12 18 EXP_RXP3 EXP_RX3* EXP_TXN3 TP16 TP_RSV_TP6 RSV_TP6
N37 G40 F10 EXP_TX3* C9 N21
PCIE
18 EXP_RXN3 EXP_TXN3 18
HAJ16 N38 HA16* HD13* G41 HDJ13 EXP_RXP4 J9 EXP_RX4 EXP_TX4 A9 EXP_TXP4 1D5V_CORE DDC_DATA N18 DDCA_DATA
18 EXP_RXP4 EXP_TXP4 18 DDCA_DATA 19
HAJ17 R32 HA17* HD14* F40 HDJ14
18 EXP_RXN4
EXP_RXN4 H10 EXP_RX4* EXP_TX4* B7 EXP_TXN4
EXP_TXN4 18 DDC_CLK N20 DDCA_CLK DDCA_CLK 19
Place close to
HAJ18 R36 HA18* HD15* F43 HDJ15 EXP_RXP5 F7 EXP_RX5 EXP_TX5 D7 EXP_TXP5
EXP_TXP5 18 M17 RESERVED GMCH
HAJ19 HA19* HDJ16 18 EXP_RXP5 EXP_RXN5 EXP_TXN5
U37 HD16* F37 F9 EXP_RX5* EXP_TX5* D6 L17 RESERVED REFSET A20 REFSET Within 500 mils
HAJ20 R35 HA20* HD17* E37 HDJ17 EXP_RXP6 C4 EXP_RX6 EXP_TX6 A6 EXP_TXP6
EXP_TXP6 18
DREFCLKP J15 CK_96M_P_GMCH 7
18 EXP_RXP6
HAJ21 R38 HA21* HD18* J35 HDJ18 EXP_RXN6 D3 EXP_RX6* EXP_TX6* B5 EXP_TXN6
EXP_TXN6 18 R27 RESERVED DREFCLKN H15 CK_96M_N_GMCH 7
HAJ22 HA22* HDJ19 18 EXP_RXN6 EXP_RXP7 EXP_TX7 EXP_TXP7
V33 HD19* D39 G6 EXP_RX7 E2 EXP_TXP7 18 U27 RESERVED 2D5V_MCH
*
18 EXP_RXP7 EXP_TX7*
HAJ23 U34 HA23* HD20* C41 HDJ20
18 EXP_RXN7
EXP_RXN7 J6 EXP_RX7* F1 EXP_TXN7
EXP_TXN7 18 Intel
M15 RESERVED EXTTS* J20 EXTTSJ R177 10K +/-5%
HAJ24 U32 HA24* HD21* B39 HDJ21 EXP_RXP8 K9 EXP_RX8 EXP_TX8 G2 EXP_TXP8
EXP_TXP8 18
Symbol 1.0 update
L15 RESERVED RESERVED M11
HAJ25 HA25* HD22* HDJ22 18 EXP_RXP8 EXP_RXN8 EXP_TXN8
V42 B40
18 EXP_RXN8
K8 EXP_RX8* EXP_TX8* J1 EXP_TXN8 18 RESERVED V30
HAJ26 HA26* HDJ23 EXP_RXP9 EXP_TXP9 NC PLTRSTJ
HAJ27
U35
Y36 HA27*
HD23*
HD24*
H34
C37 HDJ24 18
18
EXP_RXP9
EXP_RXN9
EXP_RXN9
F4
G4
EXP_RX9
EXP_RX9*
EXP_TX9
EXP_TX9*
J3
K4 EXP_TXN9
EXP_TXP9
EXP_TXN9
18
18
BB2
BA2 NC MISC RSTIN*
PWROK
AJ12
AJ9 PWRGD_3V
PLTRSTJ 20,27
HAJ28 Y38 HA28* HD25* J32 HDJ25 EXP_RXP10 M6 EXP_RX10 EXP_TX10 L4 EXP_TXP10
EXP_TXP10 18 AW26 NC ICH_SYNC* M18 ICH_SYNCJ
ICH_SYNCJ 20
HAJ29 HA29* HD26* HDJ26 18 EXP_RXP10 EXP_RXN10 EXP_TX10* EXP_TXN10 NC
AA37 B35
18 EXP_RXN10
M7 EXP_RX10* M4
EXP_TXN10 18
AW2
HAJ30 V32 HA30* HD27* J34 HDJ27
18 EXP_RXP11
EXP_RXP11 K2 EXP_RX11 EXP_TX11 M2 EXP_TXP11
EXP_TXP11 18 AV27 NC RESERVED A43
HAJ31 Y34 HA31* HD28* B34 HDJ28 EXP_RXN11 L1 EXP_RX11* EXP_TX11* N1 EXP_TXN11 AV26 NC
AA35 RSVD HD29* F32 HDJ29 EXP_RXP12 U11 EXP_RX12 EXP_TX12 P2 EXP_TXP12 E35 NC NC BC43 REFSET
18 EXP_RXP12 EXP_TXP12 18
AA42 RSVD HD30* L32 HDJ30 EXP_RXN12 U10 EXP_RX12* EXP_TX12* T1 EXP_TXN12 C42 NC NC BC42 R178
18 EXP_RXN12 EXP_TXN12 18 NC
AA34 RSVD HD31* J31 HDJ31 EXP_RXP13 R8 EXP_RX13 EXP_TX13 T4 EXP_TXP13
EXP_TXP13 18 B42 NC BC2 255
HD32* HDJ32 18 EXP_RXP13 EXP_RXN13 EXP_TXN13 NC NC
AA38 RSVD H31
18 EXP_RXN13
R7 EXP_RX13* EXP_TX13* U4 EXP_TXN13 18 B41 BC1
HD33* M33 HDJ33 EXP_RXP14 P4 EXP_RX14 EXP_TX14 U2 EXP_TXP14
EXP_TXP14 18
NC BB43
HD34* 18 EXP_RXP14 +/-1%
11 HREQJ[4..0]
K31 HDJ34
18 EXP_RXN14
EXP_RXN14 N3 EXP_RX14* EXP_TX14* V1 EXP_TXN14
EXP_TXN14 18 AJ27 RESERVED NC BB1
HREQJ0 E41 HREQ0* HD35* M27 HDJ35 EXP_RXP15 Y10 EXP_RX15 EXP_TX15 V3 EXP_TXP15
EXP_TXP15 18 AG27 RESERVED NC C2
HREQJ1 HD36* HDJ36 18 EXP_RXP15 EXP_RXN15 EXP_TXN15 RESERVED NC
D41 HREQ1* K29
18 EXP_RXN15
Y11 EXP_RX15* EXP_TX15* W4 EXP_TXN15 18
AG26 B43
HREQJ2 K36 HREQ2* HD37* F31 HDJ37 AG25 RESERVED NC B3
HREQJ3 G37 HREQ3* HD38* H29 HDJ38 DMI_RXP0 Y7 DMI_RX0 AJ24 RESERVED NC B2
HREQJ4 HD39* HDJ39 20 DMI_RXP0 DMI_RXN0 DMI_TX0 DMI_TXP0 NC BLUE
E42 HREQ4* F29
20 DMI_RXN0
Y8 DMI_RX0* W2 DMI_TXP0 20 A42
HD40* L27 HDJ40 DMI_RXP1 AA9 DMI_RX1 DMI_TX0* Y1 DMI_TXN0 AD30 RESERVED 2D5V_DAC GREEN
20 DMI_RXP1 DMI_TXN0 20
11
11
HADSTBJ0
HADSTBJ1
M36
V35
HADSTB0*
HADSTB1*
HD41*
HD42*
M24
J26
HDJ41
HDJ42 20
20
DMI_RXN1
DMI_RXP2
DMI_RXN1
DMI_RXP2
AA10
AA6
DMI_RX1*
DMI_RX2 DMI DMI_TX1
DMI_TX1*
AA2
AB1
DMI_TXP1
DMI_TXN1
DMI_TXP1
DMI_TXN1
20
20
AC34
Y30
RESERVED
RESERVED
RESERVED
RESERVED
AK21
AJ23
RED
HD43* K26 HDJ43 DMI_RXN2 AA7 DMI_RX2* DMI_TX2 Y4 DMI_TXP2

DMI_TXP2 20
Y33 RESERVED RESERVED AJ26
20 DMI_RXN2 RESERVED
HDSTBP0 HD44* HDJ44 DMI_RXP3 DMI_RX3 DMI_TX2* DMI_TXN2 RESERVED R174
11
11
HDSTBPJ0
HDSTBNJ0
K41
L43 HDSTBN0* HD45*
G26
H24 HDJ45 20
20
DMI_RXP3
DMI_RXN3
DMI_RXN3
AC9
AC8 DMI_RX3* DMI_TX3
AA4
AB3 DMI_TXP3
DMI_TXN2
DMI_TXP3
20
20 1D5V_PE_GMCH
AF31
AD31 RESERVED
RESERVED
RESERVED
RESERVED
AL29
AL20 R149 R153 150 * *R175 R176
150 *150
HDBIJ0 K40 HDINV_0* HD46* K24 HDJ46 DMI_TX3* AC4 DMI_TXN3 U30 AJ21 4.7K 4.7K
11 HDBIJ0 DMI_TXN3 20 RESERVED
11 HDSTBPJ1 F35 HDSTBP1 HD47* F24 HDJ47
7 CK_PE_100M_P_GMCH B14 GCLKP V31 RESERVED AL26 +/-5% +/-5% +/ -1% +/ -1% +/ -1%
*
G34 HDSTBN1* HD48* E31 HDJ48
7 CK_PE_100M_N_GMCH B16 GCLKN EXP_COMPO AC12 GMCH_EXP_COMP R201 +/-1% AA30 RESERVED RESERVED AK27
C 11
11
HDSTBNJ1
HDBIJ1
HDBIJ1 A38 HDINV_1* HD49* A33 HDJ49 EXP_COMPI AC11 AC30 RESERVED 5 OF 7 RESERVED AJ29 DDCA_DATA C
J27 HDSTBP2 HD50* E40 HDJ50 R169 0 +/-5% Dummy F15 SDVO_CTRLDATA 24.9 RESERVED AG29
11 HDSTBPJ2 18 SDVO_CTRLDATA
11 HDSTBNJ2 M26 HDSTBN2* HD51* D37 HDJ51 R156 0 +/-5% Dummy E15 SDVO_CTRLCLK DDCA_CLK
HDBIJ2 HDINV_2* HDJ52 18 SDVO_CTRLCLK width 10 mils, spacing 7 mils
11 HDBIJ2 E29 HD52* C39
E34 HDSTBP3 HD53* D38 HDJ53
2 OF 7
11 HDSTBPJ3
11 HDSTBNJ3
B37 HDSTBN3* HD54* D33 HDJ54
HDBIJ3 B32 HDINV_3* HD55* C35 HDJ55 unstuff when no internal
11 HDBIJ3
HD56* D34 HDJ56
W42 HADS* HD57* C34 HDJ57 graphics connection
11 HADSJ
W40 HTRDY* HD58* B31 HDJ58
11 HTRDYJ HDRDY* HD59* HDJ59 2D5V_MCH 3D3V_SYS
V41 C31
11 HDRDYJ
P40 HDEFER* HD60* C32 HDJ60
11 HDEFERJ
W41 HHITM* HD61* D32 HDJ61
11 HITMJ HHIT* HD62* HDJ62 CRB 1.03 pull-up to 2.5V
U41 B30
11 HITJ HLOCK* HD63* HDJ63
U40 D30
11 HLOCKJ
HBREQ0*
11
11
HBR0J
HBNRJ
AA41
U39 HBNR* HSWING B27 HSWING *R170
4.7K *R155
4.7K
HBPRI* HSCOMP HSCOMP +/-5% +/-5%
11
11
HBPRIJ
HDBSYJ
D42
U42 HDBSY*
HRS0*
HRCOMP
C27
A28 HRCOMP Dummy Dummy *R146
1K
T40 +/-5%
11 HRSJ0 HRS1* MCH_GTLREF
11 HRSJ1
Y43 HDVREF D27 Dummy
11 HRSJ2
T43 HRS2* HACCVREF D28
C30 HCPURST*
11 HCPURSTJ
F38 HPCREQ* HCLKP M31 CK_200M_P_GMCH 7
Y40 HEDRDY* HCLKN M29 CK_200M_N_GMCH 7
GMCH_EXP_EN_HDR GMCH_EXP_EN
1 OF 7 18 GMCH_EXP_EN_HDR
Signal termination (follow Intel reference 0p7)

Intel confirm
FSB_VTT COMP SIGNAL TERMINATION

FSB_VTT
B
*R150
301
B
*
+/-1% R160 60.4 +/-1% HSCOMP place near GMCH

15 mils width
C176 20 mils spacing
2.2pF
*
*
R159 62+/-5% HSWING 50V, NPO, +/-0.25pF
*
C0603 R165 1K+/-5% Dummy GMCH_EXP_SLR
Dummy
R151 C148 ATX dummy
1
84.5 10nF C175

+/-1% * 25V, X7R, +/-10% * 1uF
BTX pop
10V, X5R, +/-10% 5 mils width, 5 mils spacing in the breakout

2
5 mils width, 8 mils spacing after the breakout

max. 750 mils
HSWING voltage should be 0.22*FSB_VTT

12 mils width, 10 mils spacing
max. 3 inches long
caps should be placed near GMCH pin.
FSB_VTT
HRCOMP R168 16.9 +/-1%
CLIP1N1 10 mils width, 7 mils spacing R141

U9_1 124
1 max. 500 mils
1 +/-1%
2
1 A2 D 2 MCH_GTLREF_CPU 11
1 2
R158
Clip_2P
FOXCONN
MCH_GTLREF
5 CLIP3N1
B 5C 6
1
6 1 R140 C147 10
*
1
210 0.1uF +/-5% C159

Heatsink 2
2
+/-1% * 16V, Y5V, +80%/-20% 220pF
A Clip_2P PWRGD_3V 50V, NPO, +/-5%
A
2
20,27 PWRGD_3V
R213
10K Close to GMCH
Need to apply Heatsink for Lakeport chipset. +/-5% GTLREF voltage should be 0.63*VTT
R0603 12 mils width, 15 mils spacing
Dummy divider should be within 1.5" of the GTLREF pin
0.22nF caps should be placed near MCH pin
place series resistor as close to divider FOXCONN PCEG
Title
LAKEPORT GMCH -1
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
U9B U9C
16,17 M_MA_B[13..0] M_DQS_P_B[7..0] 16
16,17 M_MA_A[13..0] M_MA_A0 SMA_A0 1.0 SDQS_A0 M_DQS_P_A0
M_DQS_P_A[7..0] 16
M_MA_B0
M_MA_B1
BB22 SMA_B0 1.0 SDQS_B0 AM8 M_DQS_P_B0
M_DQS_N_B0
M_DQS_N_B[7..0] 16
BA32 AU4 M_DQS_N_A[7..0] 16
BB21 SMA_B1 SDQS_B0* AM6 M_DQM_B[7..0] 16
M_MA_A1 AW32 SMA_A1 SDQS_A0* AR2 M_DQS_N_A0 M_MA_B2 BA21 SMA_B2 SDM_B0 AL11 M_DQM_B0
M_DQM_A[7..0] 16 M_MD_B[63..0] 16
M_MA_A2 BB30 SMA_A2 SDM_A0 AR3 M_DQM_A0
M_MD_A[63..0] 16
M_MA_B3 AY21 SMA_B3
M_MA_A3 BA30 SMA_A3 M_MA_B4 BC20 SMA_B4 SDQ_B0 AL6 M_MD_B0
M_MA_A4 AY30 SMA_A4 SDQ_A0 AP3 M_MD_A0 M_MA_B5 AY19 SMA_B5 SDQ_B1 AL8 M_MD_B1
M_MA_A5 BA27 SMA_A5 SDQ_A1 AP2 M_MD_A1 M_MA_B6 AY20 SMA_B6 SDQ_B2 AP8 M_MD_B2
M_MA_A6 BC28 SMA_A6 SDQ_A2 AU3 M_MD_A2 M_MA_B7 BA18 SMA_B7 SDQ_B3 AP9 M_MD_B3
M_MA_A7 AY27 SMA_A7 SDQ_A3 AV4 M_MD_A3 M_MA_B8 BA19 SMA_B8 SDQ_B4 AJ11 M_MD_B4
M_MA_A8 AY28 SMA_A8 SDQ_A4 AN1 M_MD_A4 M_MA_B9 BB18 SMA_B9 SDQ_B5 AL9 M_MD_B5
M_MA_A9 BB27 SMA_A9 SDQ_A5 AP4 M_MD_A5 M_MA_B10 BA22 SMA_B10 SDQ_B6 AM10 M_MD_B6
M_MA_A10 AY33 SMA_A10 SDQ_A6 AU5 M_MD_A6 M_MA_B11 BB17 SMA_B11 SDQ_B7 AP6 M_MD_B7
D
M_MA_A11 AW27 SMA_A11 SDQ_A7 AU2 M_MD_A7 M_MA_B12 BA17 SMA_B12 M_DQS_P_B[7..0] 16 D
M_MA_A12 BB26 SMA_A12 M_DQS_P_A[7..0] 16
M_MA_B13 AW42 SMA_B13 SDQS_B1 AV7 M_DQS_P_B1
M_DQS_N_B[7..0] 16
M_MA_A13 BC38 SMA_A13 SDQS_A1 BA3 M_DQS_P_A1
M_DQS_N_A[7..0] 16 SDQS_B1* AR9 M_DQS_N_B1
M_DQM_B[7..0] 16
SDQS_A1* BB4 M_DQS_N_A1
M_DQM_A[7..0] 16 16,17 M_WEJ_B
BB23 SWE_B* SDM_B1 AW7 M_DQM_B1
M_MD_B[63..0] 16
BB35 SWE_A* SDM_A1 AY2 M_DQM_A1 AY24 SCAS_B*
16,17 M_WEJ_A M_MD_A[63..0] 16 16,17 M_CASJ_B
BA37 SCAS_A* BA23 SRAS_B* SDQ_B8 AU7 M_MD_B8
16,17 M_CASJ_A 16,17 M_RASJ_B
16,17 M_RASJ_A
BA34 SRAS_A* 16,17 M_BS_B[2..0] SDQ_B9 AV6 M_MD_B9
SDQ_A8 AW3 M_MD_A8 M_BS_B0 AW23 SBS_B0 SDQ_B10 AV12 M_MD_B10
M_BS_A0 BC33 SBS_A0 SDQ_A9 AY3 M_MD_A9 M_BS_B1 AY23 SBS_B1 SDQ_B11 AM11 M_MD_B11
M_BS_A1 AY34 SBS_A1 SDQ_A10 BA7 M_MD_A10 M_BS_B2 AY17 SBS_B2 SDQ_B12 AR5 M_MD_B12
M_BS_A2 BA26 SBS_A2 SDQ_A11 BB7 M_MD_A11
16,17 M_CSJ_B[1..0] SDQ_B13 AR7 M_MD_B13
SDQ_A12 AV1 M_MD_A12 M_CSJ_B0 BA40 SCS_B0* SDQ_B14 AR12 M_MD_B14
16,17 M_BS_A[2..0] M_CSJ_A0 SDQ_A13 M_MD_A13 M_CSJ_B1 M_MD_B15
16,17 M_CSJ_A0
BB37 SCSB_A0* AW4 AW41 SCS_B1* SDQ_B15 AR10
M_CSJ_A1 BA39 SCSB_A1* SDQ_A14 BC6 M_MD_A14 BA41 SCS_B2*
16,17 M_CSJ_A1 SDQ_A15 M_DQS_P_B[7..0] 16
BA35 SCSB_A2* AY7 M_MD_A15 AW40 SCS_B3* SDQS_B2 AV13 M_DQS_P_B2
M_DQS_N_B[7..0] 16
AY38 SCSB_A3* 16,17 M_CKE_B[1..0]
SDQS_B2* AT13 M_DQS_N_B2
SDQS_A2 M_DQS_P_A[7..0] 16 M_DQM_B[7..0] 16
AY11 M_DQS_P_A2
M_DQS_N_A[7..0] 16
M_CKE_B0 BA14 SCKE_B0 SDM_B2 AP13 M_DQM_B2
M_MD_B[63..0] 16
16,17 M_CKE_A[1..0] SCKE_A0
M_CKE_A0 BB25 SDQS_A2* BA10 M_DQS_N_A2
M_DQM_A[7..0] 16
M_CKE_B1 AY16 SCKE_B1
M_CKE_A1 AY25 SCKE_A1 SDM_A2 BB10 M_DQM_A2
M_MD_A[63..0] 16 BA13 SCKE_B2 SDQ_B16 AM15 M_MD_B16
BC24 SCKE_A2 BB13 SCKE_B3 SDQ_B17 AM13 M_MD_B17
BA25 SCKE_A3 SDQ_A16 AW12 M_MD_A16 SDQ_B18 AV15 M_MD_B18
SDQ_A17 AY10 M_MD_A17 16,17 M_ODT_B[1..0] M_ODT_B0 AY42 SODT_B0 SDQ_B19 AM17 M_MD_B19
16,17 M_ODT_A[1..0] M_ODT_A0 AW37 SODT_A0 SDQ_A18 BA12 M_MD_A18 M_ODT_B1 AV40 SODT_B1 SDQ_B20 AN12 M_MD_B20
M_ODT_A1 AY39 SODT_A1 SDQ_A19 BB12 M_MD_A19 AV43 SODT_B2 SDQ_B21 AR13 M_MD_B21
AY37 SODT_A2 SDQ_A20 BA9 M_MD_A20 AU40 SODT_B3 SDQ_B22 AP15 M_MD_B22
BB40 SODT_A3 SDQ_A21 BB9 M_MD_A21 SDQ_B23 AT15 M_MD_B23
SDQ_A22 BC11 M_MD_A22
M_DQS_P_B[7..0] 16
SDQ_A23 AY12 M_MD_A23 SDQS_B3 AU23 M_DQS_P_B3
SCLK_A0 M_DQS_N_B[7..0] 16
M_CK_P_A0 BB32 M_DQS_P_A[7..0] 16 16 M_CK_P_B0 AM29 SCLK_B0 SDQS_B3* AR23 M_DQS_N_B3
M_DQM_B[7..0] 16
16 M_CK_P_A0 M_CK_N_A0 SCLK_A0* SDQS_A3 M_DQS_P_A3 SCLK_B0* M_DQM_B3
16 M_CK_N_A0
AY32 AU18
M_DQS_N_A[7..0] 16 16 M_CK_N_B0
AM27 SDM_B3 AP23
M_MD_B[63..0] 16
M_CK_P_A1 AY5 SCLK_A1 SDQS_A3* AR18 M_DQS_N_A3
M_DQM_A[7..0] 16 16 M_CK_P_B1 AV9 SCLK_B1
16 M_CK_P_A1 M_CK_N_A1 SCLK_A1* SDM_A3 M_DQM_A3 SDQ_B24 M_MD_B24
16 M_CK_N_A1
BB5 AP18 M_MD_A[63..0] 16 16 M_CK_N_B1 AW9 SCLK_B1* AM24
M_CK_P_A2 AK42 SCLK_A2 16 M_CK_P_B2
AL38 SCLK_B2 SDQ_B25 AM23 M_MD_B25
16 M_CK_P_A2 SDQ_B26
16 M_CK_N_A2
M_CK_N_A2 AK41 SCLK_A2* SDQ_A24 AM20 M_MD_A24
16 M_CK_N_B2 AL36 SCLK_B2* AV24 M_MD_B26
BA31 SCLK_A3 SDQ_A25 AM18 M_MD_A25 AP26 SCLK_B3 SDQ_B27 AM26 M_MD_B27
BB31 SCLK_A3* SDQ_A26 AV20 M_MD_A26 AR26 SCLK_B3* SDQ_B28 AP21 M_MD_B28
AY6 SCLK_A4 SDQ_A27 AM21 M_MD_A27 AU10 SCLK_B4 SDQ_B29 AR21 M_MD_B29
BA5 SCLK_A4* SDQ_A28 AP17 M_MD_A28 AT10 SCLK_B4* SDQ_B30 AP24 M_MD_B30
C AH40 SCLK_A5 SDQ_A29 AR17 M_MD_A29 AJ38 SCLK_B5 SDQ_B31 AT24 M_MD_B31 C
AH43 SCLK_A5* SDQ_A30 AP20 M_MD_A30 AJ36 SCLK_B5* M_DQS_P_B[7..0] 16
SDQ_A31 AT20 M_MD_A31 SDQS_B4 AT29 M_DQS_P_B4
M_DQS_N_B[7..0] 16
BC16 RSVD M_DQS_P_A[7..0] 16 SDQS_B4* AV29 M_DQS_N_B4
M_DQM_B[7..0] 16
AY14 RSVD SDQS_A4 AU35 M_DQS_P_A4
M_DQS_N_A[7..0] 16 SDM_B4 AR29 M_DQM_B4
M_MD_B[63..0] 16
AW17 RSVD SDQS_A4* AV35 M_DQS_N_A4
M_DQM_A[7..0] 16
AW18 RSVD SDM_A4 AT34 M_DQM_A4
M_MD_A[63..0] 16 SDQ_B32 AU27 M_MD_B32
AL39 RSVD SDQ_B33 AN29 M_MD_B33
SDQ_A32 AP32 M_MD_A32 SDQ_B34 AR31 M_MD_B34
SDQ_A33 AV34 M_MD_A33 SDQ_B35 AM31 M_MD_B35
SDQ_A34 AV38 M_MD_A34 SDQ_B36 AP27 M_MD_B36
SDQ_A35 AU39 M_MD_A35 SDQ_B37 AR27 M_MD_B37
SDQ_A36 AV32 M_MD_A36 SDQ_B38 AP31 M_MD_B38
AK40 RSVD SDQ_A37 AT32 M_MD_A37 DDR_GMCH_VREF_B AM2 SVREF1 SDQ_B39 AU31 M_MD_B39
SDQ_A38 AR34 M_MD_A38
M_DQS_P_B[7..0] 16
SDQ_A39 AU37 M_MD_A39 SDQS_B5 AP36 M_DQS_P_B5
M_DQS_N_B[7..0] 16
SDQS_B5* AM35 M_DQS_N_B5
M_DQS_P_A[7..0] 16 M_DQM_B[7..0] 16
SDQS_A5 M_DQS_P_A5 SDM_B5 M_DQM_B5
DDR_GMCH_VREF_A AM4 SVREF0 SDQS_A5*
SDM_A5
AP42
AP40
AP39
M_DQS_N_A5
M_DQM_A5
M_DQS_N_A[7..0] 16
M_DQM_A[7..0] 16
M_MD_A[63..0] 16
DDR_B SDQ_B40
AR38
AP35 M_MD_B40
M_MD_B[63..0] 16
SDQ_B41 AP37 M_MD_B41

SDQ_A40 AR41 M_MD_A40 AK18 RSV_TP3 SDQ_B42 AN32 M_MD_B42
DDR_A SDQ_A41
SDQ_A42
SDQ_A43
AR42
AN43
AM40
M_MD_A41
M_MD_A42
M_MD_A43
1D8V_STR
WW39 MOW/CRB1.01 update
AK23 RSV_TP2 SDQ_B43
SDQ_B44
SDQ_B45
AL35
AR35
AU38
M_MD_B43
M_MD_B44
M_MD_B45
SDQ_A44 AU41 M_MD_A44 (must remove pull-down resistor) SDQ_B46 AM38 M_MD_B46
SDQ_A45 AU42 M_MD_A45 Double check in DG1.0 AM3 SOCOMP1 SDQ_B47 AM34 M_MD_B47
AL17 RSV_TP1 SDQ_A46 AP41 M_MD_A46 AJ8 SOCOMP0
M_DQS_P_B[7..0] 16
AK17 RSV_TP0 SDQ_A47 AN40 M_MD_A47 SRCOMP1 AJ6 SRCOMP1 SDQS_B6 AG34 M_DQS_P_B6
M_DQS_N_B[7..0] 16
R220 80.6 +/-1% SRCOMP0 AL5 SRCOMP0 SDQS_B6* AG32 M_DQS_N_B6
M_DQS_P_A[7..0] 16 M_DQM_B[7..0] 16
SDQS_A6 AG42 M_DQS_P_A6
M_DQS_N_A[7..0] 16
SDM_B6 AJ39 M_DQM_B6
M_MD_B[63..0] 16
SDQS_A6* AG41 M_DQS_N_A6
M_DQM_A[7..0] 16
SDM_A6 AG40 M_DQM_A6
M_MD_A[63..0] 16
C272 SDQ_B48 AL34 M_MD_B48
1
0.1uF R219 SDQ_B49 M_MD_B49
SDQ_A48 AL41 M_MD_A48 * 16V, Y5V, +80%/-20% 80.6 SDQ_B50
AJ34
AF32 M_MD_B50
SDQ_A49 AL42 M_MD_A49 +/-1% SDQ_B51 AF34 M_MD_B51
2
SDQ_A50 AF39 M_MD_A50 SDQ_B52 AL31 M_MD_B52
B
SDQ_A51 AE40 M_MD_A51 SDQ_B53 AJ32 M_MD_B53
B
SDQ_A52 AM41 M_MD_A52 SDQ_B54 AG35 M_MD_B54
SDQ_A53 AM42 M_MD_A53 SDQ_B55 AD32 M_MD_B55
SDQ_A54 AF41 M_MD_A54
M_DQS_P_B[7..0] 16
SDQ_A55 AF42 M_MD_A55 SDQS_B7 AD36 M_DQS_P_B7
M_DQS_N_B[7..0] 16
SDQS_B7* AD38 M_DQS_N_B7
M_DQS_P_A[7..0] 16 M_DQM_B[7..0] 16
SDQS_A7 AC42 M_DQS_P_A7
M_DQS_N_A[7..0] 16 SDM_B7 AD39 M_DQM_B7
M_MD_B[63..0] 16
SDQS_A7* AC41 M_DQS_N_A7
M_DQM_A[7..0] 16
SDM_A7 AC40 M_DQM_A7
M_MD_A[63..0] 16
SDQ_B56 AC32 M_MD_B56
SDQ_B57 AD34 M_MD_B57
SDQ_A56 AD40 M_MD_A56 SDQ_B58 Y32 M_MD_B58
SDQ_A57 AD43 M_MD_A57 SDQ_B59 AA32 M_MD_B59
SDQ_A58 AA39 M_MD_A58 SDQ_B60 AF35 M_MD_B60
SDQ_A59 AA40 M_MD_A59 SRCOMP[1:0] SDQ_B61 AF37 M_MD_B61
SDQ_A60 AE42 M_MD_A60 10 mils width, 10 mils spacing, max 1.5" length SDQ_B62 AC33 M_MD_B62
SDQ_A61 AE41 M_MD_A61 place cap/res within 1" of GMCH package
4 OF 7 SDQ_B63 AC35 M_MD_B63
SDQ_A62 AB41 M_MD_A62
3 OF 7 SDQ_A63 AB42 M_MD_A63
1D8V_STR
DDR_GMCH_VREF_A
C253
1
0.1uF
* 16V, Y5V, +80%/-20%
*R228
2
1K
+/-1%
DDR_GMCH_VREF_B
C258
1
R232 0.1uF
A * 1K * 16V, Y5V, +80%/-20% A
+/-1%
2
FOXCONN PCEG
width 12 mils, spacing 12 mils
Title
5 mils width/spacing minimum for a max. of 300 mils
in the GMCH break-out area LAKEPORT GMCH -2
place each cap to Vref pin Size Document Number Rev
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
U9E
1D8V_STR
1D5V_CORE VCCSM BC18
N17 VCC 1.0 VCCSM BC22
P17 VCC VCCSM BC26
AH4 VCC VCCSM BC31
AJ5 VCC VCCSM BC35 1D5V_CORE 1D5V_CORE
AK4 VCC VCCSM BC13 U9F U9I
VCCSM U9H
AF30 VCC BB42
AK20 VCC VCCSM BB38 A16 AL2 BB39 M10
VSS VSS VSS VSS
AK3 VCC VCCSM BB33 AJ15 VCC 1.0 VCC AC15 A22
VSS VSS
AL21 BB41
VSS VSS
M13
AK2 VCC VCCSM BB28 AG23 VCC VCC AC17 A26 AL23 BB6 M20
VCC VCC VSS VSS VSS VSS
AJ14 VCCSM BB24 AG22 VCC AC18 A31
VSS VSS
AL24 BC4
VSS VSS
M21
AK14 VCC VCCSM BB20 AG21 VCC VCC AC20 A35 AL27 BC9 M3
VCCSM VCC VCC VSS VSS VSS VSS
AK15 VCC BB16 AG20 AC24 A4
VSS VSS
AL3 C12
VSS VSS
M35
AJ13 VCC VCCSM AY41 AG19 VCC VCC AC26 A40 AL32 C14 M37
VCC VSS VSS VSS VSS
AH2 VCC VCCSM AW21 AG18 VCC AC27 AA11
VSS VSS
AL33 C22
VSS VSS
M5
D AH1 VCC VCCSM AW13 AG17 VCC VCC AD15 AA12 AL37 C3 M8 D
AG14 VCC VCCSM AV31 AG15 AD17 AA14
VSS VSS
AL43 C40
VSS VSS
M9
AG13 VCC VCCSM AV21 AB18 VCC VCC AJ17 AA21 AL7 C5 N13
VCC VSS VSS VSS VSS
AG12 VCC VCCSM AW35 Y27 VCC AD19 AA23
VSS VSS
AM33 C7
VSS VSS
N15
AG11 VCC VCCSM AW34 Y25 VCC VCC AD21 AA25 AM36 D1 N2
VCC VSS VSS VSS VSS
AG10 VCC VCCSM AW31 Y19 VCC AD23 AA27
VSS VSS
AM37 D10
VSS VSS
N24
AG9 VCC VCCSM AW29 Y18 VCC VCC AD25 AA29 AM39 D16 N26
VCC VCCSM VCC VCC VSS VSS VSS VSS
AG8 AW24 W27 AD26 AA3 AM5 D2 N27
VCC VCCSM VCC VCC VSS VSS VSS VSS
AG7 AW20 W26 AE17 AA31 AM7 D20 N29
VSS VSS VSS VSS
AG6 VCC VCCSM AW15 W20 VCC VCC AE18 AA33
VSS VSS
AM9 D21
VSS VSS
N31
AG5 VCC VCCSM AV42 U19 VCC VCC AE20 AA36 AN13 D43 N33
VCC VCC VCC VSS VSS VSS VSS
AG4 VCCSM AV23 U18 AE22 AA8
VSS VSS
AN15 D5
VSS VSS
N36
AG3 VCC VCCSM AV18 U17 VCC VCC AE24 AB2 AN17 E12 N39
VSS VSS VSS VSS
AG2 VCC U15 VCC VCC AJ18 AB43 AN18 E13 N43
AF14 VCC R24 AE26 AC10
VSS VSS
AN2 E17
VSS VSS
N6
AF13 VCC 1D5V_PE_GMCH R23 VCC VCC AE27 AC14 AN20 E18 N8
VSS VSS VSS VSS
AF12 VCC VCC_EXP AD4 R21 VCC VCC AF15 AC19 AN21 E20 P14
VCC_EXP VCC VCC VSS VSS VSS VSS
AF11 VCC AD5 R20 AF17 AC2 AN23 E21 P15
POWER
POWER
AF10 VCC VCC_EXP AD6 R18 AF19 AC21
VSS VSS
AN24 E3
VSS VSS
P24
AF9 VCC VCC_EXP AD8 AF29 VCC VCC AF21 AC23
VSS VSS
AN26 E32
VSS VSS
P26
AF8 VCC VCC_EXP AD10 R17 VCC VCC AF23 1D8V_STR AC25 AN27 E4 P27
VCC VCC VCC VSS VSS VSS VSS
AF7 VCC_EXP AD12 R15 AJ20 AC29
VSS VSS
AN31 E7
VSS VSS
P29
AF6 VCC VCC_EXP N5 U20 VCC AC3 AN4 E9 P3
VSS VSS VSS VSS
AD14 VCC VCC_EXP N7 U21 VCC VCCSM BC40 AC31 AN42 F13 P30
VCC VCC_EXP VCC VSS VSS VSS VSS
AC22 N9 U22 VCCSM AY43 AC36
VSS VSS
AP10 F18
VSS VSS
R12
AB23 VCC VCC_EXP N10 U23 VCC AC37 AP12 F2 R14
VCC_EXP VSS VSS VSS VSS
AB22 VCC N12 U24 VCC AC38 AP29 F26 R26
VCC_EXP VCC VSS VSS VSS VSS
AB21 VCC R5 U25 AC39
VSS VSS
AP34 F34
VSS VSS
R29
AA22 VCC VCC_EXP R10 U26 VCC AC7 AP38 F42 R30
VSS VSS VSS VSS
P21 VCC VCC_EXP AE2 V15 VCC AD11 AP5 F6 R31
VSS VSS VSS VSS
P20 VCC VCC_EXP R11 V17 VCC AD13 AP7 G10 R34
P18 VCC R13 V18 AD18
VSS VSS
AR1 G13
VSS VSS
R37
FSB_VTT VCC_EXP U6 AF25 VCC AD20 AR15 G15 R39
VCC_EXP VSS VSS VSS VSS
F27 VTT U7 AF26 VCC AD22 AR20 G18 R6
VTT VCC_EXP VCC VSS VSS VSS VSS
G23 U8 AF27 AD24 AR24 G20 R9
H23 VTT U13 AG24 AD27
VSS VSS
AR32 G21
VSS VSS
T2
J23 VTT VCC_EXP V5 V19 VCC AD29 AR37 G24 T42
VCC VSS VSS VSS VSS
K23 VTT VCC_EXP V6 V20 AD33
VSS VSS
AR39 G27
VSS VSS
U12
C L23 VTT VCC_EXP V7 V21 VCC AD35 AR43 G29 U14 C
VSS VSS VSS VSS
M23 VTT VCC_EXP V9 V22 VCC AD37
VSS VSS
AR6 G3
VSS VSS
U29
A24 VTT VCC_EXP AE3 V23 VCC AD42 AT12 G31 U3
VCC VSS VSS VSS VSS
N23 VTT VCC_EXP V10 V25 AD7
VSS VSS
AT17 G32
VSS VSS
U31
C26 VTT VCC_EXP V13 V27 VCC AD9 AT18 G35 U33
VSS VSS VSS VSS
D23 VTT VCC_EXP Y13 W17 VCC AE19 AT21 G38 U36
VCC VSS VSS VSS VSS
D24 VTT VCC_EXP AA5 W18 AE21
VSS VSS
AT23 G5
VSS VSS
U38
D25 VTT VCC_EXP AA13 W19 VCC AE23 AT26 G7 U5
VSS VSS VSS VSS
P23 VTT VCC_EXP AC5 W22 VCC AE25 AT27 G9 U9
VCC VSS VSS VSS VSS
F23 VTT VCC_EXP AC6 W24 AF1
VSS VSS
AT31 H12
VSS VSS
V11
E27 VTT VCC_EXP AC13 Y15 VCC AF18 AU12 H17 V12
VSS VSS VSS VSS
E26 VTT VCC_EXP AD1 Y17 VCC AF2
VSS VSS
AU13 H26
VSS VSS
V14
E24 VTT VCC_EXP AD2 Y21 VCC AF20 AU15 H27 V2
VCC VSS VSS VSS VSS
E23 VTT VCC_EXP AE4 Y23 AF22
VSS VSS
AU17 H32
VSS VSS
V24
C25 VTT VCC_EXP N11 AA15 VCC AF24 AU20 J10 V26
VSS VSS VSS VSS
C23 VTT AA17 VCC AF3 AU21 J12 V29
VCC VSS VSS VSS VSS
B26 VTT AA18 AF33
VSS VSS
AU24 J2
VSS VSS
V34
2D5V_DAC B25 VTT AA19 VCC AF36 AU26 J21 V36
VSS VSS VSS VSS
B24 VTT AA20 VCC AF38 AU29 J24 V37
VTT VCC VSS VSS VSS VSS
B23 AA24 AF43 AU32 J29 V38
VCC VSS VSS VSS VSS
AA26 AF5 AU34 J38 V39
VCCA_DPLLB VSS VSS VSS VSS
VCCA_DPLLB B19 AB17 VCC AG30
VSS VSS
AU6 J43
VSS VSS
V43
VCCA_SMPLL B20 VCCA_SMPLL AB19 VCC AG31 AU9 J5 V8
VCCA_HPLL VCCA_HPLL VCC VSS VSS VSS VSS
C21 AB20 AG33 AV10 J7 W21
VCCA_DPLLA VCCA_DPLLA VCC VSS VSS VSS VSS
C19 AB24 AG36 AV17 K10 W23
VSS VSS VSS VSS
C18 VCCA_DAC AB25 VCC AG37 AV2 K12 W25
VCC VSS VSS VSS VSS
2D5V_MCH B18 VCCA_DAC AB26 AG38
VSS VSS
AV37 K13
VSS VSS
W3
D19 VCC2 AB27 VCC AG39 AW10 K15 Y12
7 OF 7 AH42
VSS
VSS
VSS
VSS
AY1 K20
VSS
VSS
VSS
VSS
Y14
AJ10 B11 K27 Y2
VCCA_EXPPLL VCCA_EXPPLL VSS VSS VSS VSS
B17 AJ30 B13 K3 Y20
A18 VSSA_DAC 6 OF 7 AJ31
VSS
VSS
VSS
VSS
B21 K32
VSS
VSS
VSS
VSS
Y22
AJ33 B22 K34 Y24
AJ35 VSS VSS B28 K37 VSS VSS Y26
VSS VSS VSS VSS
AJ37 B33 K39 Y29
VSS VSS VSS VSS
AJ7 B38 K5 Y31
1D5V_CORE PCI Express PLL Analog Power VSS VSS VSS VSS
AK24 B4 K6 Y35
AK26 VSS VSS B6 K7 VSS VSS Y37
B VSS VSS VSS VSS B
2D5V_MCH Power for DAC 1D5V_CORE 1D5V_CORE AK29 B9 L12 Y39
VSS VSS VSS VSS
AK30 BA4 L13 Y42
*
L21 L0805 1uH +/-20% VCCA_EXPPLL C438 C440 VSS VSS VSS VSS
AL1 BA42 L2 Y5
1
VSS VSS VSS VSS
Dummy 0.1uF 0.1uF
CP15 C156 C177 from GMCH to 1st cap must be less than 1 inch * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
AL10
AL12
VSS VSS
BB11
BB14
L24
L26
VSS VSS
Y6
Y9
1
VSS VSS VSS VSS

10uF 0.1uF 2D5V_DAC Dummy Dummy
2 1
* * AL13 BB19 L29
2
6.3V, X5R, +/-10%
16V, X7R, +/-10% VSS VSS VSS
AL15 BB3 L31
*
FB12 2 VSS VSS VSS

X_COPPER 1+-25% R164 0 +/-5% 2D5V_DAC AL18 BB34 L42
2
VSS VSS VSS

FB 180 Ohm C150 C191 C190 QG82945G QG82945G
1
Host PLL power

* EC36 * 0.1uF
* 0.1uF
* 10nF
FB13 FB L0805 600 Ohm VCCA_HPLL 16V, X7R, +/-10% 25V, X7R, +/-10%
* 100uF
2
Dummy 2D5V_DAC Filter

+/-20% Dummy
16V, Y5V, +80%/-20%
C161 C189 1D5V_CORE 1D5V_CORE
1
1uF 0.1uF
2
CP14
1 * *
10V, X5R, +/-10% 16V, X7R, +/-10%
Dummy C439 C437
2
1
0.1uF 0.1uF
X_COPPER
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
1D5V_CORE Power for PCIE I/O and DMI I/O Dummy Dummy
2
2
L18 1 2 L0805 10uH VCCA_DPLLA
Dummy from GMCH to 1st cap must be less than 1 inch 1D5V_PE_GMCH
CP12 EC37 C188 1D5V_CORE
*
1
2 1 X_COPPER * 220uF
6.3V, +/-20% * 0.1uF
16V, X7R, +/-10%
L24Dummy
1206 L1206 0.1uH
1D5V_PE_GMCH place GMCH backside Place in 1D5V_CORE plane as close to the GMCH as possible
EC43 C234 C233 C232

2
Display PLL power CP17 2 1X_COPPER * 220uF

6.3V, +/-20% * 10uF
*
10V, Y5V, +80%/-20%
10uF
* 0.1uF
10V, Y5V, +80%/-20%
16V, X7R, +/-10% EC46 C243 C242 C244 C245
1
L17 1 2 L0805 10uH VCCA_DPLLB CP20 2 1X_COPPER C0805
* 1000uF
* 10uF
* 10uF
* 0.1uF
* 0.1uF
2
Dummy Dummy 1D8V_STR Connect ground sides of caps with traces to GND balls 6.3V, +/-20% 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% 16V, X7R, +/-10% 16V, X7R, +/-10%
CP11 EC34 C192 CP19 2 1X_COPPER (less than 100 mils from the package) Dummy
1
2
2 1 X_COPPER * 220uF
6.3V, +/-20% * 0.1uF
16V, X7R, +/-10%
PCI Express Filter
2
C275 C276 C273 EC48 1D5V_CORE Decoupling

1
A
System Memory PLL power FSB_VTT
Place in FSB_VTT plane as close to the GMCH as possible
(less than 100 mils from the package) * 0.1uF
16V, X7R, +/-10% * 2.2uF
* 0.1uF
16V, X7R, +/-10%
* 1000uF
6.3V, +/-20%
A
2
*
L20 L1206 10uH VCCA_SMPLL

+/-20% Dummy
C160
1
C178 0.1uF EC38 C152 C128 C129 C130 C181 C186

CP13
* *
1
2 1 1uF 16V, Y5V, +80%/-20%

* 100uF
* 10uF
* 10uF 10uF
* 0.1uF
* 0.1uF
* 0.1uF
* C274 C318 C263
1
10V, X5R, +/-10% Dummy 16V, +/-20% 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% 16V, X7R, +/-10% 16V, X7R, +/-10% 2.2uF 2.2uF 0.1uF
* * *
2
Dummy Dummy C0805 16V, X7R, +/-10% Dummy 16V, X7R, +/-10%
X_COPPER
FOXCONN PCEG
2
Dummy Dummy
2
FSB_VTT Decoupling Title

LAKEPORT GMCH -3
from GMCH to 1st cap must be less than 1 inch. GMCH Memory Decoupling
If 0.5 Ohm, +/- 1%, R0603 is not easy get, you could replace by 0 Ohm, +/- 1%, R0603. Size Document Number Rev
C 945M09 1.0
Date: Wednesday, August 22, 2007 Sheet 15 of 32

5 4 3 2 1

5 4 3 2 1
1D8V_STR 1D8V_STR
3D3V_SYS
3D3V_SYS
191
194
181
175
170
197
172
187
184
178
189
238
51
56
62
72
75
78
53
59
64
69
67
191
194
181
175
170
197
172
187
184
178
189
238
DIMM2
51
56
62
72
75
78
53
59
64
69
67
DIMM1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDSPD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
2 7 M_DQS_P_B0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDSPD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
14 M_DQS_P_B[7..0] VSS DQS<0>
2 7 M_DQS_P_A0 5 16 M_DQS_P_B1
14 M_DQS_P_A[7..0] VSS DQS<0> VSS DQS<1>
5 16 M_DQS_P_A1 8 28 M_DQS_P_B2
VSS DQS<1> 14 M_DQM_B[7..0] VSS DQS<2>
8 28 M_DQS_P_A2 11 37 M_DQS_P_B3
D 14 M_DQM_A[7..0] VSS DQS<2> VSS DQS<3> D
11 37 M_DQS_P_A3 14 84 M_DQS_P_B4
VSS DQS<3> 14 M_DQS_N_B[7..0] VSS DQS<4>
14 84 M_DQS_P_A4 17 93 M_DQS_P_B5
14 M_DQS_N_A[7..0] VSS DQS<4> VSS DQS<5>
17 93 M_DQS_P_A5 14 M_MD_B[63..0] 20 105 M_DQS_P_B6
VSS DQS<5> M_DQS_P_A6 VSS DQS<6> M_DQS_P_B7
14 M_MD_A[63..0] 20 105 23 114
23 VSS DQS<6> 114 M_DQS_P_A7 26 VSS DQS<7> 46
VSS DQS<7> 14,17 M_CKE_B[1..0] VSS DQS<8>
14,17 M_CKE_A[1..0] 26 46 29
VSS DQS<8> VSS M_DQM_B0
29 32 125
32 VSS 125 M_DQM_A0 35 VSS DM0/DQS9 134 M_DQM_B1
14 M_CK_P_A[2..0] VSS DM0/DQS9 14,17 M_CSJ_B[1..0] VSS DM1/DQS10
35 134 M_DQM_A1 38 146 M_DQM_B2
VSS DM1/DQS10 M_DQM_A2 VSS DM2/DQS11 M_DQM_B3
14 M_CK_N_A[2..0] 38 146 14,17 M_BS_B[2..0] 41 155
41 155 44 202
44 VSS DM3/DQS12 202 M_DQM_A4 47 VSS DM4/DQS13 211 M_DQM_B5
14,17 M_CSJ_A[1..0] VSS DM4/DQS13 14,17 M_MA_B[13..0] VSS DM5/DQS14
47 211 M_DQM_A5 50 223 M_DQM_B6
14,17 M_BS_A[2..0] 50 223 14,17 M_ODT_B[1..0] 65 232
65 VSS DM6/DQS15 232 M_DQM_A7 66 VSS DM7/DQS16 164
VSS DM7/DQS16 VSS DM8/DQS17
14,17 M_MA_A[13..0] 66 164 79
79 VSS DM8/DQS17 82 VSS 6 M_DQS_N_B0
VSS 14 M_CK_P_B[2..0] VSS DQS#<0>
82 6 M_DQS_N_A0 85 15 M_DQS_N_B1
14,17 M_ODT_A[1..0] VSS DQS#<0> VSS DQS#<1>
85 15 M_DQS_N_A1 88 27 M_DQS_N_B2
VSS DQS#<1> 14 M_CK_N_B[2..0] VSS DQS#<2>
88 27 M_DQS_N_A2 91 36 M_DQS_N_B3
VSS DQS#<2> M_DQS_N_A3 VSS DQS#<3> M_DQS_N_B4
91 36 94 83
94 83 97 92
97 92 100 104
100 104 103 113
VSS DQS#<6> M_DQS_N_A7 VSS DQS#<7>
103 113 106 45
VSS DQS#<7> VSS DQS#<8>
106 45 109
VSS DQS#<8> VSS
109 112 126
112 VSS 126 115 VSS NC/DQS9# 135
VSS NC/DQS9# VSS NC/DQS10#
115 135 118 147
1D8V_STR VSS NC/DQS10# VSS NC/DQS11#
118 147 121 156
121 VSS NC/DQS11# 156 124 VSS NC/DQS12# 203
124 203 127 212
127 212 130 224
130 224 133 233
133 VSS NC/DQS15# 233 136 VSS NC/DQS16# 165
136 165 139
VSS NC/DQS17# VSS M_MD_B0
*R341 C337 139 142 3
1
C 1K 0.1uF VSS M_MD_A0 VSS DQ<0> M_MD_B1 C

+/-1% * 142
145
VSS
VSS
DQ<0>
DQ<1>
3
4 M_MD_A1
145
148
VSS
VSS
DQ<1>
DQ<2>
4
9 M_MD_B2
148 9 M_MD_A2 151 10 M_MD_B3
2
151 VSS DQ<2> 10 M_MD_A3 DDRVREFA 154 VSS DQ<3> 122 M_MD_B4
DDRVREFA VSS DQ<3> M_MD_A4 VSS DQ<4> M_MD_B5
154 122 157 123
VSS DQ<4> M_MD_A5 VSS DQ<5> M_MD_B6
157 123 160 128
160 128 163 129
1
*R340 C335 163
VSS DQ<7>
129
* * C351 166
VSS DQ<8>
12
1
1K 0.1uF M_MD_A8 C336 0.1uF M_MD_B9

+/-1% * 166
169
VSS DQ<8>
12
13 M_MD_A9 0.1uF Dummy
169
198
VSS DQ<9>
13
21 M_MD_B10
2
198 21 Dummy 201 22
2
201 VSS DQ<10> 22 M_MD_A11 204 VSS DQ<11> 131 M_MD_B12

204 131 207 132
210 140 213 141
213 141 216 24
219 25 222 30
222 30 225 31
228 143 231 144
234 149 237 150
237 VSS DQ<22> 150 M_MD_A23 VSS DQ<23> 33 M_MD_B24
VSS DQ<23> M_MD_A24 DQ<24> M_MD_B25
33 18 34
DQ<24> M_MD_A25 RC1 DQ<25> M_MD_B26
18 34 55 39
55 RC1 DQ<25> 39 M_MD_A26 DDRVREFA 1 RC0 DQ<26> 40 M_MD_B27
DDRVREFA RC0 DQ<26> M_MD_A27 SMB_CLK_MAIN 120 VREF DQ<27> M_MD_B28
1 40 152
VREF DQ<27> 7,18,20,23 SMB_CLK_MAIN SCL DQ<28>
SMB_CLK_MAIN 120 152 M_MD_A28 SMB_DATA_MAIN 119 153 M_MD_B29
7,18,20,23 SMB_CLK_MAIN SCL DQ<28> 7,18,20,23 SMB_DATA_MAIN SDA DQ<29>
SMB_DATA_MAIN 119 153 M_MD_A29 101 158 M_MD_B30
7,18,20,23 SMB_DATA_MAIN SDA DQ<29> SA2 DQ<30>
101 158 M_MD_A30 240 159 M_MD_B31
SA2 DQ<30> M_MD_A31 SA1 DQ<31> M_MD_B32
240 159 3D3V_SYS 239 80
SA1 DQ<31> M_MD_A32 SA0 DQ<32> M_MD_B33
239 80 81
SA0 DQ<32> 81 M_MD_A33 M_CSJ_B0 193 DQ<33> 86 M_MD_B34
M_CSJ_A0 DQ<33> M_MD_A34 M_CSJ_B1 S0# DQ<34> M_MD_B35
193 86 76 87
M_CSJ_A1 S0# DQ<34> M_MD_A35 S1# DQ<35> M_MD_B36
76 87 199
S1# DQ<35> M_MD_A36 M_BS_B0 DQ<36> M_MD_B37
199 71 200
M_BS_A0 71 DQ<36> 200 M_MD_A37 M_BS_B1 190 BA0 DQ<37> 205 M_MD_B38
B BA0 DQ<37> BA1 DQ<38> B
M_BS_A1 190 205 M_MD_A38 M_BS_B2 54 206 M_MD_B39
M_BS_A2 BA1 DQ<38> M_MD_A39 M_MA_B0 A16/BA2 DQ<39> M_MD_B40
54 206 188 89
M_MA_A0 A16/BA2 DQ<39> M_MD_A40 M_MA_B1 A0 DQ<40> M_MD_B41
188 89 183 90
M_MA_A1 A0 DQ<40> M_MD_A41 M_MA_B2 A1 DQ<41> M_MD_B42
183 90 63 95
63 95 182 96
182 96 61 208
61 208 60 209
60 209 180 214
M_MA_A6 180 A5 DQ<45> 214 M_MD_A46 M_MA_B7 58 A6 DQ<46> 215 M_MD_B47
58 215 179 98
179 98 177 99
177 99 70 107
M_MA_A10 A9 DQ<49> M_MD_A50 M_MA_B11 A10/AP DQ<50> M_MD_B51
70 107 57 108
M_MA_A11 57 A10/AP DQ<50> 108 M_MD_A51 M_MA_B12 176 A11 DQ<51> 217 M_MD_B52
176 217 196 218
M_MA_A13 A12 DQ<52> M_MD_A53 A13 DQ<53> M_MD_B54
196 218 174 226
A13 DQ<53> M_MD_A54 A14 DQ<54> M_MD_B55
174 226 173 227
A14 DQ<54> M_MD_A55 A15 DQ<55> M_MD_B56
173 227 110
A15 DQ<55> M_MD_A56 M_CASJ_B DQ<56> M_MD_B57
110 14,17 M_CASJ_B 74 111
M_CASJ_A DQ<56> M_MD_A57 M_RASJ_B CAS# DQ<57> M_MD_B58
14,17 M_CASJ_A
74 111 14,17 M_RASJ_B
192 116
M_RASJ_A CAS# DQ<57> M_MD_A58 M_WEJ_B RAS# DQ<58> M_MD_B59
14,17 M_RASJ_A 192 116 14,17 M_WEJ_B 73 117
M_WEJ_A 73 RAS# DQ<58> 117 M_MD_A59 68 WE# DQ<59> 229 M_MD_B60
14,17 M_WEJ_A WE# DQ<59> NC1 DQ<60>
68 229 M_MD_A60 102 230 M_MD_B61
NC1 DQ<60> M_MD_A61 NC/TEST DQ<61> M_MD_B62
102 230 19 235
NC/TEST DQ<61> M_MD_A62 M_ODT_B0 NC2 DQ<62> M_MD_B63
19 235 195 236
M_ODT_A0 NC2 DQ<62> M_MD_A63 M_ODT_B1 ODT0 DQ<63>
195 236 77
M_ODT_A1 77 ODT0 DQ<63> 42 ODT1 52 M_CKE_B0
ODT1 M_CKE_A0 CB<0> CKE0 M_CKE_B1
42 52 43 171
CB<0> CKE0 M_CKE_A1 CB<1> CKE1 M_CK_P_B0
43 171 48 185
CB<1> CKE1 M_CK_P_A0 CB<2> CK0 M_CK_N_B0
48 185 49 186
CB<2> CK0 M_CK_N_A0 CB<3> CK0# M_CK_P_B1
49 186 161 137
CB<3> CK0# M_CK_P_A1 CB<4> CK1/RFU M_CK_N_B1
161 137 162 138
CB<4> CK1/RFU M_CK_N_A1 CB<5> CK1#/RFU M_CK_P_B2
162 138 167 220
CB<5> CK1#/RFU M_CK_P_A2 CB<6> CK2/RFU M_CK_N_B2
167 220 168 221
CB<6> CK2/RFU CB<7> CK2#/RFU
242
243
241
168 221 M_CK_N_A2
CB<7> CK2#/RFU
242
243
241
DDRII 242
243
241
A A
DDRII
242
243
241
FOXCONN PCEG
Title
DIMM D DDRII-A1,A2
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
channel A channel B
D D
14,16 M_CKE_A[1..0]
14,16 M_CKE_B[1..0]
14,16 M_CSJ_A[1..0]
14,16 M_CSJ_B[1..0]
14,16 M_BS_A[2..0]
14,16 M_BS_B[2..0]
14,16 M_MA_A[13..0]
14,16 M_MA_B[13..0]
14,16 M_ODT_A[1..0]
14,16 M_ODT_B[1..0]
VTT_DDR VTT_DDR
DDR Controll group signals VTT_DDR
Pls change the value to 47ohm
******
R328 39+/-5% M_CKE_A1
if used in sis project
Pls change the value to 47ohm
R329 39+/-5% M_CKE_A0
if used in sis project
* **** ***
R368 39+/-5% M_CSJ_B0
R334 39+/-5% M_CSJ_A0
VTT_DDR R365 39+/-5% M_CKE_B1
R338 39+/-5% M_CSJ_A1
R366 39+/-5% M_CKE_B0
R339 39+/-5% M_ODT_A1
RN32
*1 2
33+/-5% M_MA_A3
M_MA_A2 R336 39+/-5% M_ODT_A0
RN38
*1 2
33 +/-5% M_MA_B0
M_BS_B0 R369 39+/-5% M_ODT_B0
3 4 M_MA_A1 3 4 M_BS_B1
5 6 5 6 R371 39+/-5% M_CSJ_B1
7 8 VTT_DDR 7 8
RN31
*1 2
33+/-5% M_MA_A5
M_MA_A8 RN39
*1 33 +/-5% M_WEJ_B
M_WEJ_B 14,16
R372 39+/-5% M_ODT_B1
3 4 2
5 6
M_MA_A6
M_MA_A4
RN33
*1 2
33 +/-5% M_MA_A10
M_BS_A0 3 4
M_RASJ_B
M_CASJ_B
M_RASJ_B
M_CASJ_B
14,16
14,16
R367 33+/-5% M_BS_B2
7 8 3 4 M_BS_A1 5 6
5 6 7 8
C RN30
* 13 2
4
33+/-5% M_MA_A12
M_MA_A11 7 8
M_RASJ_A
M_RASJ_A 14,16
R370 33+/-5% M_MA_B13 C
M_MA_A7 VTT_DDR
5 6 M_MA_A9
****
7 8 R333 33+/-5% M_WEJ_A
M_WEJ_A 14,16
*
R244 33 +/-5% M_MA_A0 R330 33+/-5% M_BS_A2
R335 33+/-5% M_CASJ_A

M_CASJ_A 14,16
RN35
*1 2
33 +/-5% M_MA_B3
M_MA_B2
R337 33+/-5% M_MA_A13 3 4 M_MA_B1
5 6
DDR Command group signals 7 8
RN37
*1 2
33 +/-5% M_MA_B5
M_MA_B8
3 4 M_MA_B6
5 6 M_MA_B4
7 8
RN36
*1 2
33 +/-5% M_MA_B12
M_MA_B11
3 4 M_MA_B7
5 6 M_MA_B9
7 8
*
R250 33+/-5% M_MA_B10
VTT_DDR VTT_DDR
VTT_DDR VTT_DDR
B B
C334 C397 C383 C378 C393 C382 C384 C394 C392 C329
1
4.7uF 4.7uF C347 C385 C330 C331 C332 C344 C345 C333 C398 C395
* * * * * * * * * *
1
10V, Y5V, +80%/-20% 4.7uF 4.7uF
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10V, Y5V, +80%/-20% * * * * * * * * * * 10V, Y5V, +80%/-20%
2
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10V, Y5V, +80%/-20%
2
1D8V_STR
1D8V_STR
C315 C338 C354 C339 C340 C316 C352 C376

1
C377 C353 C379 C402 C389 C388 C387 C386

* * * * * * * *
1
1
* * * * * * * *
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF

2
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

A 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF A
2
2
FOXCONN PCEG
Title
DDRII A & B Term
C 945M09 1.0
Date: Thursday, August 23, 2007 Sheet 17 of 32

5 4 3 2 1

5 4 3 2 1
3D3V_DUAL 3D3V_SYS 12V_SYS 12V_SYS 3D3V_SYS
PCI-E1_16X
12V_SYS 3D3V_SYS 3D3V_DUAL
B1 A1
B2 12V PRSNT1# A2
12V 12V C92 C100 C101
B3 A3
RSVD1 12V 0.1uF 0.1uF 0.1uF
7,16,20,23 SMB_CLK_MAIN
SMB_CLK_MAIN
B4
B5
GND
SMCLK
GND
JTAG2
A4
A5 * 25V, X7R, +/-10% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
SMB_DATA_MAIN B6 A6 Dummy
7,16,20,23 SMB_DATA_MAIN SMDAT JTAG3
B7 A7
GND JTAG4
B8 A8
3.3V JTAG5
B9 A9
JTAG1 3.3V
B10 A10
WAKEJ 3.3VAUX 3.3V ICH_G_PLTRSTJ
D B11 A11 ICH_G_PLTRSTJ 27 D
20 WAKEJ WAKE# PWRGD
All AC Coupling caps. should be placed within 250 mils of the connector KEY
C116 B12 A12 12V_SYS 3D3V_SYS
0.1uF C118 B13 RSVD2 GND A13 CK_PE_100M_P_16PORT
GND REFCLK+ CK_PE_100M_P_16PORT 7
16V, X7R, +/-10% EXP_TXP0_C 0.1uF B14 A14 CK_PE_100M_N_16PORT
13 EXP_TXP0 CK_PE_100M_N_16PORT 7
*
EXP_TXN0_C HSOP0 REFCLK- EC21 EC41
13 EXP_TXN0 B15 A15
*
HSON0 GND
SDVO_CTRLCLK
16V, X7R, +/-10% B16
B17
GND HSIP0
A16
A17
EXP_RXP0 13 * 470uF
16V, +/-20%
* 1000uF
6.3V, +/-20%
13 SDVO_CTRLCLK PRSNT2_B17# HSIN0 EXP_RXN0 13
B18 A18
C124 GND GND
0.1uF C125
16V, X7R, +/-10% EXP_TXP1_C 0.1uF B19 A19
13 EXP_TXP1
*
EXP_TXN1_C HSOP1 RSVD5
13 EXP_TXN1 B20 A20
*
C127 16V, X7R, +/-10% B21 HSON1 GND A21
0.1uF C131 GND HSIP1 EXP_RXP1 13
B22 A22
EXP_TXP2_C GND HSIN1 EXP_RXN1 13
16V, X7R, +/-10% 0.1uF B23 A23
13 EXP_TXP2
*
EXP_TXN2_C HSOP2 GND
13 EXP_TXN2 B24 A24
*
C134 16V, X7R, +/-10% HSON2 GND
B25 A25
B26 A26
16V, X7R, +/-10% EXP_TXP3_C 0.1uF GND HSIN2 EXP_RXN2 13
13 EXP_TXP3 B27 A27
* 13 EXP_TXN3
EXP_TXN3_C B28
HSOP3 GND
A28
*
16V, X7R, +/-10% HSON3 GND
B29 A29
GND HSIP3 EXP_RXP3 13
B30 A30
SDVO_CTRLDATA RSVD3 HSIN3 EXP_RXN3 13
13 SDVO_CTRLDATA
B31 A31
C145 PRSNT2_B31# GND
B32 A32
0.1uF C151 GND RSVD6
16V, X7R, +/-10% EXP_TXP4_C 0.1uF B33 A33
13 EXP_TXP4
*

B34 A34
13 EXP_TXN4
*
C155 16V, X7R, +/-10% HSON4 GND
B35 A35
0.1uF C162 B36 GND HSIP4 A36 EXP_RXP4 13
B37 A37
13 EXP_TXP5
*

13 EXP_TXN5 B38 A38
*
C172 16V, X7R, +/-10% HSON5 GND
B39 A39
0.1uF C179 B40 GND HSIP5 A40 EXP_RXP5 13
13 EXP_TXP6 B41 A41
*

13 EXP_TXN6 B42 A42
*
C C197 16V, X7R, +/-10% B43 HSON6 GND A43 C
B44 A44
13 EXP_TXP7 B45 A45
*
EXP_TXN7_C B46 HSOP7 GND A46

13 EXP_TXN7
*
16V, X7R, +/-10% HSON7 GND
B47 A47
13 GMCH_EXP_EN_HDR B48 A48
PRSNT2_B48# HSIN7 EXP_RXN7 13
B49 A49
C203 GND GND
0.1uF C208
16V, X7R, +/-10% EXP_TXP8_C 0.1uF B50 A50
13 EXP_TXP8
*

13 EXP_TXN8 B51 A51
*
C213 16V, X7R, +/-10% B52 HSON8 GND A52
B53 A53
16V, X7R, +/-10% EXP_TXP9_C 0.1uF B54 GND HSIN8 A54 EXP_RXN8 13
13 EXP_TXP9
*

B55 A55
13 EXP_TXN9
*
C216 16V, X7R, +/-10% HSON9 GND
B56 A56
0.1uF C217 B57 A57
B58 A58
13 EXP_TXP10
*

13 EXP_TXN10 B59 A59
*
C218 16V, X7R, +/-10% B60 HSON10 GND A60
B61 A61
13 EXP_TXP11
*

*
C230 16V, X7R, +/-10% B64 HSON11 GND A64

B65 A65
13 EXP_TXP12 B66 A66
*
EXP_TXN12_C B67 HSOP12 GND A67

13 EXP_TXN12
*
C237 16V, X7R, +/-10% HSON12 GND

B68 A68
B69 A69
EXP_TXP13_C GND HSIN12 EXP_RXN12 13
16V, X7R, +/-10% 0.1uF B70 A70
13 EXP_TXP13
*

*
C240 16V, X7R, +/-10% HSON13 GND

B72 A72
B73 A73
13 EXP_TXP14
*

13 EXP_TXN14
B75 A75
*
C248 16V, X7R, +/-10% HSON14 GND 12V_SYS 3D3V_SYS

B76 A76 EXP_RXP14 13
0.1uF C249 GND HSIP14
B77 A77
B 13 EXP_TXP15 B
*
EXP_TXN15_C HSOP15 GND C90 C166

*
HSON15 GND
16V, X7R, +/-10% B80
B81
GND
PRSNT2_B81#
HSIP15
HSIN15
A80
A81
EXP_RXP15
EXP_RXN15
13
13
* 0.1uF
25V, X7R, +/-10% * 0.1uF
16V, Y5V, +80%/-20%
B82 A82
RSVD4 GND
Slot-PCIE-16X
All AC Coupling caps. should be placed within 250 mils of the connector
3D3V_DUAL 3D3V_SYS 12V_SYS 3D3V_DUAL 12V_SYS

12V_SYS 3D3V_SYS
C104 EC29
PCI-E1_1X * 0.1uF
16V, Y5V, +80%/-20%
* 470uF
16V, +/-20%
B1
12V PRSNT1#
A1 Dummy
B2 A2
12V 12V
B3 A3
RSVD 12V
B4 A4
SMB_CLK_MAIN GND GND
B5 A5
SMB_DATA_MAIN B6 SMCLK JTAG2 A6
SMDAT JTAG3
B7 A7
GND JTAG4
B8 A8
3.3V JTAG5
B9 A9
JTAG1 3.3V
B10 A10
WAKEJ 3.3VAUX 3.3V ICH_G_PLTRSTJ
B11 A11
WAKE# PWRGD
KEY
B12 A12
RSVD1 GND CK_PE_100M_P_1PORT
B13 A13
A GND REFCLK+ CK_PE_100M_N_1PORT CK_PE_100M_P_1PORT 7 A
20 HSO_P4_SLOT B14 A14 CK_PE_100M_N_1PORT 7
HSOP0 REFCLK-
20 HSO_N4_SLOT B15 A15
B16 HSON0 GND A16
GND HSIP0 HSI_P4 20
B17 A17
PRSNT2# HSIN0 HSI_N4 20
B18 A18
GND GND
Slot_PCI-X1
FOXCONN PCEG
Title
PCI Express x16 Gfx Slot
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
RGB routing
1. from GMCH to the first 150 ohm resistor: 12 mils(min. 6 mils spacing )
2. from the first 150 ohm res. to the second 150 ohm resistor: 7 mils
3. from the second 150 ohm resistor to connector: 4 mils
4. spacing minimum 6 mils, 30 mils spacing is recommended
5. R,G,B should be length matched to 200 mils, max. length is 8400 mils
6. R,G,B signals should be ground referenced
D D
L6
*
RED 2 1 L2
13 RED
5V_SYS
5V_SYS 5V_SYS 0 100nH
+/-5%
R39 C40
*
*
150 10pF C29 C6
C91 1 2 2D5V_MCH +/ -1% * 50V, NPO, +/-5%
* 10pF
* 22pF F1
0.1uF Dummy 50V, NPO, +/-5% 50V, NPO, +/-5% Fuse 1.5A
* C97 * D18
0.1uF
BAV99
16V, Y5V, +80%/-20%
L7
L_RED
*
EMI cap. for RGB layer change GREEN 2 1 L3 L_GREEN
13 GREEN 100nH L_BLUE
0
C35 +/-5%
VGA
*R43 * 10pF C30 C7
3
150 50V, NPO, +/-5% 10pF 22pF VGA
1 2 2D5V_MCH +/ -1% Dummy * 50V, NPO, +/-5% * 50V, NPO, +/-5% 5V_DDCA_CLK 15 SCL GND 5
5V_DDCA_DATA 10 GND
C 14 VSYNC ID0 4 C
D11
9 NC
BAV99 13 HSYNC B 3
8 GND
12 SDA G 2
7 GND
11 ID1 R 1
L8 C47 6 GND
0.1uF
*
*
BLUE 2 1 L4 DZ11AA1-HW7-4F
16
17
13 BLUE 100nH
0
+/-5%
*R44 C46 C31 C8
3
150 10pF 10pF 22pF
5V_SYS
5V_SYS 1 2 2D5V_MCH +/ -1% * 50V, NPO, +/-5% * 50V, NPO, +/-5% * 50V, NPO, +/-5%
2D5V_MCH Dummy
2
D10
D4 BAV99
BAV99 3
R28 R29
4.7K 4.7K
+/-5% +/-5%
1
The 150 Ohm resistors near VGA connector and

G
Q4 2N7002-7-F minimizing length to filter. The filters to VGA

connector maximum distance 800 mils.
*
S D R15 100 +/-1% 5V_DDCA_CLK

13 DDCA_CLK
G
S D R14 100 +/-1% 5V_DDCA_DATA

13 DDCA_DATA
5V_VSYNC
5V_SYS
3
Q2 5V_HSYNC
B 1 2 B
2N7002-7-F
C5 C3
D13 10pF 10pF
BAV99 * *
50V, NPO, +/-5% 50V, NPO, +/-5%
3D3V_SYS
U7 *R31
0
1 5 +/-5%
OE# VCC
Dummy
13 VSYNC 2
A
*
3 4 R17 0 +/-5% 5V_VSYNC
GND Y
NC7SZ125
C39
*
3
D20
2 1
U3 0.1uF
3D3V_SYS
1 5 BAV99
A OE# VCC D19 A
2 1
2 BAV99
13 HSYNC A
3
*
3 4 R16 0 +/-5% 5V_HSYNC
GND Y
NC7SZ125
*R30
0
+/-5%
Dummy FOXCONN PCEG
Title
VGA Connector
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
GPIO[39:36,23:21,19,7:0]: default as inputs and should be

pulled up to Vcc3_3 if unused.
U12F GPIO[31:29,15:8]: default as inputs and should be pulled up to
VccSus3_3 if unused.
ICH7
double check unused GPIO
DMI_TXN0 V26 DMI0RXN USBP0N F1 USBP0N pins
13 DMI_TXN0 USBP0N 25
DMI_TXP0 V25 DMI0RXP USBP0P F2 USBP0P
13 DMI_TXP0 USBP0P 25
13 DMI_RXN0
DMI_RXN0 U28 DMI0TXN USBP1N G4 USBP1N
USBP1N 25
DMI_RXP0 DMI0TXP USBP1P USBP1P
13 DMI_RXP0 DMI_TXN1
U27
Y26 DMI1RXN USBP2N
G3
H1 USBP2N USBP1P 25 U12C
13 DMI_TXN1 USBP2N 25
DMI_TXP1 DMI1RXP USBP2P USBP2P
13 DMI_TXP1
DMI_RXN1
Y25
W28 DMI1TXN USBP3N
H2
J4 USBP3N USBP2P 25 ICH7 SIO PME change to GPIO8
D 13 DMI_RXN1 USBP3N 25 27 L_AD[3..0] D
DMI
DMI_RXP1 W27 DMI1TXP USBP3P J3 USBP3P
13 DMI_RXP1 DMI_TXN2 USBP4N USBP3P 25 ICH7_GPIO0
13 DMI_TXN2
AB26 DMI2RXN USBP4N K1
USBP4N 25
AA5 LDRQ1*/GPIO23 GPIO0/BM_BUSY* AB18
13 DMI_TXP2
DMI_TXP2 AB25 DMI2RXP USBP4P K2 USBP4P
USBP4P 25
L_AD0 AA6 LAD0 GPIO6 AC21 S1_LED 30
DMI_RXN2 AA28 DMI2TXN USBP5N L4 USBP5N L_AD1 AB5 LAD1 GPIO7 AC18 BOARD4
13 DMI_RXN2 USBP5N 24
LPC
DMI_RXP2 AA27 DMI2TXP USBP5P L5 USBP5P L_AD2 AC4 LAD2 GPIO8 E21 L_PMEJ
13 DMI_RXP2 USBP5P 24 L_PMEJ 27
13 DMI_TXN3
DMI_TXN3 AD25 DMI3RXN USBP6N M1 USBP6N
USBP6N 25
L_AD3 Y6 LAD3 GPIO9 E20 ICH_SPI_WPJ
DMI_TXP3 AD24 DMI3RXP USBP6P M2 USBP6P AC3 LDRQ0* GPIO10 A20 ICH7_GPIO10
13 DMI_TXP3 USBP6P 25 27 L_DRQ0J
DMI_RXN3 AC28 DMI3TXN USBP7N N4 USBP7N AB3 LFRAME* GPIO12 F19 ICH7_GPIO12
13 DMI_RXN3 DMI_RXP3 USBP7P USBP7N 24 27 L_FRAMEJ WOLJ
AC27 DMI3TXP USBP7P N3 GPIO13 E19
WOLJ 24
**
13 DMI_RXP3 USBP7P 24
USB
26 ICH_BCLK
ICH_BCLK R322 22 +/-5%
U1 ACZ_BCLK GPIO14 R4 ICH7_GPIO14
R319 33 +/-5%
R5 ACZ_RST* GPIO15 E22 ICH7_GPIO15
26 ICH_RSTJ
AUDIO
F26 PERN_1 OC0* D3
USB_OCJ_FRONT1 25
T2 ACZ_SDI_0 GPIO16/DPRSLPVR AC22
1D5V_GPIO16 10
F25 PERP_1 OC1* C4 T3 ACZ_SDI_1 GPIO18/STPPCI* AC20 BOARD1
E28 PETN_1 OC2* D5 T1 ACZ_SDI_2 GPIO20/STPCPU* AF21 BOARD2
**
26 ICH_SDIN2 ACZ_SDOUT
E27 PETP_1 OC3* D4
USB_OCJ_BACK1 25 26 ICH_SDOUT
R321 33+/-5% T4 ACZ_SDOUT GPIO24 R3
24 HSI_N2_LAN H26 PERN_2 OC4* E5
26 ICH_SYNC
R320 33+/-5% ACZ_SYNC R6 ACZ_SYNC GPIO25 D20
24 HSI_P2_LAN H25 PERP_2 OC5*/GPIO29 C3
7 CK_14M_ICH
AC1 CLK14 EL_RSVD/GPIO26 A21
24 HSO_N2_LAN
C307 0.1uF 16V, X7R, +/-10% G28 PETN_2 OC6*/GPIO30 A2 EL_STATE0/GPIO27 B21 1D8V_GPIO27 9
**
C306 0.1uF 16V, X7R, +/-10% G27 PETP_2 OC7*/GPIO31 B3 W1 EE_CS EL_STATE1/GPIO28 E23
EPROM
24 HSO_P2_LAN 1D8V_GPIO28 9
K26 PERN_3 W3 EE_DIN GPIO32/CLKRUN* AG18 BOARD3
K25 PERP_3 Y2 EE_DOUT GPIO33/AZ_DOCK_EN* AC19
CBLID_P 21
J28 PETN_3 USBRBIAS D1 USBRBIAS_ICH R315 22.6 +/-1% ICH_BCLK Y1 EE_SHCLK GPIO34/AZ_DOCK_RST* U2
1D5V_GPIO34 10
J27 PETP_3 USBRBIAS* D2 GPIO35 AD21
PCI-EXPRESS
M26 PERN_4 V3 LAN_CLK GPIO38 AD20 BOARD0
18 HSI_N4
M25 PERP_4 C319 U3 LAN_RSTSYNC GPIO39 AE20 ICH7_GPIO39
18 HSI_P4
C310 0.1uF 16V, X7R, +/-10% PETN_4 22pF R274 10K ICH_LAN_RSTJ C19 LAN_RST* CPUPWRGD_GPIO49
18 HSO_N4_SLOT L28
* AG24
**
CPU_PWRG 11
*
C311 0.1uF 16V, X7R, +/-10% L27 PETP_4 CLK48 B2 CK_48M_ICH 50V, NPO, +/-5% +/-5% U5 LAN_RXD0
18 HSO_P4_SLOT CK_48M_ICH 7
P26 PERN_5 V4 LAN_RXD1 THRM* AF20 ICH_THRM_UP
LAN
ICH_VRMPWRGD_UP ICH_THRM_UP 27
P25 PERP_5 T5 LAN_RXD2 VRMPWRGD AD22
MISC
DMI compensation: N28 PETN_5 USBRBIAS connection U7 LAN_TXD0 MCH_SYNC* AH20
ICH_SYNCJ 13
5 mils width, 7 mils spacing N27 PETP_5 5 mils width, length no longer than 500 mils V6 LAN_TXD1 PWRBTN* C23
PWRBTNJ 27
Place the resistor within 500 mils of ICH7 T25 PERN_6 Trace tied together close to pins. V7 LAN_TXD2 RI* A28 ICH_RIJ_PU
T24 PERP_6 SUS_STAT* A27 LPCPDJ
R28 PETN_6 ICH_RTCX1 AB1 RTCX1 SUSCLK C20 TP_SUSCLK VCCRTC
RTC
TP29
1D5V_PE_ICH R27 PETP_6 ICH_RTCX2 AB2 RTCX2 SYS_RST* A22
ICH_SYS_RSTJ 7,11,30
21,30 RTCRSTJ
RTCRSTJ AA3 RTCRST* PLTRST* C26 PLTRSTJ
*
DMI_COMP_ICH WAKEJ PLTRSTJ 13,27

R305 24.9 +/-1% C25 DMI_ZCOMP WAKE* F20
WAKEJ 18
C D25 DMI_IRCOMP 3D3V_DUAL S3_LED B23 SMBALERT*/GPIO11 INTRUDER* Y5 R323 C
30 S3_LED INTRUDERJ 30
7,16,18,23 SMB_CLK_MAIN RN27
C22 SMBCLK PWROK AA4
PWRGD_3V 13,27
390K
7 CK_PE_100M_N_ICH
CK_PE_100M_N_ICH AE28 DMI_CLKN B22 SMBDATA RSMRST* Y4 RSMRSTJ
RSMRSTJ 27
+/-5%
7,16,18,23 SMB_DATA_MAIN
CK_PE_100M_P_ICH AE27 DMI_CLKP 2 of 6 1* 2 A26 LINKALERT* INTVRMEN W4 INTVRMEN
SMB
7 CK_PE_100M_P_ICH
3 4 B25 SMLINK0 SPKR A19 SPKR
SPKR 30
1 5 6 A25 SMLINK1 check pull-up resistor
7 8 10K SLP_S3* B24
SLP_S3J 27
ICH_SPI_MOSI P5 SPI_MOSI SLP_S4* D23
SLP_S4J 7,9
ICH_SPI_MISO SPI_MISO SLP_S5*
SPI
P2 F22
ICH_SPI_CSJ
+/-5% P6 SPI_CS*
ICH_SPI_CLK R2 SPI_CLK TP0/BATLOW* C21 ICH_BATLOW_PU
SPI_ARB P1 SPI_ARB TP1/DPRSTP* AF24 TP_ICH7_AF24
TP33 TP36
TP2/DPSLP* AH25 TP_ICH7_AH25
TP37
TP3 TP_ICH7_F21
4 of 6 F21 TP30
ICH_RTCX2
1
ICH_RTCX1
3D3V_DUAL
3D3V_DUAL
R327 3D3V_DUAL R324
10M VCCRTC
+/-5% 4.7K *
*
R289
8.2K
+/-5% WOLJ
ICH7_GPIO12
RN24 1
*
3
2 10K +/-5%
4
+/-5% RSMRSTJ S3_LED 5 6
X2 ICH7_GPIO10 7 8
XTAL-32.768kHz C322 INTRUDERJ R326 1M +/-5%
ICH_RIJ_PU 1uF
*
*
10V, Y5V, +80%/-20% WAKEJ R208 1K+/-5%
* Dummy 3D3V_SYS
C355 C356 LPCPDJ R288 10K +/-5% Dummy
*
12pF 12pF
* 50V, NPO, +/-5% * 50V, NPO, +/-5%
B B
ICH7_GPIO39 R360 10K +/-5% L_PMEJ

*
RN25 1 2 10K +/-5%
*
3D3V_DUAL ICH7_GPIO15 3 4
RN34 ICH7_GPIO14 5 6
ICH_VRMPWRGD_UP *
1
3
2
4
ICH_BATLOW_PU 7 8
ICH_THRM_UP 5 6
ICH7_GPIO0 7 8
10K
+/-5%
2
4
6
8
3D3V_DUAL
RN29
SPI Interface
10K
R352 0 +/-5% ICH_VRMPWRGD_UP
+/-5% 7,8 VRM_PWRGD
Dummy
*
3D3V_DUAL
1
3
5
7
X2_1
ICH_SPI_CSJ
U13 *R238
3.3KOhm
+/-1% 3D3V_SYS
1 8
*
ICH_SPI_MISO R318 47 +/-5% 2 CS VCC 7 ICH_SPI_HOLDJ

**
ICH_SPI_WPJ DO HOLD R239 47+/-5% ICH_SPI_CLK

3 6
WP CLK R240 47+/-5% ICH_SPI_MOSI
4 5
Crystal Retainer GND DIO R355
*4.7K Dummy*R356 Dummy

4.7K *R348
4.7K *R346
4.7K *R347
4.7K
Socket +/-5% +/-5% +/-5%
This clip is for ICH7 +/-5% +/-5%
32.768Khz Crystal clip.
BOARD4
BOARD3
BOARD2
BOARD1
BOARD0
A A
U13_1
*R349
4.7K
+/-5%
*R357
Dummy
4.7K
+/-5%
*R358
Dummy
4.7K
+/-5%
1 8
CS VCC
2 DO 7
HOLD
3 6
WP CLK
4 GND DIO 5 FOXCONN PCEG
W25X40VAIZ Title
ICH7 -1
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
U12B 1
ICH7 SATA_TXP0 C432 10nF1 2 25V, X7R, +/-10% SATA_TXP0_C 2
** **
SATA_TXN0 C431 10nF1 2 25V, X7R, +/-10% SATA_TXN0_C 3 8
PIDE_D0 AB15 DD0 SATA0RXN AF3 SATA_RXN0 4 SATA_1 3D3V_SYS
PIDE_D1 AE14 DD1 SATA0RXP AE3 SATA_RXP0 SATA_RXN0 C428 10nF1 2 25V, X7R, +/-10% SATA_RXN0_C 5 9 CONN_SATA
PIDE_D2 AG13 DD2 SATA0TXN AG2 SATA_TXN0 SATA_RXP0 C425 10nF1 2 25V, X7R, +/-10% SATA_RXP0_C 6
PIDE_D3 AF13 DD3 SATA0TXP AH2 SATA_TXP0 7
D D
PIDE_D4 AD14 DD4 RSVD/SATA1RXN AE5 SATA_RXN1
PIDE_D5 AC13 DD5 RSVD/SATA1RXP AD5 SATA_RXP1 1
PIDE_D6 AD12 DD6 RSVD/SATA1TXN AG4 SATA_TXN1 SATA_TXP1 C418 10nF1 2 25V, X7R, +/-10% SATA_TXP1_C 2
** **
PIDE_D7 AC12 DD7 RSVD/SATA1TXP AH4 SATA_TXP1 SATA_TXN1 C409 10nF1 2 25V, X7R, +/-10% SATA_TXN1_C 3 8 SATA_2 R343
PIDE_D8 AE12 DD8 SATA2RXN AF7 SATA_RXN2 4 CONN_SATA R344 4.7K
*
SATA
PIDE_D9 AF12 DD9 SATA2RXP AE7 SATA_RXP2 SATA_RXN1 C405 10nF1 2 25V, X7R, +/-10% SATA_RXN1_C 5 9 8.2K +/-5%
PIDE_D10 AB13 DD10 SATA2TXN AG6 SATA_TXN2 SATA_RXP1 C404 10nF1 2 25V, X7R, +/-10% SATA_RXP1_C 6 +/-5%
PIDE_D11 AC14 DD11 SATA2TXP AH6 SATA_TXP2 7
PIDE_D12 AF14 DD12 IDE RSVD/SATA3RXN AD9 SATA_RXN3
PIDE_D13 AH13 DD13 RSVD/SATA3RXP AE9 SATA_RXP3
PIDE_D14 AH14 DD14 RSVD/SATA3TXN AG8 SATA_TXN3 PIDE1
PIDE_D15 AC15 DD15 RSVD/SATA3TXP AH8 SATA_TXP3 P_IDERSTJ 1 2
SATACLKN AF1 CK_SATA_100M_N_ICH PIDE_D7 3 4 PIDE_D8
CK_SATA_100M_N_ICH 7
PIDE_DAKJ AF16 DDACK* SATACLKP AE1 CK_SATA_100M_P_ICH PIDE_D6 5 6 PIDE_D9
CK_SATA_100M_P_ICH 7
PIDE_DREQ AE15 DDREQ PIDE_D5 7 8 PIDE_D10
R342
PIDE_IORJ AF15 DIOR* PIDE_D4 9 10 PIDE_D11
*
PIDE_IOWJ AH15 DIOW* SATARBIASN AH10 SATARBIAS_ICH +/-1% PIDE_D3 11 12 PIDE_D12
PIDE_RDY AG16 IORDY AG10 SATARBIAS connection PIDE_D2 13 14 PIDE_D13
SATARBIASP
AF18 SATA_LED 24.9 5 mils width, length no longer than 500 mils PIDE_D1 15 16 PIDE_D14
SATALED*
PIDE_A0 AH17 DA0 Trace tied together close to pins. PIDE_D0 17 18 PIDE_D15
PIDE_A1 AE17 DA1 GPIO21/SATA0GP AF19 R345 10K 19
3D3V_SYS X
*
PIDE_A2 AF17 DA2 GPIO19/SATA1GP AH18 +/-5% PIDE_DREQ 21 22
GPIO36/SATA2GP AH19 PIDE_IOWJ 23 24 Cable detection
PIDE_CS1J AE16 DCS1* GPIO37/SATA3GP AE19 PIDE_IORJ 25 26 high: 40-conductor cable(ATA 33)
PIDE_CS3J AD16 DCS3* PIDE_RDY 27 28 low: 80-conductor cable(ATA 66/100)
A20GATE AE22 A20GATE 27
PIDE_DAKJ 29 30
A20M* AH28 A20MJ 11
IRQ14 31 32
IRQ14 AH16 IDEIRQ CPUSLP* AG27 PIDE_A1 33 34
CBLID_P 20
IGNNE* AG22
IGNNEJ 11
1 PIDE_A0 35 36 PIDE_A2
INIT3_3V* AG21 SATA_TXP2 C429 10nF1 2 25V, X7R, +/-10% SATA_TXP2_C 2 PIDE_CS1J 37 38 PIDE_CS3J
** **
HOST
INIT* AF22 SATA_TXN2 C426 10nF1 2 25V, X7R, +/-10% SATA_TXN2_C 3 8 SATA_3 PIDE_LED 39 40
INITJ 11
INTR AF25
INTR 11
4 CONN_SATA
FERR* FERRJ SATA_RXN2 C420 10nF1 25V, X7R, +/-10% SATA_RXN2_C C370
NMI
AG26
AH24
FERRJ
NMI
11
11
SATA_RXP2 C410 10nF1
2
2 25V, X7R, +/-10% SATA_RXP2_C
5
6
9 Header_2X20_20
* 47nF *R359
10K
RCIN* AG23
KBRSTJ 27
7 16V, X7R, +/-10% +/-5%
SERIRQ AH21 HDD1 C0603
SERIRQ 27
SMI* AF23 SMIJ 11 1 Dummy
C STPCLK* AH22 SATA_TXP3 C430 10nF1 2 25V, X7R, +/-10% SATA_TXP3_C 2 C
STPCLKJ 11
** **
3 of 6 THERMTRIP* AF26 THERMTRIPJ
THERMTRIPJ 11
SATA_TXN3 C427 10nF1 2 25V, X7R, +/-10% SATA_TXN3_C 3 8 SATA_4
4 CONN_SATA
SATA_RXN3 C421 10nF1 2 25V, X7R, +/-10% SATA_RXN3_C 5 9
1 ? SATA_RXP3 C411 10nF1 2 25V, X7R, +/-10% SATA_RXP3_C 6
7 IDE data lines should be matched to strobes(IORJ, RDY)within +/- 250 mils,
strobes should be matched to their complement within +/- 10 mils
FSB_VTT
R351 62 THERMTRIPJ
R400
*
33 P_IDERSTJ
27 IDE_RSTJ +/-5%
R350 62 FERRJ
C436
1
placed near IDE connector 0.1uF
Place at ICH7 end of route * 16V, Y5V, +80%/-20%
Dummy
2
C350
1uF
* 10V, Y5V, +80%/-20%
B B
3D3V_SYS
R399 R398
* 10K * 10K
+/-5% +/-5%
PIDE_LED
3D3V_DUAL D44
2
VCCRTC 3
HDD_LEDJ 30
1
VBAT D26
1 width 20 mils SATA_LED
BAT54A
3
D27 C A LS4148-F 2
BAT54C *R190
20K
+/-1%
C214
BATT1
*R188
1K * 1uF
10V, Y5V, +80%/-20%
+/-5% RTCRSTJ
LITHIUM BATT
RTCRSTJ 20,30
CR2032
1
C225
*
+
A Battery BAT1 1uF A

+
10V, Y5V, +80%/-20%

+
2
Socket _
For battery cell.

Battery Holder
-
FOXCONN PCEG
Title
ICH7 -2
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
U12E
U12D
ICH7
U12A ICH7 1D5V_CORE
1D5V_CORE REF5V E4 VSS VSS A4
ICH7 AD[31..0]
AG11 VSS VSS A23
A1 VCC1_5_A C27 VSS VSS B1
AD[31..0] 23
AB10 VCC1_5_A V5REF AD17 R14 VSS VSS B8
1
PAR E10 PAR AD0 E18 AD0 AB17 VCC1_5_A V5REF G10 R15 VSS VSS B11
23 PAR
23 DEVSELJ
DEVSELJ A12 DEVSEL* AD1 C18 AD1 AB7 VCC1_5_A REF5V_SUS L29 R16 VSS VSS B14
7 CK_33M_ICH A9 PCICLK AD2 A16 AD2 AB8 VCC1_5_A V5REF_SUS F6 VCCRTC L0805 10uH R17 VSS VSS B17
* PCIRST*
R273 0 +/-5% B18 AD3 F18 AD3 AB9 VCC1_5_A R18 VSS VSS B20
2
23,27 PCIRSTJ
23 IRDYJ IRDYJ Dummy A7 IRDY* AD4 E16 AD4 AC10 VCC1_5_A VCCRTC W5 1D5V_CORE T6 VSS VSS B26
PMEJ B19 PME* AD5 A18 AD5 AC17 VCC1_5_A T12 VSS VSS B28
23
23
PMEJ
SERRJ SERRJ
STOPJ
B10
F15
SERR* PCI AD6
AD7
E17
A17
AD6
AD7
AC6
AC7
VCC1_5_A VCCUSBPLL C1 T13
T14
VSS VSS C2
C6
23 STOPJ STOP* VCC1_5_A VSS VSS
LOCKJ E11 PLOCK* AD8 A15 AD8 AC8 VCC1_5_A VCCSATAPLL AD2 VCCSATAPLL T15 VSS VSS D10
23 LOCKJ
23 TRDYJ TRDYJ F14 TRDY* AD9 C14 AD9 AD10 VCC1_5_A T16 VSS VSS D13
23 PERRJ PERRJ C9 PERR* AD10 E14 AD10 AD6 VCC1_5_A VCCDMIPLL AG28 VCCDMIPLL C346 C328 T17 VSS VSS D18
1
AD11 1D05V_ICH
23 FRAMEJ FRAMEJ F16 FRAME*
AD12
D14
B12
AD11
AD12
AE10
AE6
VCC1_5_A
VCC1_5_A VCC1_05 L11
*10uF
* 0.1uF
10V, Y5V, +80%/-20%16V, X7R, +/-10% U12
U4 VSS
VSS
VSS
VSS
D21
D24
D GNT0J AD13 D
E7 GNT0* AD13 C13 AF10 VCC1_5_A VCC1_05 L12 U13 VSS VSS E1
2
23 GNT1J D16 GNT1* AD14 G15 AD14 AF5 VCC1_5_A VCC1_05 L14 U14 VSS VSS E2
23 GNT2J D17 GNT2* AD15 G13 AD15 AF6 VCC1_5_A VCC1_05 L16 U15 VSS VSS E8
F13 GNT3* AD16 E12 AD16 AF9 VCC1_5_A VCC1_05 L17 U16 VSS VSS E15
GNT4J A14 GNT4*/GPIO48 AD17 C11 AD17 AG5 VCC1_5_A VCC1_05 L18 U17 VSS VSS F3
GNT5J D8 GNT5*/GPIO17 AD18 D11 AD18 AG9 VCC1_5_A VCC1_05 M11 U24 VSS VSS F4
AD19 A11 AD19 AH5 VCC1_5_A VCC1_05 M18 U25 VSS VSS F5
23 PREQ0J D7 REQ0* AD20 A10 AD20 AH9 VCC1_5_A VCC1_05 P11 U26 VSS VSS F12
23 PREQ1J C16 REQ1* AD21 F11 AD21 F17 VCC1_5_A VCC1_05 P18 V2 VSS VSS F27
23 PREQ2J C17 REQ2* AD22 F10 AD22 G17 VCC1_5_A VCC1_05 T11 V13 VSS VSS F28
23 PREQ3J E13 REQ3* AD23 E9 AD23 H6 VCC1_5_A VCC1_05 T18 1D5V_CORE V15 VSS VSS G1
23 PREQ4J A13 REQ4*/GPIO22 AD24 D9 AD24 H7 VCC1_5_A VCC1_05 U11 V24 VSS VSS G5
C8 GPIO1/REQ5* AD25 B9 AD25 J6 VCC1_5_A VCC1_05 U18 V27 VSS VSS G2
23 PREQ5J
AD26 A8 AD26 J7 VCC1_5_A VCC1_05 V11 V28 VSS VSS G6
23 INTAJ A3 PIRQA* AD27 A6 AD27 1D5V_PE_ICH T7 VCC1_5_A VCC1_05 V12 W6 VSS VSS G9
23 INTBJ B4 PIRQB* AD28 C7 AD28 VCC1_05 V14 W24 VSS VSS G14
23 INTCJ C5 PIRQC* AD29 B6 AD29 D26 VCC1_5_B VCC1_05 V16 C358 C357 W25 VSS VSS G18
1
AD30 AD30
23
23
INTDJ
INTEJ
B5
G8
PIRQD*
GPIO2/PIRQE* AD31
E6
D6 AD31
D27
D28
VCC1_5_B
VCC1_5_B
VCC1_05
VCC1_05
V17
V18 * 0.1uF
* 0.1uF
16V, Y5V, +80%/-20%
W26
16V, Y5V, +80%/-20%
Y3
VSS
VSS
VSS
VSS
G21
G24
23 INTFJ F7 GPIO3/PIRQF* E24 VCC1_5_B Dummy Dummy Y24 VSS VSS G25
2
F8 GPIO4/PIRQG* C/BE0* B15 CBEJ0 E25 VCC1_5_B FSB_VTT Y27 VSS VSS G26
23 INTGJ CBEJ0 23
23 INTHJ G7 GPIO5/PIRQH* C/BE1* C12 CBEJ1 E26 VCC1_5_B V_CPU_IO AE23 Y28 VSS VSS H3
CBEJ2 CBEJ1 23
C/BE2* D12 F23 VCC1_5_B V_CPU_IO AE26 AA1 VSS VSS H4
POWER
1 of 6 C/BE3* C15 CBEJ3 CBEJ2
CBEJ3
23
23
F24 VCC1_5_B V_CPU_IO AH26 3D3V_SYS AA24 VSS VSS H5
3D3V_SYS G22 VCC1_5_B AA25 H24
VSS VSS
G23 VCC1_5_B VCC3_3 A5 AA26 VSS VSS H27
1 H22 VCC1_5_B VCC3_3 AA7 close AD2, C1 AB4 VSS VSS H28
H23 VCC1_5_B VCC3_3 AB12 AB6 VSS VSS J1
GNT5J GNT4J BOOT J22 VCC1_5_B VCC3_3 AB20 AB11 VSS VSS J2
*
* *
0 1 SPI GNT5J R269 2.2K +/-5% GNT4J R272 8.2K+/-5% J23 VCC1_5_B VCC3_3 AC16 AB14 VSS VSS J5
1 0 PCI Dummy K22 VCC1_5_B VCC3_3 AD13 AB16 VSS VSS J24
1 1 LPC K23 VCC1_5_B VCC3_3 AD18 AB19 VSS VSS J25
GNT0J R268 8.2K+/-5% L22 VCC1_5_B VCC3_3 AG12 AB21 VSS VSS J26
L23 VCC1_5_B VCC3_3 AG15 AB24 VSS VSS K24
M22 VCC1_5_B VCC3_3 AG19 AB27 VSS VSS K27
M23 VCC1_5_B VCC3_3 AH11 AB28 VSS VSS K28
N22 VCC1_5_B VCC3_3 B13 AC2 VSS VSS L13
N23 VCC1_5_B VCC3_3 B16 AC5 VSS VSS L15
P22 VCC1_5_B VCC3_3 B27 AC9 VSS VSS L24
1D05V_ICH 1D5V_CORE P23 B7 AC11 L25
VCC1_5_B VCC3_3 VSS VSS
R22 VCC1_5_B VCC3_3 C10 AD1 VSS VSS L26
R23 VCC1_5_B VCC3_3 D15 AD3 VSS VSS M3
R24 VCC1_5_B VCC3_3 F9 AD4 VSS VSS M4
1D5V_CORE R25 VCC1_5_B VCC3_3 G11 AD7 VSS VSS M5
C400 C366 C304 C299 R26 VCC1_5_B VCC3_3 G12 AD8 VSS VSS M12
VCCDMIPLL LRC Filter
1
* 0.1uF
* 10nF
25V, X7R, +/-10% * 0.1uF
* 0.1uF
16V, Y5V, +80%/-20%
T22
T23
VCC1_5_B
VCC1_5_B
VCC3_3
VCC3_3
G16
U6 3D3V_DUAL
AD11
AD15
VSS
VSS
VSS
VSS
M13
M14
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% T26 VCC1_5_B VCCSUS3_3 A24 AD19 VSS VSS M15
2
Dummy Dummy T27 VCC1_5_B VCCSUS3_3 C24 AD23 VSS VSS M16
*
L28 VCCDMIPLL T28 VCC1_5_B VCCSUS3_3 D19 AE2 VSS VSS M17
C +/-10% L1206 1uH U22 D22 AE4 M24 C
VCC1_5_B VCCSUS3_3 VSS VSS
C348 C343 U23 VCC1_5_B VCCSUS3_3 E3 AE8 VSS VSS M27
Rated at least 100mA
* 10uF
* 0.1uF
6.3V, X5R, +/-10%
16V, X7R, +/-10%
V22
V23
VCC1_5_B
VCC1_5_B
VCCSUS3_3
VCCSUS3_3
G19
K3
AE11
AE13
VSS
VSS
VSS
VSS
M28
N1
W22 VCC1_5_B VCCSUS3_3 K4 AE18 VSS VSS N2
W23 VCC1_5_B VCCSUS3_3 K5 AE21 VSS VSS N5
ICH7 Core decoupling caps. Y22 VCC1_5_B VCCSUS3_3 K6 AE24 VSS VSS N6
Y23 VCC1_5_B VCCSUS3_3 L1 AE25 VSS VSS N11
AA22 VCC1_5_B VCCSUS3_3 L2 AF2 VSS VSS N12
Place LRC near pin AG28 AA23 VCC1_5_B VCCSUS3_3 L3 AF4 VSS VSS N13
AB22 VCC1_5_B VCCSUS3_3 L6 AF8 VSS VSS N14
AB23 VCC1_5_B VCCSUS3_3 L7 AF11 VSS VSS N15
AC23 VCC1_5_B VCCSUS3_3 M6 AF27 VSS VSS N16
AC24 VCC1_5_B VCCSUS3_3 M7 AF28 VSS VSS N17
1D5V_PE_ICH 3D3V_SYS AC25 VCC1_5_B VCCSUS3_3 N7 AG1 VSS VSS N18
AC26 VCC1_5_B VCCSUS3_3 P7 AG3 VSS VSS N24
1D5V_CORE AD26 VCC1_5_B VCCSUS3_3 R7 AG7 VSS VSS N25
AD27 VCC1_5_B VCCSUS3_3 V1 AG14 VSS VSS N26
C327 C296 C314 C287 AD28 VCC1_5_B VCCSUS3_3 V5 AG17 VSS VSS P12
VCC1_5_B LC Filter
* 0.1uF
* 0.1uF
*0.1uF 0.1uF
* VCCSUS3_3 W2 AG20 VSS VSS P13
*
16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20% L26 VCCSUS3_3 W7 AG25 VSS VSS P14
16V, Y5V, +80%/-20% L1206 0.47uH AH1 VSS VSS P15
VCCSUS1_05 AA2 TP_ICH7_AA2 AH3 VSS VSS P3
TP_ICH7_C28 TP35
VCCSUS1_05 C28 TP28 VSS P4
FB15 2 1FB L0603 47 Ohm 1D5V_PE_ICH VCCSUS1_05 G20 TP_ICH7_G20 VSS P16
TP_ICH7_K7 TP31
+/-25% VCCSUS1_05 K7 AH7 VSS VSS P17
TP32
Dummy EC45 C295 VCCSUS1_05 Y7 TP_ICH7_Y7 AH23 VSS VSS P24
* 5 of 6 TP34
Place near B27
470uF
16V, +/-20% * 0.1uF
16V, X7R, +/-10%
AH27 VSS VSS
VSS
P27
P28
Place near AD28, T28, D28 AH12 VSS VSS R1
PCI-E decoupling caps. 1 ? VSS R11
VSS R12
VSS R13
6 of 6
co-layout with inductor Place LC near pin D28
Rated at least 1A,
ESR max. 20 mohm
VCCDMIPLL
C342
1
* 10nF
25V, X7R, +/-10%
2
3D3V_SYS FSB_VTT FSB_VTT FSB_VTT

Place near AG28
B 1D5V_CORE 1D5V_CORE B
DMI decoupling caps. 5V_SB_SYS 3D3V_DUAL

C305 C360 C277 C363 C349 C364
1
* 0.1uF
Dummy
16V, Y5V, +80%/-20% * 1uF
10V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
Dummy * 0.1uF
16V, Y5V, +80%/-20% * 4.7uF
16V, Y5V, +80%/-20%
A
2
R297 D34
10 LS4148-F
REF5V_SUS
Place near AH5 Place near AH9 Place near U6
C
+/-5%
1D5V_CORE 1D5V_CORE
REF5V_SUS
C293
C298
* 0.1uF
Audio decoupling caps. Place near AE23, AE26 Place near AH26
1
C294
* 10nF 16V, X7R, +/-10%
3D3V_SYS
* 0.1uF
16V, Y5V, +80%/-20%
25V, X7R, +/-10%
place cap. near pin F6
VCCSATAPLL
2
within 40 mils CPU decoupling caps.

3D3V_SYS
V5REF_SUS / 3D3V_SB Power Sequencing
C279 C341
Place near A1 Place near C1 * 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
3D3V_DUAL C280
double check in new CRB or DG * 0.1uF

16V, Y5V, +80%/-20%
Place near AH11 Place near AD2 VCCRTC
Place near AG15, AB12

C308 C309 C300 5V_SYS 3D3V_SYS C323
1
* 0.1uF
Dummy *
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
* 10nF
SATA decoupling caps. * 1uF
10V, Y5V, +80%/-20%
A
25V, X7R, +/-10%

IDE decoupling caps.
2
Place near E3
*R354
1K
D41
LS4148-F
+/-1%
C
Place near L1 Place near K3 3D3V_SYS
REF5V 3D3V_DUAL
REF5V
Place near W5
C362
USB decoupling caps. * 0.1uF
16V, X7R, +/-10%
A A
place cap. near pin AD17 C361 C292 C278 C359 C320 RTC decoupling caps.
within 40 mils * 0.1uF
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
V5REF / 3D3V_SYS Power Sequencing

U12_1 8 CLIP2S1
8D 7
1
7 1
Place near V1
2
2
Clip_2P Place near A5, B7, B13, B16
LAN decoupling caps.
CLIP4S1
PCI decoupling caps.
3 1
4 B
3
4
1 FOXCONN PCEG
2
2 Title
Heatsink
Clip_2P ICH7-3
Custom 945M09 1.0

5 4 3 2 1

5 4 3 2 1
5V_SYS
3D3V_SYS 3D3V_SYS 5V_SYS

PCI-2
-12V_SYS 5V_SYS place this slot near board edge 12V_SYS 3D3V_SYS 3D3V_SYS
-12V_SYS 5V_SYS PCI-1 12V_SYS

Note: 20-24 mils place this slot near PCI-E x1 Slot
PCI2 Slot,PCI CONN
B1 A1
-12V TRST# PCI1 Slot,PCI CONN
B2 A2
TCK +12V
D B3 A3 B1 A1 D
GND1 TMS -12V TRST#
B4 A4 B2 A2
B5 TDO TDI A5 B3 TCK +12V A3
+5V1 +5V2 INTBJ GND1 TMS
B6 A6 B4 A4
INTCJ +5V3 INTA# INTDJ TDO TDI
B7 A7 B5 A5
INTAJ B8 INTB# INTC# A8 B6 +5V1 +5V2 A6 INTGJ
INTD# +5V4 3D3V_DUAL INTFJ +5V3 INTA# INTEJ
B9 A9 B7 A7
PRSNT1# RSV1 INTHJ INTB# INTC#
B10 A10 B8 A8
B11 RSV2 +5V5 A11 B9 INTD# +5V4 A9
PRSNT2# RSV3 PRSNT1# RSV1
B12 A12 B10 A10
GND2 GND3 RSV2 +5V5 3D3V_DUAL
B13 A13 B11 A11
GND4 GND5 PRSNT2# RSV3
B14 A14 B12 A12
B15 RSV4 SB3V A15 B13 GND2 GND3 A13
GND6 RESET# PCIRSTJ 22,27 GND4 GND5
7 CK_33M_PCI1 B16 A16 B14 A14
CLK +5V6 RSV4 SB3V
B17 A17 GNT2J 22 B15 A15 PCIRSTJ 22,27
PREQ2J B18 GND7 GNT# A18 B16 GND6 RESET# A16
REQ# GND8 7 CK_33M_PCI2 CLK +5V6
B19 A19 PMEJ 22 B17 A17 GNT1J 22
AD31 B20 +5V7 PCI_PME# A20 AD30 PREQ1J B18 GND7 GNT# A18
AD29 AD(31) AD(30) REQ# GND8 PMEJ
B21 A21 B19 A19
AD(29) +3.3V1 AD28 AD31 +5V7 PCI_PME# AD30
B22 A22 B20 A20
AD27 GND9 AD(28) AD26 AD29 AD(31) AD(30)
B23 A23 B21 A21
AD25 AD(27) AD(26) AD(29) +3.3V1 AD28
B24 A24 R144 B22 A22
AD(25) GND10 AD24 AD27 GND9 AD(28) AD26
B25 A25 B23 A23
*
CBEJ3 +3.3V2 AD(24) IDSEL1 IDSEL1 AD18 AD25 AD(27) AD(26)
22 CBEJ3 B26 A26 B24 A24 R132
AD23 C/BE#(3) IDSEL AD(25) GND10 AD24
B27 A27 B25 A25
*
AD(23) +3.3V3 AD22 CBEJ3 +3.3V2 AD(24) IDSEL2 IDSEL2 AD17
B28 A28 B26 A26
AD21 GND11 AD(22) AD20 330 AD23 C/BE#(3) IDSEL
B29 A29 B27 A27
AD19 AD(21) AD(20) +/-5% AD(23) +3.3V3 AD22
B30 A30 B28 A28
B31 AD(19) GND12 A31 AD18 AD21 B29 GND11 AD(22) A29 AD20 330
AD17 +3.3V4 AD(18) AD16 AD19 AD(21) AD(20) +/-5%
B32 A32 B30 A30
AD(17) AD(16) AD(19) GND12 AD18
B33 A33 B31 A31
B34 C/BE#(2) +3.3V5 A34 FRAMEJ AD17 B32 +3.3V4 AD(18) A32 AD16
22 CBEJ2 GND13 FRAME# FRAMEJ 22 AD(17) AD(16)
IRDYJ B35 A35 CBEJ2 B33 A33
22 IRDYJ IRDY# GND14 C/BE#(2) +3.3V5
B36 A36 TRDYJ B34 A34 FRAMEJ
+3.3V6 TRDY# TRDYJ 22 GND13 FRAME#
DEVSELJ B37 A37 IRDYJ B35 A35
22 DEVSELJ DEVSEL# GND15 IRDY# GND14
B38 A38 STOPJ B36 A36 TRDYJ
GND16 STOP# STOPJ 22 +3.3V6 TRDY#
LOCKJ B39 A39 DEVSELJ B37 A37
22 LOCKJ LOCK# +3.3V7 DEVSEL# GND15
PERRJ B40 A40 PSCLK B38 A38 STOPJ
C 22 PERRJ
B41 PERR# SDONE A41 PSDATA LOCKJ B39 GND16 STOP# A39 C
SERRJ +3.3V8 SBO# PERRJ LOCK# +3.3V7 PSCLK
B42 A42 B40 A40
22 SERRJ SERR# GND17 PERR# SDONE
B43 A43 PAR B41 A41 PSDATA
+3.3V9 PAR PAR 22 +3.3V8 SBO#
CBEJ1 B44 A44 AD15 SERRJ B42 A42
22 CBEJ1 AD14 C/BE#(1) AD(15) SERR# GND17 PAR
B45 A45 B43 A43
AD(14) +3.3V10 AD13 CBEJ1 +3.3V9 PAR AD15
B46 A46 B44 A44
AD12 GND18 AD(13) AD11 AD14 C/BE#(1) AD(15)
B47 A47 B45 A45
AD10 AD(12) AD(11) AD(14) +3.3V10 AD13
B48 A48 B46 A46
AD(10) GND19 AD9 AD12 GND18 AD(13) AD11
B49 A49 B47 A47
GND20 AD(9) AD10 AD(12) AD(11)
B48 A48
AD(10) GND19 AD9
B49 A49
AD8 B52 A52 CBEJ0 GND20 AD(9)
AD(8) C/BE#(0) CBEJ0 22
AD7 B53 A53
B54 AD(7) +3.3V11 A54 AD6 AD8 B52 A52 CBEJ0
AD5 +3.3V12 AD(6) AD4 AD7 AD(8) C/BE#(0)
B55 A55 B53 A53
AD3 AD(5) AD(4) AD(7) +3.3V11 AD6
B56 A56 B54 A54
B57 AD(3) GND21 A57 AD2 AD5 B55 +3.3V12 AD(6) A55 AD4
AD1 GND22 AD(2) AD0 AD3 AD(5) AD(4)
B58 A58 B56 A56
AD(1) AD(0) AD(3) GND21 AD2
B59 A59 B57 A57
ACK64J B60 +5V8 +5V9 A60 REQ64_1J AD1 B58 GND22 AD(2) A58 AD0
ACK64# REQ64# AD(1) AD(0)
B61 A61 B59 A59
B62 +5V10 +5V11 A62 ACK64J B60 +5V8 +5V9 A60 REQ64_2J
+5V12 +5V13 ACK64# REQ64#
B61 A61
B62 +5V10 +5V11 A62
+5V12 +5V13
AD[31..0]
AD[31..0] 22
-12V_SYS 5V_SYS 12V_SYS

3D3V_SYS
-12V_SYS 5V_SYS
PSCLK 3D3V_SYS
SMB_CLK_MAIN 7,16,18,20
B B
C89 C95 C93 C132
* 0.1uF
25V, X7R, +/-10% *
EC23
1000uF * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
25V, X7R, +/-10% * 0.1uF
Dummy
16V, Y5V, +80%/-20%
Dummy PSDATA C88 C98 C96 C120
SMB_DATA_MAIN 7,16,18,20
6.3V, +/-20% Dummy 0.1uF 0.1uF 0.1uF 0.1uF
Dummy
* EC18 * 25V, X7R, +/-10% * *
Dummy
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
100uF
CE20D50H110
16V, +/-20%
5V_SYS
3D3V_SYS
RN23
*
1
3
2 RN14
4 8.2K
INTAJ
INTCJ
INTAJ
INTCJ
22
22
REQ64_2J
8 7
5 6 +/-5% INTBJ
INTBJ 22
REQ64_1J
7 8 INTDJ 6 5 ACK64J
INTDJ 22 4 3 *
2 1
2.7K
+/-5%
*
1
3
2 RN15
4 8.2K
INTGJ
INTEJ
INTGJ
INTEJ
22
22
5 6 +/-5% INTHJ
INTHJ 22
7 8 INTFJ
INTFJ 22
3D3V_SYS
*
1
3
2 RN17
4 8.2K
PREQ2J
PREQ0J
22
22 *
1 2 RN21 STOPJ
A 5 6 +/-5% PREQ1J 22 3 4 8.2K LOCKJ A
7 8 5 6 +/-5% PERRJ
PREQ5J 22
7 8 SERRJ
**
8.2K R271
PREQ4J 22
+/-5% R270
PREQ3J 22
+/-5%
8.2K
*
1 2 RN20 FRAMEJ FOXCONN PCEG
3 4 8.2K IRDYJ
5 6 +/-5% TRDYJ Title
7 8 DEVSELJ PCI Slots 1, 2
C
945M09 1.0

5 4 3 2 1

5 4 3 2 1
VDD33
3D3V_DUAL
E
*R11
0
B Q1
BCP69T1G
@8111C/8111B +/-5% U21 @8111B U22 @8101E U23 @8111C @8111B 3D3V_DUAL R60 +/-5% VDD33
* *
R401 2.49K+/-1% @8111C
C
4
0
*
C11 C21 CTRL18 L1 4.7uH AVDDL
1
R402 2KOhm 1uF 0.1uF C71 C70 C26
* *
1
@8101E +/-1% Dummy @8111B C49 C51 0.1uF
@8111C
* * *
1
RTL8101E-GR RTL8111C-GR * 0.1uF
* 0.1uF
2
RTL8111B-VC-GR R23 +/-5% C65 C4 10uF 10uF 16V, Y5V, +80%/-20%
*
2
2KOhm R24 @8101E 16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20% 10V, Y5V, +80%/-20%
* *
VDD33
AVDDH
2
XTAL2
XTAL1
DVDD
+/-1% 0 10V, Y5V, +80%/-20%
DVDD
DVDD
LED0
LED1
LED2
LED3
D D
#R401#R402 AVDDL R67 +/-5% 10uF 10uF
CTRL15
AVDDL
2
@8111C 10V, Y5V, +80%/-20%
RSET
0 10V, Y5V, +80%/-20%
VDD33
U4 AVDDH R27 +/-5%

65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDDH VDD33
E
RSET B Q3 C23 0
VDD15E
VDD33D
VDD15D
65
VCTRL15
NC22
CKTAL2
CKTAL1
NC21
LED0
LED1
LED2
LED3
NC20
NC19
NC18
1
BCP69T1G 0.1uF
@8111B *
CTRL18 1 48 EESK 16V, Y5V, +80%/-20%
C
4
2
AVDDH 2 VCTRL18 EESK 47 EEDI/AUX CTRL15 R49 +/-5%
AVDD33 EEDI/AUX DVDD
MDI0+ 3 46 VDD33 @8101E
MDI0- MDIP0 VDD33C EEDO 0 C24 C79 C42 C27 C55
4 45
1
AVDDL MDIN0 EEDO EECS 3D3V_SYS C50 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
5
AVDD18A EECS
44
* * * * *
1
MDI1+
RTL8101E DVDD
MDI1-
6
7 MDIP1 VDD15C
43
42 *C10 *C52 * 0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
2
AVDDL MDIN1 NC17 DVDD R58 10uF 10uF 16V, Y5V, +80%/-20% AVDDL R64 0 +/-5%
8 41
* AVDDL EVDD18
2
MDI2+ AVDD18B NC16 1K 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20%
9 40
MDI2- NC1 NC15 +/-1% @8101E @8101E/8111B #R403#FB16
10 39
AVDDL NC2 NC14 DVDD C74 C75
11 38
1
MDI3+ NC3 NC13 VDD33 R55 0.1uF 0.1uF
MDI3-
12
13
NC4
NC5
VDD33B
ISOLATEB
37
36 1 2 R403 0 +/-5% * *
AVDDL 14 35 15K +/-1% @8101E/8111B 16V, Y5V, 16V,
+80%/-20%
Y5V, +80%/-20%
2
DVDD NC6 NC12
15 34
LANWAKEB
C13
REFCLK_N
VDD15A NC11
REFCLK_P
VDD33 16 33 R57 0 DVDD

EVDD18A
EVDD18B
VDD33A NC10
PERSTB
VDD15B
*
XTAL1
EGNDA
EGNDB
+/-5% FB16 FB 100 Ohm +/-25%
*
HSON
HSOP
@8101E/8111B
HSIN
HSIP
NC7
NC8
NC9
1
R7 +/-5% CTRL15
33pF 3D3V_DUAL
X6 @8111C C20 @8111C
1
50V, NPO, +/-5% 0 0.1uF
XTAL-25MHz
*
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
#U21#U22#23 +/-30PPM C17 C2
* *
2
C12
16V, Y5V, +80%/-20%
2
XTAL2 10uF 10uF @8111C EGND R66 +/-5%
EVDD18
EVDD18
2
DVDD
EGND
10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20%

DVDD
@8111C @8111C 0
33pF
C 50V, NPO, +/-5% C
@8111C/8111B
20 WOLJ NIC_USB2
C77 1 2 0.1uF NIC_USB1 @8101E
HSI_N2_LAN 20
**
16V, X7R, +/-10%

27 LAN_RSTJ
C76 1 2 0.1uF 1:1 TX TX+ 1
HSI_P2_LAN 20
EGND
16V, X7R, +/-10% 4

75 75
20 HSO_P2_LAN CK_PE_100M_N_LAN 7
GRN_LED
YLW_LED
5
USB-2
USB-1
TX- 2
20 HSO_N2_LAN CK_PE_100M_P_LAN 7
RX RX+ 3
7
75 75
AVDDL 8
RJ45-MJ2
RX- 6
0.1 uF
*
VDD33 1000pF 2KV
FB8
U5 FB 120 Ohm
EECS 1 8 C56 @8101E Link Led
1
EESK CS VCC 0.1uF Green

EEDI/AUX
2
3
SK
DI
NC
ORG
7
6 * 250
GRN_LED
EEDO 4 5 16V, Y5V, +80%/-20%
2
DO GND
C66 C78 Link Led
1
R32AT93C46DN-SH-T 0.1uF 1nF YELLOW
* *
*
0 VDD33 50V, X7R, +/-10% 250

+/-5% 16V, Y5V, +80%/-20% @8101E
2
dummy @8101E
CONN-USBx2_RJ45
CONN-USBx2_RJ45
C69
0.1uF 16V, Y5V, +80%/-20%
1 2
*
+/-1% 3D3V_DUAL 3D3V_DUAL USE CONNECTOR(Foxconn P/N: JFM24U13-21U5W) WITH 10/100 DESIGN
B B
EEDI/AUX R33 3.6K 3D3V_DUAL
3D3V_DUAL
R61
* *R62
*
LED3 R69 0 +/-5% 330 330

+/-5% +/-5% 5V_USB2 5V_USB2
@8111C/8111B @8111C/8111B
NIC_USB #NIC_USB1#NIC_USB2
D16 D9
2
LED1 D21 C A LS4148-F BAV99 BAV99
27 USBPWR_BACK
22 28 3 3
GRN_LED
YLW_LED
21 29 L11
LED2
USB-2
USB-1
D22 C A LS4148-F C73 30 1 Dummy 2
470pF
* Right Side
1
@8101E 50V, X7R, +/-10% 4 3
9 1
MDI1+
MDI0+
MDI0+ 10 5 Common Choke 90 Ohm_2L

MDI1-
MDI0-
MDI0- 11
** **
RJ45-MJ2
MDI1+ 12 2 R56 0 +/-5%
MDI1- R50 0 +/-5% USBP5N 20
13 6
MDI2+ USBP7N 20
14
R41 * R42 * R34 * R35 * MDI2-
MDI3+
15 3 R54 0 +/-5%
USBP5P 20
49.9 49.9 49.9 49.9 AVDDL 16 7 R48 0 +/-5%
+/-1% +/-1% +/-1% +/-1% MDI3- L10 USBP7P 20
17
*
@8101E @8101E @8101E @8101E R68 0 +/-5% 18 4 1 Dummy 2

8 5V_USB2 5V_USB2
dummy C72 4 3
1
GRN_LED
C44 C34 R65 0.1uF

* Left Side
1
0.1uF 0.1uF
* Common Choke 90 Ohm_2L D8 D17
* * 0 20 23
2
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, Y5V, +80%/-20% 19 24 BAV99 BAV99
+/-5%
2
@8101E @8101E dummy 25

2
26 3 3
C67 EC15
1
3D3V_DUAL * 0.1uF
* 470uF
16V, +/-20%
1
CONN-USBX2_RJ45 16V, Y5V, +80%/-20%
*R63 2
A Dummy A
330 LED caps. should be placed
+/-5%
next to connector
LED0
C68 Green Active Left side
470pF
* 50V, X7R, +/-10% Yellow Link Right side FOXCONN PCEG
Title
PCIE LAN
C
945M09 1.0
Date: Tuesday, August 21, 2007 Sheet 24 of 32

5 4 3 2 1

5 4 3 2 1
USB Front Header 1 5V_SB_SYS 5V_SYS

USB Front Header 2
5V_USB1
5V_USB1 USBPWR1
1
1
2
2
3
3
USBPWR_FRONT
Header_1X3
F4
Fuse 2.6A USBPWR1(1-2)
D D
*
USBPWR_FRONT USBPWR_FRONT EC44 C312
C261 Jumper * 470uF 0.1uF
*
*
EC50 0.1uF R235 10K +/-5% 16V, +/-20%
* 470uF * 1
USB_OCJ_FRONT1 20
Dummy
16V, +/-20% R233 C254
15K 0.1uF FOR EMI ISSUE
FOR EMI ISSUE +/-1% * 16V, Y5V, +80%/-20%
2
5V_USB1 D31 5V_USB1 D32

BAV99 BAV99
2 1 2 1
F_USB1 F_USB2
3
1 2 1 2
**
**
**
**
R204 0 +/-5% 3 4 R215 0 +/-5% R309 0 +/-5% 3 4 R317 0 +/-5%
20 USBP0N R203 0 +/-5% R214 0 +/-5% USBP2N 20 20 USBP4N R308 0 +/-5% R316 0 +/-5% USBP6N 20
5 6 5 6
20 USBP0P USBP2P 20 20 USBP4P USBP6P 20
7 8 7 8
L22 10 L23 10 L27
X X
1 Dummy 2 1 Dummy 2 5V_USB1 5V_USB1 L25 1 Dummy 2 5V_USB1 5V_USB1
3
5V_USB1 1 Dummy 2
Header_2X5_K9 Header_2X5_K9
3
4 3 4 3 1 2 1 2 4 3 1 2 1 2
1 2 4 3
5V_USB1 Common Choke 90 Ohm_2L Common Choke 90 Ohm_2L Common Choke 90 Ohm_2L
3
D30 D33 Common Choke 90 Ohm_2L D37 D35

D29 USB Front Header II BAV99 BAV99 BAV99 BAV99
1 2
BAV99
D28
BAV99
C C
Rear Dual USB Connector 5V_SYS

EMI
5V_USB2 5V_SYS
5V_SB_SYS
USBPWR2 C301 C414 C262 C291
1
0.1uF 0.1uF 0.1uF 0.1uF
1
2 1
2 5V_USB2 * * * *
3 Dummy
2
3 16V, Y5V, +80%/-20%
Header_1X3 16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
USBPWR2(1-2) F3
Fuse 2.6A
*
Jumper USBPWR_BACK R10 10K +/-5%

USBPWR_BACK USB_OCJ_BACK1 20
1
C1 EC16 R12 C9
1
* 0.1uF * 470uF 15K

*
+/-1%
0.1uF
16V, Y5V, +80%/-20%
5V_SYS
2
16V, +/-20% 2
B B
L9 Dummy C227
12
9
CONN-USBx2 0.1uF
1 2
* 16V, Y5V, +80%/-20%
4 3
2
1
Common Choke 90 Ohm_2L
**
BOTTOM
R37 0 +/-5% 2
20 USBP1N R36 0 +/-5%
20 USBP1P
3
5V_USB2 5V_USB2
3
4
1 2 1 2 EMI 030907
D14 D7
5
TOP
BAV99 BAV99
6
**
R25 0 +/-5%
20 USBP3N
R26 0 +/-5% 7
20 USBP3P
L5 Dummy 8
1 2
5V_USB2
3
4 3
1 2 USB
10
11
Common Choke 90 Ohm_2L

5V_USB2
3
D3
BAV99 1 2
D6
BAV99
A A
FOXCONN PCEG
Title
USB
945M09 1.0

5 4 3 2 1

5 4 3 2 1
3D3V_SYS 5V_AUDIO Rear AUDIO

ALC662
25
38
1
9
U2
DVdd1
DVdd2
AVdd1
AVdd2
3
AUD_PRESENCE_L GPIO1
2
GPIO0
AUD_RST# 11
ALC662 35 FRONT-L
20 ICH_RSTJ RESET# FRONT_L
AUDIO_BCLK 6 36 FRONT-R
20 ICH_BCLK BCLK FRONT_R CMIC1-VREFO-L
20 ICH_SYNC 10 37
*
R59 22 +/-5% SYNC LINE1-VREFO-R 10K R18
8 33 5V_AUDIO
20 ICH_SDIN2 SDATA_IN DCVOL MIC2/LINE2-JD CMIC1-VREFO-R
20 ICH_SDOUT 5
SDATA_OUT Sense B (JD2)
34 Dummy
39
SURR-OUT-L
40 JD_REF 10uF DIP ECAP for THD+N R19
D
C60 12
JDREF (or NC)
41 +/-5% R40 2.2K * R20
D
1
* 10pF SENSEA 13 PC_BEEP
Sense A (JD1)
SURR-OUT-R
CEN-OUT
43 * 20K
Low Frequency Response * 2.2K
50V, NPO, +/-5% LINE2-L 14 44 Near the codec +/-1% R1 +/-5% +/-5%
* *
LINE2-R LINE2-L LFE-OUT MIC1-R EC5 100uF +/-20% 75 MIC1-RF FB1 FB L0603 600 Ohm MIC1_R5
15 45
*
2
LINE2-R SIDESURR-L
* *
Dummy MIC2-L 16 46 +/-5%
MIC2-R MIC2-L SIDESURR-R R6
17
CD_L MIC2-R CMIC1-VREFO-L MIC1-L EC9 100uF +/-20% 75 MIC1-LF FB2 FB L0603 600 Ohm MIC1_L2
18 28
CD_GND 19 CD_L
CD_GND
MIC1-VREFO-L
VREF
27 CODEC_VREF +/-5% *
CD_R 20 29 Close to Chip
MIC1-L CD_R LINE1-VREFO MIC2-VREFO C15 C18
21 30 Close to Chip
1
MIC1-R MIC1-L MIC2-VREFO LINE2-VREFO 4.7uF 0.1uF R2
22 31
* *
*
LINE1-L 23 MIC1-R LINE2-VREFO 32 CMIC1-VREFO-R 10V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% FRONT-R EC3 100uF +/-20% 75 LINE_OUT_R5_L FB5 FB L0603 600 Ohm LINE_OUT_R5
LINE_L MIC1-VREFO-R *
*
LINE1-R 24 Dummy +/-5%
2
LINE_R
DVss1
DVss2
AVss1
AVss2
47
SPDIF_OUT SPDIFI(EAPD)
48
SPDIFO
Close to Chip
ALC662-GR R4
*
4
7
26
42
FRONT-L EC1 100uF +/-20% 75 LINE_OUT_L2_L FB4 FB L0603 600 Ohm LINE_OUT_L2
*
*
+/-5%
AUDIO_BCLK R8
*
5V_AUDIO LINE1-R EC4 100uF +/-20% 75 LINE1-RF FB3 FB L0603 600 Ohm LINE1_R5
*
*
C61 +/-5%
1
5V_AUDIO 10pF
C16 C19 * 50V, NPO, +/-5%
1
* 4.7uF
* 0.1uF R9
*
2
10V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% C41 dummy LINE1-L EC10 100uF +/-20% 75 LINE1-LF FB6 FB L0603 600 Ohm LINE1_L2
*
1
*
4.7uF +/-5%
* *
2
Dummy 10V, Y5V, +80%/-20% C32 Place near codec

0.1uF Close to Chip
2
Dummy AUD_RST#
16V, Y5V, +80%/-20%
Place near Pin 25 10uF DIP ECAP for THD+N
C64 Low Frequency Response
1
Place near Pin 38 10pF
* 50V, NPO, +/-5%
2
C dummy C
MIC1-RF LINE_OUT_L2 LINE_OUT_R5_L
SHORT1 Place near codec MIC1-LF LINE1_L2 LINE_OUT_L2_L
C415
2 1 Dummy LINE1-RF
0.1uF 16V, Y5V, +80%/-20% 3D3V_SYS LINE1-LF
*
X_COPPER Dummy C14 C28 2 2

RN1 180pF 180pF R3 R5
* *
2
4
6
8
C419
22K 50V, NPO, +/-5%
50V, NPO, +/-5% 22K 22K
0.1uF 16V, Y5V, +80%/-20% C63 +/-5% +/-5%
*
* 13
5
7
SHORT3
Dummy
C434
* 4.7uF
10V, Y5V, +80%/-20%* C59 * C62
0.1uF +/-5% 1 1
2 1 Dummy 0.1uF 16V, Y5V, +80%/-20%
2
0.1uF 16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20% Dummy
*
X_COPPER Dummy
C435
SHORT2
2 1 Dummy 0.1uF 16V, Y5V, +80%/-20% Place near Pin 1,9
*
Dummy AUDIO
X_COPPER 5V_SB_SYS
12V_SYS LINE1_L2 32 INSULATOR
LINE1-JD 33
A
A
MIC1_L2 34
D15 MIC1_R5 LINE1_R5 35
SD103AW LINE1_R5
LS4148-F
D12 LINE_OUT_R5
U1 36
C
C
5V_AUDIO 1 3 R53 10 +/-5%
*
OUT IN LINE_OUT_L2 22
EC6 BCN1 FRONT-JD 23 37
GND
C33
* 100uF
+/-20%
C54
0.1uF
C53
4.7uF
180pF
LINE_OUT_R5
24
* 0.1uF L78L05N * * 25V,Y5V,+80/-20%
25
38
2
50V, NPO, +/-10%

16V, Y5V, +80%/-20% Dummy dummy
Dummy 25V, X7R, +/-10%
Dummy C15 MIC1_L2 2 39
Swain 110406 MIC1-JD 3
4
MIC1_R5 5
B B
1
CD_IN
12V to 5V Power Regulator D1
CD_L C36 1uF 1 10V,
2 Y5V, +80%/-20% 1 BAT54A CONN-JACK
***
2 1
CD_GND C37 1uF 1 10V,
2 Y5V, +80%/-20% 3 LINE2-VREFO 3
4 2
CD_R C38 1uF 1 10V,
2 Y5V, +80%/-20%
Header_1X4
FRONT AUDIO HEADER D2
BAT54A
1
MIC2-VREFO 3
2
SPDIF Header
RN8
*
3D3V_SYS
1
3
5
7
SPDIF_OUT
2
4
6
8
5V_SYS 1
1 MIC2-L EC12 100uF +/-20% R93
*
SPDIF_OUT 3 2.2K
* 1K
3 +/-5%
4 +/-5%
4
Close to Chip RN9 F_AUDIO
C22 Header_1X4_K2 *1 1 2
1
470pF MIC2-R EC7 100uF +/-20% 2 AUD_PRESENCE_L

* 3 4
3 4
*
50V, X7R, +/-10% 5 6

5 6
7
2
7 8 X
Dummy Close to Chip 9 10
75
+/-5% Header_2X5_K8
LINE2-R EC2 100uF +/-20% R21
* *R22
*
RN10 39.2K 20K
8
6
4
2
22K +/-1% +/-1%
Close to Chip
7
5
3
1
All JD resistors should be placed near CODEC
*
LINE2-L EC8 100uF +/-20% +/-5% MIC2/LINE2-JD
*
A A
SENSEA R46 5.1KOhm FRONT-JD
+/-1% Close to Chip
* *
R52 10K LINE1-JD

+/-1%
R38 20K MIC1-JD

+/-1%
FOXCONN PCEG
Title
ALC662
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
5V_SYS
R119 5V_SYS
*
TMPIN2 10K SIOVREF
+/-1% *R82
2.2K
5V_SYS
Dummy +/-5% 5V_SB_SYS
2
RT1 Dummy Note:
C114 10K C86
* T
* *Place CAPs close to pin 67, trace minimum 12 mils
C
2.2nF 0.1uF DTRBJ
+/-1% B Q13
50V, X7R, +/-10% Dummy MMBT3904_NL 16V, Y5V, +80%/-20%
C113
* R83
E
1
Place near pin4, 35, 99 FB9 FB L0603 600 Ohm * 0.1uF * EC31
680
*
1
GNDA C106
D
GNDA
+/-5% *
10uF
100uF
+/-20% D
RESET OPEN DRAIN
System Temperature Monitor Printer
2
35
99
67
select "high" U11
4
COM A
VCC
VCC
AVCC
VCCH
SIOVREF PD[7..0]
PD[7..0] 29
118 116 PD7
29 DCDAJ DCD1# PD7
119 115 PD6
29 RIAJ RI1# PD6
R120 120 114 PD5
29 CTSAJ CTS1# PD5
30.1K 121 113 PD4
29 DTRAJ DTR1#/JP1 PD4
Parallel Port
+/-1% 122 112 PD3
29 RTSAJ RTS1#/JP2 PD3
R0603 123 111 PD2
29 DSRAJ
****
DSR1# PD2
Dummy R87 680 SOUTB
29 SOUTA 124 110 PD1
SOUT1/JP3 PD1 PD0
Serial Port 1/2

CP8 +/-5% r0402h4 125 109
29 SINA SIN1 PD0
TMPIN1 1 2 R90 Dummy
680 RTSBJ 126 108
THERMDA 11 29 DCDBJ DCD2#/GP67 STB# STBJ 29
CP5 +/-5% 127 107
29 RIBJ RI2#/GP66 AFD# AFDJ 29
C105 1 2
X_COPPER R97 680 RTSAJ 128 106
THERMDC 11 29 CTSBJ ERRJ 29
1
3.3nF +/-5% DTRBJ CTS2#/GP65 ERR#

* 50V, X7R, +/-10% X_COPPER R99 Dummy
680 A20GATE 5V_SYS
29
29
DTRBJ
RTSBJ
RTSBJ
1
2
DTR2#/JP4
RTS2#/JP5
INIT#
SLIN#
105
104
INIT
SLINJ
29
29
THERMDA/THERMDC +/-5% 3 103
2
29 DSRBJ DSR2#/GP64 ACK# ACKJ 29

GNDA 1. width=10 mils, spacing=10 mils. SOUTB
2. route the lines in parallel *R77
4.7K
29
29
SOUTB
SINB
5
6
SOUT2/JP6
SIN2/GP63
BUSY
PE
102
101
BUSY
PE
29
29
GNDA +/-5% 100
CPU Temperature Monitor IT8718F-S/GX-L
SLCT SLCT 29 5V_SB_SYS
29
GP16/SO
*
25
GP22/SCK/VGP1
Control
Power-on
24 78 R108 10K +/-5%
*
R91 GP23/SI/VGP2 PWROK2/GP41 77 R107 10K +/-5%
Update by ITE Gary 0202
*
1K Q7 PVID5 SUSC#/GP53
B 20 76
SPI
FSB_VTT 3D3V_SYS 8,11 VID_SELECT MMBT3904_NL 8 PVID5 VIDO5/GP27 PSON#/GP42 PS_ONJ 10,30
5V_SYS +/-5% PVID4 21 75 R110 10+/-5%
8 PVID4 VIDO4/GP26 PANSWH#/GP43 PBTNJ_SIO 30
PVID1 26 72
E
8 PVID1 VIDO1/GP21/VGP0 PWRON#GP44 PWRBTNJ 20
PVID0 27 71
5V_SYS 8 PVID0 VIDO0/GP20 SUSB# SLP_S3J 20
PVID6 28
RN16 FLOPPY
8 PVID6 VIDO6/GP17 IT8718F-S/CX-L
*
1
Dummy
0
R92
CP3 FAB.B *1 2
RDATAJ
TK00J
1
1
X
2
2
4
RESETCON#/CIRTX/CE_N
30
85
R76 10K +/-5% 5V_SYS
RSMRSTJ 20
* 3 4 4 RSMRST#/CIRRX/GP55
MISC.
+/-5% 1, Add R545
X_COPPER R81 INDEXJ 5 6 DENSELJ 51 66
C * 2.2K 5 6 WPTJ 7 5 6 8 INDEXJ 63 DENSEL# IRTX/GP47 70
IRTX
IRRX
30
30
C
2
+/-5% 7 8 7 8 MOTEAJ INDEX# IRRX/GP46 R109 10M

9 10 52 68 VCCRTC
150 9 10 MTRA# COPEN# +/-5%
11 12 11 PECI 55 79
+/-5% 13 11 12 14 DRVAJ 54 PECI/AMDSI_C/DRVB# GP40 ICH_THRM_UP 20
13 14 DRVA# LAN_RSTJ
15 16 53 84
*
RTSBJ R106 DSKCHGJ 15 16 DIRJ SST/AMDSI_D/MTRB# PCIRST4#/GP10 ICH_G_PLTRSTJ LAN_RSTJ 24

17 18 57 34 CP1
VIDVCC 17 18 STEPJ DIR# PCIRST3#/GP11 SIO_PCIRSTJ ICH_G_PLTRSTJ 18
150 +/ -1% 19 20 58 33 2 1 need BIOS support
Floppy I/F
PCIRSTJ 22,23
*
19 20 WDATAJ STEP# PCIRST2#/GP12 R74 10K
21 22 56 32 3D3V_SYS
21 22 WGATEJ WDATA# PWROK1/GP13 IDE_RSTJ +/-5%
23 24 60 31 IDE_RSTJ X_COPPER
21
23 24 TK00J WGATE# PCIRST1#/GP14/I_STPCLK
25 26 62
25 26 WPTJ TRK0# VIN0
27 28 64 98 PWRGD_3V 13,20
29 27 28 30 RDATAJ 61 WPT# VIN0 97 VIN1
29 30 SIDE1J RDATA# VIN1 VIN2
31 32 59 96
VCCP 3D3V_SYS 12V_SYS 1D8V_STR 33 31 32 34 DSKCHGJ 65 HDSEL# VIN2 95
33 34 DSKCHG# VIN3/ATXPG PWRG_ATX 30
94 VIN4
Header_2X17_3 FDD VIN4 VID7
93
VIN5/VID7 VID7 11
Hardware Monitoring
92 VID6
VIN6/VID6 VIN7 VID6 11
37 91
13,20 PLTRSTJ LRESET# VIN7/PCIRSTIN# SIOVREF
38 90
1
20 L_DRQ0J LDRQ# VREF TMPIN1

39 89 C112
1
CP9 3D3V_SYS 21 SERIRQ SERIRQ TMPIN1 TMPIN2 1uF

20 L_FRAMEJ L_AD0
40
LFRAME# TMPIN2
88
*
*R111 CP6
*R116 *R118 41
LAD0 TMPIN3
87
X_COPPER
2.2K
*R117 10K 10K L_AD1 42 23 PVID2 Place cap close to pin90, and
2
LAD1 VIDO2/FAN_TAC5/GP24 PVID2 8

X_COPPER
+/-5% 2.2K +/-1% +/-1% L_AD2 43 22 PVID3

Do Not remove it.
2
L_AD3 LAD2 VIDO3/FAN_TAC4/GP25 PVID3 8

Dummy +/-5% 44
LAD3 FAN_CTL3/GP36
12
SIO_BEEP 30
LPC I/F
Dummy R94
7 CK_33M_SIO
CK_33M_SIO 47 11 FANIN3 28
8.2K L_DRQ0J PVID7 48 PCICLK FAN_TAC3/GP37 10
8 PVID7 VIDO7/GP50 FAN_CTL2/GP51 FANOUT2 28
+/-5% CK_48M_SIO 49 9
VIN0 R0603 7 CK_48M_SIO CLKIN FAN_TAC2/GP52 FANIN2 28
20 L_PMEJ 73 8 FANOUT1 28
PME#/GP54 FAN_CTL1
Dummy for KB/MOUSE wake
FAN_TAC1
7 FANIN1 28
VIN2 19 VID0
VIN4 GP30/VID0 VID1 VID0 11
45 18
21 KBRSTJ KRST#/GP62 GP31/VID1 VID1 11
VIN1 46 17 VID2
21 A20GATE GA20/JP7 GP32/VID2 VID2 11
80 16 VID3
28 KBDATA KDAT/GP61 GP33/VID3 VID3 11
81 14 VID4
28 KBCLK KCLK/GP60 GP34/VID4 VID4 11
82 13 VID5
Voltage Monitor 28
28
MSDATA
MSCLK 83
MDAT/GP57 GP35/VID5 VID5 11
KB/MS
MCLK/GP56
GNDA(D-)
B 69 VBAT B
VBAT VIDVCC
36
GNDD
GNDD
GNDD
GNDD
VIDVCC C111
1uF
* 10V, X5R, +/-10%
16V, Y5V, +80%/-20%
15
50
74
117
86
16V, Y5V, +80%/-20%
Place cap close to pin 69

C110
CP4 L_AD[3..0]
C109 C107
* 0.1uF * 0.1uF *R115
* 0.1uF
25V, X7R, *
3.3KOhm
C108
+/-10% 0.1uF 2 1
20 L_AD[3..0]
Dummy Dummy +/-1%Dummy 16V, Y5V, +80%/-20% L_AD3
Dummy X_COPPER
L_AD2
L_AD1
VTT_OUT_RIGHT GNDA L_AD0
VTT_OUT_RIGHT
3D3V_SYS R98 4.7K +/-5% A20GATE

Power On Strapping Options
**
Symbol value Description RN12 R113 R114 R85 R84
3D3V_SYS R95 10K
+/-5%
+/-5%SERIRQ
* ** *
2
4
6
8
1 Disabled. 680 680 680 680 680 RN13 1K +/-5% R96 10K KBRSTJ
+/-5% +/-5% +/-5% +/-5% +/-5%
* 13 2
*1
3
5
7
JP1/P121 Flashseg1_EN 0 Flash I/F Address Segment 1 (FFFE_0000h~FFFF_FFFFh, 4

SIO_PCIRSTJ
ICH_G_PLTRSTJ
R45 Dummy +/-5% DTRAJ
000F_0000h~000F_FFFFh) is enabled 5 6 LAN_RSTJ 4.7K

7 8
1 Disable VIDOUT pins(except VIDO6 & VIDO7) VID3 VID4
JP2/P122 VIDO_SEL VID2 VID5 5V_SYS R75 4.7K +/-5% IDE_RSTJ
0 Enable VIDOUT pins VID1
VID0
VID7
VID6 R112 4.7K +/-5% VIN7
5V_SYS
JP3/P124 CHIP_SEL -- Chip selection in configuration.
The output buffers of PCIRST1#, PCIRST2#, PCIRST3#, PCIRST4# are 3D3V_SYS 3D3V_SYS
JP4/P1 1 open-drain.
A
BUF_SEL A
0 The output buffers are push-pull. RN11

1 The default value of EC Index 15h / 16h / 17h is 00h
2
4
6
8
JP5/P2 FAN_CTL_SEL
0 The default value of EC Index 15h / 16h / 17h is 40h R88
* R89
* *R78 R100
4.7K *4.7K
* 13
5
7
4.7K 4.7K
1 The threshold voltage of VID is 2.0 / 0.8V +/-5% +/-5% +/-5% +/-5%
JP6/P5 VID_ISEL 4.7K
0 The threshold voltage of VID is 0.8 / 0.4V PVID4
PVID0
PVID1
+/-5%
FOXCONN PCEG
PVID5 PVID2
Title
1 Disable WDT to Reset PowerO.K PVID6
PVID7
PVID3
SIO 8718F
JP7/P46 WDT_SEL Size Document Number Rev
0 Enable WDT to Reset PowerO.K C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
Peak fan current draw: 1.5A

Average fan current draw: 1.1A
5V_SYS Fan start-up current draw: 2.2A
Fan start-up current draw maximum duration: 1.0 second
Fan header voltage: 12V +/- 10%
R314
* 4.7K
+/-5%
*
R313 100 +/-1%
27 FANOUT1
D D
12V_SYS
System FAN
5V_SYS
12V_SYS
EC47 C302
CPU FAN * 100uF

16V, +/-20% * 0.1uF
25V, X7R, +/-10% * R387
4.7K
Dummy Dummy +/-5%
C
* R310
*
4.7K R389 100 +/-1%
LS4148-F 27 FANOUT2
+/-5%
CPU_FAN D36
4 R311 12V_SYS
*
4 27KOhm
3 FANIN1 27
3 +/-5%
2
2
1
Max. output current = 3A 1 C303
2
R312
Header_1X4 FAN4P 22K * 47pF
+/-5% 50V, NPO, +/-5%
12V_SYS
C422
C * 0.1uF
25V, X7R, +/-10% C
Dummy
C
R388
* 4.7K
LS4148-F+/-5%
SYS_FAN D43
VCC_DUAL 4 R396
*
4 27KOhm
3
3 FANIN2 27
Max. output current = 3A 2 +/-5%
VCC_DUAL 2
1
1 C417
2
R395
Header_1X4 FAN4P 22K * 47pF
F2 +/-5% 50V, NPO, +/-5%
Fuse 1.5A
1
*
fs1813h5
RN7
8
6
4
2
7
5
3
1
*
4.7K
+/-5%
FB7
300 Ohm@100MHz
*
12V_SYS
KB/MS
16
13
B B
27 KBCLK 5 11
3 9
1 7 12V_SYS
2 17
4 8 EC22 C94
6 10
12
* 100uF
16V, +/-20% * 0.1uF
25V, X7R, +/-10%
14 Dummy Dummy
C
27 KBDATA
R101
UP DOWN
15 * 4.7K
LS4148-F+/-5%
PS2X2 D23 Dummy
PWR_NET02 NB_FAN Dummy R104
*
3 27KOhm
FANIN3 27
2 +/-5%
27 MSCLK
1 Dummy
Max. output current = 3A 2 C99
Header_1X3 R105
22K * 47pF
+/-5% 50V, NPO, +/-5%
C43
Dummy
1 Dummy Dummy
27 MSDATA
* 0.1uF
16V, Y5V, +80%/-20%
BCN4
180pF
50V, NPO, +/-10%
*
A A
FOXCONN PCEG
Title
Keyboard / Mouse / Fan
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
U10
5V_SYS 20 1 12V_SYS
VCC +12V
16 5 NRTSB -12V_SYS 5V_SYS 12V_SYS 5V_SYS
27 RTSBJ DA1 DY1 NDTRB
15 6
27 DTRBJ DA2 DY2
16V, Y5V, +80%/-20%

13 8 NSOUTB C87 C83 C82 D5 C A LS4148-F
27 SOUTB DA3 DY3 NRIB
19 2
* 0.1uF 0.1uF
* * 0.1uF C57
1
27 RIBJ RY1 RA1 NCTSB 25V, X7R, +/-10% 25V, X7R, +/-10% 0.1uF
18 3
*
2
4
6
8
27 CTSBJ RY2 RA2 NDSRB 16V, Y5V, +80%/-20%
17 4
27 DSRBJ RY3 RA3 NSINB RN5 R47 RN3
14 7
*
2
4
6
8
2
D 27 SINB RY4 RA4 D
12 9 NDCDB 10K 10K 2.7K
27 DCDBJ RY5 RA9 +/-5% +/-5%
Dummy Dummy +/-5%
* 13
5
7
11 10 -12V_SYS Dummy
*
GND -12V
1
3
5
7
GD75232
RS232 Drivers and Receivers

Dummy
placed near GD75232
PD[7..0] 33
27 PD[7..0] PD0
PD1
RN4
* 13 2
4
+/-5%
33 PD2
5 6
27 STBJ
RN2
*1 2
+/-5% PD3
7 8
27 AFDJ 3 4
27 INIT 5 6
PD4
PD5
RN6
*1 2
+/-5%
COM 2 Header 27 SLINJ 7 8 PD6 3 4
PD7 5 6
COM2 7 8
NDCDB 1 2 NSINB 33
NSOUTB 3 4 NDTRB
NDSRB 27 ERRJ
5 6
NRTSB 7 8 NCTSB
NRIB 9
27 ACKJ
27 BUSY
Header_2X5_K10
* 27 PE
27 SLCT
Dummy BCN10
* 180pF
BCN9 CONN-D-SUB
50V, NPO, +/-10%
180pF
50V, NPO, +/-10% 1
AFD1- 14
Dummy Dummy P_D0 2
C 15 C
P_D1 3
INIT1- 16
SLIN1-
P_D2 4
17
PRT PORT
P_D3 5
18
P_D4 6
19
placed near header placed near header P_D5 7 28
U6 -12V_SYS 5V_SYS 12V_SYS 20 27
5V_SYS 20 1 P_D6 8 26
VCC +12V 12V_SYS
C45 C48 C58 21
NRTSA 0.1uF 0.1uF 0.1uF P_D7
27 RTSAJ
16
DA1 DY1
5
* * * 9
16V, Y5V, +80%/-20%
15 6 NDTRA 25V, X7R, +/-10% 25V, X7R, +/-10% 22

27 DTRAJ DA2 DY2 NSOUTA ACKJ
13 8 10
27 SOUTA DA3 DY3 NRIA
19 2 23
27 RIAJ RY1 RA1 NCTSA BUSY
18 3 11
27 CTSAJ RY2 RA2 NDSRA
27 DSRAJ
17 4 24
14 RY3 RA3 7 NSINA PE 12
27 SINA RY4 RA4 NDCDA
12 9 25
27 DCDAJ RY5 RA9 SLCT 13
11 10 -12V_SYS
GND -12V
GD75232 PRT
placed near GD75232
RS232 Drivers and Receivers
* * * *
CONN-COM PORT BCN6 BCN7 BCN8 BCN5
11 180pF 180pF 180pF 180pF
NDCDA 1
NDSRA 50V, NPO, +/-10% 50V, NPO, +/-10% 50V, NPO, +/-10% 50V, NPO, +/-10%
6
NSINA 2
NRTSA 7
NSOUTA 3
NCTSA 8
NDTRA 4
B B
NRIA 9
* * 5
10
BCN2 BCN3
COM1
180pF 180pF
50V, NPO, +/-10% 50V, NPO, +/-10%
COM 1
placed near connector
A A
FOXCONN PCEG
Title
Serial / Parallel
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
for some power supplies without pw-ok function

5V_SB_SYS
-12V_SYS 3D3V_SYS 3D3V_SYS 12V_SYS 5V_SB_SYS EMI CAPS.
5V_SYS
R391 5V_SYS 5V_SYS 12V_SYS 3D3V_SYS
*
8.2K
+/-5% PWR1
13
14
+3.3V3 +3.3V1
-12V +3.3V2
1
2 *R392
8.2K
15 3 +/-5% C408 C416
1
GND4 GND1 0.1uF 0.1uF16V, Y5V, +80%/-20%
10,27 PS_ONJ 16
17
PSON
GND5
+5V1
GND2
4
5 * *
25V, X7R, +/-10%
18 6 Dummy Dummy
2
D GND6 +5V2 D
C412
* 19
20 GND7 GND3
RSVD PWR0K
7
8 R393 0 +/-5%
PWRG_ATX 27
*
0.1uF 21 9
+5V3 +5V_AUX
16V, Y5V, +80%/-20% 22 10
23 +5V4 +12V_1 11
+5V5 +12V_2
24 12
GND8 +3.3V4
HM1512E-EP1 * C413
0.1uF
16V, Y5V, +80%/-20%
SPEAKER
Clear CMOS 1
1
3 Dummy
CLR_CMOS 5V_SYS 3
JP6 CMOS RN22 4
4 H4MO2
5V_SYS 1
1
2 Header_1X4_2
20,21 RTCRSTJ 2 8 7
3 Clear (1-2)
3 SPEAKER HEADER 6
4
5
3
BUZ
C25 Header_1X3 Normal (2-3) Default * +
2 1 +
1
0.1uF
16V, Y5V, +80%/-20% * CLR_CMOS(2-3)1
100 Ohm
BUZZER
Dummy prevent clearing CMOS when power-on -
2
+/-5% -
IR Buzzer
1
1 Jumper 5V_SYS
3 IR Header
C 27 IRRX
4 3 C
4
5
27 IRTX 5 R86
Header_1X5_K2 4.7K
+/-5% D25
C
INTR 1 R180
20 SPKR
*
C102 C115 1 3 2.2K B Q20
1
0.1uF 470pF 20 INTRUDERJ +/-5% MMBT3904_NL C209

16V, Y5V, +80%/-20% * * 50V, X7R, +/-10%
2
27 SIO_BEEP
2
* 0.1uF
E
Dummy Dummy Header_1X2 16V, Y5V, +80%/-20%
2
BAT54C
Dummy
Chassis Intruder
5V_SB_SYS 5V_SYS
5V_SYS 3D3V_DUAL 3D3V_SYS
*R390
330 *R386
330
5V_SB_SYS MH5
Mounting Hole
MH6
Mounting Hole
R382 R397 +/-5% +/-5%
* 330 * 8.2K
*R394 T1 T4
6
5
6
5
+/-5% +/-5% dummy 8.2K mh40x80_8 FD2 FD4 FD1 FD3 1 1
1N4148W +/-5% 7 Dummy 4 7 Dummy 4 FMARK FMARK FMARK FMARK 2 2
B FP1 Dummy 8 3 8 3 FD40Dummy FD40Dummy FD40Dummy FD40Dummy B
1 2 PLED+ 1 2 D42 S3_LED 20 9 2 9 2 T1 T2
3 4 PLED
1
21 HDD_LEDJ
5 6 Dummy Dummy
1
7 8 mh40x80_8
7,11,20 ICH_SYS_RSTJ
9 X
Header_2X5_K10
C403 C433
27 PBTNJ_SIO
470pF 470pF 3D3V_SYS
* 50V, X7R, +/-10% * 50V, X7R, +/-10%
C0603 C0603 C424
Dummy Dummy
* 2.2uF
6.3V, Y5V, +80%/-20%
C442 0.1uF
*
16V, Y5V, +80%/-20% T2 T3

Dummy 1 1
C443 0.1uF 2 2
*
16V, Y5V, +80%/-20% MH1 MH2 MH3 MH4 T1 T2

Mounting Hole Mounting Hole Mounting Hole Mounting Hole
Front Panel Switch/LED Dummy Dummy
5V_SYS
6
5
6
5
6
5
6
5
S0: steady light
S1: blinking 7 Dummy 4 7 Dummy 4 7 Dummy 4 7 Dummy 4
HD_LED+ 1 2 Power S3~S5: off R383 8 3 8 3 8 3 8 3
HD_LED- 3 4 Power LED(Green) 3D3V_SYS 4.7K 9 2 9 2 9 2 9 2
+/-5%
1
GND 5 6 Power button
Reset button 7 8 GND R375 PLED mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8
NC 9 10 Key 4.7K
+/-5%
C
20 S1_LED B Q36
MMBT3904_NL
E
A A
FOXCONN PCEG
Title
Power / MISC Connector
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
ICH7 GPIO Summary

D
Name
GPIO0
GPIO1
Power Well
Vcc3_3
V5REF
Type
I/O
I/O
Description
Pull-up through 10K resistor(Unused)
REQ_5#
Super I/O GPIO Summary D
Name Power Plane Type Description

GPIO2 V5REF I/OD PIRQE#
GPIO16 SUS I/O VID select
GPIO3 V5REF I/OD PIRQF#
GPIO22 SUS I/O S1 LED
GPIO4 V5REF I/OD PIRQG#
GPIO23 SUS I/O S3 LED
GPIO5 V5REF I/OD PIRQH#
GPIO10 SUS I/O ICH THRM UP
GPIO6 Vcc3_3 I/O 1D5V Over voltage
GPIO36 SUS I/O Fan 3pin/4pin Det
GPIO7 Vcc3_3 I/O 1D5V Over voltage
GPIO37 MAIN I/O SIO BEEP
GPIO8 VccSus3_3 I/O L_PMEJ
GPIO9 VccSus3_3 I/O DDR 1.8V Over voltage I/O
GPIO10 VccSus3_3 I/O DDR 1.8V Over voltage I/O
GPIO11 VccSus3_3 I/O Pull-up through 10K resistor(Unused) I/O
GPIO12 VccSus3_3 I/O DDR 1.8V Over voltage
GPIO13 VccSus3_3 I/O Wake On LAN
GPIO14 VccSus3_3 I/O Pull-up through 10K resistor(Unused)
GPIO15 VccSus3_3 I/O DDR 1.8V Over voltage
GPIO16 Vcc3_3 I/O BOAD ID 0
GPIO17 Vcc3_3 I/O GNT_5#
C
GPIO18 Vcc3_3 I/O BOAD ID 1 C
GPIO19 Vcc3_3 I/O SATA_1GP

GPIO20 Vcc3_3 I/O BOAD ID 2
GPIO21 Vcc3_3 I/O SATA_0GP
GPIO22 Vcc3_3 I/O REQ_4#
GPIO23 Vcc3_3 I/O Pull-up through 10K resistor(Unused)
GPIO24 VccSus3_3 I/O (Unused)
GPIO25 VccSus3_3 I/O (Unused)
GPIO29 VccSus3_3 I/O USB OC5#
GPIO32
GPIO33
GPIO34
Vcc3_3
Vcc3_3
Vcc3_3
I/O
I/O
I/O
BOAD ID 3
IDE1 Cable Detection(33 or 66/100)
BOAD ID 4
PCI Routing Summary
GPIO35 Vcc3_3 I/O (Unused) PCI1 PCI2 LAN
GPIO36 Vcc3_3 I/O SATA_2GP INTAJ D C A
B GPIO37 Vcc3_3 I/O SATA_3GP INTBJ A D B
GPIO38 Vcc3_3 I/O FWH_TBLJ INTCJ B A

GPIO39 VccSus3_3 I/O Pull-up through 10K resistor(Unused) INTDJ C B
GPIO40 N/A N/A Not Implemented
INTEJ C
GPIO41 N/A N/A Not Implemented INTFJ B
GPIO42 N/A N/A Not Implemented INTGJ A
GPIO43 N/A N/A Not Implemented INTHJ D
GPIO44 N/A N/A Not Implemented REG#/GNT# 2 1 0 3
GPIO45 N/A N/A Not Implemented IDSEL 18 17 21 19
GPIO48 Vcc3_3 I/O GNT_4#
GPIO49 V_CPU_IO I/O CPU_PWRGD
A A
FOXCONN PCEG
Title
GPIO / IRQ / IDSEL Map
C 945M09 1.0

5 4 3 2 1

5 4 3 2 1
Modify list
D D
1. Update clockgen PWRGD circuit(by connecting directly to VRM_PWRGD)

2. Delete TPM 33M CLK(delete C26,delete RN19 pin5,6 net)
3. Delete CPU PWRGD Pull high Resistor
4. Update ESD DIODE net(change D10,D11,D13,D12 Pin3 net)
5. Add level shift for HSYNC/VSYNC(change U10,U11,R252,R255 from dummy to reserved
change R241,R242 from reserved to dummy)
6. GPIO update(change GPIO7 from 1D5V_CTL to Board_ID,change GPIO9 from 1D8V_CTL to SPI_WP
change GPIO10/12 from 1D8V_CTL to unused,change GPIO16 from Board_ID to 1D5V_CTL,change
GPIO27 from unused to 1D8V_CTL,change GPIO28 from SPI_WP to 1D8V_CTL,Change GPIO34 from
Board_ID to 1D5V_CTL,change GPIO38 from 1D5V_CTL to Board_ID;delete R262,R264,R322,R329
7. Update RSMRST# circuit(delete R320,U23,U24,R332;change R380 from dummy to reserved)
8. Delete SPI_WP header(delete WP,WP_EN)
9. Delete TPM(detele total page,remove others to page30)
10.LAN IC change from PCI LAN(8110C) to PCIE LAN8101E)
11.Add 75ohm resistor(add R410,R413,R374,R404,change R367,R368 from 0ohm to 75ohm
12.Add 22K resistor(change RN25 from dummy to reserved)
C
13.Update Front audio auto detect C
14.Delete 1D5V VIN(delete R410,CP7,C415,add R423)

15.Delete CIR(delete R321)
16.Delete CIR
17.Change C1075,C1082,C1077,C1074,C1078,C1080,C1081,C1083 footprint
from 1206 to 0805
18.Delete dummy ECAP EC32
19.Change R308 from 0ohm to 1K
20.Delete C92
21.Delete R327 and add capcitors C109(Dummy) and C111(for 8111B)
22.change the value of EC2 and EC3 from 1500uF to 1800uF
23.Add FB17 for SIO pin 99
24.Add EMI CAP
25.Add R456,R446 for EMI
26.Add R244 ,R250
27.Delete C430,C319,C365,C367
B B
A A
FOXCONN PCEG
Title
Modify List
C 945M09 1.0

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5 4 3 2 1

Foxconn Precision Co. Inc.

03. Rest Map 20. ICH7-1

12. LGA775-2 29. Serial / Parallel B

13. LAKEPORT-GMCH-1 30. Power / MISC Connectors

Date: Monday, August 20, 2007 Sheet 1 of 32

PDF created with pdfFactory trial version www.pdffactory.com

GMCH DDR2 533/667 Channel B DDR2

USB2.0 Port 8 SATA Connector 2

Date: Monday, August 20, 2007 Sheet 2 of 32

PDF created with pdfFactory trial version www.pdffactory.com

Front Panel PWROK AC_RST#

RST# PCIRST3# RST# Audio

Date: Monday, August 20, 2007 Sheet 3 of 32

PDF created with pdfFactory trial version www.pdffactory.com

MCH 133/200/266/333 MHz Diff Pair

DDR2 4 Slots 12 Diff CLKs

PCI Express/DMI 100 MHz Diff Pair

PCI Express 100 Mhz Diff Pair LAN

PCI 33 MHz PCI Slot 2

SATA 100 MHz Diff Pair

Date: Monday, August 20, 2007 Sheet 4 of 32

PDF created with pdfFactory trial version www.pdffactory.com

Vcore (Core Logic) PCI Express

4.345A(S0,S1) PCIexpress(X16)=1A Icc(Max)=0.02A(no wake)

1.5V PCI Express=tbdmA

1.8V +2.5V=tbdA BJT

*Power derived through filter FOXCONN PCEG

Date: Monday, August 20, 2007 Sheet 5 of 32

PDF created with pdfFactory trial version www.pdffactory.com

+3D3V_DUAL +3D3V_SYS +3D3V_SYS +3D3V_DUAL

+5V_SYS +5V_DUAL +5V_DUAL +5V_SYS

+3D3V_SYS +3D3V_DUAL +3D3V_DUAL +3D3V_SYS

+1D8V_STR +1D8V_STR +1D8V_STR +1D8V_STR

Date: Monday, August 20, 2007 Sheet 6 of 32

PDF created with pdfFactory trial version www.pdffactory.com

C143 C140 C170 C207 C185

CK_33M_PCI1 R161 33+/-5% SELRSET/RESET#/PCICLK32 X2 3D3V_CLK_REF_A

*internal pull-up resistor ICS9LPRS511EGLF-T

For support 1333Mhz CPU on 945GC platform

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

10pF 10pF 10pF 10pF 10pF 10pF 10pF

C0402 C0402 C0402 C0402 C0402 C0402 C0402

EMI CAPS. FOXCONN PCEG

Date: Monday, August 20, 2007 Sheet 7 of 32

PDF created with pdfFactory trial version www.pdffactory.com

C257 50V, X7R, +/-10%

15K 2.43K +/-1% Dummy

13 16V, Y5V, +80%/-20% R191 6.2K +/-1%PHASE1

R206 100 +/-1% 30 Q9 Q11 1nF

0.1uF VCC PHASE1 AOD472 AOD472 R71

35 R196 100 +/-1% C226 VCCP R189 +/-5%

R224 68K +/-1% ISEN1+ 0.1uF 2.2

R241 R212 100KOhm

30K 1uF Dummy Dummy Dummy Dummy

BOOT2 25V, X7R, +/-10% 16V, Y5V, +80%/-20% VCCP

25 25V, X7R, +/-10%

0.1uF 2.2 +/-5%