A10GX PCIE E3p1

8 7 6 5 4 3 2 1
REV DATE PAGES DESCRIPTION

NOTES:
1. Project Drawing Numbers:
Raw PCB 100-0321301-E3
Gerber Files 110-0321301-E3
PCB Design Files 120-0321301-E3
Assembly Drawing 130-0321301-E3
Fab Drawing 140-0321301-E3
Schematic Drawing 150-0321301-E3
E PCB Film 160-0321301-E3 E
Bill of Materials 170-0321301-E3
Schematic Design Files 180-0321301-E3
Functional Specification 210-0321301-E3 PAGE DESCRIPTION PAGE DESCRIPTION
PCB Layout Guidelines 220-0321301-E3
Assembly Rework 320-0321301-E3 1 Title, Notes, Block Diagram, Rev. History 37 Power1 A10 VCC ET4040 (2)
2. 1516 Parts, 84 Library Parts, 1524 Nets, 7856 Pins Arria 10 FPGA Development Kit 2 Clock Diagram 38 Power2 - A10 VCCRAM
3 PCI Express Edge Connector 39 Power2 - A10 VCCR GXB
4 Arria 10 GX Bank 2 40 Blank Page
5 Arria 10 GX Bank 3A-3D 41 Power3 - A10 VCCPT/1.8V
6 Arria 10 GX Bank 3E-3H 42 Power4 - A10 VCCIO 1.8V
7 Arria 10 Configuration 43 Power4 - A10 VCCIO FMCA
D 8 Arria 10 Clocks 44 Power4 - A10 VCCIO FMCB D
9 PLL 45 Power4 - A10 VCCIO MEM

10 PLL2 46 Arria 10 Power
11 Arria 10 XCVR Left (B1) 47 Arria 10 Ground
12 Arria 10 XCVR Right (B4) 48 Decoupling
13 5M2210 System Controller 49 Power-Down Discharge
14 Flash 50
15 10/100/1000 Ethernet PHY 51
16 EMI Connector Map 52
17 External Memory Interface 53
C C
18 DisplayPort (x4) 54
19 FMC Port A 55
20 FMC Port B 56
21 QSFP 57
22 SFP+ 58
23 SDI Transmit/Receive 59
24 User IO 60
25 On-Board USB Blaster II -1 61
26 On-Board USB Blaster II -2 62
B 27 Power Tree 63 B
28 Power Sequence Diagram 64

29 Voltage & Temperature Sense 65
30 Power Sequence Control 66
31 Power - Select Power Input 67
32 Power - DCin to 3.3V 68
33 Power - 3.3V & 5.0V
34 Power - MEM_VDD & 2.5V
35 Power1 - A10 VCC
36 Power1 A10 VCC ET4040 (1)
A A
Altera Corporation, 101 Innovation Dr., San Jose CA 95134
Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Arria 10 GX FPGA Development Kit
Size Document Number Rev
B 150-0321301-E3 (6XX-44366R) E3.1
Date: Wednesday, August 10, 2016 Sheet 1 of 49
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Clock Diagram
E E
D D
C C
B B
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI Express Edge Connector 11 PCIE_TX_P[7:0]
11 PCIE_TX_N[7:0]
11 PCIE_RX_P[7:0]
E E
11 PCIE_RX_N[7:0]
3.3V_PCIE 12V_PCIE 12V_PCIE 3.3V_PCIE
Link Width DIP Switch
J22 SW3
B1 A1 PCIE_PRSNT1n 1 8 PCIE_PRSNT2n_x1
B2 +12V PRSNT1_N A2 2 7 PCIE_PRSNT2n_x4
OPEN
B3 +12V +12V A3 3 6 PCIE_PRSNT2n_x8
B4 +12V +12V A4 4 5
PCIE_EDGE_SMBCLK B5 GND GND A5 17,34 VDD_1.35V_SET QDRIV needs 1.3V VDD.
PCIE_EDGE_SMBDAT B6 SMCLK JTAG_TCK A6 DIPSWITCH4 34 VDD_1.3V_SET SW3.4 allows changing of
B7 SMDAT JTAG_TDI A7 1.35V to 1.3V for QDRIV.
B8 GND JTAG_TDO A8
B9 +3_3V JTAG_TMS A9 3.3V
R552 DNI 3.3V_PCIE_AUX B10 JTAG_TRSTN +3_3V A10 U75
PCIE_EDGE_WAKEn R546 DNI PCIE_WAKEn_R B11 +3_3VAUX +3_3V A11 PCIE_EDGE_PERSTn 1 6
WAKE_N PERST_N A VCC
KEY PB_PERSTn 2 A&B=Y 4 PCIE_3P3V_PERSTn
B12 A12 B Y
B13 RSVD1 X1 GND A13 11 PCIE_EDGE_REFCLK_P 3 5
D GND REFCLK+ GND NC D
PCIE_RX_P0 B14 A14 11 PCIE_EDGE_REFCLK_N
PCIE_RX_N0 B15 PET0P REFCLK- A15 SN74LVC1G08_6PIN
B16 PET0N GND A16 PCIE_TX_CP0 0.22uF C722 PCIE_TX_P0
PCIE_PRSNT2n_x1 B17 GND PER0P A17 PCIE_TX_CN0 0.22uF C721 PCIE_TX_N0
B18 PRSNT2_N_X1 PER0N A18 3.3V
GND GND
S8
PCIE_RX_P1 B19 A19 1 2 PB_PERSTn R544 10.0K
PCIE_RX_N1 B20 PET1P X4 RSVD2 A20 PB Switch
B22 GND PER1P A22 PCIE_TX_CN1 0.22uF C719 PCIE_TX_N1
PCIE_RX_P2 B23 GND PER1N A23
PCIE_RX_N2 B24 PET2P GND A24
PCIE_RX_P3 B27 GND PER2N A27 3.3V 1.8V
B30 GND PER3P A30 PCIE_TX_CN3 0.22uF C715 PCIE_TX_N3 C693
C692
PCIE_PRSNT2n_x4 B31 RSVD3 PER3N A31 C706
C PRSNT2_N_X4 GND C
B32 A32 1uF 0.1uF
GND RSVD4 0.1uF
PCIE_RX_P4 B33 A33 U74
PCIE_RX_N4 B34 PET4P X8 RSVD5 A34 B1 B2
B35 PET4N GND A35 PCIE_TX_CP4 0.22uF C714 PCIE_TX_P4 PCIE_3P3V_PERSTn C1 VCC VL A1 7 PCIE_PERSTn
B36 GND PER4P A36 PCIE_TX_CN4 0.22uF C713 PCIE_TX_N4 PCIE_EDGE_SMBCLK C2 IO VCC1 IO VL1 A2 7 PCIE_SMBCLK
PCIE_RX_P5 B37 GND PER4N A37 PCIE_EDGE_SMBDAT C3 IO VCC2 IO VL2 A3 4 PCIE_SMBDAT
PCIE_RX_N5 B38 PET5P GND A38 PCIE_EDGE_WAKEn C4 IO VCC3 IO VL3 A4 7 PCIE_WAKEn
B39 PET5N GND A39 PCIE_TX_CP5 0.22uF C712 PCIE_TX_P5 IO VCC4 IO VL4
1.8V
B40 GND PER5P A40 PCIE_TX_CN5 0.22uF C711 PCIE_TX_N5 B3 B4
PCIE_RX_P6 B41 GND PER5N A41 TS GND
PCIE_RX_N6 B42 PET6P GND A42 MAX3378_UCSP
PCIE_RX_P7 B45 GND PER6N A45
PCIE_PRSNT2n_x8 B48 GND PER7P A48 PCIE_TX_CN7 0.22uF C707 PCIE_TX_N7
B49 PRSNT2_N_X8 PER7N A49
B GND GND B
PCIE_Slot
75-ohm to 100-ohm XCVR traces.
12V_PCIE 3.3V_PCIE
C254 C255 C256 C725 C724 C258 C257 C723

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U28C Arria 10 GX Bank 2 9

9
CLOCK INTERFACE
CLOCK_SDA
CLOCK_SCL
ARRIA 10 - BANK 2I-2L
QSFP_LP_MODE AK34 D32 MEM_DQ_ADDR_CMD3 DISPLAYPORT INTERFACE
QSFP_INTERRUPTn AL34 IO,LVDS2I_1P,DQ12L IO,LVDS2K_1P,DQ4L C33 MEM_DQ_ADDR_CMD4 18 DP_HOT_PLUG
IO,LVDS2I_1N,DQ12L IO,LVDS2K_1N,DQ4L
BANK-2I
BANK-2K
DP_HOT_PLUG AM30 B32 MEM_DQ_ADDR_CMD2 18 DP_RETURN
CLOCK_SDA AN30 IO,LVDS2I_2P,DQ12L IO,LVDS2K_2P,DQ4L A32 MEM_DQ_ADDR_CMD0 18 DP_AUX_CH_P
AL32 IO,LVDS2I_2N,DQ12L IO,LVDS2K_2N,DQ4L B33 MEM_DQ_ADDR_CMD5 18 DP_AUX_CH_N
E IO,LVDS2I_3P,DQ12L IO,LVDS2K_3P,DQ4L E
DP_RETURN AL33 A33 MEM_DQ_ADDR_CMD1 18 DP_CONFIG1
DP_CONFIG2 AK32 IO,LVDS2I_3N,DQ12L IO,LVDS2K_3N,DQ4L C35 MEM_DQ_ADDR_CMD7 18 DP_CONFIG2
DP_CONFIG1 AK31 IO,LVDS2I_5P,DQ12L IO,LVDS2K_5P,DQ4L D34 MEM_DQ_ADDR_CMD6
(1.2V, 1.35V, 1.5V)

IO,LVDS2I_5N,DQ12L IO,LVDS2K_5N,DQ4L MEM_ADDR_CMD29
VARIABLE EMI VCCIO

AM31 E35 24 DISP_I2C_SCL
IO,LVDS2I_6P,DQ12L IO,LVDS2K_6P,DQ4L
VCCIO = 1.8V
AM32 E34 MEM_DQ_ADDR_CMD8 24 DISP_I2C_SDA
DP_AUX_CH_P AN34 IO,LVDS2I_6N,DQ12L IO,LVDS2K_6N,DQ4L D33 MEM_DQS_ADDR_CMD_P 24 DISP_SPISS
ENABLE ARRIA 10 OCT -> DP_AUX_CH_N AM35 IO,LVDS2I_4P,DQS12L IO,LVDS2K_4P,DQS4L C34 MEM_DQS_ADDR_CMD_N
IO,LVDS2I_4N,DQSN12L IO,LVDS2K_4N,DQSN4L
AR32 G35 MEM_ADDR_CMD17 QSFP INTERFACE
AP32 IO,LVDS2I_7P,DQ13L IO,LVDS2K_7P,DQ5L H35 MEM_ADDR_CMD18 21 QSFP_MOD_SELn
AT37 IO,LVDS2I_7N,DQ13L IO,LVDS2K_7N,DQ5L G33 MEM_ADDR_CMD19 21 QSFP_RSTn
PCIE_SMBDAT AU37 IO,LVDS2I_8P,DQ13L IO,LVDS2K_8P,DQ5L F33 MEM_ADDR_CMD16 21 QSFP_SCL
AP34 IO,LVDS2I_8N,DQ13L IO,LVDS2K_8N,DQ5L E32 MEM_ADDR_CMD15 21 QSFP_SDA
AP33 IO,LVDS2I_9P,DQ13L IO,LVDS2K_9P,DQ5L F32 MEM_ADDR_CMD26
100, 1% R449 RZQ_B2I AR34 IO,LVDS2I_9N,DQ13L IO,LVDS2K_9N,DQ5L J34 24 RZQ_B2K 21 QSFP_INTERRUPTn
SFP_TX_DISABLE AR35 IO,RZQ_2I,LVDS2I_11P,DQ13L IO,RZQ_2K,LVDS2K_11P,DQ5L H34 MEM_ADDR_CMD12 21 QSFP_MOD_PRSn
IO,LVDS2I_11N,DQ13L IO,LVDS2K_11N,DQ5L Stratix 5 RZQ
SFP_MOD0_PRSNTn AT30 J33 MEM_ADDR_CMD8 100-ohm for 50-ohm RT or 25-ohm RS. 21 QSFP_LP_MODE
SFP_MOD2_SDA AR31 IO,LVDS2I_14P,DQ14L IO,LVDS2K_14P,DQ6L J32 MEM_ADDR_CMD9
D IO,LVDS2I_14N,DQ14L IO,LVDS2K_14N,DQ6L D
SFP_RS1 AT34 N34 MEM_ADDR_CMD2 SFP+ INTERFACE
SFP_TX_FAULT AT35 IO,LVDS2I_16P,DQS14L IO,LVDS2K_17P,DQ6L M35 MEM_ADDR_CMD3 22 SFP_RS0
SFP_RS0 AN31 IO,LVDS2I_16N,DQSN14L IO,LVDS2K_17N,DQ6L M32 MEM_ADDR_CMD0 22 SFP_RS1
SFP_MOD1_SCL AP31 IO,LVDS2I_17P,DQ14L IO,LVDS2K_18P,DQ6L L32 MEM_ADDR_CMD1 22 SFP_TX_DISABLE
QSFP_SDA AU31 IO,LVDS2I_17N,DQ14L IO,LVDS2K_18N,DQ6L L34 MEM_ADDR_CMD4
SFP_RX_LOS AU30 IO,LVDS2I_18P,DQ14L IO,LVDS2K_16P,DQS6L K34 MEM_ADDR_CMD5 22 SFP_RX_LOS
IO,LVDS2I_18N,DQ14L IO,LVDS2K_16N,DQSN6L
22 SFP_TX_FAULT
QSFP_MOD_PRSn AU36 U32 MEM_ADDR_CMD30 22 SFP_MOD0_PRSNTn
QSFP_MOD_SELn AU35 IO,LVDS2I_19P,DQ15L IO,LVDS2K_19P,DQ7L T32 MEM_ADDR_CMD31
QSFP_SCL AV34 IO,LVDS2I_19N,DQ15L IO,LVDS2K_19N,DQ7L R30 MEM_CLK_P 22 SFP_MOD1_SCL
QSFP_RSTn AV35 IO,LVDS2I_20P,DQ15L IO,LVDS2K_20P,DQ7L R31 MEM_CLK_N 22 SFP_MOD2_SDA
SDI_MF2_MUTE AY35 IO,LVDS2I_20N,DQ15L IO,LVDS2K_20N,DQ7L U33 MEM_ADDR_CMD20
SDI_TX_SD_HDn AW34 IO,LVDS2I_21P,DQ15L IO,LVDS2K_21P,DQ7L T33 MEM_ADDR_CMD21
IO,LVDS2I_21N,DQ15L IO,LVDS2K_21N,DQ7L SDI INTERFACE
DISP_I2C_SCL AW33 R34 MEM_ADDR_CMD22 13,23 SDI_MF2_MUTE
CLOCK_SCL AV33 IO,LVDS2I_23P,DQ15L IO,LVDS2K_23P,DQ7L P34 MEM_ADDR_CMD23 13,23 SDI_MF0_BYPASS
DISP_I2C_SDA AY34 IO,LVDS2I_23N,DQ15L IO,LVDS2K_23N,DQ7L T34 MEM_ADDR_CMD28 13,23 SDI_MF1_AUTO_SLEEP
DISP_SPISS BA35 IO,LVDS2I_24P,DQ15L IO,LVDS2K_24P,DQ7L T35 MEM_ADDR_CMD27 13,23 SDI_TX_SD_HDn
SDI_MF0_BYPASS AW32 IO,LVDS2I_24N,DQ15L IO,LVDS2K_24N,DQ7L N33 MEM_ADDR_CMD24
SDI_MF1_AUTO_SLEEP AY32 IO,LVDS2I_22P,DQS15L IO,LVDS2K_22P,DQS7L P33 MEM_ADDR_CMD25
C IO,LVDS2I_22N,DQSN15L IO,LVDS2K_22N,DQSN7L PCIe INTERFACE C
3 PCIE_SMBDAT
MEM_DQB0 AC31 D26 MEM_DQA6
IO,LVDS2J_1P,DQ8L IO,LVDS2L_1P,DQ0L
VARIABLE EMI VCCIO BANK-2J
(1.2V, 1.35V, 1.5V)BANK-2L

MEM_DQB4 AD31 E26 MEM_DMA0 MEMORY INTERFACE
MEM_DQB6 AD33 IO,LVDS2J_1N,DQ8L IO,LVDS2L_1N,DQ0L A28 MEM_DQA1
MEM_DQB5 AD32 IO,LVDS2J_2P,DQ8L IO,LVDS2L_2P,DQ0L A27 MEM_DQA2
MEM_DMB0 IO,LVDS2J_2N,DQ8L IO,LVDS2L_2N,DQ0L MEM_DQA0 8,17 MEM_ADDR_CMD[31:0]
AB32 B28
MEM_DQB1 AB31 IO,LVDS2J_3P,DQ8L IO,LVDS2L_3P,DQ0L B27 MEM_DQA3
(1.2V, 1.35V, 1.5V)
MEM_DQB3 IO,LVDS2J_3N,DQ8L IO,LVDS2L_3N,DQ0L MEM_DQA4

VARIABLE EMI VCCIO
Y31 D27 17 MEM_CLK_P

MEM_DQB2 W31 IO,LVDS2J_5P,DQ8L IO,LVDS2L_5P,DQ0L E27 MEM_DQA5 17 MEM_CLK_N
MEM_QKB_P0 Y30 IO,LVDS2J_5N,DQ8L IO,LVDS2L_5N,DQ0L C28 MEM_QKA_P0
QDR4 QKB_P0 -> MEM_DQB7 AA30 IO,LVDS2J_6P,DQ8L IO,LVDS2L_6P,DQ0L D28 MEM_DQA7 <- QDR4 QKA_P0 17 MEM_DQ_ADDR_CMD[8:0]
MEM_DQSB_P0 Y32 IO,LVDS2J_6N,DQ8L IO,LVDS2L_6N,DQ0L B26 MEM_DQSA_P0
MEM_DQSB_N0 AA32 IO,LVDS2J_4P,DQS8L IO,LVDS2L_4P,DQS0L C26 MEM_DQSA_N0 17 MEM_DQS_ADDR_CMD_P
IO,LVDS2J_4N,DQSN8L IO,LVDS2L_4N,DQSN0L 17 MEM_DQS_ADDR_CMD_N
MEM_DQB8 AE31 F28 MEM_DQA15
MEM_DQB9 AE32 IO,LVDS2J_7P,DQ9L IO,LVDS2L_7P,DQ1L F27 MEM_DQA13
MEM_DQB10 AE30 IO,LVDS2J_7N,DQ9L IO,LVDS2L_7N,DQ1L G28 MEM_DQA12 8,17 MEM_DMA[3:0]
MEM_DQB11 AF30 IO,LVDS2J_8P,DQ9L IO,LVDS2L_8P,DQ1L G27 MEM_DMA1
MEM_DQB12 AG33 IO,LVDS2J_8N,DQ9L IO,LVDS2L_8N,DQ1L H25 MEM_DQA9 8,17 MEM_DQA[33:0]
B IO,LVDS2J_9P,DQ9L IO,LVDS2L_9P,DQ1L B
MEM_DQB14 AH33 G25 MEM_DQA8
MEM_DQB32 AF32 IO,LVDS2J_9N,DQ9L IO,LVDS2L_9N,DQ1L J28 MEM_DQA32 8,17 MEM_DQSA_P[3:0]
MEM_DQB13 AG32 IO,RZQ_2J,LVDS2J_11P,DQ9L IO,RZQ_2L,LVDS2L_11P,DQ1L K27 MEM_DQA14
IO,LVDS2J_11N,DQ9L IO,LVDS2L_11N,DQ1L 8,17 MEM_DQSA_N[3:0]
MEM_DQB18 W32 D31 MEM_DQA16
MEM_DQB17 W33 IO,LVDS2J_14P,DQ10L IO,LVDS2L_14P,DQ2L C31 MEM_DQA19 17 MEM_QKA_P[1:0]
MEM_DQB21 W35 IO,LVDS2J_14N,DQ10L IO,LVDS2L_14N,DQ2L E30 MEM_DQA21
MEM_DMB2 Y35 IO,LVDS2J_17P,DQ10L IO,LVDS2L_17P,DQ2L E31 MEM_DQA17
MEM_QKB_P1 V33 IO,LVDS2J_17N,DQ10L IO,LVDS2L_17N,DQ2L E29 MEM_QKA_P1 8,17 MEM_DMB[3:0]
QDR4 QKB_P1 -> MEM_DQB23 V34 IO,LVDS2J_18P,DQ10L IO,LVDS2L_18P,DQ2L D29 MEM_DQA23 <- QDR4 QKA_P1
MEM_DQSB_P2 AA34 IO,LVDS2J_18N,DQ10L IO,LVDS2L_18N,DQ2L C30 MEM_DQSA_P2 8,17 MEM_DQB[33:0]
MEM_DQSB_N2 AA33 IO,LVDS2J_16P,DQS10L IO,LVDS2L_16P,DQS2L C29 MEM_DQSA_N2
IO,LVDS2J_16N,DQSN10L IO,LVDS2L_16N,DQSN2L 8,17 MEM_DQSB_P[3:0]
MEM_DQB31 AD34 F30 MEM_DMA3
MEM_DMB3 AC34 IO,LVDS2J_19P,DQ11L IO,LVDS2L_19P,DQ3L F29 MEM_DQA31 8,17 MEM_DQSB_N[3:0]
MEM_DQB33 AB33 IO,LVDS2J_19N,DQ11L IO,LVDS2L_19N,DQ3L K29 MEM_DQA29
MEM_DQB30 AC33 IO,LVDS2J_20P,DQ11L IO,LVDS2L_20P,DQ3L J29 MEM_DQA30 17 MEM_QKB_P[1:0]
MEM_DQB28 AD35 IO,LVDS2J_20N,DQ11L IO,LVDS2L_20N,DQ3L K31 MEM_DQA27
MEM_DQB29 AE34 IO,LVDS2J_21P,DQ11L IO,LVDS2L_21P,DQ3L K30 MEM_DQA24
A IO,LVDS2J_21N,DQ11L IO,LVDS2L_21N,DQ3L A
MEM_DQB26 AJ33 G30 MEM_DQA26 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
MEM_DQB25 AJ34 IO,LVDS2J_23P,DQ11L IO,LVDS2L_23P,DQ3L G31 MEM_DQA33 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
MEM_DQB27 AH34 IO,LVDS2J_23N,DQ11L IO,LVDS2L_23N,DQ3L H29 MEM_DQA28 Title
MEM_DQB24 AH35 IO,LVDS2J_24P,DQ11L IO,LVDS2L_24P,DQ3L H30 MEM_DQA25 Arria 10 GX FPGA Development Kit
MEM_DQSB_P3 AF33 IO,LVDS2J_24N,DQ11L IO,LVDS2L_24N,DQ3L L30 MEM_DQSA_P3
MEM_DQSB_N3 AF34 IO,LVDS2J_22P,DQS11L IO,LVDS2L_22P,DQS3L L29 MEM_DQSA_N3 Size Document Number Rev
IO,LVDS2J_22N,DQSN11L IO,LVDS2L_22N,DQSN3L
B 150-0321301-E3 (6XX-44366R) E3.1
10AX115F1932C
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U28D Arria 10 Bank 3A-3D

ARRIA 10 - BANK 3A-3D
FM_D28 AP22 AU10 FMCA_SCL FLASH/FM BUS
IO,LVDS3A_1P,DQ60R IO,LVDS3C_1P,DQ52R
BANK-3C
BANK-3A
FM_D20 AP23 AV10 FMCA_SDA
FM_D16 AT25 IO,LVDS3A_1N,DQ60R IO,LVDS3C_1N,DQ52R AU11 FMCA_LA_TX_P9 13,14 FM_D[31:0]
FM_D27 AR25 IO,LVDS3A_2P,DQ60R IO,LVDS3C_2P,DQ52R AU12 FMCA_LA_TX_N9
FM_D26 AT23 IO,LVDS3A_2N,DQ60R IO,LVDS3C_2N,DQ52R AW13 FMCA_LA_TX_P4 13,14 FM_A[26:1]
E IO,LVDS3A_3P,DQ60R IO,LVDS3C_3P,DQ52R E
FM_D22 AT24 AV13 FMCA_LA_TX_N4
FM_D12 AP26 IO,LVDS3A_3N,DQ60R IO,LVDS3C_3N,DQ52R AV11 FMCA_LA_TX_P2 13,14 FLASH_CLK
FM_D15 AR26 IO,LVDS3A_5P,DQ60R IO,LVDS3C_5P,DQ52R AW11 FMCA_LA_TX_N2 13,14 FLASH_RESETn
VCCIO = 1.8V
FMCA VARIABLE VCCIO

(1.2V, 1.5V, 1.8V)
FM_D24 AU23 IO,LVDS3A_5N,DQ60R IO,LVDS3C_5N,DQ52R AY10 FMCA_LA_TX_P10 13,14 FLASH_CEn0
FM_D30 AU22 IO,LVDS3A_6P,DQ60R IO,LVDS3C_6P,DQ52R AY11 FMCA_LA_TX_N10 13,14 FLASH_CEn1
FM_D25 AR24 IO,LVDS3A_6N,DQ60R IO,LVDS3C_6N,DQ52R AW12 FMCA_LA_RX_P9 13,14 FLASH_OEn
DEFAULT 1.8V
FM_D19 AP24 IO,LVDS3A_4P,DQS60R IO,LVDS3C_4P,DQS52R AY12 FMCA_LA_RX_N9 13,14 FLASH_WEn
IO,LVDS3A_4N,DQSN60R IO,LVDS3C_4N,DQSN52R 13,14 FLASH_ADVn
FM_D14 BA25 AR9 FMCA_LA_TX_P7 13,14 FLASH_RDYBSYn0
FM_D4 AY25 IO,LVDS3A_7P,DQ61R IO,LVDS3C_7P,DQ53R AT9 FMCA_LA_TX_N7
FM_D6 AY24 IO,LVDS3A_7N,DQ61R IO,LVDS3C_7N,DQ53R AT13 FMCA_LA_RX_P6
FM_D13 BA24 IO,LVDS3A_8P,DQ61R IO,LVDS3C_8P,DQ53R AU13 FMCA_LA_RX_N6
FM_D2 AU25 IO,LVDS3A_8N,DQ61R IO,LVDS3C_8N,DQ53R AU8 FMCA_LA_RX_P8
IO,LVDS3A_9P,DQ61R IO,LVDS3C_9P,DQ53R FMC PORT A INTERFACE
FM_D7 AV25 AT8 FMCA_LA_RX_N8
FM_D11 AW22 IO,LVDS3A_9N,DQ61R IO,LVDS3C_9N,DQ53R AP14 RZQ_B3C R352 100, 1% 19 FMCA_LA_RX_P[14:0]
FLASH_RDYBSYn0 AY22 RZQ_3A,LVDS3A_11P,DQ61R IO,RZQ_3C,LVDS3C_11P,DQ53R AP13
IO,LVDS3A_11N,DQ61R IO,LVDS3C_11N,DQ53R 19 FMCA_LA_RX_N[14:0]
FLASH_ADVn BC25 BD13
FLASH_CLK BB25 IO,LVDS3A_14P,DQ62R IO,LVDS3C_14P,DQ54R BD12 19 FMCA_LA_TX_P[16:0]
D IO,LVDS3A_14N,DQ62R IO,LVDS3C_14N,DQ54R D
FLASH_WEn BD26 BC14
FLASH_OEn BC26 IO,LVDS3A_17P,DQ62R IO,LVDS3C_17P,DQ54R BD14 19 FMCA_LA_TX_N[16:0]
FM_D1 BA22 IO,LVDS3A_17N,DQ62R IO,LVDS3C_17N,DQ54R BC13
FLASH_CEn0 BB22 IO,LVDS3A_18P,DQ62R IO,LVDS3C_18P,DQ54R BB13 19 FMCA_GA[1:0]
FLASH_CEn1 BB23 IO,LVDS3A_18N,DQ62R IO,LVDS3C_18N,DQ54R BB12
FLASH_RESETn BA23 IO,LVDS3A_16P,DQS62R IO,LVDS3C_16P,DQS54R BB11
IO,LVDS3A_16N,DQSN62R IO,LVDS3C_16N,DQSN54R
FM_D3 BD21 BC16 FMCA_GA0 19 FMCA_3P3V_SDA
FM_D5 BD22 IO,LVDS3A_19P,DQ63R IO,LVDS3C_19P,DQ55R BB16 19 FMCA_3P3V_SCL
FM_D29 BC19 IO,LVDS3A_19N,DQ63R IO,LVDS3C_19N,DQ55R BD17
FM_D23 BD19 IO,LVDS3A_20P,DQ63R IO,LVDS3C_20P,DQ55R BD16 FMCA_GA1
FM_D17 BA19 IO,LVDS3A_20N,DQ63R IO,LVDS3C_20N,DQ55R BA15 FMCA_LA_RX_P12
IO,LVDS3A_21P,DQ63R IO,LVDS3C_21P,DQ55R ARRIA 10 USB INTERFACE
FM_D18 BA20 BA14 FMCA_LA_RX_N12
FM_D8 BC21 IO,LVDS3A_21N,DQ63R IO,LVDS3C_21N,DQ55R BC18 FMCA_LA_TX_P15 26 USB_DATA[7:0]
FM_D9 BB21 IO,LVDS3A_23P,DQ63R IO,LVDS3C_23P,DQ55R BD18 FMCA_LA_TX_N15
FM_D10 BC20 IO,LVDS3A_23N,DQ63R IO,LVDS3C_23N,DQ55R BB17 FMCA_LA_RX_P13 26 USB_ADDR[1:0]
FM_D0 BB20 IO,LVDS3A_24P,DQ63R IO,LVDS3C_24P,DQ55R BB18 FMCA_LA_RX_N13
FM_D31 BA17 IO,LVDS3A_24N,DQ63R IO,LVDS3C_24N,DQ55R BB15 FMCA_LA_TX_P12 26 USB_RESETn
FM_D21 BA18 IO,LVDS3A_22P,DQS63R IO,LVDS3C_22P,DQS55R BC15 FMCA_LA_TX_N12 26 USB_OEn
C IO,LVDS3A_22N,DQSN63R IO,LVDS3C_22N,DQSN55R C
26 USB_RDn
FMCA_LA_RX_P4 AR16 AJ11 USB_DATA0 26 USB_WRn
IO,LVDS3B_1P,DQ56R IO,LVDS3D_1P,DQ48R
BANK-3D
BANK-3B
FMCA_LA_RX_N4 AP16 AK12 USB_DATA1

FMCA_LA_TX_P11 AU18 IO,LVDS3B_1N,DQ56R IO,LVDS3D_1N,DQ48R AL12 FM_A3
FMCA_LA_TX_N11 AT18 IO,LVDS3B_2P,DQ56R IO,LVDS3D_2P,DQ48R AL13 FM_A11
FMCA_LA_TX_P3 AT17 IO,LVDS3B_2N,DQ56R IO,LVDS3D_2N,DQ48R AK14 FM_A25
FMCA_LA_TX_N3 AU17 IO,LVDS3B_3P,DQ56R IO,LVDS3D_3P,DQ48R AJ14 FM_A20
FMCA_LA_TX_P5 AT14 IO,LVDS3B_3N,DQ56R IO,LVDS3D_3N,DQ48R AH10 FM_A15
FMCA VARIABLE VCCIO
(1.2V, 1.5V, 1.8V)
FMCA_LA_TX_N5 AR14 IO,LVDS3B_5P,DQ56R IO,LVDS3D_5P,DQ48R AH11 FM_A12

VCCIO = 1.8V
FMCA_LA_RX_P3 AR15 IO,LVDS3B_5N,DQ56R IO,LVDS3D_5N,DQ48R AJ12 FM_A19 3.3V 1.8V

FMCA_LA_RX_N3 AT15 IO,LVDS3B_6P,DQ56R IO,LVDS3D_6P,DQ48R AJ13 FM_A23
DEFAULT 1.8V
FMCA_LA_TX_P6 AR17 IO,LVDS3B_6N,DQ56R IO,LVDS3D_6N,DQ48R AH13 FM_A21

FMCA_LA_TX_N6 AP17 IO,LVDS3B_4P,DQS56R IO,LVDS3D_4P,DQS48R AH14 FM_A18
IO,LVDS3B_4N,DQSN56R IO,LVDS3D_4N,DQSN48R
FMCA_LA_RX_P14 AY17 AF12 FM_A24
FMCA_LA_RX_N14 AW17 IO,LVDS3B_7P,DQ57R IO,LVDS3D_7P,DQ49R AE12 FM_A6 U79
3.3V to 1.8V R662 R661 R659 R660 C794
FMCA_LA_RX_P1 AV14 IO,LVDS3B_7N,DQ57R IO,LVDS3D_7N,DQ49R AG12 FM_A22 12 11 10.0K 10.0K 10.0K 10.0K 0.1uF
FMCA_LA_RX_N1 AW14 IO,LVDS3B_8P,DQ57R IO,LVDS3D_8P,DQ49R AG11 FM_A14 R657 R658 C795 VCC VCC2
FMCA_LA_TX_P14 AY16 IO,LVDS3B_8N,DQ57R IO,LVDS3D_8N,DQ49R AF14 FM_A16 10.0K 10.0K 0.01uF 2 7
B IO,LVDS3B_9P,DQ57R IO,LVDS3D_9P,DQ49R DISCEN READY B
FMCA_LA_TX_N14 AW16 AF15 FM_A17 1 8
FMCA_LA_RX_P10 AY15 IO,LVDS3B_9N,DQ57R IO,LVDS3D_9N,DQ49R AE14 USB_RESETn ENABLE FAULTn
FMCA_LA_RX_N10 AY14 IO,RZQ_3B,LVDS3B_11P,DQ57R IO,RZQ_3D,LVDS3D_11P,DQ49R AE15 USB_WRn
IO,LVDS3B_11N,DQ57R IO,LVDS3D_11N,DQ49R FMCA_3P3V_SCL 4 3 FMCA_SCL
FMCA_LA_RX_P5 AW18 AL15 USB_OEn FMCA_3P3V_SDA 9 SCLIN SCLOUT 10 FMCA_SDA
FMCA_LA_RX_N5 AV18 IO,LVDS3B_14P,DQ58R IO,LVDS3D_14P,DQ50R AK15 USB_RDn SDAIN SDAOUT
FMCA_LA_TX_P8 AV19 IO,LVDS3B_14N,DQ58R IO,LVDS3D_14N,DQ50R AL19 USB_DATA6
FMCA_LA_TX_N8 AW19 IO,LVDS3B_17P,DQ58R IO,LVDS3D_17P,DQ50R AL20 USB_DATA7 5 6
FMCA_LA_TX_P16 AV20 IO,LVDS3B_17N,DQ58R IO,LVDS3D_17N,DQ50R AM17 USB_DATA4 ACCn GND
FMCA_LA_TX_N16 AU20 IO,LVDS3B_18P,DQ58R IO,LVDS3D_18P,DQ50R AL17 USB_DATA5 LTC4315
FMCA_LA_RX_P7 AU21 IO,LVDS3B_18N,DQ58R IO,LVDS3D_18N,DQ50R AM15 USB_ADDR0
FMCA_LA_RX_N7 AV21 IO,LVDS3B_16P,DQS58R IO,LVDS3D_16P,DQS50R AL14 USB_ADDR1
FMCA_LA_TX_P13 AT19 AN11 USB_DATA2
FMCA_LA_TX_N13 AT20 IO,LVDS3B_19P,DQ59R IO,LVDS3D_19P,DQ51R AN10 USB_DATA3
FMCA_LA_RX_P11 AP21 IO,LVDS3B_19N,DQ59R IO,LVDS3D_19N,DQ51R AL10 FM_A8
FMCA_LA_RX_N11 AR21 IO,LVDS3B_20P,DQ59R IO,LVDS3D_20P,DQ51R AK11 FM_A26
FMCA_LA_RX_P2 AP18 IO,LVDS3B_20N,DQ59R IO,LVDS3D_20N,DQ51R AN13 FM_A4
FMCA_LA_RX_N2 AN19 IO,LVDS3B_21P,DQ59R IO,LVDS3D_21P,DQ51R AM13 FM_A5
A IO,LVDS3B_21N,DQ59R IO,LVDS3D_21N,DQ51R A
FMCA_LA_RX_P0 AR20 AP11 FM_A10 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
FMCA_LA_RX_N0 AR19 IO,LVDS3B_23P,DQ59R IO,LVDS3D_23P,DQ51R AR10 FM_A9 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
FMCA_LA_TX_P0 AR22 IO,LVDS3B_23N,DQ59R IO,LVDS3D_23N,DQ51R AM12 FM_A2 Title
FMCA_LA_TX_N0 AT22 IO,LVDS3B_24P,DQ59R IO,LVDS3D_24P,DQ51R AM11 FM_A1 Arria 10 GX FPGA Development Kit
FMCA_LA_TX_P1 AN20 IO,LVDS3B_24N,DQ59R IO,LVDS3D_24N,DQ51R AN15 FM_A7
FMCA_LA_TX_N1 AP19 IO,LVDS3B_22P,DQS59R IO,LVDS3D_22P,DQS51R AN14 FM_A13 Size Document Number Rev
B 150-0321301-E3 (6XX-44366R) E3.1
10AX115F1932C
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U28E Arria 10 Bank 3E-3H

ARRIA 10 - BANK 3E-3H MAX V INTERFACE
USER IO INTERFACE
FMCB_RX_LED R12 K22 FMCB_GA0 13 MAX5_BEn[3:0]
R11 IO,LVDS3E_1P,DQ44R IO,LVDS3G_1P,DQ36R L22 FMCB_GA1 24 USER_DIPSW[7:0]
IO,LVDS3E_1N,DQ44R IO,LVDS3G_1N,DQ36R
BANK-3E
BANK-3G
VID4 N10 K20 FMCB_LA_TX_P14 13 MAX5_OEn
VID5 M10 IO,LVDS3E_2P,DQ44R IO,LVDS3G_2P,DQ36R L19 FMCB_LA_TX_N14 24 USER_LED_G[7:0] 13 MAX5_CSn
VID3 L12 IO,LVDS3E_2N,DQ44R IO,LVDS3G_2N,DQ36R J19 FMCB_LA_TX_P2 13 MAX5_WEn
E IO,LVDS3E_3P,DQ44R IO,LVDS3G_3P,DQ36R E
VID1 M11 K19 FMCB_LA_TX_N2 24 USER_LED_R[7:0]
N13 IO,LVDS3E_3N,DQ44R IO,LVDS3G_3N,DQ36R L20 FMCB_LA_TX_P15
N14 IO,LVDS3E_5P,DQ44R IO,LVDS3G_5P,DQ36R K21 FMCB_LA_TX_N15 24 USER_PB[2:0]
FMCB VARIABLE VCCIO

(1.2V, 1.5V, 1.8V)
VID2 N11 IO,LVDS3E_5N,DQ44R IO,LVDS3G_5N,DQ36R M21 FMCB_LA_RX_P14 FMC PORT A INTERFACE
VCCIO = 1.8V
P11 IO,LVDS3E_6P,DQ44R IO,LVDS3G_6P,DQ36R M20 FMCB_LA_RX_N14
P13 IO,LVDS3E_6N,DQ44R IO,LVDS3G_6N,DQ36R J22 FMCB_LA_TX_P16 13,19,24,26 FMCA_PRSNTn
DEFAULT 1.8V
FMCA_TX_LED P12 IO,LVDS3E_4P,DQS44R IO,LVDS3G_4P,DQS36R J21 FMCB_LA_TX_N16 35 VID[5:0]
IO,LVDS3E_4N,DQSN44R IO,LVDS3G_4N,DQSN36R
FMCB_PRSNTn P17 H20 FMCB_LA_RX_P8 7,35 VID_EN FMC PORT B INTERFACE
FMCA_PRSNTn P16 IO,LVDS3E_7P,DQ45R IO,LVDS3G_7P,DQ37R G20 FMCB_LA_RX_N8
N16 IO,LVDS3E_7N,DQ45R IO,LVDS3G_7N,DQ37R G21 FMCB_LA_RX_P1 20 FMCB_LA_RX_P[14:0]
N15 IO,LVDS3E_8P,DQ45R IO,LVDS3G_8P,DQ37R H21 FMCB_LA_RX_N1 9 A10_SI516_FS
T14 IO,LVDS3E_8N,DQ45R IO,LVDS3G_8N,DQ37R H19 FMCB_LA_RX_P9 20 FMCB_LA_RX_N[14:0]
R15 IO,LVDS3E_9P,DQ45R IO,LVDS3G_9P,DQ37R H18 FMCB_LA_RX_N9
100, 1% R368 RZQ_B3E V14 IO,LVDS3E_9N,DQ45R IO,LVDS3G_9N,DQ37R F19 RZQ_B3G R382 100, 1% 20 FMCB_LA_TX_P[16:0]
W14 IO,RZQ_3E,LVDS3E_11P,DQ45R IO,RZQ_3G,LVDS3G_11P,DQ37R E19
IO,LVDS3E_11N,DQ45R IO,LVDS3G_11N,DQ37R 20 FMCB_LA_TX_N[16:0]
MAX5_CSn AD14 H14
MAX5_BEn2 AD13 IO,LVDS3E_14P,DQ46R IO,LVDS3G_14P,DQ38R H15 20 FMCB_GA[1:0]
D IO,LVDS3E_14N,DQ46R IO,LVDS3G_14N,DQ38R D
FMCA_RX_LED Y10 E14
MAX5_BEn1 Y11 IO,LVDS3E_17P,DQ46R IO,LVDS3G_17P,DQ38R F14
MAX5_BEn0 AB13 IO,LVDS3E_17N,DQ46R IO,LVDS3G_17N,DQ38R G16 13,20,24,26 FMCB_PRSNTn
MAX5_OEn AA14 IO,LVDS3E_18P,DQ46R IO,LVDS3G_18P,DQ38R G15 20 FMCB_3P3V_SDA
MAX5_BEn3 AC13 IO,LVDS3E_18N,DQ46R IO,LVDS3G_18N,DQ38R F15 20 FMCB_3P3V_SCL
MAX5_WEn AB12 IO,LVDS3E_16P,DQS46R IO,LVDS3G_16P,DQS38R E15
IO,LVDS3E_16N,DQSN46R IO,LVDS3G_16N,DQSN38R
A10_SI516_FS R946 DNI V13 J17 FMCB_SCL USER I/O INTERFACE
W13 IO,LVDS3E_19P,DQ47R IO,LVDS3G_19P,DQ39R J18
USER_PB2 U11 IO,LVDS3E_19N,DQ47R IO,LVDS3G_19N,DQ39R H16 24 FMCA_RX_LED
T10 IO,LVDS3E_20P,DQ47R IO,LVDS3G_20P,DQ39R J16 FMCB_SDA 24 FMCA_TX_LED
USER_PB1 U12 IO,LVDS3E_20N,DQ47R IO,LVDS3G_20N,DQ39R L18 FMCB_LA_RX_P13
USER_PB0 T12 IO,LVDS3E_21P,DQ47R IO,LVDS3G_21P,DQ39R M18 FMCB_LA_RX_N13 24 FMCB_RX_LED
Y14 IO,LVDS3E_21N,DQ47R IO,LVDS3G_21N,DQ39R M16 FMCB_LA_RX_P12 24 FMCB_TX_LED
Y15 IO,LVDS3E_23P,DQ47R IO,LVDS3G_23P,DQ39R M17 FMCB_LA_RX_N12
W12 IO,LVDS3E_23N,DQ47R IO,LVDS3G_23N,DQ39R M15 FMCB_LA_TX_P13
FMCB_TX_LED W11 IO,LVDS3E_24P,DQ47R IO,LVDS3G_24P,DQ39R L15 FMCB_LA_TX_N13
IO,LVDS3E_24N,DQ47R IO,LVDS3G_24N,DQ39R ARRIA 10 CLOCKS
V11 K16 FMCB_LA_TX_P10
VID0 W10 IO,LVDS3E_22P,DQS47R IO,LVDS3G_22P,DQS39R K17 FMCB_LA_TX_N10 9 SDI_CLK148_UP
C IO,LVDS3E_22N,DQSN47R IO,LVDS3G_22N,DQSN39R C
9 SDI_CLK148_DOWN
FMCB_LA_RX_P0 D17 B20 USER_LED_R4
IO,LVDS3F_1P,DQ40R IO,LVDS3H_1P,DQ32R
BANK-3H
BANK-3F
FMCB_LA_RX_N0 D16 C20

FMCB_LA_RX_P5 B16 IO,LVDS3F_1N,DQ40R IO,LVDS3H_1N,DQ32R D18 USER_LED_G7
FMCB_LA_RX_N5 C16 IO,LVDS3F_2P,DQ40R IO,LVDS3H_2P,DQ32R C18 USER_LED_G6
FMCB_LA_TX_P1 C15 IO,LVDS3F_2N,DQ40R IO,LVDS3H_2N,DQ32R D19 USER_LED_R6
FMCB_LA_TX_N1 B15 IO,LVDS3F_3P,DQ40R IO,LVDS3H_3P,DQ32R C19 USER_LED_R5 3.3V 1.8V
FMCB_LA_TX_P0 A17 IO,LVDS3F_3N,DQ40R IO,LVDS3H_3N,DQ32R A22 USER_DIPSW4
FMCB VARIABLE VCCIO
(1.2V, 1.5V, 1.8V)
FMCB_LA_TX_N0 B17 IO,LVDS3F_5P,DQ40R IO,LVDS3H_5P,DQ32R B22 USER_DIPSW3

VCCIO = 1.8V
FMCB_LA_TX_P4 A15 IO,LVDS3F_5N,DQ40R IO,LVDS3H_5N,DQ32R B21 USER_DIPSW5

FMCB_LA_TX_N4 A14 IO,LVDS3F_6P,DQ40R IO,LVDS3H_6P,DQ32R C21 USER_DIPSW6
DEFAULT 1.8V
FMCB_LA_RX_P3 A18 IO,LVDS3F_6N,DQ40R IO,LVDS3H_6N,DQ32R A20 USER_DIPSW7

FMCB_LA_RX_N3 B18 IO,LVDS3F_4P,DQS40R IO,LVDS3H_4P,DQS32R A19 USER_LED_G5 U80
3.3V to 1.8V R668 R667 R665 R666 C796
IO,LVDS3F_4N,DQSN40R IO,LVDS3H_4N,DQSN32R 12 11 10.0K 10.0K 10.0K 10.0K 0.1uF
FMCB_LA_RX_P2 A13 A23 USER_DIPSW2 R664 R663 C797 VCC VCC2
FMCB_LA_RX_N2 B13 IO,LVDS3F_7P,DQ41R IO,LVDS3H_7P,DQ33R B23 USER_DIPSW1 10.0K 10.0K 0.01uF 2 7
FMCB_LA_TX_P6 B12 IO,LVDS3F_7N,DQ41R IO,LVDS3H_7N,DQ33R A25 1 DISCEN READY 8
FMCB_LA_TX_N6 A12 IO,LVDS3F_8P,DQ41R IO,LVDS3H_8P,DQ33R A24 USER_DIPSW0 ENABLE FAULTn
FMCB_LA_RX_P4 D12 IO,LVDS3F_8N,DQ41R IO,LVDS3H_8N,DQ33R D21
B IO,LVDS3F_9P,DQ41R IO,LVDS3H_9P,DQ33R B
FMCB_LA_RX_N4 D11 D22 FMCB_3P3V_SCL 4 3 FMCB_SCL
FMCB_LA_TX_P3 D13 IO,LVDS3F_9N,DQ41R IO,LVDS3H_9N,DQ33R D24 FMCB_3P3V_SDA 9 SCLIN SCLOUT 10 FMCB_SDA
FMCB_LA_TX_N3 C13 IO,RZQ_3F,LVDS3F_11P,DQ41R IO,RZQ_3H,LVDS3H_11P,DQ33R C24 VID_EN SDAIN SDAOUT
IO,LVDS3F_11N,DQ41R IO,LVDS3H_11N,DQ33R
FMCB_LA_RX_P11 K14 E22 SDI_CLK148_UP 5 6
FMCB_LA_RX_N11 J14 IO,LVDS3F_14P,DQ42R IO,LVDS3H_14P,DQ34R E21 SDI_CLK148_DOWN ACCn GND
FMCB_LA_TX_P11 H13 IO,LVDS3F_14N,DQ42R IO,LVDS3H_14N,DQ34R F25 LTC4315
FMCB_LA_TX_N11 J13 IO,LVDS3F_17P,DQ42R IO,LVDS3H_16P,DQS34R E25
FMCB_LA_RX_P10 M12 IO,LVDS3F_17N,DQ42R IO,LVDS3H_16N,DQSN34R F22
FMCB_LA_RX_N10 L13 IO,LVDS3F_18P,DQ42R IO,LVDS3H_17P,DQ34R G22
FMCB_LA_TX_P12 M13 IO,LVDS3F_18N,DQ42R IO,LVDS3H_17N,DQ34R H23
FMCB_LA_TX_N12 L14 IO,LVDS3F_16P,DQS42R IO,LVDS3H_18P,DQ34R H24
IO,LVDS3F_16N,DQSN42R IO,LVDS3H_18N,DQ34R
FMCB_LA_TX_P8 F13 J24 USER_LED_G4
FMCB_LA_TX_N8 G13 IO,LVDS3F_19P,DQ43R IO,LVDS3H_19P,DQ35R J23
FMCB_LA_RX_P7 G11 IO,LVDS3F_19N,DQ43R IO,LVDS3H_19N,DQ35R L25 USER_LED_G3
FMCB_LA_RX_N7 G12 IO,LVDS3F_20P,DQ43R IO,LVDS3H_20P,DQ35R K25 USER_LED_G2
FMCB_LA_TX_P5 E11 IO,LVDS3F_20N,DQ43R IO,LVDS3H_20N,DQ35R K26 USER_LED_G1
FMCB_LA_TX_N5 E10 IO,LVDS3F_21P,DQ43R IO,LVDS3H_21P,DQ35R J26 USER_LED_R1
A IO,LVDS3F_21N,DQ43R IO,LVDS3H_21N,DQ35R A
FMCB_LA_RX_P6 E12 L23 USER_LED_R3 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
FMCB_LA_RX_N6 F12 IO,LVDS3F_23P,DQ43R IO,LVDS3H_23P,DQ35R M23 USER_LED_R7 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
FMCB_LA_TX_P9 H11 IO,LVDS3F_23N,DQ43R IO,LVDS3H_23N,DQ35R L27 USER_LED_R0 Title
FMCB_LA_TX_N9 H10 IO,LVDS3F_24P,DQ43R IO,LVDS3H_24P,DQ35R L28 USER_LED_G0 Arria 10 GX FPGA Development Kit
FMCB_LA_TX_P7 G10 IO,LVDS3F_24N,DQ43R IO,LVDS3H_24N,DQ35R L24
FMCB_LA_TX_N7 F10 IO,LVDS3F_22P,DQS43R IO,LVDS3H_22P,DQS35R K24 USER_LED_R2 Size Document Number Rev
IO,LVDS3F_22N,DQSN43R IO,LVDS3H_22N,DQSN35R
B 150-0321301-E3 (6XX-44366R) E3.1
10AX115F1932C
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Arria 10 Configuration
FPGA_nCONFIG
A10_VCCIO_1.8V Pull-up not needed for FPP.
FPGA_DCLK R405 DNI C565 DNI Pull-up needed for AS.
R422 10.0K FPGA_nCONFIG
E E
R404 R427 DNI
R412 1.00k FPGA_nIO_PULLUP
DNI
A10_VCCIO_1.8V
U28A
ARRIA 10 CONFIGURATION
MSEL0 13 AN26 BANK CSS AM21 26 A10_JTAG_TCK
MSEL1 13 AL28 MSEL0 TCK AN21 26 A10_JTAG_TDI
MSEL2 13 AK25 MSEL1 TDI AL29 26 A10_JTAG_TDO
MSEL2 TDO AL24 26 A10_JTAG_TMS
FPGA_DCLK 13,14 AM26 TMS AL30 FPGA_TRST 1.00k R436
DCLK TRST
FPGA_nCONFIG 13 AK30 AL27 14 FPGA_AS_DATA0
FPGA_nIO_PULLUP AN24 nCONFIG AS_DATA0,ASDO AL22 14 FPGA_AS_DATA1
R402 1.00k FPGA_nCE AM25 nIO_PULLUP AS_DATA1 AM20 14 FPGA_AS_DATA2
nCE AS_DATA2 AL25 14 FPGA_AS_DATA3
AS_DATA3
FPGA_CONFIG_D[31:0] 13 BANK 2A AM23 14 FPGA_nCSO A10_VCCIO_1.8V
FPGA_CONFIG_D0 AU27 nCSO0 AN25
D LVDS2A_1n,DQ28L,DATA0 nCSO1 D
FPGA_CONFIG_D1 AU28 AM27 10.0K R426
FPGA_CONFIG_D2 AP28 LVDS2A_1p,DQ28L,DATA1 nCSO2 10.0K R423
CvP CLKUSR 100MHz
FPGA_CONFIG_D3 AR29 LVDS2A_2n,DQ28L,DATA2 13,35
AP27 FPGA_CONF_DONE A10_VCCIO_1.8V A10_VCCIO_1.8V
FPGA_CONFIG_D4 AT28 LVDS2A_2p,DQ28L,DATA3 CONF_DONE AN2913 FPGA_nSTATUS
FPGA_CONFIG_D5 AT29 LVDS2A_3n,DQ28L,DATA4 nSTATUS C175 0.01uF
FPGA_CONFIG_D6 AW27 LVDS2A_3p,DQ28L,DATA5 X7
FPGA_CONFIG_D7 AY27 LVDS2A_4n,DQSn28L,DATA6 4 1
FPGA_CONFIG_D8 AY26 LVDS2A_4p,DQS28L,DATA7 VCC EN
FPGA_CONFIG_D9 AW26 LVDS2A_5n,DQ28L,DATA8 BD32 A10_CVP_100M 3 2
FPGA_CONFIG_D10 AV26 LVDS2A_5p,DQ28L,DATA9 LVDS2A_18n,DQ30L,CLKUSR OUT GND
FPGA_CONFIG_D11 AU26 LVDS2A_6n,DQ28L,DATA10 BD29 3 PCIE_SMBCLK 100MHz
FPGA_CONFIG_D12 AV29 LVDS2A_6p,DQ28L,DATA11 LVDS2A_23p,DQ31L,DEV_OE BD27
13,24 CPU_RESETn
FPGA_CONFIG_D13 AV30 LVDS2A_7n,DQ29L,DATA12 LVDS2A_24p,DQ31L,DEV_CLRn
FPGA_CONFIG_D14 AV31 LVDS2A_7p,DQ29L,DATA13
FPGA_CONFIG_D15 AW31 LVDS2A_8n,DQ29L,DATA14
LVDS2A_8p,DQ29L,DATA15 BC2924 PCIE_LED_G3
FPGA_CONFIG_D16 AW28 LVDS2A_23n,DQ31L,INIT_DONE BD2824 PCIE_LED_X8
FPGA_CONFIG_D17 AV28 LVDS2A_9n,DQ29L,DATA16 LVDS2A_24n,DQ31L,CRCERROR AY29 3 PCIE_WAKEn
FPGA_CONFIG_D18 AY31 LVDS2A_9p,DQ29L,DATA17 LVDS2A_11n,DQ29L,nCEO
C PLL_2A_CLKOUT1n,DQSn29L,DATA18 C
FPGA_CONFIG_D19 AY30
FPGA_CONFIG_D20 BA29 PLL_2A_CLKOUT1p,DQS29L,DATA19 BC30 3 PCIE_PERSTn
FPGA_CONFIG_D21 BA30 CLK_2A_1n,DQ29L,DATA20 LVDS2A_19p,DQ31L,nPERSTL0 BC2824 PCIE_LED_G2
FPGA_CONFIG_D22 BA32 CLK_2A_1p,DQ29L,DATA21 LVDS2A_20p,DQ31L,nPERSTL1 BB2724 PCIE_LED_X4
FPGA_CONFIG_D23 BB32 CLK_2A_0n,DQ30L,DATA22 LVDS2A_22p,DQS31L,nPERSTR0 BA2724 PCIE_LED_X1
FPGA_CONFIG_D24 BA33 CLK_2A_0p,DQ30L,DATA23 LVDS2A_21p,DQ31L,nPERSTR1 BB26
13 FPGA_CvP_CONFDONE
FPGA_CONFIG_D25 BB33 LVDS2A_14n,DQ30L,DATA24 LVDS2A_22n,DQSn31L,CvP_CONFDONE
FPGA_CONFIG_D26 BB31 LVDS2A_14p,DQ30L,DATA25
FPGA_CONFIG_D27 BC31 PLL_2A_CLKOUT0n,DQ30L,DATA26 BB28
13 FPGA_PR_DONE
FPGA_CONFIG_D28 BC33 PLL_2A_CLKOUT0p,DQ30L,DATA27 LVDS2A_20n,DQ31L,PR_DONE BD31
13 FPGA_PR_REQUEST
FPGA_CONFIG_D29 BD33 LVDS2A_16n,DQSn30L,DATA28 LVDS2A_18p,DQ30L,PR_REQUEST BB30
13 FPGA_PR_READY
FPGA_CONFIG_D30 BA34 LVDS2A_16p,DQS30L,DATA29 LVDS2A_19n,DQ31L,PR_READY BA28
13 FPGA_PR_ERROR
FPGA_CONFIG_D31 BB35 LVDS2A_17n,DQ30L,DATA30 LVDS2A_21n,DQ31L,PR_ERROR
LVDS2A_17p,DQ30L,DATA31 AW29
35 FPGA_VID_EN
RZQ_2A,LVDS2A_11p,DQ29L
R424 1.00k
TEMPDIODE_P 29 N20
TEMPDIODE_N 29 N21 TEMPDIODEp CORE
TEMPDIODEn
B B
10AX115F1932C
A10_VCCIO_1.8V A10_VCCIO_1.8V
SW5
8 1 MSEL0 R475 1.00k FPGA_CvP_CONFDONE 10.0K R392
7 2 MSEL1 R476 1.00k
OPEN
6 3 MSEL2 R489 1.00k FPGA_PR_DONE 10.0K R410

5 4 VID_EN R490 1.00k FPGA_PR_READY 10.0K R425
FPGA_PR_ERROR 10.0K R411
DIPSWITCH4 6,35 VID_EN
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ETHERNET INTERFACE
U28B
Arria 10 Clocks 15
15
ENET_RX_P
ENET_RX_N
ARRIA 10 CONFIGURATION 15 ENET_TX_P
15 ENET_TX_N
BANK-2I 15 ENET_RESETn
CLK_50 AU33 AT32 15 ENET_MDIO
AT33 CLK_2I_0P,DQ14L VCCIO = 1.8V PLL_2I_CLKOUT0P,DQ14L AU32 15 ENET_MDC
R450 100, 1% CLK_FPGA_B2_P AR36 CLK_2I_0N,DQ14L PLL_2I_CLKOUT0N,DQ14L AN33 15 ENET_INTn
E CLK_2I_1P,DQ13L PLL_2I_CLKOUT1P,DQS13L E
CLK_FPGA_B2_N AR37 AM33
CAN BE REMOVED FOR ARRIA 10 AND USE OCT -> CLK_2I_1N,DQ13L PLL_2I_CLKOUT1N,DQSn13L
MEMORY INTERFACE
4,17 MEM_ADDR_CMD[31:0]
BANK-2J
MEM_DQB16 U31 W34 MEM_DQB22
MEM_DQB19 V31 CLK_2J_0P,DQ10L VARIABLE EMI VCCIO PLL_2J_CLKOUT0P,DQ10L Y34 MEM_DQB20 4,17 MEM_DMA[3:0]
MEM_DMB1 AG31 CLK_2J_0N,DQ10L (1.2V, 1.35V, 1.5V) PLL_2J_CLKOUT0N,DQ10L AJ32 MEM_DQSB_P1
MEM_DQB15 AH31 CLK_2J_1P,DQ9L PLL_2J_CLKOUT1P,DQS9L AJ31 MEM_DQSB_N1 4,17 MEM_DQA[33:0]
CLK_2J_1N,DQ9L PLL_2J_CLKOUT1N,DQSn9L
4,17 MEM_DQSA_P[3:0]
BANK-2K 4,17 MEM_DQSA_N[3:0]
MEM_ADDR_CMD10 H31 M33 MEM_ADDR_CMD6
MEM_ADDR_CMD11 J31 CLK_2K_0P,DQ6L VARIABLE EMI VCCIO PLL_2K_CLKOUT0P,DQ6L L33 MEM_ADDR_CMD7
R448 100, 1% CLK_EMI_P F34 CLK_2K_0N,DQ6L (1.2V, 1.35V, 1.5V) PLL_2K_CLKOUT0N,DQ6L H33 MEM_ADDR_CMD13 4,17 MEM_DMB[3:0]
CLK_EMI_N F35 CLK_2K_1P,DQ5L PLL_2K_CLKOUT1P,DQS5L G32 MEM_ADDR_CMD14
CLK_2K_1N,DQ5L PLL_2K_CLKOUT1N,DQSn5L 4,17 MEM_DQB[33:0]
4,17 MEM_DQSB_P[3:0]
BANK-2L
D
MEM_DQA20 A30 B31 MEM_DQA18 D
MEM_DMA2 A29 CLK_2L_0P,DQ2L VARIABLE EMI VCCIO PLL_2L_CLKOUT0P,DQ2L B30 MEM_DQA22 4,17 MEM_DQSB_N[3:0]
MEM_DQA10 G26 CLK_2L_0N,DQ2L (1.2V, 1.35V, 1.5V) PLL_2L_CLKOUT0N,DQ2L H28 MEM_DQSA_P1
MEM_DQA11 H26 CLK_2L_1P,DQ1L PLL_2L_CLKOUT1P,DQS1L J27 MEM_DQSA_N1
CLK_2L_1N,DQ1L PLL_2L_CLKOUT1N,DQSn1L ARRIA 10 CLOCKS
9 CLK_50
BANK-3A 9 CLK_125_P
R403 100, 1% CLK_125_P BD24 BC23 ENET_TX_P 9 CLK_125_N
CAN BE REMOVED FOR ARRIA 10 AND USE OCT -> CLK_125_N BC24 CLK_3A_0P,DQ62R VCCIO = 1.8VPLL_3A_CLKOUT0P,DQ62R BD23 ENET_TX_N 9 CLK_FPGA_B2_P
R406 100, 1% ENET_RX_P AV24 CLK_3A_0N,DQ62R PLL_3A_CLKOUT0N,DQ62R AW23 ENET_RESETn 9 CLK_FPGA_B2_N
CAN BE REMOVED FOR ARRIA 10 AND USE OCT -> ENET_RX_N AW24 CLK_3A_1P,DQ61R PLL_3A_CLKOUT1P,DQS61R AV23 FLASH_RDYBSYn1 9 CLK_FPGA_B3_P
CLK_3A_1N,DQ61R PLL_3A_CLKOUT1N,DQSn61R 9 CLK_FPGA_B3_N
10 CLK_EMI_P
BANK-3B 10 CLK_EMI_N
R383 100, 1% FMCA_CLK_M2C_P0 AY20 AW21
FMCA_CLK_M2C_N0 AY19 CLK_3B_0P,DQ58R FMCA VARIABLE VCCIO PLL_3B_CLKOUT0P,DQ58R AY21
R369 100, 1% FMCA_LA_RX_CLK_P0 AV15 CLK_3B_0N,DQ58R DEFAULT 1.8V PLL_3B_CLKOUT0N,DQ58R AV16
FMCA_LA_RX_CLK_N0 AU15 CLK_3B_1P,DQ57R (1.2V, 1.5V, 1.8V)PLL_3B_CLKOUT1P,DQS57R AU16
CLK_3B_1N,DQ57R PLL_3B_CLKOUT1N,DQSn57R
C C
BANK-3C
R353 100, 1% FMCA_CLK_M2C_P1 BA12 BB10
FMCA_CLK_M2C_N1 BA13 CLK_3C_0P,DQ54R FMCA VARIABLE VCCIO PLL_3C_CLKOUT0P,DQ54R BA10
R336 100, 1% FMCA_LA_RX_CLK_P1 AT10 CLK_3C_0N,DQ54R DEFAULT 1.8V PLL_3C_CLKOUT0N,DQ54R AP12
FMCA_LA_RX_CLK_N1 AR11 CLK_3C_1P,DQ53R (1.2V, 1.5V, 1.8V)PLL_3C_CLKOUT1P,DQS53R AR12
CLK_3C_1N,DQ53R PLL_3C_CLKOUT1N,DQSn53R FLASH INTERFACE
13,14 FLASH_RDYBSYn1
BANK-3D FMC PORT A INTERFACE

USB_FPGA_CLK AM18 AM16 USB_FULL
ENET_MDIO AL18 CLK_3D_0P,DQ50R VCCIO = 1.8V PLL_3D_CLKOUT0P,DQ50R AN16 USB_EMPTY 19 FMCA_CLK_M2C_P[1:0]
ENET_MDC AF13 CLK_3D_0N,DQ50R PLL_3D_CLKOUT0N,DQ50R AE11 USB_SCL
ENET_INTn AG13 CLK_3D_1P,DQ49R PLL_3D_CLKOUT1P,DQS49R AD12 USB_SDA 19 FMCA_CLK_M2C_N[1:0]
CLK_3D_1N,DQ49R PLL_3D_CLKOUT1N,DQSn49R
A10_VCCIO_1.8V 19 FMCA_LA_RX_CLK_P[1:0]
BANK-3E S5_MSEL3 R305 DNI
MAX5_CLK AB11 AA13 S5_MSEL4 R307 1.00k 19 FMCA_LA_RX_CLK_N[1:0]
S5_MSEL3 AC11 CLK_3E_0P,DQ46R VCCIO = 1.8V PLL_3E_CLKOUT0P,DQ46R Y12 STRATIX V MSEL PINS.
R14 CLK_3E_0N,DQ46R PLL_3E_CLKOUT0N,DQ46R U13 CAN BE DELETED IN REV B
CLK_3E_1P,DQ45R PLL_3E_CLKOUT1P,DQS45R FMC PORT B INTERFACE
B P14 T13 R306 1.00k B
CLK_3E_1N,DQ45R PLL_3E_CLKOUT1N,DQSn45R R308 DNI 20 FMCB_CLK_M2C_P[1:0]
BANK-3F 20 FMCB_CLK_M2C_N[1:0]
R349 100, 1% FMCB_CLK_M2C_P0 J12 K11
FMCB_CLK_M2C_N0 K12 CLK_3F_0P,DQ42R FMCB VARIABLE VCCIO PLL_3F_CLKOUT0P,DQ42R J11 20 FMCB_LA_RX_CLK_P[1:0]
R333 100, 1% FMCB_LA_RX_CLK_P0 C11 CLK_3F_0N,DQ42R DEFAULT 1.8V PLL_3F_CLKOUT0N,DQ42R C14
FMCB_LA_RX_CLK_N0 C10 CLK_3F_1P,DQ41R (1.2V, 1.5V, 1.8V) PLL_3F_CLKOUT1P,DQS41R D14 20 FMCB_LA_RX_CLK_N[1:0]
CLK_3F_1N,DQ41R PLL_3F_CLKOUT1N,DQSn41R
ARRIA 10 USB INTERFACE
BANK-3G 25 USB_FPGA_CLK
R378 100, 1% FMCB_CLK_M2C_P1 F17 E16 26 USB_FULL
FMCB_CLK_M2C_N1 G17 CLK_3G_0P,DQ38R FMCB VARIABLE VCCIOPLL_3G_CLKOUT0P,DQ38R E17 26 USB_EMPTY
R379 100, 1% FMCB_LA_RX_CLK_P1 G18 CLK_3G_0N,DQ38RDEFAULT 1.8V PLL_3G_CLKOUT0N,DQ38R E20 26 USB_SCL
FMCB_LA_RX_CLK_N1 F18 CLK_3G_1P,DQ37R (1.2V, 1.5V, 1.8V)PLL_3G_CLKOUT1P,DQS37R F20 1 J7 26 USB_SDA
CLK_3G_1N,DQ37R PLL_3G_CLKOUT1N,DQSn37R
MAX V INTERFACE
BANK-3H
2
3
4
5
R391 100, 1% CLK_FPGA_B3_P F23 E24 SMA_CLK_OUT 13 MAX5_CLK
CAN BE REMOVED FOR ARRIA 10 AND USE OCT -> CLK_FPGA_B3_N G23 CLK_3H_0P,DQ34R VCCIO = 1.8V PLL_3H_CLKOUT0P,DQ34R F24
A CLK_3H_0N,DQ34R PLL_3H_CLKOUT0N,DQ34R A
C23 C25 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
D23 CLK_3H_1P,DQ33R PLL_3H_CLKOUT1P,DQS33R B25 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
CLK_3H_1N,DQ33R PLL_3H_CLKOUT1N,DQSn33R Title
10AX115F1932C
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Clocks
2.5V
2.5V_Si570 2.5V 2.5V
R524 4.70K Si570_EN
R435 4.70K CLOCK_SDA L22 L9
R511 4.70K CLOCK_SCL C689 C700
E Si53311_VDD BLM15AG221SN1 E
X3 0.1uF 10uF BLM15AG221SN1
SI570_EN 13 2 6 C701 1.8V
OE VCC
CLOCK_I2C_SDA 7 4 100M_OSC_CP C238 0.1uF 1uF L8
SDA CLK+ R207 100, 1% CLK1n C680 C210
CLOCK_I2C_SCL 8 5 100M_OSC_CN C239 0.1uF DNI
SCL CLK- 1uF 1uF
3 1
17
18
19
GND NC
7
Si570 Programmable Oscillator U42
Use Clock Control GUI SI570
VREF
VDD
VDDOA
VDDOB
(Default 100MHz) 100M_OSC_P 10 5 8 CLK_FPGA_B2_P
I2C Address 00 HEX 100M_OSC_N 11 CLK0 Q0 4 8 CLK_FPGA_B2_N
CLK0 Q0
J6 1 CLKIN_SMA R52 22.0 CLKIN_SMA_CMOS 14 32 8 CLK_FPGA_B3_P
C679 0.1uF CLK1n 15 CLK1 BANK A Q1 31 8 CLK_FPGA_B3_N
CLK1 OUTPUT Q1
CLK_SEL 13,248 30
5
4
3
2
CLK_SEL Q2 29
Si53311_VDD Q2
D D
CLK_SEL = LOW selects (CLK0p/n) Si570 input R196 4.70K OEA 12 BANK A
CLK_SEL = HIGH selects (CLK1p/n) SMA input 1 OEA CONTROL 28
3 DIVA Q3 27
LVDS OUTPUT 2 SFOUTA[0] Q3
2.5V 1.8V SFOUTA[1] BANK B 26 REFCLK1_CP C225 0.1uF 11 REFCLK1_P
Si53311_VDD OUTPUT Q4 25 REFCLK1_CN C214 0.1uF 11 REFCLK1_N
R195 4.70K OEB 13 BANK B Q4
C165 C164 24 OEB CONTROL 21 REFCLK4_CP C208 0.1uF 12 REFCLK4_P
C574
DIVB Q5
GND_PAD
22 20 REFCLK4_CN 12 REFCLK4_N
1uF 0.1uF 0.1uF LVDS OUTPUT 23 SFOUTB[0] Q5 C209 0.1uF
U60 SFOUTB[1]
GND
NC1
NC2
B1 B2
CLOCK_I2C_SDA C1 VCC VL A1 4 CLOCK_SDA
CLOCK_I2C_SCL C2 IO VCC1 IO VL1 A2 4 CLOCK_SCL Si53301_11
9
16
6
33
SI516_FS C3 IO VCC2 IO VL2 A3 6 A10_SI516_FS
C4 IO VCC3 IO VL3 A4
1.8V IO VCC4 IO VL4
B3 B4
TS GND
C C
MAX3378_UCSP
2.5V
R452 4.70K
X2
CLK125_EN 13 1 4 8 CLK_125_P
10,13 CLOCK_I2C_SCL EN OUT
10,13 CLOCK_I2C_SDA 2.5V 2 5 8 CLK_125_N
NC OUTn
6 3
VCC GND
C618 C619
2.5V_Si516 2.5V 125.0MHz
0.1uF 10uF
L15
C572 C573
0.1uF 10uF BLM15AG221SN1

X1 1.8V
SI516_FS 13,24 2 6
FS(OE) VDD
B B
CLOCK_I2C_SDA 7 4 REFCLK_SDI_CP C155 0.1uF
11 REFCLK_SDI_P C101 C100
NC(SDA) CLK+ 1.8V
CLOCK_I2C_SCL 8 5 REFCLK_SDI_CN C154 0.1uF
11 REFCLK_SDI_N X4 0.1uF 10uF U53
NC(SCL) CLK- CLK50_EN 13 1 4 2
Populated with Si516. 3 1 SI571_VCONTROL EN VCC VDD 8 13 MV_CLK_50
FS Control on DIPSWITCH GND VC 2 3 CLKIN_50 3 CLKOUT1 9 8 CLK_50
FS=0: 148.35MHz Si516_148.5M_148.35M GND OUT CLKIN CLKOUT2 10
FS=1: 148.50MHz 2.5V 50MHz 6 CLKOUT3
C64 C71
I2C only available if Si571 is populated. From FPGA 7 OE1 4
SDI_CLK148_UP 6 R446 180K R947 2.2uF 0.1uF 5 OE2 OE_OSC
SDI_CLK148_DOWN 6 R445 180K DNI OE3 1
1.8V GND
C604 SL18860DC
R444 R56 10.0K
4.99K 1.0nF
A C603 A
0.1uF Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLL (2)
E E
C109 DNI
1.8V
Y3 U26
3
25.00MHz 7 1.8V_PLL2 L14
4 2 1 VDD1 24 C443 C488 C490 C489 C469 C470
2 CLKIN_P VDD2 11
3 CLKIN_N VDDO3 15 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF BLM15AG221SN1
1
C117 DNI CLKIN VDDO2 16
4 VDDO1 20
5 I2C_LSB VDDO0
6 FDBK_P 8 R106 4.70K
FDBK_N INTR
CLOCK_I2C_SCL 12 9 8 CLK_EMI_P
SCL CLK3B 10 8 CLK_EMI_N
CLOCK_I2C_SDA 19 CLK3A 133.33MHz
D SDA D
13 REFCLK_QSFP_CP C130 0.1uF 11 REFCLK_QSFP_P
CLK2B 14 REFCLK_QSFP_CN 11 REFCLK_QSFP_N
CLK2A C129 0.1uF
644.53125MHz
17 REFCLK_SFP_CP C119 0.1uF 11 REFCLK_SFP_P
CLK1B 18 REFCLK_SFP_CN 11 REFCLK_SFP_N
CLK1A C118 0.1uF
644.53125MHz
21 REFCLK_DP_CP C111 0.1uF 11 REFCLK_DP_P
CLK0B 22 REFCLK_DP_CN 11 REFCLK_DP_N
CLK0A C110 0.1uF
270MHz 1.8V
LVDS
23 4,9 CLOCK_SDA
RSVD_GND 25 Si5338 Programmable Oscillator Use Clock Control GUI (Defaults 4,9 CLOCK_SCL
EPAD CLK[0:3] = 270MHz, 644.53125MHz, 644.53125MHz, 133.33MHz)
I2C Address 7A HEX
Si5338A-CUSTOM
2.5V
9,13 CLOCK_I2C_SCL
9,13 CLOCK_I2C_SDA
C C
C65 DNI
1.8V
Y2 U14
3
25.00MHz 7 1.8V_PLL L13

4 2 1 VDD1 24 C390 C357 C348 C358 C359 C391
2 CLKIN_P VDD2 11
3 CLKIN_N VDDO3 15 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF BLM15AG221SN1
1
C72 DNI CLKIN VDDO2 16

1.8V_PLL 4 VDDO1 20
5 I2C_LSB VDDO0
6 FDBK_P 8 R81 4.70K
FDBK_N INTR
CLOCK_I2C_SCL 12 9 REFCLK_SMA_CP C102 0.1uF 11 REFCLK_SMA_P
SCL CLK3B 10 REFCLK_SMA_CN C103 0.1uF 11 REFCLK_SMA_N
CLOCK_I2C_SDA 19 CLK3A 302.083333MHz
SDA 13 REFCLK_FMCB_CP C94 0.1uF 12 REFCLK_FMCB_P
CLK2B 14 REFCLK_FMCB_CN C74 0.1uF 12 REFCLK_FMCB_N
CLK2A 625MHz
B 17 REFCLK_FMCA_CP C73 0.1uF 12 REFCLK_FMCA_P B
CLK1B 18 REFCLK_FMCA_CN C66 0.1uF 12 REFCLK_FMCA_N
CLK1A 625MHz
21 PCIE_OB_REFCLK_CP C59 0.1uF 11 PCIE_OB_REFCLK_P
CLK0B 22 PCIE_OB_REFCLK_CN C58 0.1uF 11 PCIE_OB_REFCLK_N
CLK0A 100MHz
LVDS
23
RSVD_GND 25 Si5338 Programmable Oscillator Use Clock Control GUI
EPAD (Defaults CLK[0:3] = 100MHz, 625MHz, 625MHz, 302.083333MHz)
I2C Address 7C HEX
Si5338A-CUSTOM
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U28I
U28F
ARRIA 10 - LEFT TRANSCEIVER BANK-1C Arria 10 Transceivers Left ARRIA 10 - LEFT TRANSCEIVER BANK-1F
SFP_RX_P AA42 AB44 SFP_TX_P 9 REFCLK1_P

AW38 BC38 SFP_RX_N AA41 GXBL1F_RX_CH0P,GXBL1F_REFCLK0P GXBL1F_TX_CH0P AB43 SFP_TX_N 9 REFCLK1_N
AW37 GXBL1C_RX_CH0P,GXBL1C_REFCLK0P GXBL1C_TX_CH0P BC37 GXBL1F_RX_CH0N,GXBL1F_REFCLK0N GXBL1F_TX_CH0N
GXBL1C_RX_CH0N,GXBL1C_REFCLK0N GXBL1C_TX_CH0N W42 Y44
GXBL1F_RX_CH1P,GXBL1F_REFCLK1P GXBL1F_TX_CH1P PCIe INTERFACE
BA38 BD40 W41 Y43 3 PCIE_RX_P[7:0]
BA37 GXBL1C_RX_CH1P,GXBL1C_REFCLK1P GXBL1C_TX_CH1P BD39 GXBL1F_RX_CH1N,GXBL1F_REFCLK1N GXBL1F_TX_CH1N 3 PCIE_RX_N[7:0]
E GXBL1C_RX_CH1N,GXBL1C_REFCLK1N GXBL1C_TX_CH1N E
Y40 V44
AY40 BB40 Y39 GXBL1F_RX_CH2P,GXBL1F_REFCLK2P GXBL1F_TX_CH2P V43 3 PCIE_TX_P[7:0]
AY39 GXBL1C_RX_CH2P,GXBL1C_REFCLK2P GXBL1C_TX_CH2P BB39 GXBL1F_RX_CH2N,GXBL1F_REFCLK2N GXBL1F_TX_CH2N 3 PCIE_TX_N[7:0]
GXBL1C_RX_CH2N,GXBL1C_REFCLK2N GXBL1C_TX_CH2N V40 T44
AV40 BC42 V39 GXBL1F_RX_CH3P,GXBL1F_REFCLK3P GXBL1F_TX_CH3P T43 3 PCIE_EDGE_REFCLK_P
AV39 GXBL1C_RX_CH3P,GXBL1C_REFCLK3P GXBL1C_TX_CH3P BC41 GXBL1F_RX_CH3N,GXBL1F_REFCLK3N GXBL1F_TX_CH3N 3 PCIE_EDGE_REFCLK_N
GXBL1C_RX_CH3N,GXBL1C_REFCLK3N GXBL1C_TX_CH3N U42 P44
PCIE_RX_P0 AT40 BB44 PCIE_TX_P0 U41 GXBL1F_RX_CH4P,GXBL1F_REFCLK4P GXBL1F_TX_CH4P P43 10 PCIE_OB_REFCLK_P
PCIE_RX_N0 AT39 GXBL1C_RX_CH4P,GXBL1C_REFCLK4P GXBL1C_TX_CH4P BB43 PCIE_TX_N0 GXBL1F_RX_CH4N,GXBL1F_REFCLK4N GXBL1F_TX_CH4N 10 PCIE_OB_REFCLK_N
GXBL1C_RX_CH4N,GXBL1C_REFCLK4N GXBL1C_TX_CH4N T40 M44
PCIE_RX_P1 AP40 BA42 PCIE_TX_P1 T39 GXBL1F_RX_CH5P,GXBL1F_REFCLK5P GXBL1F_TX_CH5P M43
GXBL1C_RX_CH5P,GXBL1C_REFCLK5P GXBL1C_TX_CH5P GXBL1F_RX_CH5N,GXBL1F_REFCLK5N GXBL1F_TX_CH5N DISPLAYPORT INTERFACE
PCIE_RX_N1 AP39 BA41 PCIE_TX_N1 18 DP_ML_LANE_P[3:0]
GXBL1C_RX_CH5N,GXBL1C_REFCLK5N GXBL1C_TX_CH5N 18 DP_ML_LANE_N[3:0]
W37
PCIE_EDGE_REFCLK_P AL37 10.0K R462 W38 REFCLK_GXBL1F_CHTP 10 REFCLK_DP_P
PCIE_EDGE_REFCLK_N AL38 REFCLK_GXBL1C_CHTP REFCLK_GXBL1F_CHTN 10 REFCLK_DP_N
REFCLK_GXBL1C_CHTN REFCLK_SFP_P AA37
REFCLK_SFP_N AA38 REFCLK_GXBL1F_CHBP
REFCLK_GXBL1F_CHBN SDI INTERFACE
D
PCIE_OB_REFCLK_P AN37 9 REFCLK_SDI_P D
PCIE_OB_REFCLK_N AN38 REFCLK_GXBL1C_CHBP 9 REFCLK_SDI_N
REFCLK_GXBL1C_CHBN 10AX115F1932C 23 SDI_RX_P
23 SDI_RX_N
10AX115F1932C U28J 23 SDI_TX_P
U28G ARRIA 10 - LEFT TRANSCEIVER BANK-1G 23 SDI_TX_N
ARRIA 10 - LEFT TRANSCEIVER BANK-1D
QSFP_RX_P0 R42 K44 QSFP_TX_P0 QSFP INTERFACE
PCIE_RX_P2 AN42 AY44 PCIE_TX_P2 QSFP_RX_N0 R41 GXBL1G_RX_CH0P,GXBL1G_REFCLK0P GXBL1G_TX_CH0P K43 QSFP_TX_N0 21 QSFP_RX_P[3:0]
PCIE_RX_N2 AN41 GXBL1D_RX_CH0P,GXBL1D_REFCLK0P GXBL1D_TX_CH0P AY43 PCIE_TX_N2 GXBL1G_RX_CH0N,GXBL1G_REFCLK0N GXBL1G_TX_CH0N 21 QSFP_RX_N[3:0]
GXBL1D_RX_CH0N,GXBL1D_REFCLK0N GXBL1D_TX_CH0N QSFP_RX_P1 P40 J42 QSFP_TX_P1
PCIE_RX_P3 AM40 AW42PCIE_TX_P3 QSFP_RX_N1 P39 GXBL1G_RX_CH1P,GXBL1G_REFCLK1P GXBL1G_TX_CH1P J41 QSFP_TX_N1 21 QSFP_TX_P[3:0]
PCIE_RX_N3 AM39 GXBL1D_RX_CH1P,GXBL1D_REFCLK1P GXBL1D_TX_CH1P AW41PCIE_TX_N3 GXBL1G_RX_CH1N,GXBL1G_REFCLK1N GXBL1G_TX_CH1N 21 QSFP_TX_N[3:0]
GXBL1D_RX_CH1N,GXBL1D_REFCLK1N GXBL1D_TX_CH1N N42 H44
PCIE_RX_P4 AL42 AV44 PCIE_TX_P4 N41 GXBL1G_RX_CH2P,GXBL1G_REFCLK2P GXBL1G_TX_CH2P H43 10 REFCLK_QSFP_P
PCIE_RX_N4 AL41 GXBL1D_RX_CH2P,GXBL1D_REFCLK2P GXBL1D_TX_CH2P AV43 PCIE_TX_N4 GXBL1G_RX_CH2N,GXBL1G_REFCLK2N GXBL1G_TX_CH2N 10 REFCLK_QSFP_N
GXBL1D_RX_CH2N,GXBL1D_REFCLK2N GXBL1D_TX_CH2N QSFP_RX_P2 M40 G42 QSFP_TX_P2
PCIE_RX_P5 AK40 AU42 PCIE_TX_P5 QSFP_RX_N2 M39 GXBL1G_RX_CH3P,GXBL1G_REFCLK3P GXBL1G_TX_CH3P G41 QSFP_TX_N2
GXBL1D_RX_CH3P,GXBL1D_REFCLK3P GXBL1D_TX_CH3P GXBL1G_RX_CH3N,GXBL1G_REFCLK3N GXBL1G_TX_CH3N SFP+ INTERFACE
C
PCIE_RX_N5 AK39 AU41 PCIE_TX_N5 C
GXBL1D_RX_CH3N,GXBL1D_REFCLK3N GXBL1D_TX_CH3N QSFP_RX_P3 L42 F44 QSFP_TX_P3 22 SFP_RX_P
PCIE_RX_P6 AJ42 AT44 PCIE_TX_P6 QSFP_RX_N3 L41 GXBL1G_RX_CH4P,GXBL1G_REFCLK4P GXBL1G_TX_CH4P F43 QSFP_TX_N3 22 SFP_RX_N
PCIE_RX_N6 AJ41 GXBL1D_RX_CH4P,GXBL1D_REFCLK4P GXBL1D_TX_CH4P AT43 PCIE_TX_N6 GXBL1G_RX_CH4N,GXBL1G_REFCLK4N GXBL1G_TX_CH4N
GXBL1D_RX_CH4N,GXBL1D_REFCLK4N GXBL1D_TX_CH4N K40 E42 22 SFP_TX_P
PCIE_RX_P7 AH40 AR42 PCIE_TX_P7 K39 GXBL1G_RX_CH5P,GXBL1G_REFCLK5P GXBL1G_TX_CH5P E41 22 SFP_TX_N
PCIE_RX_N7 AH39 GXBL1D_RX_CH5P,GXBL1D_REFCLK5P GXBL1D_TX_CH5P AR41 PCIE_TX_N7 GXBL1G_RX_CH5N,GXBL1G_REFCLK5N GXBL1G_TX_CH5N
GXBL1D_RX_CH5N,GXBL1D_REFCLK5N GXBL1D_TX_CH5N 10 REFCLK_SFP_P
REFCLK_QSFP_P R37 10 REFCLK_SFP_N
REFCLK1_P AG37 REFCLK_QSFP_N R38 REFCLK_GXBL1G_CHTP
REFCLK1_N AG38 REFCLK_GXBL1D_CHTP REFCLK_GXBL1G_CHTN
REFCLK_GXBL1D_CHTN U37
AJ37 10.0K R461 U38 REFCLK_GXBL1G_CHBP
REFCLK_GXBL1D_CHBP REFCLK_GXBL1G_CHBN SMA INTERFACE
10.0K R464 AJ38 10 REFCLK_SMA_P
REFCLK_GXBL1D_CHBN 10 REFCLK_SMA_N
10AX115F1932C
10AX115F1932C U28K
U28H ARRIA 10 - LEFT TRANSCEIVER BANK-1H
ARRIA 10 - LEFT TRANSCEIVER BANK-1E
B B
SDI_RX_P H40 D44 SDI_TX_P
AG42 AP44 DP_ML_LANE_P0 SDI_RX_N H39 GXBL1H_RX_CH0P,GXBL1H_REFCLK0P GXBL1H_TX_CH0P D43 SDI_TX_N
AG41 GXBL1E_RX_CH0P,GXBL1E_REFCLK0P GXBL1E_TX_CH0P AP43 DP_ML_LANE_N0 GXBL1H_RX_CH0N,GXBL1H_REFCLK0N GXBL1H_TX_CH0N
GXBL1E_RX_CH0N,GXBL1E_REFCLK0N GXBL1E_TX_CH0N G38 C42 SMA_TX_P 1 J16
AF40 AM44 DP_ML_LANE_P1 G37 GXBL1H_RX_CH1P,GXBL1H_REFCLK1P GXBL1H_TX_CH1P C41 SMA_TX_N
AF39 GXBL1E_RX_CH1P,GXBL1E_REFCLK1P GXBL1E_TX_CH1P AM43 DP_ML_LANE_N1 GXBL1H_RX_CH1N,GXBL1H_REFCLK1N GXBL1H_TX_CH1N
GXBL1E_RX_CH1N,GXBL1E_REFCLK1N GXBL1E_TX_CH1N F40 B44 1 J15
2
3
4
5
AE42 AK44 F39 GXBL1H_RX_CH2P,GXBL1H_REFCLK2P GXBL1H_TX_CH2P B43
AE41 GXBL1E_RX_CH2P,GXBL1E_REFCLK2P GXBL1E_TX_CH2P AK43 GXBL1H_RX_CH2N,GXBL1H_REFCLK2N GXBL1H_TX_CH2N
GXBL1E_RX_CH2N,GXBL1E_REFCLK2N GXBL1E_TX_CH2N E38 A42
2
3
4
5
AD40 AH44 DP_ML_LANE_P2 E37 GXBL1H_RX_CH3P,GXBL1H_REFCLK3P GXBL1H_TX_CH3P A41
AD39 GXBL1E_RX_CH3P,GXBL1E_REFCLK3P GXBL1E_TX_CH3P AH43 DP_ML_LANE_N2 GXBL1H_RX_CH3N,GXBL1H_REFCLK3N GXBL1H_TX_CH3N
GXBL1E_RX_CH3N,GXBL1E_REFCLK3N GXBL1E_TX_CH3N D40 B40
AC42 AF44 DP_ML_LANE_P3 D39 GXBL1H_RX_CH4P,GXBL1H_REFCLK4P GXBL1H_TX_CH4P B39
AC41 GXBL1E_RX_CH4P,GXBL1E_REFCLK4P GXBL1E_TX_CH4P AF43 DP_ML_LANE_N3 GXBL1H_RX_CH4N,GXBL1H_REFCLK4N GXBL1H_TX_CH4N
GXBL1E_RX_CH4N,GXBL1E_REFCLK4N GXBL1E_TX_CH4N C38 A38
AB40 AD44 C37 GXBL1H_RX_CH5P,GXBL1H_REFCLK5P GXBL1H_TX_CH5P A37
AB39 GXBL1E_RX_CH5P,GXBL1E_REFCLK5P GXBL1E_TX_CH5P AD43 GXBL1H_RX_CH5N,GXBL1H_REFCLK5N GXBL1H_TX_CH5N
GXBL1E_RX_CH5N,GXBL1E_REFCLK5N GXBL1E_TX_CH5N
A A
REFCLK_SDI_P L37 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
REFCLK_DP_P AC37 REFCLK_SDI_N L38 REFCLK_GXBL1H_CHTP Copyright (c) 2013, Altera Corporation. All Rights Reserved.
REFCLK_DP_N AC38 REFCLK_GXBL1E_CHTP REFCLK_GXBL1H_CHTN Title
REFCLK_GXBL1E_CHTN REFCLK_SMA_P N37 Arria 10 GX FPGA Development Kit
AE37 REFCLK_SMA_N N38 REFCLK_GXBL1H_CHBP
10.0K R463 AE38 REFCLK_GXBL1E_CHBP REFCLK_GXBL1H_CHBN Size Document Number Rev
REFCLK_GXBL1E_CHBN
B 150-0321301-E3 (6XX-44366R) E3.1
10AX115F1932C
10AX115F1932C Date: Wednesday, August 10, 2016 Sheet 11 of 49
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U28L
ARRIA 10 - RIGHT TRANSCEIVER BANK-4C Arria 10 Transceivers Right U28O
ARRIA 10 - RIGHT TRANSCEIVER BANK-4F
FMCA_DP_M2C_P0 AW7 BC7 FMCA_DP_C2M_P0 FMCB_DP_M2C_P0 AA3 AB1 FMCB_DP_C2M_P0

FMCA_DP_M2C_N0 AW8 GXBR4C_RX_CH0P, GXBR4C_REFCLK0P GXBR4C_TX_CH0P BC8 FMCA_DP_C2M_N0 FMCB_DP_M2C_N0 AA4 GXBR4F_RX_CH0P, GXBR4F_REFCLK0P GXBR4F_TX_CH0P AB2 FMCB_DP_C2M_N0 9 REFCLK4_P
GXBR4C_RX_CH0N, GXBR4C_REFCLK0N GXBR4C_TX_CH0N GXBR4F_RX_CH0N, GXBR4F_REFCLK0N GXBR4F_TX_CH0N 9 REFCLK4_N
FMCA_DP_M2C_P1 BA7 BD5 FMCA_DP_C2M_P1 FMCB_DP_M2C_P1 W3 Y1 FMCB_DP_C2M_P1
FMCA_DP_M2C_N1 BA8 GXBR4C_RX_CH1P, GXBR4C_REFCLK1P GXBR4C_TX_CH1P BD6 FMCA_DP_C2M_N1 FMCB_DP_M2C_N1 W4 GXBR4F_RX_CH1P, GXBR4F_REFCLK1P GXBR4F_TX_CH1P Y2 FMCB_DP_C2M_N1
E GXBR4C_RX_CH1N, GXBR4C_REFCLK1N GXBR4C_TX_CH1N GXBR4F_RX_CH1N, GXBR4F_REFCLK1N GXBR4F_TX_CH1N FMC INTERFACE E
FMCA_DP_M2C_P2 AY5 BB5 FMCA_DP_C2M_P2 FMCB_DP_M2C_P2 Y5 V1 FMCB_DP_C2M_P2 19 FMCA_DP_M2C_P[15:0]

FMCA_DP_M2C_N2 AY6 GXBR4C_RX_CH2P, GXBR4C_REFCLK2P GXBR4C_TX_CH2P BB6 FMCA_DP_C2M_N2 FMCB_DP_M2C_N2 Y6 GXBR4F_RX_CH2P, GXBR4F_REFCLK2P GXBR4F_TX_CH2P V2 FMCB_DP_C2M_N2
GXBR4C_RX_CH2N, GXBR4C_REFCLK2N GXBR4C_TX_CH2N GXBR4F_RX_CH2N, GXBR4F_REFCLK2N GXBR4F_TX_CH2N 19 FMCA_DP_M2C_N[15:0]
FMCA_DP_M2C_P3 AV5 BC3 FMCA_DP_C2M_P3 FMCB_DP_M2C_P3 V5 T1 FMCB_DP_C2M_P3
FMCA_DP_M2C_N3 AV6 GXBR4C_RX_CH3P, GXBR4C_REFCLK3P GXBR4C_TX_CH3P BC4 FMCA_DP_C2M_N3 FMCB_DP_M2C_N3 V6 GXBR4F_RX_CH3P, GXBR4F_REFCLK3P GXBR4F_TX_CH3P T2 FMCB_DP_C2M_N3 19 FMCA_DP_C2M_P[15:0]
GXBR4C_RX_CH3N, GXBR4C_REFCLK3N GXBR4C_TX_CH3N GXBR4F_RX_CH3N, GXBR4F_REFCLK3N GXBR4F_TX_CH3N
FMCA_DP_M2C_P4 AT5 BB1 FMCA_DP_C2M_P4 FMCB_DP_M2C_P4 U3 P1 FMCB_DP_C2M_P4 19 FMCA_DP_C2M_N[15:0]
FMCA_DP_M2C_N4 AT6 GXBR4C_RX_CH4P, GXBR4C_REFCLK4P GXBR4C_TX_CH4P BB2 FMCA_DP_C2M_N4 FMCB_DP_M2C_N4 U4 GXBR4F_RX_CH4P, GXBR4F_REFCLK4P GXBR4F_TX_CH4P P2 FMCB_DP_C2M_N4
GXBR4C_RX_CH4N, GXBR4C_REFCLK4N GXBR4C_TX_CH4N GXBR4F_RX_CH4N, GXBR4F_REFCLK4N GXBR4F_TX_CH4N 19 FMCA_GBTCLK_M2C_P[1:0]
FMCA_DP_M2C_P5 AP5 BA3 FMCA_DP_C2M_P5 FMCB_DP_M2C_P5 T5 M1 FMCB_DP_C2M_P5 19 FMCA_GBTCLK_M2C_N[1:0]
FMCA_DP_M2C_N5 AP6 GXBR4C_RX_CH5P, GXBR4C_REFCLK5P GXBR4C_TX_CH5P BA4 FMCA_DP_C2M_N5 FMCB_DP_M2C_N5 T6 GXBR4F_RX_CH5P, GXBR4F_REFCLK5P GXBR4F_TX_CH5P M2 FMCB_DP_C2M_N5
GXBR4C_RX_CH5N, GXBR4C_REFCLK5N GXBR4C_TX_CH5N GXBR4F_RX_CH5N, GXBR4F_REFCLK5N GXBR4F_TX_CH5N
FMCA_GBTCLK_M2C_P0 AL8 FMCB_GBTCLK_M2C_P0 W8 20 FMCB_DP_M2C_P[15:0]

FMCA_GBTCLK_M2C_N0 AL7 REFCLK_GXBR4C_CHTP FMCB_GBTCLK_M2C_N0 W7 REFCLK_GXBR4F_CHTP
REFCLK_GXBR4C_CHTN REFCLK_GXBR4F_CHTN 20 FMCB_DP_M2C_N[15:0]
REFCLK_FMCA_P AN8 REFCLK_FMCB_P AA8
REFCLK_FMCA_N AN7 REFCLK_GXBR4C_CHBP REFCLK_FMCB_N AA7 REFCLK_GXBR4F_CHBP 20 FMCB_DP_C2M_P[15:0]
D REFCLK_GXBR4C_CHBN REFCLK_GXBR4F_CHBN D
20 FMCB_DP_C2M_N[15:0]
10AX115F1932C 10AX115F1932C
U28M U28P 20 FMCB_GBTCLK_M2C_P[1:0]
ARRIA 10 - RIGHT TRANSCEIVER BANK-4D ARRIA 10 - RIGHT TRANSCEIVER BANK-4G 20 FMCB_GBTCLK_M2C_N[1:0]
FMCA_DP_M2C_P6 AN3 AY1 FMCA_DP_C2M_P6 FMCB_DP_M2C_P6 R3 K1 FMCB_DP_C2M_P6

FMCA_DP_M2C_N6 AN4 GXBR4D_RX_CH0P, GXBR4D_REFCLK0P GXBR4D_TX_CH0P AY2 FMCA_DP_C2M_N6 FMCB_DP_M2C_N6 R4 GXBR4G_RX_CH0P, GXBR4G_REFCLK0P GXBR4G_TX_CH0P K2 FMCB_DP_C2M_N6
GXBR4D_RX_CH0N, GXBR4D_REFCLK0N GXBR4D_TX_CH0N GXBR4G_RX_CH0N, GXBR4G_REFCLK0N GXBR4G_TX_CH0N
FMCA_DP_M2C_P7 AM5 AW3 FMCA_DP_C2M_P7 FMCB_DP_M2C_P7 P5 J3 FMCB_DP_C2M_P7
FMCA_DP_M2C_N7 AM6 GXBR4D_RX_CH1P, GXBR4D_REFCLK1P GXBR4D_TX_CH1P AW4 FMCA_DP_C2M_N7 FMCB_DP_M2C_N7 P6 GXBR4G_RX_CH1P, GXBR4G_REFCLK1P GXBR4G_TX_CH1P J4 FMCB_DP_C2M_N7
FMCA_DP_M2C_P8 AL3 AV1 FMCA_DP_C2M_P8 FMCB_DP_M2C_P8 N3 H1 FMCB_DP_C2M_P8
FMCA_DP_M2C_N8 AL4 GXBR4D_RX_CH2P, GXBR4D_REFCLK2P GXBR4D_TX_CH2P AV2 FMCA_DP_C2M_N8 FMCB_DP_M2C_N8 N4 GXBR4G_RX_CH2P, GXBR4G_REFCLK2P GXBR4G_TX_CH2P H2 FMCB_DP_C2M_N8
FMCA_DP_M2C_P9 AK5 AU3 FMCA_DP_C2M_P9 FMCB_DP_M2C_P9 M5 G3 FMCB_DP_C2M_P9 10 REFCLK_FMCA_P
FMCA_DP_M2C_N9 AK6 GXBR4D_RX_CH3P, GXBR4D_REFCLK3P GXBR4D_TX_CH3P AU4 FMCA_DP_C2M_N9 FMCB_DP_M2C_N9 M6 GXBR4G_RX_CH3P, GXBR4G_REFCLK3P GXBR4G_TX_CH3P G4 FMCB_DP_C2M_N9 10 REFCLK_FMCA_N
C C
FMCA_DP_M2C_P10 AJ3 AT1 FMCA_DP_C2M_P10 FMCB_DP_M2C_P10 L3 F1 FMCB_DP_C2M_P10 10 REFCLK_FMCB_P
FMCA_DP_M2C_N10 AJ4 GXBR4D_RX_CH4P, GXBR4D_REFCLK4P GXBR4D_TX_CH4P AT2 FMCA_DP_C2M_N10 FMCB_DP_M2C_N10 L4 GXBR4G_RX_CH4P, GXBR4G_REFCLK4P GXBR4G_TX_CH4P F2 FMCB_DP_C2M_N10 10 REFCLK_FMCB_N
FMCA_DP_M2C_P11 AH5 AR3 FMCA_DP_C2M_P11 FMCB_DP_M2C_P11 K5 E3 FMCB_DP_C2M_P11
FMCA_DP_M2C_N11 AH6 GXBR4D_RX_CH5P, GXBR4D_REFCLK5P GXBR4D_TX_CH5P AR4 FMCA_DP_C2M_N11 FMCB_DP_M2C_N11 K6 GXBR4G_RX_CH5P, GXBR4G_REFCLK5P GXBR4G_TX_CH5P E4 FMCB_DP_C2M_N11
AG8 R8
10.0K R335 AG7 REFCLK_GXBR4D_CHTP 10.0K R350 R7 REFCLK_GXBR4G_CHTP
REFCLK_GXBR4D_CHTN REFCLK_GXBR4G_CHTN
FMCA_GBTCLK_M2C_P1 AJ8 FMCB_GBTCLK_M2C_P1 U8
FMCA_GBTCLK_M2C_N1 AJ7 REFCLK_GXBR4D_CHBP FMCB_GBTCLK_M2C_N1 U7 REFCLK_GXBR4G_CHBP
REFCLK_GXBR4D_CHBN REFCLK_GXBR4G_CHBN
10AX115F1932C 10AX115F1932C
U28N U28Q
ARRIA 10 - RIGHT TRANSCEIVER BANK-4E ARRIA 10 - RIGHT TRANSCEIVER BANK-4H
B B
FMCA_DP_M2C_P12 AG3 AP1 FMCA_DP_C2M_P12 FMCB_DP_M2C_P12 H5 D1 FMCB_DP_C2M_P12
FMCA_DP_M2C_N12 AG4 GXBR4E_RX_CH0P, GXBR4E_REFCLK0P GXBR4E_TX_CH0P AP2 FMCA_DP_C2M_N12 FMCB_DP_M2C_N12 H6 GXBR4H_RX_CH0P, GXBR4H_REFCLK0P GXBR4H_TX_CH0P D2 FMCB_DP_C2M_N12
GXBR4E_RX_CH0N, GXBR4E_REFCLK0N GXBR4E_TX_CH0N GXBR4H_RX_CH0N, GXBR4H_REFCLK0N GXBR4H_TX_CH0N
FMCA_DP_M2C_P13 AF5 AM1 FMCA_DP_C2M_P13 FMCB_DP_M2C_P13 G7 C3 FMCB_DP_C2M_P13
FMCA_DP_M2C_N13 AF6 GXBR4E_RX_CH1P, GXBR4E_REFCLK1P GXBR4E_TX_CH1P AM2 FMCA_DP_C2M_N13 FMCB_DP_M2C_N13 G8 GXBR4H_RX_CH1P, GXBR4H_REFCLK1P GXBR4H_TX_CH1P C4 FMCB_DP_C2M_N13
FMCA_DP_M2C_P14 AE3 AK1 FMCA_DP_C2M_P14 FMCB_DP_M2C_P14 F5 B1 FMCB_DP_C2M_P14
FMCA_DP_M2C_N14 AE4 GXBR4E_RX_CH2P, GXBR4E_REFCLK2P GXBR4E_TX_CH2P AK2 FMCA_DP_C2M_N14 FMCB_DP_M2C_N14 F6 GXBR4H_RX_CH2P, GXBR4H_REFCLK2P GXBR4H_TX_CH2P B2 FMCB_DP_C2M_N14
FMCA_DP_M2C_P15 AD5 AH1 FMCA_DP_C2M_P15 FMCB_DP_M2C_P15 E7 A3 FMCB_DP_C2M_P15
FMCA_DP_M2C_N15 AD6 GXBR4E_RX_CH3P, GXBR4E_REFCLK3P GXBR4E_TX_CH3P AH2 FMCA_DP_C2M_N15 FMCB_DP_M2C_N15 E8 GXBR4H_RX_CH3P, GXBR4H_REFCLK3P GXBR4H_TX_CH3P A4 FMCB_DP_C2M_N15
AC3 AF1 D5 B5
AC4 GXBR4E_RX_CH4P, GXBR4E_REFCLK4P GXBR4E_TX_CH4P AF2 D6 GXBR4H_RX_CH4P, GXBR4H_REFCLK4P GXBR4H_TX_CH4P B6
AB5 AD1 C7 A7
AB6 GXBR4E_RX_CH5P, GXBR4E_REFCLK5P GXBR4E_TX_CH5P AD2 C8 GXBR4H_RX_CH5P, GXBR4H_REFCLK5P GXBR4H_TX_CH5P A8
A A
REFCLK4_P AC8 L8 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
REFCLK4_N AC7 REFCLK_GXBR4E_CHTP 10.0K R334 L7 REFCLK_GXBR4H_CHTP Copyright (c) 2013, Altera Corporation. All Rights Reserved.
REFCLK_GXBR4E_CHTN REFCLK_GXBR4H_CHTN Title
AE8 N8 Arria 10 GX FPGA Development Kit
10.0K R351 AE7 REFCLK_GXBR4E_CHBP N7 REFCLK_GXBR4H_CHBP
REFCLK_GXBR4E_CHBN REFCLK_GXBR4H_CHBN Size Document Number Rev
B 150-0321301-E3 (6XX-44366R) E3.1
10AX115F1932C 10AX115F1932C
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U16A
5M2210 System Controller
U16B
7 FPGA_CONFIG_D[31:0]
5,14
5,14
FM_D[31:0]
FM_A[26:1]
MAX V MAX V 7 FPGA_nSTATUS
BANK1 BANK2 7,35 FPGA_CONF_DONE
FM_D23 G2 J4 FPGA_nSTATUS SI516_FS C5 E10 7,14 FPGA_DCLK 5,14 FLASH_WEn
FM_D28 E1 DIFFIO_L8P DIFFIO_L13P K1 FPGA_CONF_DONE B1 DIFFIO_T2P DIFFIO_T13P A11 7 FPGA_nCONFIG 5,14 FLASH_CEn0
FM_D29 G3 DIFFIO_L5N DIFFIO_L13N M9 FPGA_DCLK C13 DIFFIO_T1N DIFFIO_T13N B11 5,14 FLASH_CEn1
E DIFFIO_L8N
DIFFIO_B13N/DEV_CLRn DIFFIO_T18P DIFFIO_T14P E
FM_D30 F3 K2 USB_CFG2 C4 A12 7 FPGA_PR_DONE 5,14 FLASH_OEn
FM_D31 F2 DIFFIO_L5P DIFFIO_L14N K5 USB_CFG3 B4 DIFFIO_T2N DIFFIO_T14N D7 MAX_CONF_DONE 7 FPGA_PR_REQUEST 5,14 FLASH_RDYBSYn0
FM_D24 E5 DIFFIO_L6N DIFFIO_L15P L1 USB_CFG4 A13 DIFFIO_T3P DIFFIO_T5N B12 7 FPGA_PR_READY 8,14 FLASH_RDYBSYn1
FM_D25 C3 DIFFIO_L4N DIFFIO_L15N L2 USB_CFG5 E6 IOB2_6 DIFFIO_T15N C11 7 FPGA_PR_ERROR 5,14 FLASH_RESETn
FM_D26 D3 DIFFIO_L2P DIFFIO_L16P K3 USB_CFG6 TSENSE_ALERTn B14 DIFFIO_T4P DIFFIO_T16P A7 PGM_SEL 7 FPGA_CvP_CONFDONE 5,14 FLASH_CLK
DIFFIO_L1P DIFFIO_L16N DIFFIO_T17N DIFFIO_T8N 5,14 FLASH_ADVn
FM_D27 D2 M1 USB_CFG12 A5 A6 PGM_CONFIG
FM_D20 D1 DIFFIO_L3P DIFFIO_L17P M2 USB_CFG7 A4 DIFFIO_T5P IOB2_10 D6 PGM_LED0 29 TSENSE_ALERTn
FM_D21 F1 DIFFIO_L4P DIFFIO_L17N L4 USB_CFG8 B10 IOB2_9 DIFFIO_T3N C6 PGM_LED1 29 OVERTEMPn 9 CLK125_EN
FM_D22 E3 DIFFIO_L7P DIFFIO_L18P L3 USB_CFG9 E7 IOB2_11 IOB2_15 B7 PGM_LED2 29 OVERTEMP 9 CLK50_EN
FM_D16 E4 DIFFIO_L2N DIFFIO_L18N N1 USB_CFG10 OVERTEMPn B16 DIFFIO_T6N DIFFIO_T7N 29,30 SENSE_SMB_CLK 9 Si570_EN
FM_D17 F6 DIFFIO_L3N DIFFIO_L19P M4 USB_CFG0 OVERTEMP E11 DIFFIO_T18N 29,30 SENSE_SMB_DATA 9,13,24 SI516_FS
FM_D18 F4 DIFFIO_L7N DIFFIO_L19N N2 USB_CFG11 SENSE_SMB_CLK A15 DIFFIO_T15P A2 CLK_SEL 9,10 CLOCK_I2C_SDA
FM_D19 C2 DIFFIO_L6P DIFFIO_L20P M3 USB_CFG1 SENSE_SMB_DATA B13 IOB2_7 IOB2_8 D4 CLK_ENABLE 9,10 CLOCK_I2C_SCL
DIFFIO_L1N DIFFIO_L20N DIFFIO_T16N DIFFIO_T1P
FMCA_PRSNTn G1 N3 USB_CFG13 B8 B5 FACTORY_LOAD 4,23 SDI_MF2_MUTE
FMCB_PRSNTn E2 DIFFIO_L9P DIFFIO_L21P P2 USB_CFG14 A8 DIFFIO_T9P DIFFIO_T4N C7 MAX_ERROR 4,23 SDI_MF0_BYPASS
FM_A25 H13 IOB1_1 DIFFIO_L21N A9 DIFFIO_T9N IOB2_16 B6 MAX_LOAD 4,23 SDI_MF1_AUTO_SLEEP
FM_A24 G5 DIFFIO_R11P G4 D12 DIFFIO_T10P DIFFIO_T6P C9 SENSE_SDO 4,23 SDI_TX_SD_HDn
D DIFFIO_L10N DIFFIO_L9N DIFFIO_T17P DIFFIO_T12N D
FM_A23 J13 F5 CLK125_EN E9 B3 SENSE_SDI 7 MSEL0
FLASH_WEn J1 DIFFIO_R12P IOB1_2 H1 CLOCK_I2C_SDA C10 DIFFIO_T10N IOB2_12 B9 SENSE_SCK 7 MSEL1
FM_A26 H4 DIFFIO_L11N IOB1_3 R16 FMCA_C2M_PG Si570_EN A10 IOB2_13 DIFFIO_T11P D9 SENSE_CS0n 7 MSEL2
J2 DIFFIO_L12P DIFFIO_B22P L5 FMCB_C2M_PG CLOCK_I2C_SCL C12 DIFFIO_T12P DIFFIO_T11N D8 29 SENSE_SDO
DIFFIO_L12N IOB1_5 IOB2_14 DIFFIO_T8P 29 SENSE_SDI 6 MAX5_BEn[3:0]
C8 29 SENSE_SCK
DIFFIO_T7P D10 29 SENSE_CS0n 6 MAX5_OEn
USB_M5_CLK H5 P3 26 M5_JTAG_TCK IOB2_17 D11 6 MAX5_CSn
CLK_CONFIG J5 IOB1/CLK0 TCK L6 26 M5_JTAG_TDI IOB2_18 D5 6 MAX5_WEn
IOB1/CLK1 TDI M5 26 M5_JTAG_TDO IOB2_19 E8 8 MAX5_CLK
TDO N4 26 M5_JTAG_TMS IOB2_20
TMS
5M2210ZF256 6,19,24,26 FMCA_PRSNTn
5M2210ZF256 6,20,24,26 FMCB_PRSNTn
19 FMCA_C2M_PG
U16C U16D U16E 20 FMCB_C2M_PG
MAX V MAX V MAX V 1.8V
C BANK3 BANK4 Power 7,24 CPU_RESETn C
F7 F10 9 MV_CLK_50
FPGA_PR_REQUEST T4 J15 FM_D0 FPGA_CONFIG_D0 R1 N10 MAX5_OEn G6 GNDINT VCCINT G11
FM_A1 F15 IOB4_33 DIFFIO_R13N L16 FM_D1 FPGA_CONFIG_D1 T2 DIFFIO_B1P DIFFIO_B15P T11 MAX5_CSn H7 GNDINT VCCINT H10
FM_A2 G16 DIFFIO_R6N DIFFIO_R16P L14 FM_D2 FPGA_CONFIG_D2 N6 DIFFIO_B2P DIFFIO_B15N R11 MAX5_WEn H9 GNDINT VCCINT H8
DIFFIO_R9N DIFFIO_R19N DIFFIO_B4N DIFFIO_B16N GNDINT VCCINT ON-BOARD USB BLASTER II
FM_A3 G15 K14 FM_D3 FPGA_CONFIG_D3 N5 N11 MAX5_CLK J10 J7
FM_A4 H16 DIFFIO_R8N DIFFIO_R15N L13 FM_D4 FPGA_CONFIG_D4 N7 DIFFIO_B3N DIFFIO_B17N R10 MAX5_BEn0 J8 GNDINT VCCINT J9 26 USB_CFG[14:0]
FM_A5 H15 DIFFIO_R11N DIFFIO_R18N L15 FM_D5 FPGA_CONFIG_D5 N8 DIFFIO_B7N DIFFIO_B14N M10 MAX5_BEn1 K11 GNDINT VCCINT K6
FM_A6 F16 DIFFIO_R10N DIFFIO_R17P M15 FM_D6 FPGA_CONFIG_D6 M12 DIFFIO_B10P DIFFIO_B14P T12 MAX5_BEn2 L10 GNDINT VCCINT L7 25 USB_M5_CLK
FM_A7 G14 DIFFIO_R7N DIFFIO_R19P M16 FM_D7 FPGA_CONFIG_D7 T13 IOB4_29 DIFFIO_B17P P10 MAX5_BEn3 GNDINT VCCINT 1.8V
DIFFIO_R7P DIFFIO_R18P DIFFIO_B19P DIFFIO_B16P A1 C1
FM_A8 D16 K16 FM_D8 FPGA_CONFIG_D8 T15 T9 FPGA_CONFIG_D27 A16 GNDIO VCCIO1 H6
FM_A9 E15 DIFFIO_R4N DIFFIO_R14P K15 FM_D9 FPGA_CONFIG_D9 R13 DIFFIO_B21N DIFFIO_B11N R9 FPGA_CONFIG_D26 B15 GNDIO VCCIO1 J6
DIFFIO_R5N DIFFIO_R15P DIFFIO_B19N DIFFIO_B12P GNDIO VCCIO1 MAXV DIPSWITCH
FM_A10 E16 J14 FM_D10 FPGA_CONFIG_D10 P4 K4 CPU_RESETn B2 P1
FM_A11 H14 DIFFIO_R6P DIFFIO_R13P K13 FM_D11 FPGA_CONFIG_D11 R3 DIFFIO_B1N IOB1_4 N12 SDI_MF2_MUTE G10 GNDIO VCCIO1 2.5V 9,24 CLK_SEL
FM_A12 D15 DIFFIO_R10P DIFFIO_R14N L12 FM_D12 FPGA_CONFIG_D12 T10 DIFFIO_B3P DIFFIO_B20P P13 SDI_MF0_BYPASS G7 GNDIO A14 24 CLK_ENABLE
FM_A13 F14 DIFFIO_R3N DIFFIO_R17N N16 FM_D13 FPGA_CONFIG_D13 P5 IOB4_32 DIFFIO_B22N R14 SDI_MF1_AUTO_SLEEP G8 GNDIO VCCIO2 A3 24 FACTORY_LOAD
FM_A14 C14 DIFFIO_R4P DIFFIO_R20P M13 FM_D14 FPGA_CONFIG_D14 R4 DIFFIO_B2N DIFFIO_B20N N13 SDI_TX_SD_HDn G9 GNDIO VCCIO2 F8 9,13,24 SI516_FS
FM_A15 C15 DIFFIO_R1N DIFFIO_R20N L11 FM_D15 FPGA_CONFIG_D15 R5 IOB4_31 IOB3_27 T7 FPGA_CONFIG_D28 K10 GNDIO VCCIO2 F9
DIFFIO_R2P DIFFIO_R16N DIFFIO_B5P DIFFIO_B9N K7 GNDIO VCCIO2 1.8V
B GNDIO PUSH BUTTON INTERFACE B
FM_A16 H3 D14 FLASH_CEn0 FPGA_CONFIG_D16 M8 R12 MSEL0 K8 C16 24 PGM_SEL
FM_A17 H2 DIFFIO_L11P IOB3_22 P14 FLASH_OEn FPGA_CONFIG_D17 M7 DIFFIO_B13P/DEV_OE
DIFFIO_B18P P11 MSEL1 K9 GNDIO VCCIO3 H11 24 PGM_CONFIG
FM_A18 E13 DIFFIO_L10P DIFFIO_R22N F12 FLASH_RDYBSYn0 FPGA_CONFIG_D18 T5 DIFFIO_B8P DIFFIO_B18N M11 MSEL2 R15 GNDIO VCCIO3 J11 24 MAX_RESETn
FM_A19 F13 DIFFIO_R2N IOB3_24 D13 FLASH_RESETn FPGA_CONFIG_D19 P9 DIFFIO_B6P IOB4_28 R7 FPGA_CONFIG_D25 R2 GNDIO VCCIO3 P16
FM_A20 G13 DIFFIO_R5P IOB3_21 FPGA_CONFIG_D20 M6 DIFFIO_B12N DIFFIO_B8N P8 FPGA_CONFIG_D29 T1 GNDIO VCCIO3
DIFFIO_R8P DIFFIO_B5N DIFFIO_B9P GNDIO LED INTERFACE
FM_A21 G12 N15 FLASH_CLK FPGA_CONFIG_D21 N9 R6 FPGA_CONFIG_D30 T16 L8
FM_A22 E12 DIFFIO_R9P DIFFIO_R21P N14 FLASH_ADVn FPGA_CONFIG_D23 T8 IOB4_30 DIFFIO_B7P P6 FPGA_CONFIG_D31 T6 GNDIO VCCIO4 L9 24 PGM_LED[2:0]
CLK50_EN J16 DIFFIO_R3P DIFFIO_R21N F11 FLASH_CEn1 FPGA_CONFIG_D22 R8 DIFFIO_B11P DIFFIO_B4P E14 FPGA_nCONFIG GNDIO VCCIO4 T14
DIFFIO_R12N IOB3_23 DIFFIO_B10N DIFFIO_R1P VCCIO4 T3 24 MAX_ERROR
P15 FLASH_RDYBSYn1 MAX_RESETn J3 VCCIO4 24 MAX_LOAD
DIFFIO_R22P K12 FPGA_PR_ERROR FPGA_CONFIG_D24 P7 DIFFIO_L14P 5M2210ZF256 24 MAX_CONF_DONE
MV_CLK_50 J12 IOB3_25 M14 FPGA_CvP_CONFDONE DIFFIO_B6N
FPGA_PR_DONE H12 IOB3/CLK2 IOB3_26 P12 FPGA_PR_READY
IOB3/CLK3 DIFFIO_B21P 5M2210ZF256 1.8V 1.8V
X5
5M2210ZF256 1 4
EN VCC
C128 C141
2 3 CLK_CONFIG
1.8V VCCINT 1.8V 1.8V VCCIO 1.8V 1.8V VCCIO GND OUT 2.2uF 0.1uF
A A
125MHz Altera Corporation, 101 Innovation Dr., San Jose CA 95134
C397 C426 C427 C400 C398 C402 C383 C401 C455 C458 C343 C330 C384 C399 C425 C353 C456 C457 C483 C385 Title
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FLASH
FM BUS
FM_D[31:0] 5,13
FM_A[26:1] 5,13
E E
FLASH 1-Gbit FLASH 1-Gbit
U4 1.8V U5 1.8V
PC28FxxxP30B85 PC28FxxxP30B85
FLASH A4 FLASH A4
FM_A1 A1 VPP FM_A1 A1 VPP
1.8V FM_A2 B1 A1 A6 FM_A2 B1 A1 A6
FM_A3 C1 A2 VCC H3 1.8V FM_A3 C1 A2 VCC H3 1.8V
R437 DNI FPGA_AS_DATA0 FM_A4 D1 A3 VCC FM_A4 D1 A3 VCC
R438 DNI FPGA_AS_DATA1 FM_A5 D2 A4 D5 FM_A5 D2 A4 D5
R413 DNI FPGA_AS_DATA2 FM_A6 A2 A5 VCCQ D6 FM_A6 A2 A5 VCCQ D6
R428 DNI FPGA_AS_DATA3 FM_A7 C2 A6 VCCQ G4 FM_A7 C2 A6 VCCQ G4
D A7 VCCQ A7 VCCQ D
R407 DNI FPGA_DCLK FM_A8 A3 FM_A8 A3
R414 DNI FPGA_nCSO FM_A9 B3 A8 F2 FM_D16 FM_A9 B3 A8 F2 FM_D0
FM_A10 C3 A9 D0 E2 FM_D17 FM_A10 C3 A9 D0 E2 FM_D1
FM_A11 D3 A10 D1 G3 FM_D18 FM_A11 D3 A10 D1 G3 FM_D2
FM_A12 C4 A11 D2 E4 FM_D19 FM_A12 C4 A11 D2 E4 FM_D3
FM_A13 A5 A12 D3 E5 FM_D20 FM_A13 A5 A12 D3 E5 FM_D4
FM_A14 B5 A13 D4 G5 FM_D21 FM_A14 B5 A13 D4 G5 FM_D5
1.8V FM_A15 C5 A14 D5 G6 FM_D22 FM_A15 C5 A14 D5 G6 FM_D6
U29 FM_A16 D7 A15 D6 H7 FM_D23 FM_A16 D7 A15 D6 H7 FM_D7
B4 FM_A17 D8 A16 D7 FM_A17 D8 A16 D7
VCC D3 7 FPGA_AS_DATA0 FM_A18 A7 A17 E1 FM_D24 FM_A18 A7 A17 E1 FM_D8
FPGA_DCLK B2
7,13 DQ0 D2 7 FPGA_AS_DATA1 FM_A19 B7 A18 D8 E3 FM_D25 FM_A19 B7 A18 D8 E3 FM_D9
FPGA_nCSO C2
7 C DQ1 C4 7 FPGA_AS_DATA2 FM_A20 C7 A19 D9 F3 FM_D26 FM_A20 C7 A19 D9 F3 FM_D10
S# W#/VPP/DQ2 D4 7 FPGA_AS_DATA3 FM_A21 C8 A20 D10 F4 FM_D27 FM_A21 C8 A20 D10 F4 FM_D11
B3 HOLD#/DQ3 FM_A22 A8 A21 D11 F5 FM_D28 FM_A22 A8 A21 D11 F5 FM_D12
VSS FM_A23 G1 A22 D12 H5 FM_D29 FM_A23 G1 A22 D12 H5 FM_D13
A2 C5 FM_A24 H8 NC(64M)/A23 D13 G7 FM_D30 FM_A24 H8 NC(64M)/A23 D13 G7 FM_D14
A3 NC1 NC9 D1 FM_A25 B6 NC(64M,128M)/A24 D14 E7 FM_D31 FM_A25 B6 NC(64M,128M)/A24 D14 E7 FM_D15
A4 NC2 NC10 D5 FM_A26 B8 NC/A25(512M) D15 FM_A26 B8 NC/A25(512M) D15
C NC3 NC11 NC/A26(1G) NC/A26(1G) C
A5 E1 F7 FLASH_RDYBSYn1
8,13 F7
5,13 FLASH_RDYBSYn0
1.8V B1 NC4 NC12 E2 FLASH_CLK E6 WAIT FLASH_CLK 5,13 E6 WAIT
B5 NC5 NC13 E3 CLK B2 CLK B2
C1 NC6 NC14 E4 FLASH_RESETn D4 GND H2 FLASH_RESETn 5,13 D4 GND H2
C547 C566 C3 NC7 NC15 E5 FLASH_CEn1 5,13 B4 RESET# GND H4 FLASH_CEn0 5,13 B4 RESET# GND H4
NC8 NC16 FLASH_OEn F8 CE# GND H6 FLASH_OEn 5,13 F8 CE# GND H6
0.1uF 0.1uF EPCQ1024L FLASH_WEn G8 OE# GND FLASH_WEn 5,13 G8 OE# GND
FLASH_ADVn F6 WE# H1 FLASH_ADVn 5,13 F6 WE# H1
FLASH_WPn C6 ADV# RFU0 G2 FLASH_WPn C6 ADV# RFU0 G2
WP# RFU1 F1 WP# RFU1 F1
RFU2 E8 RFU2 E8
RFU3 RFU3
PC28F00AG18 PC28F00AG18
B B
1.8V 1.8V 1.8V 1.8V 1.8V
R286 10.0K FLASH_WPn

C295 C294 C296 C313 C321 C322 R266 10.0K FLASH_WEn C311 C312 C293 C292 C319 C320
R278 10.0K FLASH_RDYBSYn0
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R279 10.0K FLASH_RDYBSYn1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
R280 10.0K FLASH_RESETn
- When using a single x16 flash device a word consists of 16 data bits so addressing starts with FM_A1 mapped to address bit 1 in software.
- When using dual x16 flash devices for an equivalent x32 (x16||x16) flash device a word consists of 32 data bits so addressing starts with FM_A1 mapped to address bit 2 in software.
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
10/100/1000 Ethernet
E E
U15A
27 8
ENET_2p5V_RESETn 28 COMA GTX_CLK 4
RESET_N TX_CLK 9
TX_EN 7
65 TX_ER
2.5V 64 CONFIG0 11
63 CONFIG1 TXD0 12
J9 2.5V 61 CONFIG2 TXD1 14
ENET_LED_LINK1000 60 CONFIG3 TXD2 16
9 ENET_LED_LINK10 59 CONFIG4 TXD3 17
GMII/MII/TBI INTERFACE
R317 49.9 MDI_P0 VCC ENET_LED_RX 58 CONFIG5 TXD4 18
C354 0.01uF R318 49.9 MDI_N0 1 CONFIG6 TXD5 19
R354 49.9 MDI_P1 TD0_P 2 MDI_P0 29 TXD6 20
TD0_N MDI0_P TXD7
MDI INTERFACE
C432 0.01uF R355 49.9 MDI_N1 MDI_N0 31
R356 49.9 MDI_P2 3 MDI_P1 33 MDI0_N 2
C433 0.01uF R370 49.9 MDI_N2 TD1_P 6 MDI_N1 34 MDI1_P RXCLK 94 R54 R55
R371 49.9 MDI_P3 TD1_N MDI_P2 39 MDI1_N RX_DV 3
MDI2_P RX_ER 0 0
D C462 0.01uF R380 49.9 MDI_N3 4 MDI_N2 41 D
TD2_P 5 MDI_P3 42 MDI2_N 95
TD2_N MDI_N3 43 MDI3_P RXD0 92
7 MDI3_N RXD1 93
TD3_P 8 ENET_2p5V_MDIO 24 RXD2 91
GND_TAB
GND_TAB
TD3_N MDIO RXD3
MGMT
ENET_2p5V_MDC 25 90
10 ENET_2p5V_INTn 23 MDC RXD4 89
2.5V GND INT_N RXD5 87
37 RXD6 86
HSDAC_P RXD7
TEST
HFJ11-1G02E 38
12
11
HSDAC_N 84
R417 ENET_RSET 30 CRS 83 SGMII Mode (default)
2.5V 56 RSET COL
10.0K
X6 SEL_FREQ 79 88E1111-B2-CAA1C000 EOL
S_CLK_P
SGMII INTERFACE
1
EN VCC
4
S_CLK_N
80 88E1111-B2-NDC2C000 Replacement
22 82 8 ENET_TX_P
2 3 ENET_XTAL_25MHZ 55 125CLK S_IN_P 81 8 ENET_TX_N
GND OUT 54 XTAL1 S_IN_N 77 8 ENET_RX_P
25.00MHz 53 XTAL2 S_OUT_P 75 8 ENET_RX_N
C586
VSSC S_OUT_N
C C
0.01uF 47 68 ENET_LED_TX
49 TRST_N LED_TX 69 ENET_LED_RX
TCK LED_RX
JTAG
44 70
2.5V R63 R86 50 TDI LED_DUPLEX 73 ENET_LED_LINK1000
46 TDO LED_LINK1000 74 ENET_LED_LINK100
4.99K 4.70K TMS LED_LINK100 76 ENET_LED_LINK10
LED_LINK10
88E1111
26
48
21
88
96
72
66
52
5
U15B ENET_DVDD 2.5V

2.5V 1.8V
VDDOH
VDDOH
VDDOH
VDDOX
VDDOX
VDDO
VDDO
VDDO
VDDO
32 1 ENET_LED_TX R388 220 D26

36 AVDD DVDD 6
35 AVDD DVDD 10 GREEN_LED C597
C587
40 AVDD DVDD 15 C569
45 AVDD DVDD 57 ENET_LED_RX R387 220 D27 1uF 0.1uF
78 AVDD DVDD 62 0.1uF
AVDD DVDD DVDD = 1.0V
67 GREEN_LED 2.5V U59
13 DVDD 71
DVDD = 1.2V B1 B2
51 NC1 DVDD 85 ENET_LED_LINK1000 R386 220 D28 R434 4.70KENET_2p5V_MDIO C1 VCC VL A1 8 ENET_MDIO
B NC2 DVDD IO VCC1 IO VL1 B
R433 4.70KENET_2p5V_MDC C2 A2 8 ENET_MDC
97 GREEN_LED R421 4.70KENET_2p5V_INTn C3 IO VCC2 IO VL2 A3 8 ENET_INTn
VSS R420 4.70KENET_2p5V_RESETn C4 IO VCC3 IO VL3 A4 8 ENET_RESETn
88E1111 ENET_LED_LINK100 R385 220 D29 IO VCC4 IO VL4
1.8V
B3 B4
GREEN_LED TS GND
MAX3378_UCSP 1.8V
5.0V ENET_LED_LINK10 R384 220 D30
ENET_MDIO R432 DNI
2.5V Place near 88E1111 PHY GREEN_LED ENET_MDC R431 DNI
C126 ENET_INTn R419 DNI
ENET_DVDD ENET_RESETn R418 DNI
1uF U25 ENET_DVDD = 1.0V/0.207A
C430 C405 C388 C431 C461 C459 C428 C404 2.5V 1 4
BIAS OUT
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 3 5 R94 15.0K
IN ADJ
ENET_DVDD C127 6 2 R93
SHDN GND 7
A EP_GND A
10uF C507 C484 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
LTC3025-1 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C429 C387 C386 C403 C460 10.0K 22uF 2.2uF Title
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
External Memory Interface Connector Map
E E
D D
C C
B B
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J14A External Memory Interface - HiLo connector POWER CONTROL

HiLo EMI - EMI SIGNALS
34 VDD_1.25V_SET
MEM_ADDR_CMD0 F1 R6 MEM_DQ_ADDR_CMD0 3,34 VDD_1.35V_SET
MEM_ADDR_CMD1 H1 MEM_ADDR_CMD0 MEM_DQ_ADDR_CMD0 T1 MEM_DQ_ADDR_CMD1 34 VDD_1.5V_SET
MEM_ADDR_CMD2 F2 MEM_ADDR_CMD1 MEM_DQ_ADDR_CMD1 R2 MEM_DQ_ADDR_CMD2
MEM_ADDR_CMD3 G2 MEM_ADDR_CMD2 MEM_DQ_ADDR_CMD2 T2 MEM_DQ_ADDR_CMD3
E MEM_ADDR_CMD3 MEM_DQ_ADDR_CMD3 E
MEM_ADDR_CMD4 H2 U2 MEM_DQ_ADDR_CMD4
MEM_ADDR_CMD5 J2 MEM_ADDR_CMD4 MEM_DQ_ADDR_CMD4 U3 MEM_DQ_ADDR_CMD5
MEM_ADDR_CMD6 K2 MEM_ADDR_CMD5 MEM_DQ_ADDR_CMD5 T4 MEM_DQ_ADDR_CMD6 J14B J14C
MEM_ADDR_CMD7 G3 MEM_ADDR_CMD6 MEM_DQ_ADDR_CMD6 U4 MEM_DQ_ADDR_CMD7 45 VDDQ_1.25V_SET
MEM_ADDR_CMD7 MEM_DQ_ADDR_CMD7 HiLo EMI - POWER HiLo EMI - GND
MEM_ADDR_CMD8 J3 T5 MEM_DQ_ADDR_CMD8 MEM_VDD 2.5V 45 VDDQ_1.35V_SET
MEM_ADDR_CMD9 L3 MEM_ADDR_CMD8 MEM_DQ_ADDR_CMD8 A1 J10 45 VDDQ_1.5V_SET
MEM_ADDR_CMD10 E4 MEM_ADDR_CMD9 V4 MEM_DQS_ADDR_CMD_P C7 L11 A5 GND GND J12
MEM_ADDR_CMD11 F4 MEM_ADDR_CMD10 MEM_DQS_ADDR_CMD_P V5 MEM_DQS_ADDR_CMD_N C9 VDD VEXT = 2.5V VEXT L13 A9 GND GND J14
MEM_ADDR_CMD12 G4 MEM_ADDR_CMD11 MEM_DQS_ADDR_CMD_N C11 VDD VEXT M8 A13 GND GND J17
MEM_ADDR_CMD13 H4 MEM_ADDR_CMD12 C13 VDD VEXT M10 A17 GND GND K3
MEM_ADDR_CMD14 J4 MEM_ADDR_CMD13 V1 MEM_CLK_P D6 VDD VEXT M12 B3 GND GND K7
MEM_ADDR_CMD14 MEM_CLK_P VDD VEXT GND GND MEMORY INTERFACE
MEM_ADDR_CMD15 K4 V2 MEM_CLK_N D8 M14 B7 K9
MEM_ADDR_CMD16 M1 MEM_ADDR_CMD15 MEM_CLK_N D10 VDD VDD = 1.2(DEFAULT) VEXT N7 B11 GND GND K11 4,8 MEM_ADDR_CMD[31:0]
MEM_ADDR_CMD17 M2 MEM_ADDR_CMD16 D12 VDD (1.2V, 1.25V, 1.35V, 1.8V) VEXT N9 B15 GND GND K13
MEM_ADDR_CMD18 N2 MEM_ADDR_CMD17 L6 D14 VDD VEXT N11 C1 GND GND K15 4 MEM_CLK_P
MEM_ADDR_CMD19 L4 MEM_ADDR_CMD18 CONFIG0 M6 E7 VDD VEXT N13 C5 GND GND L1 4 MEM_CLK_N
MEM_ADDR_CMD20 P5 MEM_ADDR_CMD19 CONFIG1 E9 VDD VEXT P8 C6 GND GND L5
MEM_ADDR_CMD21 M5 MEM_ADDR_CMD20 E11 VDD VEXT P10 C8 GND GND L8 4 MEM_DQ_ADDR_CMD[8:0]
MEM_ADDR_CMD22 P1 MEM_ADDR_CMD21 D5 E13 VDD VEXT P12 C10 GND GND L10
D MEM_ADDR_CMD22 RFU0 VDD VEXT GND GND D
MEM_ADDR_CMD23 R4 F5 F6 P14 C12 L12 4 MEM_DQS_ADDR_CMD_P
MEM_ADDR_CMD24 M4 MEM_ADDR_CMD23 RFU1 H5 F8 VDD VEXT C14 GND GND L14 4 MEM_DQS_ADDR_CMD_N
MEM_ADDR_CMD25 R3 MEM_ADDR_CMD24 RFU2 K5 F10 VDD C17 GND GND L17
MEM_ADDR_CMD26 L2 MEM_ADDR_CMD25 RFU3 N6 VDD D3 GND GND M3
MEM_ADDR_CMD27 K1 MEM_ADDR_CMD26 RFU4 R7 VDD DEFAULT IS 1.2V G15 D7 GND GND M7 4,8 MEM_DMA[3:0]
MEM_ADDR_CMD28 P2 MEM_ADDR_CMD27 RFU5 R8 VDD_1.2V_SET NOT USED. VDD_1.25V_SET E15 VDD_1.2V_SET D9 GND GND M9
MEM_ADDR_CMD29 N4 MEM_ADDR_CMD28 RFU6 VDD_1.35V_SET J15 VDD_1.25V_SET D11 GND GND M11 4,8 MEM_DQA[33:0]
MEM_ADDR_CMD30 P4 MEM_ADDR_CMD29 VDD_1.5V_SET L15 VDD_1.35V_SET D13 GND GND M13
MEM_ADDR_CMD31 N3 MEM_ADDR_CMD30 VDD_1.8V_SET NOT USED N16 VDD_1.5V_SET D15 GND GND M15 4,8 MEM_DQSA_P[3:0]
MEM_ADDR_CMD31 NO SUPPORTED 1.8V EMIF. VDD_1.8V_SET E1 GND GND N1
MEM_VDDQ 3.3V E5 GND GND N5 4,8 MEM_DQSA_N[3:0]
MEM_DMA0 B10 M16 MEM_DMB0 F12 J7 E6 GND GND N8
MEM_DMA1 C4 MEM_DMA0 MEM_DMB0 U16 MEM_DMB1 F14 VDDQ 2.5V/3.3V (VTT) J9 E8 GND GND N10 4 MEM_QKA_P[1:0]
MEM_DMA2 B17 MEM_DMA1 MEM_DMB1 U11 MEM_DMB2 G7 VDDQ 2.5V/3.3V (VTT) K6 E10 GND GND N12
MEM_DMA3 F17 MEM_DMA2 MEM_DMB2 U6 MEM_DMB3 G9 VDDQVDDQ = 1.2(DEFAULT)
2.5V/3.3V (VTT) K8 E12 GND GND N14
MEM_DMA3 MEM_DMB3 G11 VDDQ(1.1V,1.2V, 1.25V,2.5V/3.3V (VTT) K10 E14 GND GND N17 4,8 MEM_DMB[3:0]
MEM_DQA0 A4 H16 MEM_DQB0 G13 VDDQ1.35V, 1.8V) 2.5V/3.3V (VTT) K12 E17 GND GND P3
MEM_DQA1 B4 MEM_DQA0 MEM_DQB0 J16 MEM_DQB1 H6 VDDQ 2.5V/3.3V (VTT) J11 F3 GND GND P6 4,8 MEM_DQB[33:0]
MEM_DQA2 B5 MEM_DQA1 MEM_DQB1 K16 MEM_DQB2 H8 VDDQ 2.5V/3.3V (VTT) L7 F7 GND GND P7
C MEM_DQA2 MEM_DQB2 VDDQ 2.5V/3.3V (VTT) GND GND C
MEM_DQA3 B6 L16 MEM_DQB3 H10 L9 F9 P9 4,8 MEM_DQSB_P[3:0]
MEM_DQA4 A8 MEM_DQA3 MEM_DQB3 H17 MEM_DQB4 H12 VDDQ 2.5V/3.3V (VTT) F11 GND GND P11
MEM_DQA5 B8 MEM_DQA4 MEM_DQB4 K17 MEM_DQB5 VDDQ MEM_VREF F13 GND GND P13 4,8 MEM_DQSB_N[3:0]
MEM_DQA6 B9 MEM_DQA5 MEM_DQB5 K18 MEM_DQB6 N15 H14 F15 GND GND P15
MEM_DQA7 A10 MEM_DQA6 MEM_DQB6 L18 MEM_DQB7 P16 VDDQ_1.1V_SET VREF J13 G1 GND GND R1 4 MEM_QKB_P[1:0]
MEM_DQA8 B1 MEM_DQA7 MEM_DQB7 M17 MEM_DQB8 VDDQ_1.25V_SET R15 VDDQ_1.2V_SET VREF K14 G5 GND GND R5
MEM_DQA9 B2 MEM_DQA8 MEM_DQB8 N18 MEM_DQB9 VDDQ_1.35V_SET R14 VDDQ_1.25V_SET VREF G6 GND GND R9
MEM_DQA10 C2 MEM_DQA9 MEM_DQB9 P17 MEM_DQB10 VDDQ_1.5V_SET R12 VDDQ_1.35V_SET G8 GND GND R10
MEM_DQA11 C3 MEM_DQA10 MEM_DQB10 P18 MEM_DQB11 R11 VDDQ_1.5V_SET G10 GND GND R13
MEM_DQA12 E3 MEM_DQA11 MEM_DQB11 R18 MEM_DQB12 VDDQ_1.8V_SET G12 GND GND R17
MEM_DQA13 D4 MEM_DQA12 MEM_DQB12 T16 MEM_DQB13 VDDQ DEFAULT IS 1.2V G14 GND GND T3
MEM_DQA13 MEM_DQB13 HLS-180324-B-12 GND GND
MEM_DQA14 D1 T17 MEM_DQB14 VDDQ_1.2V_SET NOT USED. G17 T7
MEM_DQA15 D2 MEM_DQA14 MEM_DQB14 T18 MEM_DQB15 H3 GND GND T11
MEM_DQA16 A12 MEM_DQA15 MEM_DQB15 U15 MEM_DQB16 VDDQ_1.1V_SET and VDDQ_1.8V_SET NOT USED H7 GND GND T15
MEM_DQA17 B12 MEM_DQA16 MEM_DQB16 T14 MEM_DQB17 NO SUPPORTED 1.1V or 1.8V EMIF PLANNED. H9 GND GND U1
MEM_DQA18 B13 MEM_DQA17 MEM_DQB17 U14 MEM_DQB18 H11 GND GND U5
MEM_DQA19 B14 MEM_DQA18 MEM_DQB18 V14 MEM_DQB19 H13 GND GND U9
MEM_DQA20 C15 MEM_DQA19 MEM_DQB19 T13 MEM_DQB20 H15 GND GND U13
MEM_DQA21 A16 MEM_DQA20 MEM_DQB20 T12 MEM_DQB21 MEM_VDD J1 GND GND U17
B MEM_DQA21 MEM_DQB21 GND GND B
MEM_DQA22 B16 U12 MEM_DQB22 J5 V3
MEM_DQA23 A18 MEM_DQA22 MEM_DQB22 V12 MEM_DQB23 J6 GND GND V7
MEM_DQA24 C16 MEM_DQA23 MEM_DQB23 T10 MEM_DQB24 J8 GND GND V11
MEM_DQA25 D16 MEM_DQA24 MEM_DQB24 U10 MEM_DQB25 C730 Place near GND GND V15
C728 C729
MEM_DQA26 E16 MEM_DQA25 MEM_DQB25 V10 MEM_DQB26 HILO connector GND
MEM_DQA27 F16 MEM_DQA26 MEM_DQB26 T9 MEM_DQB27 10uF 1uF 0.1uF J14 VDD pins HLS-180324-B-12
MEM_DQA28 D17 MEM_DQA27 MEM_DQB27 T8 MEM_DQB28
MEM_DQA29 C18 MEM_DQA28 MEM_DQB28 U8 MEM_DQB29
MEM_DQA30 D18 MEM_DQA29 MEM_DQB29 U7 MEM_DQB30
MEM_DQA31 E18 MEM_DQA30 MEM_DQB30 V6 MEM_DQB31
MEM_DQA32 E2 MEM_DQA31 MEM_DQB31 R16 MEM_DQB32
MEM_DQA33 G16 MEM_DQA32 MEM_DQB32 T6 MEM_DQB33
MEM_DQA33 MEM_DQB33 MEM_VDDQ
MEM_DQSA_P0 A6 H18 MEM_DQSB_P0
MEM_DQSA_N0 A7 MEM_DQSA_P0 MEM_DQSB_P0 J18 MEM_DQSB_N0
MEM_DQSA_P1 A2 MEM_DQSA_N0 MEM_DQSB_N0 U18 MEM_DQSB_P1
MEM_DQSA_N1 A3 MEM_DQSA_P1 MEM_DQSB_P1 V18 MEM_DQSB_N1 C733 Place near
C731 C732
MEM_DQSA_P2 A14 MEM_DQSA_N1 MEM_DQSB_N1 V16 MEM_DQSB_P2 HILO connector
MEM_DQSA_N2 A15 MEM_DQSA_P2 MEM_DQSB_P2 V17 MEM_DQSB_N2 10uF 1uF 0.1uF J14 VDDQ pins
A MEM_DQSA_N2 MEM_DQSB_N2 A
MEM_DQSA_P3 F18 V8 MEM_DQSB_P3 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
MEM_DQSA_N3 G18 MEM_DQSA_P3 MEM_DQSB_P3 V9 MEM_DQSB_N3 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
MEM_DQSA_N3 MEM_DQSB_N3 Title
MEM_QKA_P0 A11 M18 MEM_QKB_P0 Arria 10 GX FPGA Development Kit
MEM_QKA_P1 B18 MEM_QKA_N0 MEM_QKB_N0 V13 MEM_QKB_P1
MEM_QKA_N1 MEM_QKB_N1 Size Document Number Rev
B 150-0321301-E3 (6XX-44366R) E3.1
HLS-180324-B-12
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Display Port (x4)

DISPLAYPORT INTERFACE
1.8V 3.3V
E
11 DP_ML_LANE_P[3:0] E
C305 C290 C306
11 DP_ML_LANE_N[3:0]
0.1uF 0.1uF 1uF
3.3V 3.3V U47 4 DP_HOT_PLUG
C323 C331 1 11 4 DP_RETURN
0.1uF 0.1uF DP_HOT_PLUG 2 VL VCC 10 DP_3p3V_HOT_PLUG 4 DP_AUX_CH_P
3.3V DP_RETURN 3 IO VL1 IO VCC1 9 DP_3p3V_RETURN 4 DP_AUX_CH_N
DP_CONFIG1 4 IO VL2 IO VCC2 8 DP_3p3V_CONFIG1
DP_CONFIG2 5 IO VL3 IO VCC3 7 DP_3p3V_CONFIG2 4 DP_CONFIG1
82401646 82401646 IO VL4 IO VCC4 1.8V 4 DP_CONFIG2
5
R589 6 12
D41 VDD GND IO6 IO5 VDD GND IO6 IO5 D39 DNI GND OE
ST2149B
F1
500mA, Resettable
IO1 IO2 IO3 IO4 IO1 IO2 IO3 IO4
4
D D
J5
20 1 DP_ML_LANE_CP0 C57 0.1uF DP_ML_LANE_P0
DP_PWR ML_LANE_0P 3 DP_ML_LANE_CN0 DP_ML_LANE_N0
R281 100K DP_3p3V_HOT_PLUG 18 ML_LANE_0N C56 0.1uF
DP_3p3V_RETURN R268 DNI DP_RTN 19 HP_DETECT 4 DP_ML_LANE_CP1 C51 0.1uF DP_ML_LANE_P1
R269 0 RTN ML_LANE_1P 6 DP_ML_LANE_CN1 DP_ML_LANE_N1
ML_LANE_1N C50 0.1uF
R271 1M DP_3p3V_CONFIG1 13 7 DP_ML_LANE_CP2 C40 0.1uF DP_ML_LANE_P2
R270 1M DP_3p3V_CONFIG2 14 CONFIG1 ML_LANE_2P 9 DP_ML_LANE_CN2 DP_ML_LANE_N2
CONFIG2 ML_LANE_2N C39 0.1uF
2 10 DP_ML_LANE_CP3 C31 0.1uF DP_ML_LANE_P3
5 GND ML_LANE_3P 12 DP_ML_LANE_CN3 DP_ML_LANE_N3
8 GND ML_LANE_3N C30 0.1uF
11 GND 15 DP_AUX_CP
16 GND AUX_CH_P 17 DP_AUX_CN Auxilary Channel -> Bidirctional LVDS 1Mbps/(720Mbps optional).
GND AUX_CH_N
21 23 Quartus IO Standard = BLVDS
22 MH1 MH3 24 TX -> DIFF SSTL-1.8
MH2 MH4 RX -> LVDS
C FogBugz Case 135234 & 147387 C
0472720024
1M R267
GND_DP GND_DP
1.8V 3.3V
Usually 3.3V for DP_AUX_CP C309 0.1uF
4.7nF C297 GND_DP DP, but Arria 10
is 1.8V LVDS.
R264 R265 R285 100K R276
10.0K DNI 49.9
DP_AUX_CH_P
VBIAS_DP DP_AUX_CH_N
C304 C310 1.8V 3.3V

R277 R262 DNI R275
10uF 0.1uF 10.0K 49.9
R263 100K
B B
DP_AUX_CN C291 0.1uF
1) TX uses diff sstl18 configuration, which is able to meet peak-to-peak differential voltage and common mode voltage spec for DP.
2) RX uses LVDS input, but user need to ensure pin voltage at NF receiver end is <1.9v.
a. If the channel is AC couple, then user need to choose the correct Vbias_RX so that Vpin < 1.9v. The spec is 0 – 2v, which is quite
wide. Selecting Vbias_Rx at 2v region will cause NF device to have reliability issue.
b. If the channel is DC couple, user need to make sure TX common mode voltage + ground reference differences between Tx and Rx will not
cause Vpin for NF to be higher than 1.9v.
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FMC Port A E20

E23
J1F
GND E17
J1A
LVDS P/N NEED TO BE MATCHED BY +/-10ps WITH COMPENSATION ON BOARD FOR PACKAGE DELAYS. E26 GND GND E14
E29 GND GND E11
FMCA_LA_RX_CLK_P0 G6 G18 FMCA_LA_RX_P6 E38 GND GND E8
FMCA_LA_RX_CLK_N0 G7 LA_P0_CC LA_P16 G19 FMCA_LA_RX_N6 E32 GND GND E5
FMCA_LA_RX_CLK_P1 D8 LA_N0_CC LA_N16 D20 FMCA_LA_TX_P8 J1B J1C E35 GND GND E4
FMCA_LA_RX_CLK_N1 D9 LA_P1_CC LA_P17 D21 FMCA_LA_TX_N8 F4 F13 E40 GND GND E1
E LA_N1_CC LA_N17 HA_P0_CC HA_P12 GND GND E
FMCA_LA_TX_P0 H7 C22 FMCA_LA_RX_P7 F5 F14 FMCA_DP_C2M_P11 K25 J30 K2 F39
FMCA_LA_TX_N0 H8 LA_P2 LA_P18_CC C23 FMCA_LA_RX_N7 E2 HA_N0_CC HA_N12 E12 FMCA_DP_C2M_N11 K26 HB_P0_CC HB_P11 J31 K3 GND GND F36
FMCA_LA_RX_P0 G9 LA_N2 LA_N18_CC H22 FMCA_LA_TX_P9 E3 HA_P1_CC HA_P13 E13 J24 HB_N0_CC HB_N11 F31 K6 GND GND F33
FMCA_LA_RX_N0 G10 LA_P3 LA_P19 H23 FMCA_LA_TX_N9 FMCA_DP_M2C_P11 K7 HA_N1_CC HA_N13 J15 J25 HB_P1 HB_P12 F32 K9 GND GND F30
LA_N3 LA_N19 FMCA_DP_M2C_N11 K8 HA_P2 HA_P14 J16 F22 HB_N1 HB_N12 E30 K12 GND GND F27
FMCA_LA_TX_P1 H10 G21 FMCA_LA_RX_P8 J6 HA_N2 HA_N14 F16 F23 HB_P2 HB_P13 E31 K15 GND GND F24
FMCA_LA_TX_N1 H11 LA_P4 LA_P20 G22 FMCA_LA_RX_N8 J7 HA_P3 HA_P15 F17 E21 HB_N2 HB_N13 K34 FMCA_DP_C2M_P14 K18 GND GND F21
FMCA_LA_TX_P2 D11 LA_N4 LA_N20 H25 FMCA_LA_TX_P10 HA_N3 HA_N15 E22 HB_P3 HB_P14 K35 FMCA_DP_C2M_N14 K21 GND GND F18
FMCA_LA_TX_N2 D12 LA_P5 LA_P21 H26 FMCA_LA_TX_N10 F7 E15 HB_N3 HB_N14 K24 GND GND F15
FMCA_LA_RX_P1 C10 LA_N5 LA_N21 G24 FMCA_LA_RX_P9 F8 HA_P4 HA_P16 E16 F25 J33 K27 GND GND F12
FMCA_LA_RX_N1 C11 LA_P6 LA_P22 G25 FMCA_LA_RX_N9 E6 HA_N4 HA_N16 K16 FMCA_DP_M2C_P14 F26 HB_P4 HB_P15 J34 K30 GND GND F9
FMCA_LA_TX_P3 H13 LA_N6 LA_N22 D23 FMCA_LA_TX_P11 E7 HA_P5 HA_P17_CC K17 FMCA_DP_M2C_N14 E24 HB_N4 HB_N15 F34 K33 GND GND F6
FMCA_LA_TX_N3 H14 LA_P7 LA_P23 D24 FMCA_LA_TX_N11 FMCA_DP_M2C_P12 K10 HA_N5 HA_N17_CC J18 E25 HB_P5 HB_P16 F35 K36 GND GND F3
LA_N7 LA_N23 FMCA_DP_M2C_N12 K11 HA_P6 HA_P18 J19 FMCA_DP_C2M_P12 K28 HB_N5 HB_N16 K37 FMCA_DP_C2M_P15 K39 GND GND F2
FMCA_LA_RX_P2 G12 H28 FMCA_LA_TX_P12 J9 HA_N6 HA_N18 F19 FMCA_DP_C2M_N12 K29 HB_P6_CC HB_P17_CC K38 FMCA_DP_C2M_N15 J1 GND GND G40
FMCA_LA_RX_N2 G13 LA_P8 LA_P24 H29 FMCA_LA_TX_N12 J10 HA_P7 HA_P19 F20 J27 HB_N6_CC HB_N17_CC J36 J4 GND GND G38
FMCA_LA_TX_P4 D14 LA_N8 LA_N24 G27 FMCA_LA_RX_P10 HA_N7 HA_N19 J28 HB_P7 HB_P18 J37 J5 GND GND G35
FMCA_LA_TX_N4 D15 LA_P9 LA_P25 G28 FMCA_LA_RX_N10 F10 E18 HB_N7 HB_N18 J8 GND GND G32
FMCA_LA_RX_P3 C14 LA_N9 LA_N25 D26 FMCA_LA_TX_P13 F11 HA_P8 HA_P20 E19 F28 E33 J11 GND GND G29
D LA_P10 LA_P26 HA_N8 HA_N20 HB_P8 HB_P19 GND GND D
FMCA_LA_RX_N3 C15 D27 FMCA_LA_TX_N13 E9 K19 FMCA_DP_M2C_P15 F29 E34 J14 G26
FMCA_LA_TX_P5 H16 LA_N10 LA_N26 C26 FMCA_LA_RX_P11 E10 HA_P9 HA_P21 K20 FMCA_DP_M2C_N15 E27 HB_N8 HB_N19 F37 J17 GND GND G23
FMCA_LA_TX_N5 H17 LA_P11 LA_P27 C27 FMCA_LA_RX_N11 FMCA_DP_M2C_P13 K13 HA_N9 HA_N21 J21 E28 HB_P9 HB_P20 F38 J20 GND GND G20
LA_N11 LA_N27 FMCA_DP_M2C_N13 K14 HA_P10 HA_P22 J22 FMCA_DP_C2M_P13 K31 HB_N9 HB_N20 E36 J23 GND GND G17
FMCA_LA_RX_P4 G15 H31 FMCA_LA_TX_P14 J12 HA_N10 HA_N22 K22 FMCA_DP_C2M_P10 FMCA_DP_C2M_N13 K32 HB_P10 HB_P21 E37 J26 GND GND G14
FMCA_LA_RX_N4 G16 LA_P12 LA_P28 H32 FMCA_LA_TX_N14 J13 HA_P11 HA_P23 K23 FMCA_DP_C2M_N10 HB_N10 HB_N21 J29 GND GND G11
FMCA_LA_TX_P6 D17 LA_N12 LA_N28 G30 FMCA_LA_RX_P12 HA_N11 HA_N23 ASP-134486-01 J32 GND GND G8
FMCA_LA_TX_N6 D18 LA_P13 LA_P29 G31 FMCA_LA_RX_N12 ASP-134486-01 J35 GND GND G5
FMCA_LA_RX_P5 C18 LA_N13 LA_N29 H34 FMCA_LA_TX_P15 J38 GND GND G4
FMCA_LA_RX_N5 C19 LA_P14 LA_P30 H35 FMCA_LA_TX_N15 J40 GND GND G1
LA_N14 LA_N30 FMC INTERFACE GND GND
FMCA_LA_TX_P7 H19 G33 FMCA_LA_RX_P13 H3 A40
FMCA_LA_TX_N7 H20 LA_P15 LA_P31 G34 FMCA_LA_RX_N13 A10_VCCIO_FMCA H6 GND GND A37
LA_N15 LA_N31 H37 FMCA_LA_TX_P16 J1E 8 FMCA_LA_RX_CLK_P[1:0] H9 GND GND A36
LA_P32 H38 FMCA_LA_TX_N16 3.3V A10_VCCIO_FMCA H12 GND GND A33
LA_N32 G36 FMCA_LA_RX_P14 D32 E39 limited to 1.8V 8 FMCA_LA_RX_CLK_N[1:0] H15 GND GND A32
LA_P33 G37 FMCA_LA_RX_N14 3P3VAUX VADJ F40 H18 GND GND A29
LA_N33 D40 VADJ G39 5 FMCA_LA_RX_P[14:0] H21 GND GND A28
C39 3P3V VADJ H40 H24 GND GND A25
ASP-134486-01 D36 3P3V VADJ 5 FMCA_LA_RX_N[14:0] H27 GND GND A24
C 3P3V GND GND C
D38 K40 H30 A21
3P3V VIO_B_M2C J39 5 FMCA_LA_TX_P[16:0] H33 GND GND A20
12V VIO_B_M2C VREF_FMCA H36 GND GND A17
C35 K1 5 FMCA_LA_TX_N[16:0] H39 GND GND A16
C37 12P0V VREF_B_M2C H1 D2 GND GND A13
12P0V VREF_A_M2C PG_M2C only on High D3 GND GND A12
Pincount versions. 8 FMCA_CLK_M2C_P[1:0] D6 GND GND A9
3.3V 3.3V D7 GND GND A8
R249 10.0KFMCA_C2M_PG D1 F1 FMCA_M2C_PG R246 10.0K 8 FMCA_CLK_M2C_N[1:0] D10 GND GND A5
PG_C2M PG_M2C D13 GND GND A4
J1D FMCA_PRSNTn H2
6,13,24,26 D16 GND GND A1
PRSNT_M2C_L D34 FMCA_JTAG_RST R250 10.0K D19 GND GND B39
FMCA_DP_C2M_P0 C2 C6 FMCA_DP_M2C_P0 FMCA_3P3V_SDA C31
5 TRST D33
25 FMCA_JTAG_TMS D22 GND GND B38
FMCA_DP_C2M_N0 C3 DP0_C2M_P DP0_M2C_P C7 FMCA_DP_M2C_N0 FMCA_3P3V_SCL C30
5 SDA TMS D31
25 FMCA_JTAG_TDO D25 GND GND B35
FMCA_DP_C2M_P1 A22 DP0_C2M_N DP0_M2C_N A2 FMCA_DP_M2C_P1 SCL TDO D30
25 FMCA_JTAG_TDI D28 GND GND B34
FMCA_DP_C2M_N1 A23 DP1_C2M_P DP1_M2C_P A3 FMCA_DP_M2C_N1 FMCA_DP_M2C_P10 K4 TDI D29
25 FMCA_JTAG_TCK 12 FMCA_DP_C2M_P[15:0] D37 GND GND B31
FMCA_DP_C2M_P2 A26 DP1_C2M_N DP1_M2C_N A6 FMCA_DP_M2C_P2 FMCA_DP_M2C_N10 K5 CLK2_BIDIR_P TCK D39 GND GND B30
FMCA_DP_C2M_N2 A27 DP2_C2M_P DP2_M2C_P A7 FMCA_DP_M2C_N2 J2 CLK2_BIDIR_N H4 FMCA_CLK_M2C_P0 12 FMCA_DP_C2M_N[15:0] C1 GND GND B27
FMCA_DP_C2M_P3 A30 DP2_C2M_N DP2_M2C_N A10 FMCA_DP_M2C_P3 CLK2_BIDIR, CLK3_BIDIR, J3 CLK3_BIDIR_PCLK0_M2C_P H5 FMCA_CLK_M2C_N0 C4 GND GND B26
B DP3_C2M_P DP3_M2C_P CLK3_BIDIR_NCLK0_M2C_N 12 FMCA_DP_M2C_P[15:0] GND GND B
FMCA_DP_C2M_N3 A31 A11 FMCA_DP_M2C_N3 and CLK_DIR only on High G2 FMCA_CLK_M2C_P1 C5 B23
FMCA_DP_C2M_P4 A34 DP3_C2M_N DP3_M2C_N A14 FMCA_DP_M2C_P4 Pincount versions. B1 CLK1_M2C_P G3 FMCA_CLK_M2C_N1 C8 GND GND B22
FMCA_DP_C2M_N4 A35 DP4_C2M_P DP4_M2C_P A15 FMCA_DP_M2C_N4 CLK_DIR CLK1_M2C_N 12 FMCA_DP_M2C_N[15:0] C9 GND GND B19
DP4_C2M_N DP4_M2C_N FMCA_GA0 C34 B40 C12 GND GND B18
FMCA_DP_C2M_P5 A38 A18 FMCA_DP_M2C_P5 FMCA_GA1 D35 GA0 RES0 5 FMCA_GA[1:0] C13 GND GND B15
FMCA_DP_C2M_N5 A39 DP5_C2M_P DP5_M2C_P A19 FMCA_DP_M2C_N5 GA1 C16 GND GND B14
FMCA_DP_C2M_P6 B36 DP5_C2M_N DP5_M2C_N B16 FMCA_DP_M2C_P6 ASP-134486-01 C17 GND GND B11
FMCA_DP_C2M_N6 B37 DP6_C2M_P DP6_M2C_P B17 FMCA_DP_M2C_N6 A10_VCCIO_FMCA 13 FMCA_C2M_PG C20 GND GND B10
FMCA_DP_C2M_P7 B32 DP6_C2M_N DP6_M2C_N B12 FMCA_DP_M2C_P7 C21 GND GND B7
FMCA_DP_C2M_N7 B33 DP7_C2M_P DP7_M2C_P B13 FMCA_DP_M2C_N7 C24 GND GND B6
FMCA_DP_C2M_P8 B28 DP7_C2M_N DP7_M2C_N B8 FMCA_DP_M2C_P8 12 FMCA_GBTCLK_M2C_P[1:0] C25 GND GND B3
FMCA_DP_C2M_N8 B29 DP8_C2M_P DP8_M2C_P B9 FMCA_DP_M2C_N8 R240 12 FMCA_GBTCLK_M2C_N[1:0] C28 GND GND B2
FMCA_DP_C2M_P9 B24 DP8_C2M_N DP8_M2C_N B4 FMCA_DP_M2C_P9 C29 GND GND C40
DP9_C2M_P DP9_M2C_P DNI GND GND
FMCA_DP_C2M_N9 B25 B5 FMCA_DP_M2C_N9 C32 C38
DP9_C2M_N DP9_M2C_N VREF_FMCA C33 GND GND C36
D4 FMCA_GBTCLK_M2C_P0 GND GND
GBTCLK0_M2C_P D5 FMCA_GBTCLK_M2C_N0 ASP-134486-01
GBTCLK0_M2C_N B20 FMCA_GBTCLK_M2C_P1 C262 C261
GBTCLK1_M2C_P B21 FMCA_GBTCLK_M2C_N1 R239
A GBTCLK1_M2C_N A
0.1uF 0.1uF DNI Altera Corporation, 101 Innovation Dr., San Jose CA 95134
ASP-134486-01 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FMC Port B E20

E23
J2F
GND E17
J2A E26 GND GND E14
LVDS P/N NEED TO BE MATCHED BY +/-10ps WITH COMPENSATION ON BOARD FOR PACKAGE DELAYS. E29 GND GND E11
FMCB_LA_RX_CLK_P0 G6 G18 FMCB_LA_RX_P6 E38 GND GND E8
FMCB_LA_RX_CLK_N0 G7 LA_P0_CC LA_P16 G19 FMCB_LA_RX_N6 E32 GND GND E5
FMCB_LA_RX_CLK_P1 D8 LA_N0_CC LA_N16 D20 FMCB_LA_TX_P8 J2B J2C E35 GND GND E4
FMCB_LA_RX_CLK_N1 D9 LA_P1_CC LA_P17 D21 FMCB_LA_TX_N8 F4 F13 E40 GND GND E1
E LA_N1_CC LA_N17 HA_P0_CC HA_P12 GND GND E
FMCB_LA_TX_P0 H7 C22 FMCB_LA_RX_P7 F5 F14 FMCB_DP_C2M_P11K25 J30 K2 F39
FMCB_LA_TX_N0 H8 LA_P2 LA_P18_CC C23 FMCB_LA_RX_N7 E2 HA_N0_CC HA_N12 E12 FMCB_DP_C2M_N11K26 HB_P0_CC HB_P11 J31 K3 GND GND F36
FMCB_LA_RX_P0 G9 LA_N2 LA_N18_CC H22 FMCB_LA_TX_P9 E3 HA_P1_CC HA_P13 E13 J24 HB_N0_CC HB_N11 F31 K6 GND GND F33
FMCB_LA_RX_N0 G10 LA_P3 LA_P19 H23 FMCB_LA_TX_N9 FMCB_DP_M2C_P11 K7 HA_N1_CC HA_N13 J15 J25 HB_P1 HB_P12 F32 K9 GND GND F30
LA_N3 LA_N19 FMCB_DP_M2C_N11 K8 HA_P2 HA_P14 J16 F22 HB_N1 HB_N12 E30 K12 GND GND F27
FMCB_LA_TX_P1 H10 G21 FMCB_LA_RX_P8 J6 HA_N2 HA_N14 F16 F23 HB_P2 HB_P13 E31 K15 GND GND F24
FMCB_LA_TX_N1 H11 LA_P4 LA_P20 G22 FMCB_LA_RX_N8 J7 HA_P3 HA_P15 F17 E21 HB_N2 HB_N13 K34 FMCB_DP_C2M_P14 K18 GND GND F21
FMCB_LA_TX_P2 D11 LA_N4 LA_N20 H25 FMCB_LA_TX_P10 HA_N3 HA_N15 E22 HB_P3 HB_P14 K35 FMCB_DP_C2M_N14 K21 GND GND F18
FMCB_LA_TX_N2 D12 LA_P5 LA_P21 H26 FMCB_LA_TX_N10 F7 E15 HB_N3 HB_N14 K24 GND GND F15
FMCB_LA_RX_P1 C10 LA_N5 LA_N21 G24 FMCB_LA_RX_P9 F8 HA_P4 HA_P16 E16 F25 J33 K27 GND GND F12
FMCB_LA_RX_N1 C11 LA_P6 LA_P22 G25 FMCB_LA_RX_N9 E6 HA_N4 HA_N16 K16 FMCB_DP_M2C_P14 F26 HB_P4 HB_P15 J34 K30 GND GND F9
FMCB_LA_TX_P3 H13 LA_N6 LA_N22 D23 FMCB_LA_TX_P11 E7 HA_P5 HA_P17_CC K17 FMCB_DP_M2C_N14 E24 HB_N4 HB_N15 F34 K33 GND GND F6
FMCB_LA_TX_N3 H14 LA_P7 LA_P23 D24 FMCB_LA_TX_N11 FMCB_DP_M2C_P12 K10 HA_N5 HA_N17_CC J18 E25 HB_P5 HB_P16 F35 K36 GND GND F3
LA_N7 LA_N23 FMCB_DP_M2C_N12 K11 HA_P6 HA_P18 J19 FMCB_DP_C2M_P12K28 HB_N5 HB_N16 K37 FMCB_DP_C2M_P15 K39 GND GND F2
FMCB_LA_RX_P2 G12 H28 FMCB_LA_TX_P12 J9 HA_N6 HA_N18 F19 FMCB_DP_C2M_N12K29 HB_P6_CC HB_P17_CC K38 FMCB_DP_C2M_N15 J1 GND GND G40
FMCB_LA_RX_N2 G13 LA_P8 LA_P24 H29 FMCB_LA_TX_N12 J10 HA_P7 HA_P19 F20 J27 HB_N6_CC HB_N17_CC J36 J4 GND GND G38
FMCB_LA_TX_P4 D14 LA_N8 LA_N24 G27 FMCB_LA_RX_P10 HA_N7 HA_N19 J28 HB_P7 HB_P18 J37 J5 GND GND G35
FMCB_LA_TX_N4 D15 LA_P9 LA_P25 G28 FMCB_LA_RX_N10 F10 E18 HB_N7 HB_N18 J8 GND GND G32
FMCB_LA_RX_P3 C14 LA_N9 LA_N25 D26 FMCB_LA_TX_P13 F11 HA_P8 HA_P20 E19 F28 E33 J11 GND GND G29
D LA_P10 LA_P26 HA_N8 HA_N20 HB_P8 HB_P19 GND GND D
FMCB_LA_RX_N3 C15 D27 FMCB_LA_TX_N13 E9 K19 FMCB_DP_M2C_P15 F29 E34 J14 G26
FMCB_LA_TX_P5 H16 LA_N10 LA_N26 C26 FMCB_LA_RX_P11 E10 HA_P9 HA_P21 K20 FMCB_DP_M2C_N15 E27 HB_N8 HB_N19 F37 J17 GND GND G23
FMCB_LA_TX_N5 H17 LA_P11 LA_P27 C27 FMCB_LA_RX_N11 FMCB_DP_M2C_P13 K13 HA_N9 HA_N21 J21 E28 HB_P9 HB_P20 F38 J20 GND GND G20
LA_N11 LA_N27 FMCB_DP_M2C_N13 K14 HA_P10 HA_P22 J22 FMCB_DP_C2M_P13K31 HB_N9 HB_N20 E36 J23 GND GND G17
FMCB_LA_RX_P4 G15 H31 FMCB_LA_TX_P14 J12 HA_N10 HA_N22 K22 FMCB_DP_C2M_P10 FMCB_DP_C2M_N13K32 HB_P10 HB_P21 E37 J26 GND GND G14
FMCB_LA_RX_N4 G16 LA_P12 LA_P28 H32 FMCB_LA_TX_N14 J13 HA_P11 HA_P23 K23 FMCB_DP_C2M_N10 HB_N10 HB_N21 J29 GND GND G11
FMCB_LA_TX_P6 D17 LA_N12 LA_N28 G30 FMCB_LA_RX_P12 HA_N11 HA_N23 ASP-134486-01 J32 GND GND G8
FMCB_LA_TX_N6 D18 LA_P13 LA_P29 G31 FMCB_LA_RX_N12 ASP-134486-01 J35 GND GND G5
FMCB_LA_RX_P5 C18 LA_N13 LA_N29 H34 FMCB_LA_TX_P15 J38 GND GND G4
LA_P14 LA_P30 FMC INTERFACE GND GND
FMCB_LA_RX_N5 C19 H35 FMCB_LA_TX_N15 J40 G1
FMCB_LA_TX_P7 H19 LA_N14 LA_N30 G33 FMCB_LA_RX_P13 H3 GND GND A40
FMCB_LA_TX_N7 H20 LA_P15 LA_P31 G34 FMCB_LA_RX_N13 A10_VCCIO_FMCB 8 FMCB_LA_RX_CLK_P[1:0] H6 GND GND A37
LA_N15 LA_N31 H37 FMCB_LA_TX_P16 J2E H9 GND GND A36
LA_P32 H38 FMCB_LA_TX_N16 3.3V A10_VCCIO_FMCB 8 FMCB_LA_RX_CLK_N[1:0] H12 GND GND A33
LA_N32 G36 FMCB_LA_RX_P14 D32 E39 limited to 1.8V H15 GND GND A32
LA_P33 G37 FMCB_LA_RX_N14 3P3VAUX VADJ F40 6 FMCB_LA_RX_P[14:0] H18 GND GND A29
LA_N33 D40 VADJ G39 H21 GND GND A28
C39 3P3V VADJ H40 6 FMCB_LA_RX_N[14:0] H24 GND GND A25
ASP-134486-01 D36 3P3V VADJ H27 GND GND A24
C 3P3V GND GND C
D38 K40 6 FMCB_LA_TX_P[16:0] H30 A21
3P3V VIO_B_M2C J39 H33 GND GND A20
12V VIO_B_M2C VREF_FMCB 6 FMCB_LA_TX_N[16:0] H36 GND GND A17
C35 K1 H39 GND GND A16
C37 12P0V VREF_B_M2C H1 8 FMCB_CLK_M2C_P[1:0] D2 GND GND A13
12P0V VREF_A_M2C D3 GND GND A12
PG_M2C only on High 8 FMCB_CLK_M2C_N[1:0] D6 GND GND A9
3.3V Pincount versions. 3.3V D7 GND GND A8
R247 10.0KFMCB_C2M_PG D1 F1 FMCB_M2C_PG R245 10.0K D10 GND GND A5
PG_C2M PG_M2C D13 GND GND A4
J2D FMCB_PRSNTn H2
6,13,24,26 D16 GND GND A1
PRSNT_M2C_L D34 FMCB_JTAG_RST R248 10.0K D19 GND GND B39
FMCB_DP_C2M_P0 C2 C6 FMCB_DP_M2C_P0 FMCB_3P3V_SDA 6C31 TRST D33
25 FMCB_JTAG_TMS D22 GND GND B38
FMCB_DP_C2M_N0 C3 DP0_C2M_P DP0_M2C_P C7 FMCB_DP_M2C_N0 FMCB_3P3V_SCL 6C30 SDA TMS D31
25 FMCB_JTAG_TDO D25 GND GND B35
FMCB_DP_C2M_P1 A22 DP0_C2M_N DP0_M2C_N A2 FMCB_DP_M2C_P1 SCL TDO D30
25 FMCB_JTAG_TDI D28 GND GND B34
FMCB_DP_C2M_N1 A23 DP1_C2M_P DP1_M2C_P A3 FMCB_DP_M2C_N1 FMCB_DP_M2C_P10 K4 TDI D29
25 FMCB_JTAG_TCK 12 FMCB_DP_C2M_P[15:0] D37 GND GND B31
FMCB_DP_C2M_P2 A26 DP1_C2M_N DP1_M2C_N A6 FMCB_DP_M2C_P2 FMCB_DP_M2C_N10 K5 CLK2_BIDIR_P TCK D39 GND GND B30
FMCB_DP_C2M_N2 A27 DP2_C2M_P DP2_M2C_P A7 FMCB_DP_M2C_N2 J2 CLK2_BIDIR_N H4 FMCB_CLK_M2C_P0 12 FMCB_DP_C2M_N[15:0] C1 GND GND B27
FMCB_DP_C2M_P3 A30 DP2_C2M_N DP2_M2C_N A10 FMCB_DP_M2C_P3 CLK2_BIDIR, CLK3_BIDIR, J3 CLK3_BIDIR_PCLK0_M2C_P H5 FMCB_CLK_M2C_N0 C4 GND GND B26
B DP3_C2M_P DP3_M2C_P CLK3_BIDIR_NCLK0_M2C_N 12 FMCB_DP_M2C_P[15:0] GND GND B
FMCB_DP_C2M_N3 A31 A11 FMCB_DP_M2C_N3 and CLK_DIR only on High G2 FMCB_CLK_M2C_P1 C5 B23
FMCB_DP_C2M_P4 A34 DP3_C2M_N DP3_M2C_N A14 FMCB_DP_M2C_P4 Pincount versions. B1 CLK1_M2C_P G3 FMCB_CLK_M2C_N1 C8 GND GND B22
FMCB_DP_C2M_N4 A35 DP4_C2M_P DP4_M2C_P A15 FMCB_DP_M2C_N4 CLK_DIR CLK1_M2C_N 12 FMCB_DP_M2C_N[15:0] C9 GND GND B19
DP4_C2M_N DP4_M2C_N FMCB_GA0 C34 B40 C12 GND GND B18
FMCB_DP_C2M_P5 A38 A18 FMCB_DP_M2C_P5 FMCB_GA1 D35 GA0 RES0 6 FMCB_GA[1:0] C13 GND GND B15
FMCB_DP_C2M_N5 A39 DP5_C2M_P DP5_M2C_P A19 FMCB_DP_M2C_N5 GA1 C16 GND GND B14
FMCB_DP_C2M_P6 B36 DP5_C2M_N DP5_M2C_N B16 FMCB_DP_M2C_P6 ASP-134486-01 C17 GND GND B11
FMCB_DP_C2M_N6 B37 DP6_C2M_P DP6_M2C_P B17 FMCB_DP_M2C_N6 A10_VCCIO_FMCB 13 FMCB_C2M_PG C20 GND GND B10
FMCB_DP_C2M_P7 B32 DP6_C2M_N DP6_M2C_N B12 FMCB_DP_M2C_P7 C21 GND GND B7
FMCB_DP_C2M_N7 B33 DP7_C2M_P DP7_M2C_P B13 FMCB_DP_M2C_N7 C24 GND GND B6
FMCB_DP_C2M_P8 B28 DP7_C2M_N DP7_M2C_N B8 FMCB_DP_M2C_P8 12 FMCB_GBTCLK_M2C_P[1:0] C25 GND GND B3
FMCB_DP_C2M_N8 B29 DP8_C2M_P DP8_M2C_P B9 FMCB_DP_M2C_N8 R238 12 FMCB_GBTCLK_M2C_N[1:0] C28 GND GND B2
FMCB_DP_C2M_P9 B24 DP8_C2M_N DP8_M2C_N B4 FMCB_DP_M2C_P9 C29 GND GND C40
DP9_C2M_P DP9_M2C_P DNI GND GND
FMCB_DP_C2M_N9 B25 B5 FMCB_DP_M2C_N9 C32 C38
DP9_C2M_N DP9_M2C_N VREF_FMCB C33 GND GND C36
D4 FMCB_GBTCLK_M2C_P0 GND GND
GBTCLK0_M2C_P D5 FMCB_GBTCLK_M2C_N0 ASP-134486-01
GBTCLK0_M2C_N B20 FMCB_GBTCLK_M2C_P1 C259 C260
GBTCLK1_M2C_P B21 FMCB_GBTCLK_M2C_N1 R237
A GBTCLK1_M2C_N A
0.1uF 0.1uF DNI Altera Corporation, 101 Innovation Dr., San Jose CA 95134
ASP-134486-01 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
5 4 3 2 1
Quad Small Form-factor Pluggable (QSFP) Interface

QSFP INTERFACE
11 QSFP_RX_P[3:0]
NOTE 1: Bypass Capacitors should be placed as close to the associated 20-pin 11 QSFP_RX_N[3:0]
D
connector as possible. D
NOTE 2: Assuming that the SFP RD 100-ohm termination on the Host Board FPGA 11 QSFP_TX_P[3:0]
device will be implemented via the on-chip termination circuit. 11 QSFP_TX_N[3:0]
NOTE 3: DC blocking capacitors are in the module for RX and TX.
3.3V
NOTE 4: 1uH inductors should have a DC Resistance of less than 0.1-ohm. 4 QSFP_MOD_SELn
QSFP_3p3V_MOD_SELn R486 4.70K 4 QSFP_RSTn
QSFP_3p3V_RSTn R500 4.70K 4 QSFP_SCL
QSFP_3p3V_SCL R516 4.70K 4 QSFP_SDA
QSFP_3p3V_SDA R528 4.70K
QSFP_VCC QSFP_3p3V_LP_MODE R485 4.70K 4 QSFP_INTERRUPTn
QSFP_VCCR QSFP_3p3V_INTERRUPTn R501 4.70K 4 QSFP_MOD_PRSn
3.3V QSFP_VCCT QSFP_VCCT J18 QSFP_3p3V_MOD_PRSn R517 4.70K
L20 30
1 2 QSFP_VCCT 10 VCC
29 VCCR
C694 4 QSFP_LP_MODE
C673 1.0uH C684 VCCT
C657
22uF QSFP_TX_P0 36 17 QSFP_RX_P0
0.1uF 22uF 0.1uF QSFP_TX_N0 37 TD1_P RD1_P 18 QSFP_RX_N0
QSFP_VCCR TD1_N RD1_N
L21 QSFP_TX_P1 3 22 QSFP_RX_P1
1 2 QSFP_VCCR QSFP_TX_N1 2 TD2_P RD2_P 21 QSFP_RX_N1
TD2_N RD2_N
C 1.0uH C
C685 C695 QSFP_TX_P2 33 14 QSFP_RX_P2
QSFP_TX_N2 34 TD3_P RD3_P 15 QSFP_RX_N2 3.3V 1.8V
0.1uF 22uF TD3_N RD3_N
QSFP_TX_P3 6 25 QSFP_RX_P3
QSFP_VCC QSFP_TX_N3 5 TD4_P RD4_P 24 QSFP_RX_N3 C674
C663
L19 TD4_N RD4_N C658
1 2 QSFP_VCC 28 QSFP_3p3V_INTERRUPTn 1uF 0.1uF
QSFP_3p3V_MOD_SELn 8 INTn 27 QSFP_3p3V_MOD_PRSn 0.1uF
1.0uH C662 MOD_SELn MOD_PRSn U65
C656
QSFP_3p3V_LP_MODE 31 1 B1 B2
0.1uF 22uF LP_MODE GND 4 QSFP_3p3V_MOD_SELn C1 VCC VL A1 QSFP_MOD_SELn
QSFP_3p3V_RSTn 9 GND 7 QSFP_3p3V_RSTn C2 IO VCC1 IO VL1 A2 QSFP_RSTn
RSTn GND 13 QSFP_3p3V_SCL C3 IO VCC2 IO VL2 A3 QSFP_SCL
QSFP_3p3V_SCL 11 GND 16 QSFP_3p3V_SDA C4 IO VCC3 IO VL3 A4 QSFP_SDA
QSFP_3p3V_SDA 12 SCL GND 19 IO VCC4 IO VL4
1.8V
Maximum power is <= 3.5W (1.06 A) SDA GND 20 B3 B4
Maximum inrush current = 1.3A GND 23 TS GND
GND 26 MAX3378_UCSP
GND 32
GND 35 3.3V 1.8V
GND 38
GND QSFP_CAGE1
39 45 C696 C705
40 CAGE_GND CAGE_GND 46 C686
B B
41 CAGE_GND CAGE_GND 47 1uF 0.1uF
42 CAGE_GND CAGE_GND 48 0.1uF
43 CAGE_GND CAGE_GND 49 U68
44 CAGE_GND CAGE_GND 50 B1 B2
CAGE_GND CAGE_GND QSFP_3p3V_LP_MODE C1 VCC VL A1 QSFP_LP_MODE
QSFP_AND_CAGE QSFP_3p3V_INTERRUPTn C2 IO VCC1 IO VL1 A2 QSFP_INTERRUPTn
QSFP_3p3V_MOD_PRSn C3 IO VCC2 IO VL2 A3 QSFP_MOD_PRSn
GND_QSFP_CAGE GND_QSFP_CAGE IO VCC4 IO VL4
1.8V
B3 B4
10.0K R465 TS GND
MAX3378_UCSP
4.7nF C651
GND_QSFP_CAGE
A A

Title
B 150-0321301-E3 (6XX-44366R) E3.1
5 4 3 2 1
8 7 6 5 4 3 2 1
Small Form Factor Pluggable Plus (SFP+) Connector
NOTE 1: Bypass Capacitors should be placed as close to the associated 20-pin

connector as possible.
E E
NOTE 2: Assuming that the SFP RD 100-ohm termination on the Host Board FPGA
device will be implemented via the on-chip termination circuit.
NOTE 3: DC blocking capacitors are in the module for RX and TX.
SFP_VCCR SFP_VCCT
3.3V SFP_VCCT J12
16 18 SFP_TX_P
L16 1 2 4.7uH 15 VCCT TD_P 19 SFP_TX_N
VCCR TD_N
C568 C585 C567 SFP_RX_P 13 8 SFP_3p3V_RX_LOS
SFP_RX_N 12 RD_P RX_LOS 2 SFP_3p3V_TX_FLT
0.1uF 0.1uF 22uF RD_N TX_FAULT
SFP_VCCR SFP_3p3V_TX_DIS 3 1 3.3V SFP+ INTERFACE
SFP_3p3V_RS0 7 TX_DISABLE VEET 17
D RS0 VEET D
L17 1 2 4.7uH SFP_3p3V_RS1 9 20 SFP_3p3V_RS0 R440 4.70K 11 SFP_TX_P
RS1 VEET SFP_3p3V_RS1 R454 4.70K 11 SFP_TX_N
C620 C596 C595 SFP_3p3V_MOD0_PRSNTn 6 10 SFP_3p3V_TX_FLT R415 4.70K
SFP_SCL 5 MOD_ABS VEER 11 SFP_3p3V_TX_DIS R416 4.70K 11 SFP_RX_P
0.1uF 0.1uF 22uF SFP_SDA 4 SCL VEER 14 SFP_3p3V_MOD0_PRSNTn R439 4.70K 11 SFP_RX_N
SDA VEER SFP_3p3V_RX_LOS R453 4.70K
21 32 SFP_SCL R430 4.70K
22 CAGE_GND CAGE_GND 33 SFP_SDA R429 4.70K 4 SFP_RS0
23 CAGE_GND CAGE_GND 34 4 SFP_RS1
Level I power is < 1W (0.3 A) 24 CAGE_GND CAGE_GND 35 B1 4 SFP_TX_DISABLE
Level II power is < 1.5W (0.45 A) 25 CAGE_GND CAGE_GND 36
Level II Instantaneous peak current per rail 600mA 26 CAGE_GND CAGE_GND 37
27 CAGE_GND CAGE_GND 38 4 SFP_RX_LOS
28 CAGE_GND CAGE_GND 39 4 SFP_TX_FAULT
29 CAGE_GND CAGE_GND 40 4 SFP_MOD0_PRSNTn
CAGE_GND CAGE_GND SFP modules have RS1 connected to GND.
3.3V 1.8V 30 41 SFP+_CAGE If using SFP+ Rate Select pin are defined as:
31 CAGE_GND MH1 42 4 SFP_MOD1_SCL
CAGE_GND MH2 RS1=0 -> TX datarates <= 4.25GB/s
4 SFP_MOD2_SDA
C625 C624 SFP+_AND_CAGE RS1=1 -> TX datarates > 4.25GB/s
C C
C626
1uF 0.1uF GND_SFP_CAGE GND_SFP_CAGE RS0=0 -> RX datarates <= 4.25GB/s
0.1uF RS0=1 -> RX datarates > 4.25GB/s
U62 Optical (SFP+) Transceiver Cage & Connector
B1 B2
SFP_3p3V_RS0 C1 VCC VL A1 SFP_RS0
SFP_3p3V_RS1 C2 IO VCC1 IO VL1 A2 SFP_RS1
SFP_3p3V_TX_FLT C3 IO VCC2 IO VL2 A3 SFP_TX_FAULT
SFP_3p3V_TX_DIS C4 IO VCC3 IO VL3 A4 SFP_TX_DISABLE
IO VCC4 IO VL4
1.8V
B3 B4 10.0K R466
TS GND
MAX3378_UCSP
4.7nF C652
3.3V 1.8V
C621 C622
B C623 GND_SFP_CAGE B
1uF 0.1uF
0.1uF
U61
B1 B2
SFP_3p3V_MOD0_PRSNTn C1 VCC VL A1 SFP_MOD0_PRSNTn
SFP_3p3V_RX_LOS C2 IO VCC1 IO VL1 A2 SFP_RX_LOS
SFP_SCL C3 IO VCC2 IO VL2 A3 SFP_MOD1_SCL
SFP_SDA C4 IO VCC3 IO VL3 A4 SFP_MOD2_SDA
IO VCC4 IO VL4
1.8V
B3 B4
TS GND
MAX3378_UCSP
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SDI Cable Driver, Equalizer, and SMB
75 Ohm Single-Ended Impedance

E E
3.3V SDI_AVDD
M22468 Pin compatible to:
M22428 (Gen2 3G/6G SDI Cable Driver) L10
L7 120 Ohm FB 3.9nH
2.5V M23428 (12G Cable Driver) 1 2
C236 C235 C681 C205
L6 DNI SDI_TXBNC C237 4.7uFSDI_TXBNC_P 1 J21
0.1uF 0.1uF 0.01uF 0.01uF U41 R194 75 SMB
SDI CABLE DRIVER
100 Ohm Differential Impedance 2 13
2
3
4
5
7 AVDD SDO1P 12
SDI_TX_P 11 C213 4.7uF AVDD SDO1N R193 75
SDI_AVDD
SDI_TXCAP_P 16 11 SDI_TXDRV_P
SDI_TX_N 11 C207 4.7uF SDI_TXCAP_N 1 SDIP SDO2P 10 SDI_TXDRV_N
SDI_AVDD SDIN SDO2N SDI_AVDD DNI 75-ohm to SDI_AVDD
14 4 R163 DNI R205 75 resitors for 12G.
6 MUTE1 NC R162 DNI
MUTE2 3
SDI_SD_HDn AVSS L12
D SDI_AVDD 9 8 3.9nH D
SDI_AVDD 1.8V SD/XHD AVSS 15 1 2 SDI_TXDRV_TERM
R525 750 SDI_TX_RSET 5 AVSS 17 Pin 4 -> GEN2 EQ Control:
R526 DNI Pull-down for 12G RSET CNTR_PAD Float = no input EQ R206 75
C670 C671 C672 M22468 Low = 2dB EQ
R176 R177 High = 4dB EQ C247 4.7uF R212 75
1uF 0.1uF U66 0.1uF
B1 B2 Layout Notes:
SDI_SD_HDn C1 VCC VL A1
4,13 SDI_TX_SD_HDn
IO VCC1 IO VL1 DNI for resistors and
C2 A2 49.9 49.9
C3 IO VCC2 IO VL2 A3 SDI_TX capacitors for GEN2
IO VCC3 IO VL3 devices. Layout Notes (M22468) SDI Cable Driver:
C4 A4 - The RSET resistor should be located close to pin 5.
1.8V IO VCC4 IO VL4 Minimize stubs in
B3 B4 C206 C224 layout. - Remove GND under pin 5 and the RSET resistor.
TS GND - The 49.9-ohm resistors should be placed close to device pins 16 and 1 (SDIP/SDIN).
MAX3378_UCSP 0.01uF 0.01uF
C C
75 Ohm Single-Ended Impedance
L11 5.6nH
1 2
4.7uF for 12G 2.5V_SDI 2.5V
J20 1 SDI_IN_P1 SDI_EQIN_P C233 1uF
SMB M22544 Pin Compatible to: L5
R201 75 R202 M23544 (12G EQ + Reclocker) 120 Ohm FB
75 DNI for 12G C690 C691 C682 C683
5
4
3
2
U40 0.1uF 0.1uF 0.01uF 0.01uF

SDI CABLE EQUALIZER
4.7uF for 12G SDI_EQIN_P1 3 20
SDI_EQIN_N C234 1uF SDI_EQIN_N1 4 SDIP VCC 24
R203 2.5V_SDI SDIN VCC
DISABLE SDO1 -> 7 15 SDO_P C203 4.7uF 11 SDI_RX_P
75-ohm for 12G SDO1_DISABLE SDO0P 14 SDO_N C204 4.7uF 11 SDI_RX_N
AGXp 8 SDO0N
B AGC+ B
37.4 C223 33nF AGCn 9
AGC- 17
MUTEREF 11 SDO1N 18 100 Ohm Differential Impedance
MODE_SEL = 0 -> HARDWARE MODE MUTEREF SDO1P
R174 DNI R204 10.0K MODE_SEL 6
MODE_SEL 1
MF0_BYPASS 10 VEE 2 R534 0
MF1_AUTO_SLEEP 19 MF0 VEE 5 R535 DNI
MF2_MUTE 21 MF1 VEE 12 1uF and 10uF for 12G
2.5V_SDI R192 0 MF3_xSD 22 MF2 VEE 16
2.5V D33 MF3 VEE 23
1.8V
R499 49.9 13 VEE 25
GREEN_LED xCS VEE_PAD
C703 C702 M22544
C704 2.5V_SDI
1uF 0.1uF Layout Notes (M22544) SDI Cable Equalizer:
0.1uF R173 10.0K MF1_AUTO_SLEEP - The AGC 33nF capacitor should be located close to the device pins 8 and 9 (AGC+/AGC-).
U73
B1 B2 R175 10.0K MF0_BYPASS
- Clear GND under the AGC 33nF capacitor.
A VCC VL A1 A
MF0_BYPASS C1 4,13 SDI_MF0_BYPASS R191 10.0K MF2_MUTE Altera Corporation, 101 Innovation Dr., San Jose CA 95134
MF1_AUTO_SLEEP C2 IO VCC1 IO VL1 4,13
A2 SDI_MF1_AUTO_SLEEP Copyright (c) 2013, Altera Corporation. All Rights Reserved.
MF2_MUTE C3 IO VCC2 IO VL2 A34,13 SDI_MF2_MUTE Title
C4 IO VCC3 IO VL3 A4 Arria 10 GX FPGA Development Kit
IO VCC4 IO VL4
1.8V
B3 B4 Size Document Number Rev
TS GND
B 150-0321301-E3 (6XX-44366R) E3.1
MAX3378_UCSP
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
User I/O
2.5V 4,9 CLOCK_SDA
MAX_ERROR RES_MAX_ERROR R243 22.0 7,13 CPU_RESETn

D16 RED_LED 2.5V D10 LED_GR 2.5V
R217 75 1 G 3 USER_LED_G0 6 USER_PB[2:0]
E E
MAX_LOAD RES_MAX_LOAD R244 22.0 USER_LED_R0 4 R 2 PGM_LED0 RESn_PGM_LED0 R234 22.0 PUSH BUTTON INTERFACE
D15 GREEN_LED R218 75 D14 GREEN_LED 13 PGM_SEL
13 PGM_CONFIG
D9 LED_GR 13 MAX_RESETn
MAX_CONF_DONE RES_CONF_DONEn R242 22.0 R219 75 1 G 3 USER_LED_G1 PGM_LED1 RESn_PGM_LED1 R235 22.0
D17 GREEN_LED D13 GREEN_LED LED INTERFACE
USER_LED_R1 4 R 2 13 PGM_LED[2:0]
2.5V R220 75
PGM_LED2 RESn_PGM_LED2 R236 22.0 13 MAX_ERROR
FMCA_RX_LED RESn_FMAC_RX_LED R233 22.0 D8 LED_GR D12 GREEN_LED 13 MAX_LOAD
D2 GREEN_LED R221 75 1 G 3 USER_LED_G2 13 MAX_CONF_DONE
13,29 OVERTEMPn
USER_LED_R2 4 R 2
FMCA_TX_LED RESn_FMCA_TX_LED R216 22.0 R222 75 6 USER_LED_G[7:0]
D1 GREEN_LED 2.5V
D7 LED_GR 6 USER_LED_R[7:0]
R223 75 1 G 3 USER_LED_G3 S6
D
FMCA_PRSNTn R241 22.0 GREEN_LED 1 2 PGM_CONFIG R12 10.0K D
D11 USER_LED_R3 4 R 2 PB Switch 6 FMCA_RX_LED
R224 75 S5 6 FMCA_TX_LED
2.5V 1 2 PGM_SEL R11 10.0K 6,13,19,26 FMCA_PRSNTn
D6 LED_GR PB Switch
FMCB_RX_LED RESn_FMCB_RX_LED R254 22.0 R225 75 1 G 3 USER_LED_G4 S7 6 FMCB_RX_LED
D20 GREEN_LED 1 2 MAX_RESETn R13 10.0K 6 FMCB_TX_LED
USER_LED_R4 4 R 2 PB Switch 6,13,20,26 FMCB_PRSNTn
R226 75
FMCB_TX_LED RESn_FMCB_TX_LED R253 22.0
D18 GREEN_LED D5 LED_GR S4 1.8V 7 PCIE_LED_X1
R227 75 1 G 3 USER_LED_G5 1 2 CPU_RESETn R10 10.0K 7 PCIE_LED_X4
PB Switch 7 PCIE_LED_X8
FMCB_PRSNTn R255 22.0 GREEN_LED USER_LED_R5 4 R 2 7 PCIE_LED_G2
D21 R228 75 7 PCIE_LED_G3
2.5V D4 LED_GR 1.8V DIPSWITCH INTERFACE
R229 75 1 G 3 USER_LED_G6 S3
PCIE_LED_X1 YELLOW_LED R551 22.0 1 2 USER_PB0 R9 10.0K 6 USER_DIPSW[7:0]
C D34 USER_LED_R6 4 R 2 PB Switch C
R230 75 S2
PCIE_LED_X4 YELLOW_LED R550 22.0 1 2 USER_PB1 R8 10.0K 9,13 CLK_SEL
D35 D3 LED_GR PB Switch 13 CLK_ENABLE
R231 75 1 G 3 USER_LED_G7 S1 13 FACTORY_LOAD
PCIE_LED_X8 YELLOW_LED R549 22.0 1 2 USER_PB2 R7 10.0K 9,13 SI516_FS
D36 USER_LED_R7 4 R 2 PB Switch
R232 75 4 RZQ_B2K
PCIE_LED_G2 YELLOW_LED R548 22.0
D37
PCIE_LED_G3 YELLOW_LED R547 22.0 5.0V J10

D38 1
2 SPACER1
3 B2
4 SPACER2
2.5V SPI_SS_DISP 5
1.8V SW6 6 SPACER3
SW2
16 1 USER_DIPSW0 RN1H 8 9 10K 10 1 CLK_SEL R518 10.0K I2C_SCL_DISP 7
B 15 2 USER_DIPSW1 RN1G 7 10 10K 9 2 CLK_ENABLE R529 10.0K I2C_SDA_DISP 8 B
OPEN
14 3 USER_DIPSW2 RN1F 6 11 10K 8 3 SI516_FS R530 10.0K 9 2x16 LCD I2C

13 4 USER_DIPSW3 RN1E 5 12 10K 7 4 FACTORY_LOAD R537 10.0K 10
12 5 USER_DIPSW4 RN1D 4 13 10K 6 5 RZQ_B2K
11 6 USER_DIPSW5 RN1C 3 14 10K LCD_HEADER
10 7 USER_DIPSW6 RN1B 2 15 10K DIPSWITCH5
9 8 USER_DIPSW7 RN1A 1 16 10K
R545 R536 5.0V 1.8V
DIPSWITCH8 169, 0.1% 240, 0.1%
DNI
DNI
DNI
C654 C194
C193
0.1uF 1uF
0.1uF
R484
R483
R482 U64
B1 B2
I2C_SCL_DISP C1 VCC VL A1 4 DISP_I2C_SCL
I2C_SDA_DISP C2 IO VCC1 IO VL1 A2 4 DISP_I2C_SDA
SPI_SS_DISP C3 IO VCC2 IO VL2 A3 4 DISP_SPISS
A IO VCC4 IO VL4 A
1.8V Altera Corporation, 101 Innovation Dr., San Jose CA 95134
B3 B4 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
TS GND Title
MAX3378_UCSP Arria 10 GX FPGA Development Kit
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
On-Board USB Blaster II - Part 1 ARRIA 10 USB INTERFACE

U49A 8 USB_FPGA_CLK
J3 FX2_SDA R16 0 MAX_SDA MAX II
MICRO_USB_CONN 3.3V BANK1 MAX V USB INTERFACE
1 VBUS_5V FX2_SCL B1 J1 FX2_FLAGB
VBUS
2 FX2_D_N C282 0.1uF FX2_PB0 C1 IOB1_1 IOB1_25 J2 13 USB_M5_CLK
D- IOB1_2 IOB1_26
E D+ 3
FX2_D_P C2 K2 E
4 R260 DNI U2 C3 IOB1_3 IOB1_27 L2
ID IOB1_4 IOB1_28 JTAG INTERFACE
5 1 4 C4 M1 FX2_PA1
GND VCC FX2_PB1 D1 IOB1_5 IOB1_29 M2 19 FMCA_JTAG_TCK
1M R258 D2 IOB1_6 IOB1_30 N1 FX2_PA4 19 FMCA_JTAG_TMS
9
8
7
6
100K R259 FX2_RESETn 2 3 D3 IOB1_7 IOB1_31 N2 FX2_PA2 19 FMCA_JTAG_TDO

RESET MR IOB1_8 IOB1_32 19 FMCA_JTAG_TDI
MAX811 D4 N4
FX2_PB7 E1 IOB1_9 IOB1_33 P1 FX2_PA3 20 FMCB_JTAG_TCK
4.7nF C275 E2 IOB1_10 IOB1_34 P2 20 FMCB_JTAG_TMS
E3 IOB1_11 IOB1_35 P3 20 FMCB_JTAG_TDO
3.3V E4 IOB1_12 IOB1_36 P4 20 FMCB_JTAG_TDI
U1 FX2_PB5 IOB1_13 IOB1_37 FX2_PA6
U45 3.3V F1 R1
1 3 42 FX2_RESETn F2 IOB1_14 IOB1_38 R2 FX2_PA5
3 D+ 2 7 AVCC RESET 15 FX2_SCL R14 2.00K F3 IOB1_15 IOB1_39 R3
GND D- AVCC SCL 16 FX2_SDA R15 2.00K IOB1_16 IOB1_40
TPD2EUSB30 11 SDA F4 R4
17 VCC 44 FX2_WAKEUP FX2_PB6 G1 IOB1_17 IOB1_41 T1
27 VCC WAKEUP G2 IOB1_18 IOB1_42 T2
32 VCC 29 FX2_FLAGA G3 IOB1_19 IOB1_43 T4
D VCC CTL0 IOB1_20 IOB1_44 D
43 30 FX2_FLAGB G4 U1
55 VCC CTL1 31 FX2_FLAGC FX2_FLAGC H1 IOB1_21 IOB1_45 U3
VCC CTL2 FX2_FLAGA H2 IOB1_22 IOB1_46 V1
Y1 9 1 FX2_SLRDn H4 IOB1_23 IOB1_47 V3
DMINUS RDY0 IOB1_24 IOB1_48
4
8 2 FX2_SLWRn W1
1 3 IFCLK = 48MHz DPLUS RDY1 IOB1_49
FX2_CLK 13 54
24.00MHz 24M_XTALIN 5 IFCLK CLKOUT FX2_CLK K1 W2 C_USB_MAX_TCK R23 0 FX2_PD0
2
24M_XTALOUT 4 XTALIN FX2_PA0 L1 IOB1/GCLK0 TCK U2 C_USB_MAX_TDI R25 0 FX2_PD2

XTALOUT IOB1/GCLK1 TDI V2 C_USB_MAX_TDO R26 0 FX2_PD3
C265 C264
FX2_PA0 33 18 FX2_PB0 TDO T3 C_USB_MAX_TMS R24 0 FX2_PD1
12pF 12pF FX2_PA1 34 PA0 PB0 19 FX2_PB1 TMS
FX2_PA2 35 PA1 PB1 20 FX2_PB2
FX2_PA3 36 PA2 PB2 21 FX2_PB3 EPM1270_M256FBGA
FX2_PA4 37 PA3 PB3 22 FX2_PB4 U49D
FX2_PA5 38 PA4 PB4 23 FX2_PB5
PA5 PB5 MAX II
FX2_PA6 39 24 FX2_PB6 BANK4
FX2_PA7 40 PA6 PB6 25 FX2_PB7 U13 W17
PA7 PB7 CAN WE USE MAX II TO LEVEL TRANSLATE USB_CLK? U14 IOB4_1 IOB4_25 W18
C IOB4_2 IOB4_26 C
14 45 FX2_PD0 U15 W3
RESERVED PD0 46 FX2_PD1 1.8V 3.3V U16 IOB4_3 IOB4_27 W4
6 PD1 47 FX2_PD2 U4 IOB4_4 IOB4_28 W5
10 AGND PD2 48 FX2_PD3 0.1uF C506 0.1uF C505 U5 IOB4_5 IOB4_29 W6
AGND PD3 49 FX2_PD4 U6 IOB4_6 IOB4_30 W7
12 PD4 50 FX2_PD5 U58 1uF C504 U7 IOB4_7 IOB4_31 W8
26 GND PD5 51 FX2_PD6 B2 B1 IOB4_8 IOB4_32
28 GND PD6 52 FX2_PD7 VL VCC U8 W9
41 GND PD7 USB_FPGA_CLK C4 A4 FX2_CLK V14 IOB4_9 IOB4_33 Y1 FX2_PA7
53 GND USB_M5_CLK C3 IO_VL1 IO_VCC1 A3 V15 IOB4_10 IOB4_34 Y10 FX2_SLWRn
56 GND 57 C2 IO_VL2 IO_VCC2 A2 V16 IOB4_11 IOB4_35 Y11 FX2_SLRDn
GND EXPOSED_PAD C1 IO_VL3 IO_VCC3 A1 V17 IOB4_12 IOB4_36 Y12 FMCA_JTAG_TMS
CY7C68013A_QFN 1.8V IO_VL4 IO_VCC4 V18 IOB4_13 IOB4_37 Y14 FMCA_JTAG_TDI
B3 B4 V4 IOB4_14 IOB4_38 Y15 FMCA_JTAG_TCK
EN GND V5 IOB4_15 IOB4_39 Y16 FMCB_JTAG_TDO
VBUS_5V R257 10.0K FX2_WAKEUP PLACE NEAR CY7C68013A MAX13042 IOB4_16 IOB4_40
3.3V V6 Y17 FMCB_JTAG_TMS
V7 IOB4_17 IOB4_41 Y18 FMCB_JTAG_TDI
R256 C273 W10 IOB4_18 IOB4_42 Y19 FMCB_JTAG_TCK
B IOB4_19 IOB4_43 B
W11 Y2 FX2_PB4
20.0K 0.1uF C267 C268 C271 C274 C284 C266 C270 C283 W13 IOB4_20 IOB4_44 Y3 FX2_PB3
W14 IOB4_21 IOB4_45 Y4 FX2_PB2
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF W15 IOB4_22 IOB4_46 Y5 FX2_PD5
W16 IOB4_23 IOB4_47 Y6 FX2_PD4
IOB4_24 IOB4_48
Y7 FX2_PD7
FX2_RESETn Y13 IOB4_49 Y8 FX2_PD6
FMCA_JTAG_TDO W12 IOB4/DEV_CLRn IOB4_50 Y9 MAX_SDA
IOB4/DEV_OE IOB4_51
EPM1270_M256FBGA
3.3V
3.3V
J23
A R502 1.00K C_USB_MAX_TCK 1 2 A
C_USB_MAX_TDO 3 1 2 4
3 4 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
R531 1.00K C_USB_MAX_TMS 5 6 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
7 5 6 8 Title
C_USB_MAX_TDI 9 7 8 10 Arria 10 GX FPGA Development Kit
9 10
DNI Size Document Number Rev
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8
SW4
1 A10_JTAG_BYPASSn R473 10.0K
1.8V On-Board USB Blaster II - Part 2
7 2 M5_JTAG_BYPASSn R474 10.0K ARRIA 10 USB INTERFACE
OPEN
6 3 FMCA_JTAG_BYPASSn R487 10.0K
5 4 FMCB_JTAG_BYPASSn R488 10.0K 5 USB_DATA[7:0]
E DIPSWITCH4 Logic 0 = Device JTAG Bypass 5 USB_ADDR[1:0] E

Logic 1 = Device JTAG Enable U49C
U49B MAX II 8 USB_FULL
MAX II BANK3 8 USB_EMPTY
BANK2 USB_DATA2 B20 J20 USB_DATA0 8 USB_SCL
JTAG_RX A1 B14 USB_CFG7 M5_JTAG_BYPASSn C18 IOB3_1 IOB3_25 K19 8 USB_SDA
USB_CFG14 A10 IOB2_1 IOB2_25 B15 USB_CFG1 C19 IOB3_2 IOB3_26 K20 USB_RDn
USB_CFG11 A11 IOB2_2 IOB2_26 B16 USB_CFG4 USB_EMPTY C20 IOB3_3 IOB3_27 L19 C_JTAG_TCK 5 USB_RESETn
USB_CFG10 A12 IOB2_3 IOB2_27 B17 USB_CFG8 D17 IOB3_4 IOB3_28 M19 USB_DATA5 5 USB_OEn
USB_CFG13 A13 IOB2_4 IOB2_28 B18 USB_CFG0 D18 IOB3_5 IOB3_29 N17 5 USB_RDn
USB_CFG12 A14 IOB2_5 IOB2_29 B19 FMCB_PRSNTn D19 IOB3_6 IOB3_30 N19 5 USB_WRn
USB_CFG5 A15 IOB2_6 IOB2_30 B2 JTAG_TX USB_ADDR0 D20 IOB3_7 IOB3_31 N20 USB_DATA7
USB_CFG9 A16 IOB2_7 IOB2_31 B3 FMCB_JTAG_BYPASSn IOB3_8 IOB3_32
IOB2_8 IOB2_32 E17 P17
IOB3_9 IOB3_33 MAX V USB INTERFACE
USB_CFG2 A17 B4 E18 P18 1.8V
USB_CFG6 A18 IOB2_9 IOB2_33 B5 C_JTAG_TMS E19 IOB3_10 IOB3_34 P19 13 USB_CFG[14:0]
USB_CFG3 A19 IOB2_10 IOB2_34 B6 USB_FULL E20 IOB3_11 IOB3_35 P20 A10_JTAG_TDI 10.0K R30
SC_RX A2 IOB2_11 IOB2_35 B7 F17 IOB3_12 IOB3_36 R17
USB_DATA3 A20 IOB2_12 IOB2_36 B8 F18 IOB3_13 IOB3_37 R18
C_JTAG_TDO A3 IOB2_13 IOB2_37 B9 F19 IOB3_14 IOB3_38 R19
D IOB2_14 IOB2_38 IOB3_15 IOB3_39 D
SC_TX A4 C14 USB_ADDR1 F20 R20 A10_JTAG_TCK 1.00k R32
1.8V FMCA_PRSNTn A5 IOB2_15 IOB2_39 C15 IOB3_16 IOB3_40
IOB2_16 IOB2_40 G17 T17
R43 10.0K M5_JTAG_TDI A6 C16 G18 IOB3_17 IOB3_41 T18
IOB2_17 IOB2_41 IOB3_18 IOB3_42 JTAG INTERFACE
M5_JTAG_TDO A7 C17 A10_JTAG_BYPASSn C_JTAG_TDI G19 T19 USB_WRn
R44 10.0K M5_JTAG_TMS A8 IOB2_18 IOB2_42 C5 USB_OEn G20 IOB3_19 IOB3_43 T20 USB_SCL
R45 1.00k M5_JTAG_TCK A9 IOB2_19 IOB2_43 C6 H17 IOB3_20 IOB3_44 U17 7 A10_JTAG_TCK
B10 IOB2_20 IOB2_44 C7 H19 IOB3_21 IOB3_45 U18 7 A10_JTAG_TMS
B11 IOB2_21 IOB2_45 D13 USB_DATA1 H20 IOB3_22 IOB3_46 U19 7 A10_JTAG_TDO
B12 IOB2_22 IOB2_46 D14 USB_DISABLEn J19 IOB3_23 IOB3_47 U20 USB_RESETn 7 A10_JTAG_TDI
B13 IOB2_23 IOB2_47 D15 FMCB_JTAG_MASTERn IOB3_24 IOB3_48
IOB2_24 IOB2_48 V19 13 M5_JTAG_TCK
D16 IOB3_49 V20 USB_SDA 1.8V 13 M5_JTAG_TMS
IOB2_49 D5 FMCA_JTAG_MASTERn IOB3_50 W19 13 M5_JTAG_TDO
IOB2_50 D6 USB_DATA6 M20 IOB3_51 W20 A10_JTAG_TMS 10.0K R31 13 M5_JTAG_TDI
IOB2_51 D7 USB_DATA4 L20 IOB3/GCLK2 IOB3_52 Y20 A10_JTAG_TDO
1.8V IOB2_52 D8 FMCA_JTAG_BYPASSn IOB3/GCLK3 IOB3_53
IOB2_53 6,13,19,24 FMCA_PRSNTn
C EPM1270_M256FBGA 6,13,20,24 FMCB_PRSNTn C
R33 1.00k USB_SCL EPM1270_M256FBGA
R27 1.00k USB_SDA
R39 1.00k USB_FULL
R40 1.00k USB_EMPTY
U49E
R42 DNI FMCA_JTAG_MASTERn MAX II 2.5V
R46 DNI FMCB_JTAG_MASTERn Power
J4 K4
J17_JTAG_TCK R491 DNI C664 DNI U12 GNDINT VCCINT U11
M17 GNDINT VCCINT L17
D12 GNDINT VCCINT D11
GNDINT VCCINT PLACE NEAR MAX II (U25)
USB Blaster Programming Header R503
(uses JTAG mode only) 1.00k 3.3V 2.5V 3.3V 3.3V
H3 K3
J3 GNDIO VCCIO1 L3
2.5V 2.5V M4 GNDIO VCCIO1 L4
J17 2.5V N3 GNDIO VCCIO1 M3 C18 C43 C19 C17 C32 C33
R504 1.00k USB_DISABLEn 2 1 J17_JTAG_TCK U9 GNDIO VCCIO1 1.8V
4 2 1 3 J17_JTAG_TDO V8 GNDIO C9 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
B 4 3 GNDIO VCCIO2 B
6 5 J17_JTAG_TMS R477 1.00k V9 C10
8 6 5 7 V13 GNDIO VCCIO2 D10
10 8 7 9 J17_JTAG_TDI R467 1.00k H18 GNDIO VCCIO2 C11
10 9 J17 GNDIO VCCIO2 1.8V 1.8V 1.8V
2X5_100mil N18 GNDIO J18
C8 GNDIO VCCIO3 K17
D9 GNDIO VCCIO3 K18
C12 GNDIO VCCIO3 L18 C42 C41 C34 C35
C13 GNDIO VCCIO3 3.3V
1.8V M18 GNDIO U10 0.1uF 0.1uF 0.1uF 0.1uF
1.8V 2.5V GNDIO VCCIO4 V10
JTAG_RX RESn_JTAG_RXR314 22.0 VCCIO4 V11
0.1uF C741 0.1uF C742 D22 GREEN_LED VCCIO4 V12
VCCIO4
U76 1uF C740
B2 B1 JTAG_TX RESn_JTAG_TX R313 22.0 EPM1270_M256FBGA
VL VCC D23 GREEN_LED
C_JTAG_TCK C4 A4 J17_JTAG_TCK
C_JTAG_TDO C3 IO_VL1 IO_VCC1 A3 J17_JTAG_TDO
A IO_VL2 IO_VCC2 A
C_JTAG_TMS C2 A2 J17_JTAG_TMS SC_RX RESn_SC_RX R312 22.0 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
C_JTAG_TDI C1 IO_VL3 IO_VCC3 A1 J17_JTAG_TDI D24 GREEN_LED Copyright (c) 2013, Altera Corporation. All Rights Reserved.
1.8V IO_VL4 IO_VCC4 Title
B3 B4 Arria 10 GX FPGA Development Kit
EN GND SC_TX RESn_SC_TX R311 22.0
MAX13042 D25 GREEN_LED Size Document Number Rev
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Tree
E E
D D
C C
B B
A A

Title
C 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Title
C 150-0321301-E3 (6XX-44366R) E3.1
5 4 3 2 1
8 7 6 5 4 3 2 1
Voltage &Temp Sense 3.3V
5.0V
R21
R20
R18
R19
5.0V
C697 C698 R539
R521
R507
R522
R506
E U44 0.1uF 10uF 0 E
10.0K
10.0K
10.0K
10.0K
A10_VCC_SENSE_P 35 21 9
A10_VCC_SENSE_N 35 22 CH0 VCC 3.3V
CH1 11 U46
A10_VCCRAM_SENSE_P 38 23 REF+ 6 9 13 OVERTEMPn
CH2 ADD1 OVERTn
10.0K
10.0K
10.0K
10.0K
A10_VCCRAM_SENSE_N 38 24 12 10 11 13 TSENSE_ALERTn
CH3 REF- R538 ADD0 ALERTn
A10_VCCRT_GXB_SENSE_P 3925 DNI TEMPDIODE_P 73 14
13,30 SENSE_SMB_CLK
A10_VCCRT_GXB_SENSE_N 3926 CH4 19 TEMPDIODE_N 74 DXP SMBCLK 12
13,30 SENSE_SMB_DATA
CH5 F0 DXN SMBDATA
A10_VCCPT_SENSE_P 41 27 R533 3.3V 2
A10_VCCPT_SENSE_N 41 28 CH6 0 R17 200 15 GND1 7
CH7 17 SENSE5_SDO 1 STBYn GND2 8
A10_VCCIO_MEM_SENSE_P 451 SDO 20 SENSE5_SDI VCC GND3
A10_VCCIO_MEM_SENSE_N 452 CH8 SDI 18 SENSE5_SCK C6 5
CH9 SCK 16 SENSE5_CS0n 0.1uF 13 NC1
A10_VCCIO_FMCA_SENSE_P 433 CSn 16 NC2
A10_VCCIO_FMCA_SENSE_N 434 CH10 5.0V 2.5V NC3
CH11 MAX1619
D A10_VCCIO_FMCB_SENSE_P 445 ADDR = 01 D
A10_VCCIO_FMCB_SENSE_N 446 CH12 C228 C227
C244
CH13
A10_VCCIO_1.8V_SENSE_P 427 13 1uF 0.1uF 0.1uF 2.5V
A10_VCCIO_1.8V_SENSE_N 428 CH14 NC1 14 U71 OVERTEMPn RESn_LED_FAN R472 22.0
CH15 NC2 B1 B2 D32 RED_LED
10 15 SENSE5_CS0n C1 VCC VL A1 13 SENSE_CS0n
COM GND SENSE5_SDO C2 IO VCC1 IO VL1 A2 13 SENSE_SDO
LTC2418 SENSE5_SDI C3 IO VCC2 IO VL2 A3 13 SENSE_SDI 12V
SENSE5_SCK C4 IO VCC3 IO VL3 A4 13 SENSE_SCK J19
2.5V IO VCC4 IO VL4 1
R505 10.0K B3 B4 2 TSENSE_FAN_CNTL
TS GND
MAX3378_UCSP B3 22_23_2021
Q3
13 OVERTEMP
FDV305N
C FAN_2pin_Conn C
B B
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
5 4 3 2 1
Power Sequence Controller VDD33
R722 R723 R724 R725 R726 R727 R728 R729 R730 R731 R732
5.49K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
12V 12V_OUT
PM_SHARE_CLK
D PM_CNTL1 D
PM_RSTn
R735 PM_ALERT
100K U81 PM_PWRGD
PM_FAULTB00
14 12 PM_FAULTB01
4V R738 200 VIN_SNS VIN_EN C808 PM_FAULTB10
R739 200 C809 0.1uF C810 0.1uF 36 34 0.1uf PM_FAULTB11
3.3V 37 VSENSEP0 REFP 35 LT_SDA
R740 R741 200 42 VSENSEM0 REFM 13 LT_SCL
49.9K R742 200 C811 0.1uF C812 0.1uF 43 VSENSEP1 NC
46 VSENSEM1 39
A10_VCC 47 VSENSEP2 VDACP0 38
R743 200 48 VSENSEM2 VDACM0 40
R744 200 C813 0.1uF C814 0.1uF 49 VSENSEP3 VDACP1 41
52 VSENSEM3 VDACM1 44
A10_VCCRT_GXB 53 VSENSEP4 VDACP2 45
R745 200 62 VSENSEM4 VDACM2 50
R746 200 C815 0.1uF C816 0.1uF 63 VSENSEP5 VDACP3 51
A10_VCCPT 64 VSENSEM5 VDACM3 55 35 VDAC_VCC
R747 200 1 VSENSEP6 VDACP4 54
R748 200 C817 0.1uF C818 0.1uF 2 VSENSEM6 VDACM4 56 39 VDAC_VCCRT
A10_VCCIO_1.8V 3 VSENSEP7 VDACP5 57
R749 200 VSENSEM7 VDACM5 59 41 VDAC_VCCPT
C
R754 200 C819 0.1uF C820 0.1uF LT_SCL 28 VDACP6 58
C
LT_SDA 27 SCL VDACM6 60 42 VDAC_VCCIO_1.8V

PM_ASEL0 32 SDA VDACP7 61
PM_ASEL1 33 ASEL0 VDACM7
POWER_EN 30 ASEL1 4
PM_CNTL1 31 CONTROL0 VOUT_EN0 5 SW7
PM_RSTn 22 CONTROL1 VOUT_EN1 6 1 7
these GND connections WDI/RESET VOUT_EN2 7 2 8
needs to be placed close VOUT_EN3
OPEN
PM_FAULTB00 23 8 3 9
to a GND pin of the BGA! PM_FAULTB01 24 FAULTB00 VOUT_EN4 9 4 10
PM_FAULTB10 25 FAULTB01 VOUT_EN5 10 5 11
PM_FAULTB11 26 FAULTB10 VOUT_EN6 11 6 12
FAULTB11 VOUT_EN7
PM_SHARE_CLK 21 29 PM_ALERT DIPSW06
SHARE_CLK GND ALERTB 20 PM_PWRGD
19 PAD PWRGD 15
65 WP VPWR 18 VDD33
SENSE_SMB_CLK 13,29 R1000 0 E-PAD VDD25
SENSE_SMB_DATA 13,29 R1001 0 16
VDD33_OUT 17
LTC2977 VDD33_IN
C821 C822 C823
I2C Interface J24 LTC2977 VDD33
B 1 2 LT_SDA 0.1uf 0.1uf 0.1uf B
3 1 2 4 LT_SCL Address Select = 7'h5C
5 3 4 6 PM_ALERT
PM_CNTL1 7 5 6 8
9 7 8 10 PM_ASEL0
9 10 PM_ASEL1 R751 R756 R757 R752 R758 R753
11 12
11 12 10K 10K 10K 10K 10K 10K
2x6HDR
EN_12V 31
EN_POWER_SEQ 31,32
EN_A10_VCC 35,36,49
EN_A10_GROUP2 38,39,49
EN_A10_1.8V 41,49
EN_A10_VCCIO 34,42,43,44,45,49
POWER_EN
POWER_EN 31
A A

Title
B 150-0321301-E3 (6XX-44366R) E3.1
5 4 3 2 1
8 7 6 5 4 3 2 1
DC_IN = 12V from a laptop power supply. Power - Select Power Input 30 EN_12V
12V U27
DC Input DC_INPUT FDMC2514SDC 30,32 EN_POWER_SEQ
J13 1 12V_OUT
1 2 30 POWER_EN
VOUT 2 3 5
VOUT 3
E GND E
4
GND
5
SGND 6 U55 4
SGND 7 3 1 U17
SGND 8 2 GATE OUT 6 FDMC2514SDC
SGND 9 IN VDD 4 12V_OUT 1 DC_IN_12V 12V
SGND 5 GND 7 2 R316
PD-40S NC EP_GND 5 3
SGND LTC4357
0.003
D31
C434 C116
C726
R393
C526 12V_OUT 4 47uF 47uF
1M
4.7nF 20V 20V
REVERSE VOLTAGE PROTECTION 4.7nF

MMBD1205 U22
5
R327 DNI U52
FDMC2514SDC 4 6
GATE
D VIN VOUT D
12V_PCIE 1 R328 DNI EN_12V R340 0
SHOULD SHIELD JUST BE 2 8
TIED DIRECTLY TO GND? 3 5 12V_OUT SHDN 7
R323 5.49M 3 FAULT
UV 1
R324 2 GND 9
100K OV GND
4 LTC4365-1
U54 R325
3 1 U86
2 GATE OUT 6 FDMC2514SDC 200k
IN VDD 4 3.3V_PCIE 1 3.3V_PCIE_MUX
5 GND 7 2
DC_INPUT NC EP_GND 5 3
LTC4357
R991 DNI
C783 C784 C792 C793 C930 C929
12V_OUT 4 C928 DNI
C C
100uF 100uF 100uF 100uF R992 47uF 47uF
20V 20V
5
U13 0 U87
FDMC2514SDC 4 6
GATE
1 R956 VIN VOUT 3.3V_PCIE
EN_POWER_SEQ R953
12V from ATX 2 8
3 5 SHDN 7
0 3 FAULT
UV 1
2 GND 9 10K
OV GND
4 LTC4365-1
U50
3 1
2 GATE OUT 6
IN VDD 4
5 GND 7
NC EP_GND
B B
LTC4357
12V_ATX
Power On Switch
J4 DC_IN -> 12V 12V_PCIE ATX DC_IN_ATX
6 1 (Laptop Supply) (2x4 ATX) (Voltage Selected
4 SENSE0 12V 2 DC_INPUT by LTC4357)
5 SENSE1 12V 3 12V_PCIE 60.4K R1 4 1
7 GND 12V 12V 12V 12V from 12V_ATX_IN
8 GND 60.4K R6 POWER_EN 2.98V 5 2
GND 6 3 12V 0V 12V from DC_IN->12V
PCIe 2x4 ATX ENABLE WITHOUT SWITCH IF R5
BOARD IS IN PC CHASSIS. 20.0K 0V 12V 12V from 12V_ATX_IN
SW1
A 12V ATX INPUT (12.5A) SW_SLIDE_DPDT A
Sense0 = GND Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Sense1 = GND Arria 10 GX FPGA Development Kit
A 2 x 4 auxiliary power connector is plugged into the
card. The card can draw up to150 W from the Size Document Number Rev
auxiliary power connector. B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
5 4 3 2 1
Power - 12V to 3.3V

This output is set a little higher than
3.3V (3.45V) by R1004 to give it priority
over 3.3V_PCIe through the MUX.
3.3V_MUX
12V
12V U89B
U89C
A6 F11 M2 A1
A7 GND1 GND24 F12 M3 VIN1 VOUT1_1 A2
R1002 B6 GND2 GND25 G1 C983 C987 C988 C984 C989 C985 M4 VIN2 VOUT1_2 A3
R1003 B7 GND3 GND26 G3 M5 VIN3 VOUT1_3 A4 C986 C990 C991 C992
4.70K GND4 GND27 VIN4 VOUT1_4
D1 G10 22uF 22uF 22uF 22uF 10uF 10uF M6 A5
D
U89A D2 GND5 GND28 G12 M7 VIN5 VOUT1_5 B1 100uF 100uF 100uF 100uF D
C5 G9 3p3V_PGOOD 35 D3 GND6 GND29 H1 M8 VIN6 VOUT1_6 B2
10.0K C8 VOUTS1 PGOOD1 G8 D4 GND7 GND30 H2 M9 VIN7 VOUT1_7 B3
C993 VOUTS2 PGOOD2 GND8 GND31 VIN8 VOUT1_8
D9 H3 M10 B4
H8 G2 C1093 100pF D10 GND9 GND32 H4 M11 VIN9 VOUT1_9 B5
J7 INTVCC SW1 D11 GND10 GND33 H5 L2 VIN10 VOUT1_10 C1
EXTVCC D5 C1092 220pF D12 GND11 GND34 H6 L3 VIN11 VOUT1_11 C2
30,31 EN_POWER_SEQ 4.7uF F5 VFB1 E1 GND12 GND35 H7 L4 VIN12 VOUT1_12 C3
F9 RUN1 E2 GND13 GND36 H9 L5 VIN13 VOUT1_13 C4
RUN2 G11 R1004 E3 GND14 GND37 H10 L6 VIN14 VOUT1_14
J6 SW2 E4 GND15 GND38 H11 L7 VIN15
TEMP 12.7K GND16 GND39 VIN16
D7 E10 H12 L8
C994 0.01uF E5 VFB2 E11 GND17 GND40 J1 L9 VIN17
D8 TRACK1 G5 E12 GND18 GND41 J5 L10 VIN18 A8
TRACK2 CLKOUT F8 F1 GND19 GND42 J8 L11 VIN19 VOUT2_1 A9
C6 DIFFOUT F2 GND20 GND43 J12 J2 VIN20 VOUT2_2 A10
G4 FSET E6 F3 GND21 GND44 K1 J3 VIN21 VOUT2_3 A11 C996
C995 C997 C998
PHASMD COMP1 E7 F10 GND22 GND45 K5 J4 VIN22 VOUT2_4 A12
F4 COMP2 GND23 GND46 K6 J9 VIN23 VOUT2_5 B8 100uF 100uF 100uF 100uF
MODE-PLLIN E8 C7 GND47 K7 J10 VIN24 VOUT2_6 B9
DIFFP E9 D6 SGND1 GND48 K8 J11 VIN25 VOUT2_7 B10
DIFFN G6 SGND2 GND49 K12 K2 VIN26 VOUT2_8 B11
LTM4620A G7 SGND3 GND50 L1 K3 VIN27 VOUT2_9 B12
F6 SGND4 GND51 L12 K4 VIN28 VOUT2_10 C9 Remote
F7 SGND5 GND52 M1 K9 VIN29 VOUT2_11 C10 Sense Near
SGND6 GND53 M12 K10 VIN30 VOUT2_12 C11 U35
GND54 VIN31 VOUT2_13
1
K11 C12
LTM4620A VIN32 VOUT2_14 V47 V48
SNS RSNS
SNS RSNS
LTM4620A
2
C C
12V
12V
U90B
U90C
R1005 A6 F11 M2 A1
R1006 A7 GND1 GND24 F12 M3 VIN1 VOUT1_1 A2
4.70K GND2 GND25 VIN2 VOUT1_2
B6 G1 C1003 C1004 C999 C1005 C1002 C1006 M4 A3 C1007 C1008 C1000 C1009
U90A B7 GND3 GND26 G3 M5 VIN3 VOUT1_3 A4
C5 G9 D1 GND4 GND27 G10 22uF 22uF 22uF 22uF 10uF 10uF M6 VIN4 VOUT1_4 A5 100uF 100uF 100uF 100uF
10.0K C8 VOUTS1 PGOOD1 G8 D2 GND5 GND28 G12 M7 VIN5 VOUT1_5 B1
C1001 VOUTS2 PGOOD2 GND6 GND29 VIN6 VOUT1_6
D3 H1 M8 B2
H8 G2 D4 GND7 GND30 H2 M9 VIN7 VOUT1_7 B3
J7 INTVCC SW1 D9 GND8 GND31 H3 M10 VIN8 VOUT1_8 B4
EXTVCC D5 D10 GND9 GND32 H4 M11 VIN9 VOUT1_9 B5
4.7uF F5 VFB1 D11 GND10 GND33 H5 L2 VIN10 VOUT1_10 C1
F9 RUN1 D12 GND11 GND34 H6 L3 VIN11 VOUT1_11 C2
RUN2 G11 E1 GND12 GND35 H7 L4 VIN12 VOUT1_12 C3
J6 SW2 E2 GND13 GND36 H9 L5 VIN13 VOUT1_13 C4
TEMP D7 E3 GND14 GND37 H10 L6 VIN14 VOUT1_14
E5 VFB2 E4 GND15 GND38 H11 L7 VIN15
D8 TRACK1 G5 E10 GND16 GND39 H12 L8 VIN16
TRACK2 CLKOUT F8 E11 GND17 GND40 J1 L9 VIN17
C6 DIFFOUT E12 GND18 GND41 J5 L10 VIN18 A8
G4 FSET E6 F1 GND19 GND42 J8 L11 VIN19 VOUT2_1 A9
PHASMD COMP1 E7 F2 GND20 GND43 J12 J2 VIN20 VOUT2_2 A10 C1010 C1011 C1012 C1013
F4 COMP2 F3 GND21 GND44 K1 J3 VIN21 VOUT2_3 A11
MODE-PLLIN E8 F10 GND22 GND45 K5 J4 VIN22 VOUT2_4 A12 100uF 100uF 100uF 100uF
DIFFP E9 GND23 GND46 K6 J9 VIN23 VOUT2_5 B8
DIFFN C7 GND47 K7 J10 VIN24 VOUT2_6 B9
LTM4620A D6 SGND1 GND48 K8 J11 VIN25 VOUT2_7 B10
G6 SGND2 GND49 K12 K2 VIN26 VOUT2_8 B11
G7 SGND3 GND50 L1 K3 VIN27 VOUT2_9 B12
F6 SGND4 GND51 L12 K4 VIN28 VOUT2_10 C9
F7 SGND5 GND52 M1 K9 VIN29 VOUT2_11 C10
B SGND6 GND53 M12 K10 VIN30 VOUT2_12 C11 B
GND54 K11 VIN31 VOUT2_13 C12
LTM4620A VIN32 VOUT2_14
connect AGND to
LTM4620A
PGND through a
single via
A A

Title
C 150-0321301-E3 (6XX-44366R) E3.1
5 4 3 2 1
8 7 6 5 4 3 2 1
Power 1 - DC Input to 3.3V Output
E E
3.3V_OUT 3.3V
ADD DNI RESITOR TO
12V OUTPUT, IN CASE NEEDED 5.0V 0.00025 R165
U36 FOR MIN LOAD.
7 1 3.3V_MUXVCCP
8 IN OUT 2
IN OUT 9 R493 C676
C666 3 EPAD_VOUT
NC1 DNI
1uF 5 2.2uF 3.3V_PCIE_MUX
6 NC2 4 LT3082_SET
D NC3 SET D
3
4
D43 LTC4352CDD
LT3082 1 2
UV
OV
C665 R492 VIN VCC C699
499K C667 10
DNI CPO 7 0.1uF
REV
STATUS
DNI 12 13
FAULT
11 SOURCE EP 9
1 2 3 GATE GND
8
OUT
4
5
6
U39 C1095
FDMC2514SDC
DNI
5.0V 5
C C
R252 5
1.00k
U88
POWER LED FDMC2514SDC
4
D19
BLUE LED 5 C1094
1 2 3 U35 DNI
FDMC2514SDC
5
6
D42 LTC4352CDD
8
FAULT
STATUS
11 OUT 9
1 2 3 12 GATE GND 13
C659 SOURCE EP 7
B REV B
10
DNI CPO
1 2
OV
3.3V_MUX
UV
VIN VCC
3
4
C677
0.1uF
3.3V_MUXVCC
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power - MEM_VDD, 2.5V
3.3V
E POWER CONTROL E
MEM_VDD 17 VDD_1.25V_SET
3 VDD_1.3V_SET
3,17 VDD_1.35V_SET
17 VDD_1.5V_SET
U9 C866 C867 C868 C869
C863 C864
22uF 22uF 47uf 100UF 30,42,43,44,45,49 EN_A10_VCCIO
22uF 22uF 35 C865
36 PVIN 16
R795 37 PVIN EN6360QI VOUT 17 22pF
38 PVIN VOUT 18
DNI PVIN VOUT
39 8A 19
40 PVIN VOUT 20 R796
41 PVIN VOUT 21 160K R797
42 PVIN VOUT 22 15K
43 PVIN VOUT 23
PVIN VOUT 24 3.3V
D R793 0 51 VOUT Arria 10 2.5V (2.5V/2.307A) D
ENABLE U51 3.3V
52
AVIN C346 28 2.5V_PGOOD R345 10.0K 2.5V
R794 55 POK
57 VFB 22uF 19 5
DNI SS PVIN VOUT
3.3V 3.3V 20 6
44 21 PVIN VOUT 7 C338 C347
45 NC44 50 MEM_VDD_PGOOD R798 R343 DNI PVIN VOUT 8
59 NC45 POK 10.0K VOUT 9 47uf 47uf
3.3V 64 NC59 56 EN_A10_VCCIO R344 0 2.5V_ENABLE 27 VOUT 10
C870 65 NC64 EAOUT ENA VOUT 11 R347
66 NC65 1 3.3V VOUT C413
NC66 NC1 200k
15nF 67 2 R799 33 15pF
68 NC67 NC2 3 160K AVIN
NC68 NC3 4 SS -> 22nF * 80kOhm = 1.76msec +/-25% 31 2.5V_FB
26 NC4 5 R802 R803 R804 C412 22nF 2.5V_SS 30 VFB VFB=0.75V
R800 27 NC(SW)26 NC5 6 SS IFB=5nA
NC(SW)27 NC6 1.87M 634K 316K
0 62 7 R331 0 2.5V_LLM 26 13 R348
63 NC(SW)62 NC7 8 SYNC/LLM PGND 14
C NC(SW)63 NC8 PGND 84.5K C
9 VDD_1.25V_SET R346 DNI 2.5V_RLLM 29 15
61 NC9 10 Resistor for LLM mode only. RLLM PGND 16
R805 EN_PB NC10 11 Open (DNI) for PWM mode. PGND 17
DNI NC11 12 R806 PGND 18
48 NC12 13 VDD_1.3V_SET 316K Default to internal pull-up on LLM PGND 39
S_IN NC13 14 to allow automatic engagement of PGND
54 NC14 15 Light Load Mode. 32
M/S NC15 25 VDD_1.35V_SET Min (VIN - VOUT) = 315mV for PWM AGND
NC25 R808 0 Min (VIN - VOUT) = 800mV for LLM
NC(SW)12
NC(SW)34
NC(SW)35
NC(SW)36
NC(SW)37
NC(SW)38
58
NC(SW)1
NC(SW)2
R807 VSENSE VDD_1.5V_SET
60
NC22
NC23
NC24
NC25
DNI R809
NC3
NC4
FQADJ
DNI
49 R810 3.57K External Memory Interface Connector
S_OUT will GND the required SET pin to EN6337
1
2
3
4
12
22
23
24
25
34
35
36
37
38
28 generate VDDQ voltage for memory
PGND 29 interface. The default vaule is 1.2V.
PGND 30
PGND 31 3.3V R579
B PGND B
46 32 560
VDDB PGND 33
PGND 34
C871
PGND 69
0.22uF PGND(THRM)
47
BGND 53
AGND
EN6360QI
connect AGND to
PGND through a
single via
A A
EN_A10_VCCIO Altera Corporation, 101 Innovation Dr., San Jose CA 95134
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power - A10 VCC Route as diff pair

V54
1 2 A10_VCC_SENSE_P 29
RSNS SNS
1 2 A10_VCC_SENSE_N 29
RSNS SNS
V53
12V
C1014 C1015 R261

E E
5 6 7 8 9 22uF 22uF
0.00025
U34_INTVCC
R1007
D44 CMDSH-3 U34_INTVCC Q39 R1087 R1088
2.20 4 BSC050NE2LS 1K 1K
D45 CMDSH-3 A10_VCC_SENSE
C1016 C1017 R1008 L25

U91 3 2 1
100K
0.1uF 4.7uF LTC3877EUK 5 6 7 8 9 0.25uH A10_VCC (0.9V)
29 20 A10_VCC_PGOOD C1022 C1019 C1020 C1023 C1021 A10_VCC
28 VIN PGOOD1 21
27 INTVCC PGOOD2 Q40 330uF 330uF 220uF 220uF 10uF R1089 R1090
EXTVCC 4 BSC010NE2LSI 1K 1K
EN_A10_VCC 16
RUN 32 R1013 R1014 R1010
42 TG1 665 3.32K 0 C1018 C1087 C1088 C1090 C1091 C1089
15 ITEMP 31 R1071 0 C1024 0.1uF
U34_INTVCC ILIM BOOST1 3 2 1 R357 330uF 330uF 330uF 220uF 220uF 10uF
R1012 U34_ITH 7 33
7.32K 8 ITH1 SW1
ITH2 30 0.00025
R1015 TKSS_LTC3877 2 BG1
30.1K 9 TK/SS1 1
TK/SS2 SNSA1+ 43 Place R261 and R357 side-by-side on top layer and
C1025 17 SNSD1+ 44 route as kelvin sense to both resistors equally
D R1017 0.1uF FREQ SNS1- PLACE RESISTOR PADS OVERLAPPING using star routing through the 1K resistors. The D
R1016 100K NTC 18 SO THAT A RESISTOR CAN BE 1K resistors are for limiting eddie current
MODE/PLLIN POPULATED TO PULL-UP TO A10_VCC backflow.
20K R1019 C1026 0.22uF C1027 0.22uF R1020
R1018 86.6K 19 OR ROUTE A10_VCC_VCCLSENSE_P.
PHASMD DNI
10.0K R1021 DNI R1022 DNI A10_VCC
U34_CLKOUT 22
C1028 CLKOUT R512 0
3300pF 45 3 R513 DNI 46 A10_VCC_VCCLSENSE_P
SGND/PGND VOSNS1+ 4 R514 DNI 46 A10_VCC_VCCLSENSE_N
Default Vout = 0.9V VOSNS1- R515 0
C1029 R1026 set by Vfb resistors 24
47pF 10.7K R1028 VFB_LTC3877 6 gnd-pad TG2
5 VFB1 25 R1072 0 C1030 0.1uF PLACE RESISTOR PADS OVERLAPPING
R1029 10.0K DIFFOUT BOOST2 SO THAT A RESISTOR CAN BE
20K C1031 220pf 23 POPULATED TO PULL-DOWN TO GND OR
34 SW2 C1032 C1033 ROUTE A10_VCC_VCCLSENSE_N.
U34_INTVCC CHL_SEL 26
35 BG2 22uF 22uF
VID_EN 5 6 7 8 9
12
41 SNSA2+ 14
40 VID0 SNSD2+ 13
32 3p3V_PGOOD R1075 DNI 39 VID1 SNS2- Q41
38 VID2 C1034 0.22uF C1035 0.22uF 4 BSC050NE2LS
VID_READY R1076 0 37 VID3
36 VID4 R1031 DNI R1032 DNI
VID5 10
VFB2+ 11 R1033 L26
3.3V VFB2- VFB_LTC3877 DNI 3 2 1
5 6 7 8 9 0.25uH
C C1037 C1038 C1039 C1040 C1041 C
R1034 R1035 R1039 R1036 R1037 R1038 Q42 330uF 330uF 220uF 220uF 10uF
4.70K 4.70K DNI DNI DNI 4.70K 4 BSC010NE2LSI
R1040 R1041 R1042

A10_VCC_VID0 665 3.32K 0
A10_VCC_VID1
A10_VCC_VID2 3 2 1
A10_VCC_VID3
A10_VCC_VID4
A10_VCC_VID5
R1043 R1044 R1045 R1046 R1047 R1048

DNI DNI 4.70K 4.70K 4.70K DNI
Default Strapping VID[5:0] = 100011 = 0.95V
B 1.8V 3.3V 1.8V B

U72 3.3V 1.8V
14
VCC C246
C232
FPGA_CONF_DONE 7,131 3 FPGA_USER_MODE C230 C245 C231
FPGA_VID_EN 7 2 A0 O0 C229 1uF 0.1uF
B0 A0&B0=O0
1uF 0.1uF 0.1uF
VID_EN 6,7 4 6 VID_SELECTED 0.1uF U69
A10_VCCIO_PGOOD 5 A1 O1 U70 B1 B2 30,36,49 EN_A10_VCC
1.8V
B1 A1&B1=O1 B1 B2 A10_VCC_VID4 C1 VCC VL A1 VID4
FPGA_USER_MODE 13 11 VID_READY R519 DNI A10_VCC_VID0 C1 VCC VL A1 VID0 A10_VCC_VID5 C2 IO VCC1 IO VL1 A2 VID5
VID_SELECTED 12 A2 O2 R520 10.0K A10_VCC_VID1 C2 IO VCC1 IO VL1 A2 VID1 C3 IO VCC2 IO VL2 A3 6 VID[5:0]
B2 A2&B2=O2 A10_VCC_VID2 IO VCC2 IO VL2 IO VCC3 IO VL3
C3 A3 VID2 C4 A4
10 8 A10_VCC_VID3 C4 IO VCC3 IO VL3 A4 VID3 IO VCC4 IO VL4
9 A3 O3 IO VCC4 IO VL4 VID_READY B3 B4 36 U34_ITH
B3 A3&B3=O3 TS GND
7 VID_READY B3 B4
GND 15 R532 DNI TS GND MAX3378_UCSP
EPAD_NC MAX3378_UCSP 36 U34_CLKOUT
74VCX08BQX
36 A10_VCC_PGOOD
36 TKSS_LTC3877
VFB_LTC3877 R1077 DNI 30 VDAC_VCC
A10_VCCIO_1.8V_PGOOD 42 R397 0 A10_VCCIO_PGOOD

A A
A10_VCCIO_FMCA_PGOOD 43 R64 0
A10_VCCIO_FMCB_PGOOD 44 R114 0
A10_VCCIO_MEM_PGOOD 45 R117 0
Title
C 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
12V
Power - A10 VCC
5 6 7 8 9 C1048 C1049
E E
22uF 22uF
Q43
4 BSC050NE2LS
A10_VCC_SENSE
L27
U94_INTVCC 3 2 1
R1056 5 6 7 8 9 0.25uH
D46 CMDSH-3
2.20 R1057 R1058 C1050 C1051 C1052 C1053
665 0
D47 CMDSH-3 Q44 330uF 330uF 220uF 220uF
4 BSC010NE2LSI R1059
C1054 C1055
0.1uF 4.7uF U95 DNI

D
LTC3874IUFD#PBF D
20 24 3 2 1
19 VIN TG0
18 INTVCC 22 R1073 0 C1056 0.1uF
EXTVCC BOOST0
23
30,35,49 EN_A10_VCC 4 SW0
5 RUN0 21
C1057 RUN1 BG0
10nF
1 2
35 A10_VCC_PGOOD 8 MODE0 ISENSE0+ C1058
MODE1
35 U34_ITH
28 3 0.22uF
U94_INTVCC 9 ITH0 ISENSE0-
C1059 ITH1
47pF R1060 DNI
R1061 0 11
ILIM
C C
R1062 78.7K 10
FREQ 14
35 U34_CLKOUT 12 TG1
SYNC 16 R1074 0 C1060 0.1uF
13 BOOST1
PHASMD 15
U94_INTVCC 26 SW1
35 TKSS_LTC3877 FAULT0B 17 C1061 C1062
BG1 5 6 7 8 9
R1063 100K 25
FAULT1B 22uF 22uF
R1064 0 27 7
LOWDCR ISENSE1+ C1063 Q45
A10_VCC_PGOOD 4 BSC050NE2LS
29 6 0.22uF
GND ISENSE1-
Q47 L28
2N7002 3 2 1
LTC3874IUFD#PBF
B 5 6 7 8 9 0.25uH B
R1065 R1066 C1064 C1065 C1066 C1067

665 0
Q46 330uF 330uF 220uF 220uF
4 BSC010NE2LSI R1067
DNI
3 2 1
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
E E
D D
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C C
B B
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power - A10 VCCRAM
E E
Arria 10 - VCCRAM (0.95V/5.117A)

3.3V
U10 A10_VCCRAM_LOW A10_VCCRAM
39 20 R811
40 PVIN VOUT 21 0.003
41 PVIN VOUT 22
42 PVIN VOUT 23 C873 C874 C875 C876
43 PVIN VOUT 24 C872
44 PVIN VOUT 25
C877 C878 R812 27pF 47uf 47uf 47uf 100UF
47uf 47uf 0 46 PVIN VOUT 27 160K 3.3V
PVIN VOUT R815
R814 47 28
PVIN VOUT 12K
DNI 48
49 PVIN 66 R816 0
50 PVIN VSENSE R817
51 PVIN 63
D PVIN VFB 10.0K D
60 58 A10_VCCRAM_PGOOD
R818 0 59 AVIN POK 57
ENABLE S_OUT
68 64
65 FQADJ EAOUT
SS R819
69 29
EN_PB NC29 274K
56 30
R821 62 S_IN NC30(SW)30 31
C879
R820 4.42K 1 M/S NC30(SW)31 70
0.015uF 2 NC1 NC(SW)70 71
DNI NC2 NC(SW)71
R822 3 72
DNI 4 NC3 NC72 73
5 NC4 NC73 74
R950 6 NC5 NC74 75
DNI 7 NC6 NC75 76
8 NC7 NC76
9 NC8 67
10 NC9 NC(XREF)
C NC10 C
11 52
12 NC11 NC52 53
13 NC12 NC53
14 NC13 A10_VCCRAM_LOW
15 NC14
NC15 V34
16 SENSE_PAD
17 NC16 2 129 A10_VCCRAM_SENSE_N
18 NC17 32 SNS RSNS
19 NC18 PGND 33 A10_VCCRAM
NC19 PGND V33
34 SENSE_PAD
55 PGND 35 2 129 A10_VCCRAM_SENSE_P
C880
BGND PGND 36 SNS RSNS
0.22uF 54 PGND 37
VDDB PGND 38
61 PGND 77
AGND PGND(THRM) 30,39,49 EN_A10_GROUP2
12A
EN63A0QI
B B
connect AGND
to PGND
through a single
via
EN_A10_GROUP2
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
5 4 3 2 1
Power - A10 VCCRT GXB

Arria 10 - VCCRT_GXB (1.03V/17A)
12V
U96 R1068
A1 F11 A10_VCCRT_GXB_LOW A10_VCCRT_GXB
A2 VIN1 PGOOD1 G12
A3 VIN2 PGOOD2 100K 40A R1069
C1068 C1072 C1073 C1069 C1070 C1071 A4 VIN3 J1
D A5 VIN4 VOUT1 J2 D
100uF 100uF 22uF 22uF 10uF 10uF A6 VIN5 VOUT2 J3 0.00025 C1082
B1 VIN6 VOUT3 J4 C1074 C1075 C1076 C1077 C1078 C1079 C1080 C1081
B2 VIN7 VOUT4 J5 100UF
B3 VIN8 VOUT5 J6 100uF 100uF 100uF 100uF 22uF 22uF 10uF 10uF
B4 VIN9 VOUT6 J7
B5 VIN10 VOUT7 J8
B6 VIN11 VOUT8 J9 Remote
C1 VIN12 VOUT9 J10 Sense Near
C2 VIN13 VOUT10 K1 FPGA Power
C3 VIN14 VOUT11 K2 balls
C4 VIN15 VOUT12 K3
C5 VIN16 VOUT13 K4
C6 VIN17 VOUT14 K5
VIN18 VOUT15 K6
VOUT16 K7
VOUT17 K8
VOUT18 K9
D10 VOUT19 K10
TEMP VOUT20 K11
C1083 2.2uF A7 VOUT21 L1
D9 INTVCC1 VOUT22 L2
INTVCC2 VOUT23 L3
E12 VOUT24 L4
C EXTVCC VOUT25 C
1
L5
30,38,49 EN_A10_GROUP2 A10 VOUT26 L6 V49 V50
SNS RSNS
SNS RSNS
RUN VOUT27 L7
A11 VOUT28 L8
COMP VOUT29 L9
B12 VOUT30 L10
FSET VOUT31 L11
A8 VOUT32 M1
2
MODE_PLLIN VOUT33 M2
A9 VOUT34 M3
TRACK/SS VOUT35 M4
C1084 VOUT36 M5
D12 VOUT37 M6
1nF D11 MTP7 VOUT38 M7
C12 MTP6 VOUT39 M8
C11 MTP5 VOUT40 M9
C10 MTP4 VOUT41 M10
B11 MTP3 VOUT42 M11
A12 MTP2 VOUT43
MTP1
L12
G11 VOUT_LCL K12
H11 SGND1 DIFFOUT
H12 SGND2
B B
SGND3 J12
B7 VOSNS+ M12
B9 GND1 VOSNS-
C7 GND2 C1085
C9 GND3
D1 GND4 330pF
D2 GND5 F12 R1078 DNI 30 VDAC_VCCRT
D3 GND6 VFB
D4 GND7
D5 GND8 H9 R1070
connect AGND to D6 GND9 GND46 H8 84.5K
PGND through a D8 GND10 GND45 H7
single via E1 GND11 GND44 H6
E2 GND12 GND43 H5
E3 GND13 GND42 H4
E4 GND14 GND41 H3
E5 GND15 GND40 H2
E6 GND16 GND39 H1
A10_VCCRT_GXB_LOW E7 GND17 GND38 G9
E9 GND18 GND37 G8
V51 GND19 GND36
SENSE_PAD F1 G7
2 129 A10_VCCRT_GXB_SENSE_N F2 GND20 GND35 G6
SNS RSNS F3 GND21 GND34 G5
A A10_VCCRT_GXB F4 GND22 GND33 G4 A
V52 GND23 GND32
SENSE_PAD F5 G3
2 129 A10_VCCRT_GXB_SENSE_P F6 GND24 GND31 G2
SNS RSNS F7 GND25 GND30 G1
GND26 GND29 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
F8 F9 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
GND27 GND28 Title
LTM4637EV#PBF
B 150-0321301-E3 (6XX-44366R) E3.1
5 4 3 2 1
8 7 6 5 4 3 2 1
E E
D D
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C C
B B
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power - A10 VCCPT & 1.8V

Arria 10
VCCA_PLL, VCCH_GXB, VCCPT
E E
(1.8V/10.229A)
3.3V
U31 A10_1.8V_LOW A10_VCCPT A10_1.8V
L24
39 20 R850
40 PVIN VOUT 21 0.00025
41 PVIN VOUT 22 10A, RDC 4mOhm
42 PVIN VOUT 23 C900 C899 C901 C902 C903
43 PVIN VOUT 24 C904
44 PVIN VOUT 25
C905 C906 R851 27pF 47uf 47uf 47uf 100UF 47UF
47uf 47uf 0 46 PVIN VOUT 27 160K 3.3V
PVIN VOUT R853
R849 47 28
PVIN VOUT 12K
DNI 48
49 PVIN 66 R854 0
50 PVIN VSENSE R855
51 PVIN 63
D PVIN VFB 10.0K D
60 58 A10_1.8V_PGOOD
R856 0 59 AVIN POK 57
ENABLE S_OUT
68 64 R1079 DNI 30 VDAC_VCCPT
65 FQADJ EAOUT
69 SS 29
56 EN_PB NC29 30
R859 62 S_IN NC30(SW)30 31
C907 R857
R858 4.42K 1 M/S NC30(SW)31 70
NC1 NC(SW)70 80.6K
DNI 0.015uF 2 71
R860 3 NC2 NC(SW)71 72
DNI 4 NC3 NC72 73
5 NC4 NC73 74 A10_1.8V_LOW
R952 6 NC5 NC74 75
NC6 NC75 V45
DNI 7 76 SENSE_PAD
8 NC7 NC76 2 129 A10_VCCPT_SENSE_N
9 NC8 67 SNS RSNS
10 NC9 NC(XREF) A10_VCCPT
C NC10 V46 C
11 52 SENSE_PAD
12 NC11 NC52 53 2 129 A10_VCCPT_SENSE_P
13 NC12 NC53 SNS RSNS
14 NC13
15 NC14
16 NC15 30,49 EN_A10_1.8V
17 NC16
18 NC17 32
19 NC18 PGND 33
NC19 PGND 34
55 PGND 35
C908
BGND PGND 36
0.22uF 54 PGND 37
VDDB PGND 38
61 PGND 77
AGND PGND(THRM)
12A
EN63A0QI
B B
connect AGND
to PGND
through a single
via
EN_A10_1.8V
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power - A10 VCCIO 1.8V
E E
1.8V
V21
SENSE_PAD
2 129 A10_VCCIO_1.8V_SENSE_N
34,43,44,45,49 EN_A10_VCCIO SNS RSNS
A10_VCCIO_1.8V
35 A10_VCCIO_1.8V_PGOOD V24
SENSE_PAD
2 129 A10_VCCIO_1.8V_SENSE_P
SNS RSNS
Arria 10 VCCIO_1.8V & 1.8V (1.8V/2.08A)

3.3V
U57 3.3V
1.8V A10_VCCIO_1.8V
C467 28 A10_VCCIO_1.8V_PGOOD R398 10.0K
POK
D 22uF 19 5 R95 D
3.3V 20 PVIN VOUT 6 0.003
21 PVIN VOUT 7 C131
C442 C468
R395 DNI PVIN VOUT 8
VOUT 9 47uf 47uf 47UF
EN_A10_VCCIO R396 0 1.8V_ENABLE 27 VOUT 10
ENA VOUT 11 R400
3.3V VOUT C532
200k
33 15pF
AVIN
SS -> 22nF * 80kOhm = 1.76msec +/-25% 31 1.8V_VFB
C531 22nF 1.8V_SS 30 VFB VFB=0.75V
SS IFB=5nA R1080 DNI 30 VDAC_VCCIO_1.8V
R390 0 1.8V_LLM 26 13
SYNC/LLM PGND 14
R399 DNI 1.8V_RLLM 29 PGND 15
Resistor for LLM mode only. RLLM PGND 16
Open (DNI) for PWM mode. PGND 17 R401
PGND 18
PGND 143.0K
C 39 C
Default to internal pull-up on LLM PGND
to allow automatic engagement of 32
Light Load Mode. AGND
Min (VIN - VOUT) = 315mV for PWM
Min (VIN - VOUT) = 800mV for LLM
NC(SW)12
NC(SW)34
NC(SW)35
NC(SW)36
NC(SW)37
NC(SW)38
NC(SW)1
NC(SW)2
NC22
NC23
NC24
NC25
NC3
NC4
EN6337
1
2
3
4
12
22
23
24
25
34
35
36
37
38
3.3V R584
560
B B
A A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power - A10 VCCIO FMCA

FMCA_ADJ
34,42,44,45,49 EN_A10_VCCIO
V37
SENSE_PAD
35 A10_VCCIO_FMCA_PGOOD 2 129 A10_VCCIO_FMCA_SENSE_N
SNS RSNS
E A10_VCCIO_FMCA E
V38
SENSE_PAD
2 129 A10_VCCIO_FMCA_SENSE_P
SNS RSNS
3.3V
R861
10.0K
Arria 10 VCCIO_FMCA & FMCA_VADJ (1.2V/3.5A)
3.3V Variable 1.2V, 1.35V, 1.5V, 1.8V
U20
C909 28 A10_VCCIO_FMCA_PGOOD FMCA_ADJ A10_VCCIO_FMCA

POK
D 22uF 19 5 R862 D
3.3V 20 PVIN VOUT 6 0.003
21 PVIN VOUT 7 C910 C911
VOUT 9 47uf 47uf
EN_A10_VCCIO R864 0 A10_FMCA_ENABLE 27 VOUT 10
ENA VOUT 11 R865
3.3V VOUT C912
200k
33 15pF
AVIN
SS -> 22nF * 80kOhm = 1.76msec +/-25% 31 FMCA_ADJ_VFB
C913 22nF 30 VFB VFB=0.75V
SS IFB=5nA
R866 0 26 13 R867
SYNC/LLM PGND 14
PGND 332K
R868 DNI 29 15
Open (DNI) for PWM mode. PGND 17
PGND 18
PGND 39
C PGND C
Default to internal pull-up on LLM
NC(SW)12
NC(SW)34
NC(SW)35
NC(SW)36
NC(SW)37
NC(SW)38
NC(SW)1
NC(SW)2
NC22
NC23
NC24
NC25
NC3
NC4
EN6347QI
1
2
3
4
12
22
23
24
25
34
35
36
37
38
3.3V R869
560
B B
Install only one
FMCA_ADJ_VFB R1084 DNI R389 1M

R1085 DNI R394 499K
R1086 0 R409 249K
FMCA Voltage
A A
Installed VCCIO FMCA SELECT Altera Corporation, 101 Innovation Dr., San Jose CA 95134
NONE 1.2V Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R1084 1.35V Title
R1085 1.5V Arria 10 GX FPGA Development Kit
R1086 1.8V
(Default) Size Document Number Rev
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power - A10 VCCIO FMCB FMCB_ADJ
SENSE_PAD
V42
3,45,49 EN_A10_VCCIO 2 129 A10_VCCIO_FMCB_SENSE_N
SNS RSNS
A10_VCCIO_FMCB
35 A10_VCCIO_FMCB_PGOOD V41
SENSE_PAD
2 129 A10_VCCIO_FMCB_SENSE_P
SNS RSNS
E E
3.3V
R870
10.0K
Arria 10 VCCIO_FMCB & FMCB_VADJ (1.2V/3.5A)
3.3V Variable 1.2V, 1.35V, 1.5V, 1.8V
U23
C914 28 A10_VCCIO_FMCB_PGOOD FMCB_ADJ A10_VCCIO_FMCB

POK
D 22uF 19 5 R871 D
3.3V 20 PVIN VOUT 6 0.003
21 PVIN VOUT 7 C915 C916
VOUT 9 47uf 47uf
EN_A10_VCCIO R873 0 A10_FMCB_ENABLE 27 VOUT 10
ENA VOUT 11 R874
3.3V VOUT C917
200k
33 15pF
AVIN
SS -> 22nF * 80kOhm = 1.76msec +/-25% 31 FMCB_ADJ_VFB
C918 22nF 30 VFB VFB=0.75V
SS IFB=5nA
R875 0 26 13 R876
SYNC/LLM PGND 14
PGND 332K
R877 DNI 29 15
Open (DNI) for PWM mode. PGND 17
PGND 18
PGND 39
C PGND C
Default to internal pull-up on LLM
NC(SW)12
NC(SW)34
NC(SW)35
NC(SW)36
NC(SW)37
NC(SW)38
NC(SW)1
NC(SW)2
NC22
NC23
NC24
NC25
NC3
NC4
EN6347QI
1
2
3
4
12
22
23
24
25
34
35
36
37
38
3.3V R878
560
B B
Install only one
FMCB_ADJ_VFB R1083 DNI R330 1M

R1082 DNI R329 499K
R1081 0 R326 249K
FMCA Voltage
A A
Installed VCCIO FMCB SELECT Altera Corporation, 101 Innovation Dr., San Jose CA 95134
NONE 1.2V Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R1083 1.35V Title
R1082 1.5V Arria 10 GX FPGA Development Kit
R1081 1.8V
(default) Size Document Number Rev
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
17
POWER CONTROL
VDDQ_1.25V_SET
Power - A10 VCCIO MEM MEM_VDDQ
SENSE_PAD
V40
17 VDDQ_1.35V_SET 2 129 A10_VCCIO_MEM_SENSE_N
17 VDDQ_1.5V_SET SNS RSNS
3.3V A10_VCCIO_MEM
V39
49 EN_A10_VCCIO SENSE_PAD
2 129 A10_VCCIO_MEM_SENSE_P
35 A10_VCCIO_MEM_PGOOD MEM_VDDQ A10_VCCIO_MEM SNS RSNS
E E
R879
0.003
C919 C920 C921 C922
C923 C924 U24
22uF 22uF 47uf 100UF
22uF 22uF 35 C925
36 PVIN 16
R880 37 PVIN EN6360QI VOUT 17 22pF
DNI 38 PVIN VOUT 18 Arria 10 VCCIO_MEM & MEM_VDDQ (1.2V/4.7A)
PVIN VOUT
39
40 PVIN
8A
VOUT
19
20
Variable 1.2V, 1.25V, 1.35V, 1.5V
41 PVIN VOUT 21 R881 R882
42 PVIN VOUT 22 160K 15K
43 PVIN VOUT 23
PVIN VOUT 24
R883 0 51 VOUT
ENABLE
D 52 D
AVIN
R884 55
57 VFB
DNI SS 3.3V
44
45 NC44 50 A10_VCCIO_MEM_PGOOD R885
59 NC45 POK 10.0K
3.3V 64 NC59 56
C926 65 NC64 EAOUT
66 NC65 1
15nF 67 NC66 NC1 2 R886
68 NC67 NC2 3 160K
NC68 NC3 4
R887 26 NC4 5
27 NC(SW)26 NC5 6
0 62 NC(SW)27 NC6 7
63 NC(SW)62 NC7 8
NC(SW)63 NC8 9
61 NC9 10 R889 R890 R891
C EN_PB NC10 C
R888 11 1.87M 634K 316K
NC11 12
DNI NC12
48 13
S_IN NC13 14
54 NC14 15
M/S NC15 25
NC25 R892 0 VDDQ_1.25V_SET
58
R893 VSENSE VDDQ_1.35V_SET
DNI R894 60
FQADJ VDDQ_1.5V_SET
DNI
49 R895 3.57K
S_OUT
28 External Memory Interface Connector
PGND 29 will GND the required SET pin to
PGND 30 generate VDDQ voltage for memory
PGND 31 interface. The default vaule is 1.2V.
46 PGND 32
VDDB PGND 33
B PGND B
C927 34
PGND 69
0.22uF PGND(THRM)
47
BGND 53
AGND
EN6360QI
connect AGND to
PGND through a
single via
A A
EN_A10_VCCIO Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
A10_VCC
U28R
ARRIA 10 - POWER A10_VCC Arria 10 Power
R24 AA15
T15 VCC VCC AA17
T17 VCC VCC AA18
T18 VCC VCC AA19 U28S
T19 VCC VCC AA20 U28T
VCC VCC ARRIA 10 - POWER
E T20 AA22 A10_VCCIO_1.8V A10_VCCIO_1.8V A10_1.8V ARRIA 10 - TRANSCEIVER PWR E
T22 VCC VCC AA23 VCCIO (1.2V, 1.5V, 1.8V)
T24 VCC VCC AA24 AR28 AR23 AB36 A10 RREF_TR R332 2.0K
T29 VCC VCC AA25 AU29 VCCIO2A VCCIO3A AU24 AF36 VCCH_GXBLTX BUFFER PWR RREF_TR A35 RREF_TL R447 2.0K
Y29 VCC CORE PWR VCC AA27 AV27 VCCIO2A VCCIO3A AV22 AK36 VCCH_GXBL(1.8V) RREF_TL
Y27 VCC (0.83V, 0.86V, VCC AA28 AT27 VCCIO2A VCCIO3A AN23 K36 VCCH_GXBL BD10 RREF_BR R337 2.0K
Y26 VCC 0.9V) VCC AA29 VREFB2AN0 VREFB3AN0 A10_VCCIO_FMCA P36 VCCH_GXBL RREF_BR BD35 RREF_BL R451 2.0K
Y25 VCC VCC AB15 AK33 AM19 V36 VCCH_GXBL RREF_BL
Y24 VCC VCC AB16 AL31 VCCIO2I VCCIO3B AP20 VREF_FMCA VCCH_GXBL
Y22 VCC VCC AB17 AM29 VCCIO2I VCCIO3B AR18 V9
Y21 VCC VCC AB18 AR30 VCCIO2I VCCIO3B AN18 P9 VCCH_GXBR
Y20 VCC VCC AB20 A10_VCCIO_MEM VREFB2IN0 VREFB3BN0 K9 VCCH_GXBR
Y19 VCC VCC AB21 AA31 AN12 AK9 VCCH_GXBR
Y17 VCC VCC AB25 MEM_VREF AD30 VCCIO2J VCCIO3C AP15 AF9 VCCH_GXBR
Y16 VCC VCC AB26 W30 VCCIO2J VCCIO3C AR13 AB9 VCCH_GXBR
W29 VCC VCC AB27 AB30 VCCIO2J VCCIO3C AT12 VCCH_GXBR
W28 VCC VCC AB28 VREFB2JN0 VREFB3CN0 A10_VCCIO_1.8V A10_VCCRT_GXB A10_VCCRT_GXB
VCC VCC ANALOG RX PWR ANALOG TX PWR
W27 AC14 P30 AC12 (0.9V, 1.0V, 1.1V) (0.9V, 1.0V, 1.1V)
W26 VCC VCC AC19 T31 VCCIO2K VCCIO3D AD15 AM37 AK37
W24 VCC VCC AC20 V32 VCCIO2K VCCIO3D AE13 AM38 VCCR_GXBL1C VCCT_GXBL1C AK38
D VCC VCC VCCIO2K VCCIO3D VCCR_GXBL1C VCCT_GXBL1C D
W23 AC24 R32 AD11 AH37 AF37
W22 VCC VCC AC25 VREFB2KN0 VREFB3DN0 A10_VCCIO_1.8V AH38 VCCR_GXBL1D VCCT_GXBL1D AF38
W21 VCC VCC AC30 J30 AB14 AD37 VCCR_GXBL1D VCCT_GXBL1D AB37
W19 VCC VCC AD16 K28 VCCIO2L VCCIO3E W15 AD38 VCCR_GXBL1E VCCT_GXBL1E AB38
W18 VCC VCC AD17 M29 VCCIO2L VCCIO3E Y13 Y37 VCCR_GXBL1E VCCT_GXBL1E V37
W17 VCC VCC AD18 K32 VCCIO2L VCCIO3E AA12 Y38 VCCR_GXBL1F VCCT_GXBL1F V38
W16 VCC VCC AD19 VREFB2LN0 VREFB3EN0 A10_VCCIO_FMCB T37 VCCR_GXBL1F VCCT_GXBL1F P37
V29 VCC VCC AD21 K13 T38 VCCR_GXBL1G VCCT_GXBL1G P38
V28 VCC VCC AD22 A10_1.8V VCCIO3F M14 VREF_FMCB M37 VCCR_GXBL1G VCCT_GXBL1G K38
VCC VCC ANALOG PWR (1.8V) VCCIO3F VCCR_GXBL1H VCCT_GXBL1H
V24 AD23 AB23 N12 M38 K37
V23 VCC VCC AD24 AB22 VCCA_PLL VCCIO3F K15 VCCR_GXBL1H VCCT_GXBL1H
V19 VCC VCC AD26 VCCA_PLL VREFB3FN0 AM7 AK7
V18 VCC VCC AD27 A10_VCCIO_1.8V K18 AM8 VCCR_GXBR4C VCCT_GXBR4C AK8
VCC VCC CONFIG PWR VCCIO3G VCCR_GXBR4C VCCT_GXBR4C
V16 AD28 L21 AH7 AF7
VCC VCC (1.2V, 1.5V, 1.8V) VCCIO3G VCCR_GXBR4D VCCT_GXBR4D
U27 AD29 AK21 M19 AH8 AF8
U17 VCC VCC AE16 AK22 VCCPGM VCCIO3G L17 AD7 VCCR_GXBR4D VCCT_GXBR4D AB7
T30 VCC VCC AE17 VCCPGM VREFB3GN0 A10_VCCIO_1.8V AD8 VCCR_GXBR4E VCCT_GXBR4E AB8
T28 VCC VCC AE19 A10_VCCPT J25 Y7 VCCR_GXBR4E VCCT_GXBR4E V7
T27 VCC VCC AE20 IO PRE-DRIVER PWR VCCIO3H K23 Y8 VCCR_GXBR4F VCCT_GXBR4F V8
C VCC VCC (1.8V) VCCIO3H VCCR_GXBR4F VCCT_GXBR4F C
T25 AE21 AH16 M24 T7 P7
T23 VCC VCC AE22 AH19 VCCPT VCCIO3H M22 T8 VCCR_GXBR4G VCCT_GXBR4G P8
R29 VCC VCC AE24 AH21 VCCPT VREFB3HN0 M7 VCCR_GXBR4G VCCT_GXBR4G K7
R27 VCC VCC AE25 AH25 VCCPT M8 VCCR_GXBR4H VCCT_GXBR4H K8
VCC VCC VCCPT BATTERY PWR VCCR_GXBR4H VCCT_GXBR4H
R19 AE26 AH28 (1.5V, 1.8V) A10_VCCPT
R16 VCC VCC AE27 AJ22 VCCPT AL23 10AX115F1932C
AK27 VCC VCC AE29 U16 VCCPT VCCBAT A10_VCCIO_1.8V
AK24 VCC VCC AF17 U18 VCCPT
AK19 VCC VCC AF18 U20 VCCPT R21
AK16 VCC VCC AF19 U22 VCCPT VREFP_ADC P21
AJ28 VCC VCC AF20 U23 VCCPT VREFN_ADC IS THIS VREFP_ADC/VREFN_ADC?
AJ26 VCC VCC AF24 U26 VCCPT N19 VREFP_ADC up to 10mA?
AJ23 VCC VCC AF27 U28 VCCPT VSIGP_0 P19 R284VFEF_ADC R value
AJ18 VCC VCC AF29 VCCPT VSIGN_0 680 based on 20ma for
R22 VCC VCC AG17 A10_VCCRAM P18
MEM PWR V8 1.25V zener
R17 VCC VCC AG22 0.95VES/0.9V VSIGP_1 N18 SENSE_PAD D40
AK29 VCC VCC AG26 AC15 VSIGN_1 A10_VREF_ADC_P 1 2 6 4
AK26 VCC VCC AG28 AC16 VCCERAM RSNS SNS VOUT GND 5
C36
AK20 VCC VCC AH23 AC18 VCCERAM GND
B VCC VCC VCCERAM B
AK17 AH26 AC23 0.1uF 7 1
AJ29 VCC VCC AJ16 AC29 VCCERAM 8 NC7 NC1 2
AJ27 VCC VCC AF25 AC21 VCCERAM NC8 NC2 3
AJ24 VCC VCC AF28 AC26 VCCERAM NC3
AJ21 VCC VCC AG16 AC28 VCCERAM LT1389
VCC VCC VCCERAM V7
AJ19 AG18
AJ17 VCC VCC AG23 A10_VREF_ADC_N 1 2
AH29 VCC VCC AG27 10AX115F1932C RSNS SNS
AH24 VCC VCC AH18 SENSE_PAD
VCC VCC
AG15 U21
AG20 VCCP VCCP U25
AG21 VCCP Periphery PWR VCCP U30
AG25 VCCP (0.83V, 0.86V, 0.9V)VCCP V15
AG30 VCCP VCCP V20
AH15 VCCP VCCP V21
AH20 VCCP VCCP V25
AH30 VCCP VCCP V26
A VCCP VCCP A
U15 V30 Altera Corporation, 101 Innovation Dr., San Jose CA 95134
VCCP VCCP Copyright (c) 2013, Altera Corporation. All Rights Reserved.
FB1
Title
A10_VCC_VCCLSENSE_P AF22
35 R20 1 2 Arria 10 GX FPGA Development Kit
A10_VCC_VCCLSENSE_N AF23
35 VCCLSENSE ADCGND
GNDSENSE 120ohm, 800mA Size Document Number Rev
10AX115F1932C B E3.1
150-0321301-E3 (6XX-44366R)
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Arria 10 Ground
U28U U28V U28W U28X
ARRIA 10 - GND ARRIA 10 - GND ARRIA 10 - GND ARRIA 10 - GND
A11 AE40 AL21 AU14 BA11 C6 H7 R10 U28Y
A16 GND GND AE43 AL26 GND GND AU19 BA16 GND GND C9 H8 GND GND R13
E GND GND GND GND GND GND GND GND ARRIA 10 - NC/DNU E
A2 AE44 AL35 AU2 BA2 D10 H9 R18
A21 GND GND AE5 AL36 GND GND AU34 BA21 GND GND D15 J1 GND GND R2 M25 AN28
A26 GND GND AE6 AL39 GND GND AU38 BA26 GND GND D20 J10 GND GND R23 N29 NC1 DNU1 AP29
A31 GND GND AE9 AL40 GND GND AU39 BA31 GND GND D25 J15 GND GND R28 P27 NC2 DNU2 AR27
A34 GND GND AF10 AL43 GND GND AU40 BA36 GND GND D3 J2 GND GND R33 P28 NC3 DNU3 BC10
A40 GND GND AF21 AL6 GND GND AU5 BA43 GND GND D36 J36 GND GND R39 P32 NC6 DNU6 BD34
A43 GND GND AF26 AL9 GND GND AU6 BA44 GND GND D37 J37 GND GND R40 R25 NC7 DNU7
A5 GND GND AF3 AM10 GND GND AU7 BA5 GND GND D38 J38 GND GND R43 R26 NC8
A6 GND GND AF31 AM14 GND GND AU9 BA6 GND GND D4 J39 GND GND R44 M26 NC9
A9 GND GND AF35 AM22 GND GND AV12 BA9 GND GND D41 J40 GND GND R5 M27 NC10
AA1 GND GND AF4 AM24 GND GND AV17 BB14 GND GND D42 J43 GND GND R6 M28 NC11
AA10 GND GND AF41 AM3 GND GND AV3 BB19 GND GND D7 J44 GND GND R9 M30 NC12
AA11 GND GND AF42 AM34 GND GND AV32 BB24 GND GND D8 J5 GND GND T11 M31 NC13
AA16 GND GND AG1 AM36 GND GND AV36 BB29 GND GND D9 J6 GND GND T16 N23 NC14
AA2 GND GND AG10 AM4 GND GND AV37 BB3 GND GND E1 J7 GND GND T21 N24 NC15
D GND GND GND GND GND GND GND GND NC18 D
AA35 AG2 AM9 AV41 BB37 E2 K10 T36 N28
AA36 GND GND AG24 AN1 GND GND AV42 BB38 GND GND E23 K3 GND GND T4 N30 NC19
AA39 GND GND AG29 AN17 GND GND AV7 BB4 GND GND E28 K33 GND GND T41 N31 NC20
AA40 GND GND AG34 AN2 GND GND AV8 BB41 GND GND E33 K35 GND GND T42 P22 NC21
AA43 GND GND AG35 AN22 GND GND AV9 BB42 GND GND E36 K4 GND GND T9 P23 NC22
AA44 GND GND AG36 AN27 GND GND AW1 BB7 GND GND E39 K41 GND GND U1 P24 NC23
AA5 GND GND AG39 AN32 GND GND AW10 BB8 GND GND E40 K42 GND GND U10 P26 NC24
AA6 GND GND AG40 AN35 GND GND AW15 BB9 GND GND E43 L1 GND GND U14 NC25
AA9 GND GND AG43 AN36 GND GND AW2 BC1 GND GND E44 L10 GND GND U19 10AX115F1932C
AB10 GND GND AG44 AN39 GND GND AW20 BC12 GND GND E5 L11 GND GND U2
AB29 GND GND AG9 AN44 GND GND AW35 BC22 GND GND F11 L26 GND GND U34
AB3 GND GND AH12 AN5 GND GND AW36 BC27 GND GND F16 L31 GND GND U35
AB4 GND GND AH27 AP10 GND GND AW43 BC36 GND GND F3 L39 GND GND U40
C GND GND GND GND GND GND GND GND C
AC1 AH36 AP30 AW6 BC43 F37 L44 U5
AC10 GND GND AH4 AP35 GND GND AW9 BC44 GND GND F38 L5 GND GND U6
AC17 GND GND AH41 AP36 GND GND AY13 BC5 GND GND F4 L6 GND GND U9
AC2 GND GND AH42 AP37 GND GND AY18 BC6 GND GND F41 L9 GND GND V10
AC22 GND GND AH9 AP38 GND GND AY23 BC9 GND GND F42 M3 GND GND V12
AC27 GND GND AJ1 AP4 GND GND AY28 BD11 GND GND F7 M34 GND GND V17
AC36 GND GND AJ2 AP7 GND GND AY36 BD20 GND GND G1 M41 GND GND V3
AC43 GND GND AJ30 AR1 GND GND AY4 BD30 GND GND G2 N1 GND GND V41
AC44 GND GND AJ35 AR2 GND GND AY41 BD36 GND GND G24 N17 GND GND V42
AC5 GND GND AJ36 AR33 GND GND AY42 BD37 GND GND G29 N2 GND GND W1
AD10 GND GND AJ43 AR40 GND GND AY9 BD41 GND GND G39 N32 GND GND W25
AD20 GND GND AJ44 AR43 GND GND B10 BD42 GND GND G40 N35 GND GND W36
B GND GND GND GND GND GND GND GND B
AD3 AJ6 AR5 B14 BD7 G44 N39 W40
AD4 GND GND AK10 AR7 GND GND B24 BD9 GND GND G6 N43 GND GND W44
AD41 GND GND AK13 AR8 GND GND B29 C1 GND GND G9 N44 GND GND W5
AD42 GND GND AK18 AT11 GND GND B3 C12 GND GND H12 N5 GND GND W6
AD9 GND GND AK23 AT16 GND GND B34 C17 GND GND H17 N6 GND GND W9
AE1 GND GND AK28 AT21 GND GND B35 C2 GND GND H22 N9 GND GND Y18
AE10 GND GND AK3 AT26 GND GND B36 C22 GND GND H27 P10 GND GND Y23
AE33 GND GND AL1 AT4 GND GND B42 C40 GND GND H38 P35 GND GND Y4
GND GND AU1 GND GND BA1 GND GND R1 GND GND AM28
10AX115F1932C GND GND 10AX115F1932C GND GND
A 10AX115F1932C 10AX115F1932C A
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Decoupling
Do Not Copy. Decoupling requirements is design specific. Please use the Early Power Estimator and
PDN Tool available on Altera.com to determine your specific decoupling requirements.
E E
A10_VCC FPGA VCC A10_1.8V FPGA VCCA_PLL, VCCH_GXB[L,R]
C135 C25 C12 C269 C9 C11 C263 C1 C24 C85 C279 C52 C303 C20 C10 C629 C329 C280 C301 C302 C356 C414 C519 C610 C614 C612 C393 C608 C396 C395 C394
330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 330uF 4.7uF 0.47uF 0.47uF 0.47uF 0.1uF 0.01uF 0.01uF 22nF 22nF
A10_VCCPT
C485 C281 C278 C495 C494 C553 C556 C514 C578 C480 C583 C476 C478 C450 C479 C521 C500 C542 C518 C577 C590 C552 FPGA VCCPT, VCCBAT
330uF 330uF 330uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
C493 C471 C516 C538 C509 C561 C555 C491 C533
4.7uF 1uF 0.47uF 0.1uF 47nF 0.01uF 0.01uF 4.7nF 4.7nF

C589 C575 C559 C446 C543 C539 C576 C560 C497 C498 C474 C554 C537 C557 C545 C584 C452 C523 C562 C451 C540 C517 C447
D 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF D
C535 C512 C511 C522 C492 C472 C448 C475 C453
4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF

A10_VCCRAM A10_VCC
FPGA VCCERAM
C496 C515 C510 C502 C501 C524 C544

C349 C342 C341 C340 C351 C350 C352 C339 C477 C499 C520 C541 C558 C581 C734 C735 C736 C737
4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 22nF 22nF
4.7uF 1uF 0.47uF 0.22uF 0.1uF 0.1uF 0.1uF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 100uF 100uF 100uF 100uF
6.3v 6.3v 6.3v 6.3v
A10_VCCRT_GXB A10_VCCRT_GXB A10_VCCRT_GXB
C C661 C607 C606 C631 C609 C649 C650 C630 C633 C636 C634 C637 C380 C616 C369 C376 C365 C643 C372 C364 C360 C964 C965 C981 C982 C
100uF 4.7uF 1uF 0.47uF 0.22uF 0.1uF 0.1uF 47nF 0.01uF 0.01uF 4.7uF 4.7uF 0.47uF 0.22uF 0.22uF 0.1uF 47nF 47nF 0.01uF 0.01uF 0.01uF 100uF 100uF 100uF 100uF
C639 C642 C645 C647 C362 C366 C370 C374 C378 C381 C632 C638 C635 C641 C644 C646 C368 C640 C373 C377 C361
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 22nF 22nF 22nF 22nF
C611 C613 C615 C617 C382 C363 C367 C371 C375 C379
22nF 22nF 22nF 22nF 22nF 22nF 22nF 22nF 22nF 22nF A10_VCCIO_MEM
MEM_VREF A10_VCCIO_1.8V
FPGA VCCIO BANKS 2J, 2K, 2L FPGA VCCIO BANKS 2A, 2I, 3A, 3D, 3E, 3H, VCCPGM
C580 C579 C591 C605 C582 C592 C593 C546 C418 C420 C513 C534 C536 C449 C419 C564 C563 C503 C594 C525
B B
4.7uF 4.7uF 0.22uF 0.1uF 0.1uF 0.1uF 0.1uF 100uF 1uF 0.47uF 0.22uF 0.22uF 0.1uF 0.1uF 0.1uF 4.7nF 4.7nF 22nF 22nF 22nF
A10_VCCIO_FMCA
VREF_FMCA
FPGA VCCIO BANKS 3B & 3C
C424 C454 C423 C482 C421 C422 C481

SCREW1 STANDOFF1 PCB1
4.7uF 4.7uF 0.47uF 0.22uF 0.1uF 0.1uF 0.1uF
SCREW2 STANDOFF2
SCREW3 STANDOFF3 A10_VCCIO_FMCB

VREF_FMCB
SCREW4 STANDOFF4 FPGA VCCIO BANKS 3F & 3G
SCREW5 STANDOFF5 C415 C392 C445 C416 C417 C473 C444

A A
4.7uF 4.7uF 0.47uF 0.22uF 0.1uF 0.1uF 0.1uF Altera Corporation, 101 Innovation Dr., San Jose CA 95134
Title
B 150-0321301-E3 (6XX-44366R) E3.1
8 7 6 5 4 3 2 1
5 4 3 2 1
EN_A10_VCCIO 30,34,42,43,44,45
EN_A10_1.8V 30,41
EN_A10_GROUP2 30,38,39
Power-down Fast Discharge
EN_A10_VCC 30,35,36
3.3V A10_VCCIO_1.8V 3.3V A10_VCCIO_FMCA 3.3V MEM_VDD
5 5 5
R906 R916 R926
10K Q23 10K Q27 10K Q31
FDMC8878 FDMC8878 FDMC8878
D D
4 4 4
R903 R913 R923

R905 10 R915 10 R925 10
Q24 DNI 3 2 1 Q28 DNI 3 2 1 Q32 DNI 3 2 1
EN_A10_VCCIO EN_A10_VCCIO EN_A10_VCCIO
FDV305N FDV305N FDV305N
R904 R902 R914 R912 R924 R922
10 0.5 10 0.5 10 0.5
3.3V A10_VCCIO_MEM 3.3V A10_VCCIO_FMCB 3.3V 2.5V
5 5 5
R911 R921 R931
10K Q25 10K Q29 10K Q33
4 4 4
C C
R908 R918 R928

R910 10 R920 10 R930 10
Q26 DNI 3 2 1 Q30 DNI 3 2 1 Q34 DNI 3 2 1
EN_A10_VCCIO EN_A10_VCCIO EN_A10_VCCIO
R909 R907 R919 R917 R929 R927
10 0.5 10 0.5 10 0.5
3.3V A10_1.8V 3.3V A10_VCCRAM 3.3V A10_VCCRT_GXB
5 5 5
R1105 R1096 R1101
10K Q50 10K Q51 10K Q52
4 4 4
B R1102 R1093 R1098 B

R1104 10 R1095 10 R1100 10
Q53 DNI 3 2 1 Q48 DNI 3 2 1 Q49 DNI 3 2 1
EN_A10_1.8V EN_A10_GROUP2 EN_A10_GROUP2
R1103 R1091 R1094 R1092 R1099 R1097
10 0.5 10 0.5 10 0.5
3.3V A10_VCC
5
R1110
10K Q55
FDMC8878
R1106
A R1109 10 A
Q54 DNI 3 2 1
EN_A10_VCC
FDV305N Altera Corporation, 101 Innovation Dr., San Jose CA 95134
R1108 R1107 Copyright (c) 2013, Altera Corporation. All Rights Reserved.
10 0.5 Title
B 150-0321301-E3 (6XX-44366R) E3.1
5 4 3 2 1

A10GX PCIE E3p1

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9 PLL 45 Power4 - A10 VCCIO MEM

28 Power Sequence Diagram 64

PCI Express Edge Connector 11 PCIE_TX_P[7:0]

75-ohm to 100-ohm XCVR traces.

C254 C255 C256 C725 C724 C258 C257 C723

U28C Arria 10 GX Bank 2 9

(1.2V, 1.35V, 1.5V)

VARIABLE EMI VCCIO

(1.2V, 1.35V, 1.5V)BANK-2L

MEM_DQB3 IO,LVDS2J_3N,DQ8L IO,LVDS2L_3N,DQ0L MEM_DQA4

Y31 D27 17 MEM_CLK_P

U28D Arria 10 Bank 3A-3D

FMCA VARIABLE VCCIO

FMCA_LA_RX_N4 AP16 AK12 USB_DATA1

(1.2V, 1.5V, 1.8V)

FMCA_LA_TX_N5 AR14 IO,LVDS3B_5P,DQ56R IO,LVDS3D_5P,DQ48R AH11 FM_A12

FMCA_LA_RX_P3 AR15 IO,LVDS3B_5N,DQ56R IO,LVDS3D_5N,DQ48R AJ12 FM_A19 3.3V 1.8V

FMCA_LA_TX_P6 AR17 IO,LVDS3B_6N,DQ56R IO,LVDS3D_6N,DQ48R AH13 FM_A21

U28E Arria 10 Bank 3E-3H

FMCB VARIABLE VCCIO

FMCB_LA_RX_N0 D16 C20

FMCB_LA_TX_N0 B17 IO,LVDS3F_5P,DQ40R IO,LVDS3H_5P,DQ32R B22 USER_DIPSW3

FMCB_LA_TX_P4 A15 IO,LVDS3F_5N,DQ40R IO,LVDS3H_5N,DQ32R B21 USER_DIPSW5

FMCB_LA_RX_P3 A18 IO,LVDS3F_6N,DQ40R IO,LVDS3H_6N,DQ32R A20 USER_DIPSW7

6 3 MSEL2 R489 1.00k FPGA_PR_DONE 10.0K R410

BANK-3D FMC PORT A INTERFACE

0.1uF 10uF BLM15AG221SN1

25.00MHz 7 1.8V_PLL L13

C72 DNI CLKIN VDDO2 16

SFP_RX_P AA42 AB44 SFP_TX_P 9 REFCLK1_P

FMCA_DP_M2C_P0 AW7 BC7 FMCA_DP_C2M_P0 FMCB_DP_M2C_P0 AA3 AB1 FMCB_DP_C2M_P0

FMCA_DP_M2C_P2 AY5 BB5 FMCA_DP_C2M_P2 FMCB_DP_M2C_P2 Y5 V1 FMCB_DP_C2M_P2 19 FMCA_DP_M2C_P[15:0]

FMCA_GBTCLK_M2C_P0 AL8 FMCB_GBTCLK_M2C_P0 W8 20 FMCB_DP_M2C_P[15:0]

FMCA_DP_M2C_P6 AN3 AY1 FMCA_DP_C2M_P6 FMCB_DP_M2C_P6 R3 K1 FMCB_DP_C2M_P6

FLASH 1-Gbit FLASH 1-Gbit

R286 10.0K FLASH_WPn

R280 10.0K FLASH_RESETn

U15B ENET_DVDD 2.5V

32 1 ENET_LED_TX R388 220 D26

External Memory Interface Connector Map

J14A External Memory Interface - HiLo connector POWER CONTROL

Display Port (x4)

C304 C310 1.8V 3.3V

FMC Port A E20

FMC Port B E20

Quad Small Form-factor Pluggable (QSFP) Interface

Altera Corporation, 101 Innovation Dr., San Jose CA 95134

Small Form Factor Pluggable Plus (SFP+) Connector

NOTE 1: Bypass Capacitors should be placed as close to the associated 20-pin

SDI Cable Driver, Equalizer, and SMB

75 Ohm Single-Ended Impedance

U40 0.1uF 0.1uF 0.01uF 0.01uF

MAX_ERROR RES_MAX_ERROR R243 22.0 7,13 CPU_RESETn

PCIE_LED_G3 YELLOW_LED R547 22.0 5.0V J10

14 3 USER_DIPSW2 RN1F 6 11 10K 8 3 SI516_FS R530 10.0K 9 2x16 LCD I2C

On-Board USB Blaster II - Part 1 ARRIA 10 USB INTERFACE

100K R259 FX2_RESETn 2 3 D3 IOB1_7 IOB1_31 N2 FX2_PA2 19 FMCA_JTAG_TDO

24M_XTALOUT 4 XTALIN FX2_PA0 L1 IOB1/GCLK0 TCK U2 C_USB_MAX_TDI R25 0 FX2_PD2

E DIPSWITCH4 Logic 0 = Device JTAG Bypass 5 USB_ADDR[1:0] E

Altera Corporation, 101 Innovation Dr., San Jose CA 95134

Altera Corporation, 101 Innovation Dr., San Jose CA 95134