420 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO.
3, MARCH 2011
Matrix Codes for Reliable and Cost Efficient
Memory Chips
Costas Argyrides, Member, IEEE, Dhiraj K. Pradhan, Fellow, IEEE, and Taskin Kocak
Abstract—This paper presents a method to protect memories
against multiple bit upsets and to improve manufacturing yield.
The proposed method, called a Matrix code, combines Hamming
and Parity codes to assure the improvement of reliability and yield
of the memory chips in the presence of high defects and multiple
bit-upsets. The method is evaluated using fault injection experi-
ments. The results are compared to well-known techniques such as
Reed–Muller and Hamming codes. The proposed technique per-
forms better than the Hamming codes and achieves comparable
performance with Reed–Muller codes with very favorable imple-
mentation gains such as 25% reduction in area and power con-
sumption. It also achieves reliability increase by more than 50%
in some cases. Further, the yield benefits provided by the proposed
method, measured by the yield improvements per cost metric, is up
to 300% better than the ones provided by Reed–Muller codes.
Index Terms—Error correcting codes (ECCs), memories, relia-
bility, yield.
I. INTRODUCTION
S CMOS process technology scales, high-density,
A low-cost, high-speed integrated circuits with low voltage
levels and small noise margins will be increasingly susceptible
to temporary faults [1]. In very deep submicrometer technolo-
gies, single-event upsets (SEUs) like atmospheric neutrons and
alpha particles severely impact field-level product reliability,
not only for memory, but for logic as well. When these particles
hit the silicon bulk, they create minority carriers which if col-
lected by the source/drain diffusions, could change the voltage
level of the node.
This issue has drawn a growing attention from the fault tol-
erance community due to the recent increase of the soft error
rate of combinational logic circuits [2]. While effective solu-
tions to protect memory elements have already been devised [3],
the low probability of soft errors affecting CMOS combinational
circuits being latched at the output of the circuit kept this subject
as a secondary research point. Therefore, not many techniques
to cope with this problem have been proposed until now. Sim-
ilar concerns are also expressed for critical applications such as
space, where there can be potentially serious consequences for
the spacecraft, including loss of information, functional failure,
Manuscript received May 27, 2009; revised September 09, 2009. First pub-
lished December 11, 2009; current version published February 24, 2011.
C. Argyrides and D. K. Pradhan are with the Department of Computer Sci-
ence, University of Bristol, Bristol, BS8 1UB, U.K. (e-mail: costas@computer.
org; pradhan@cs.bris.ac.uk).
T. Kocak is with the Department of Computer Engineering, Bahcesehir Uni-
versity, Istanbul 34353, Turkey (e-mail: taskin.kocak@bahcesehir.edu.tr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2009.2036362
1063-8210/$26.00 © 2009 IEEE
or loss of control [4]. Although SEU is the major concern for
some critical applications, multiple bit upsets (MBU) are also
becoming important problems in designing memories mostly
because of the following.
1) The error rate of memories are increased due to the tech-
nology shrinkage [5], [6]. Therefore, the probability of
having multiple errors increases.
2) MBUs can be induced by direct ionization or nuclear recoil
after passing a high-energy ion [7].
3) The probability of having multiple errors is increased when
the size of memory is increased as demonstrated by the
experiments in [8] and [9].
Unfortunately, packaging and shielding cannot effectively
be used to shield against SEUs and MBUs, since they may be
caused by neutrons which can easily penetrate through pack-
ages [6], [10]. The most common approach to maintain a good
level of reliability for memory cells is to use error correcting
codes. Hamming and odd weight codes are largely used to pro-
tect memories against SEU because of their ability to correct
single upsets efficiently with reduced area and performance
overhead [11]. However, multiple upsets caused by a single
charged particle can provoke errors in the system protected by
these single-error correcting codes. On the other hand, there
are advanced error correcting codes such as Reed–Muller code
[12], which can cope with multiple upsets. However, this is
achieved at the expense of high area and power consumption.
The most common approach to deal with multiple errors has
been the use of interleaving in the physical arrangement of the
memory cells, so that cells that belong to the same logical word
are separated. As the errors in an MBU are physically close as
discussed in [13] they will cause single errors in different words
that can be corrected by the single error correction-double error
detection (SEC-DED) codes.
However, interleaving cannot be used, for example, in small
memories or register files, and in other cases, its use may have
an impact on floor-planning, access time and power consump-
tion, as discussed in [14]. For those reasons, the use of more
sophisticated codes or the combination of different codes has
been proposed in [15] to deal with MBUs when the use of in-
terleaving is not a valid option. More recently, codes that can
correct multiple errors only when they are adjacent have also
been proposed in [14]. These codes are tailored to the specific
patterns of errors in an MBU (again the errors will tend to be
physically close) and therefore can achieve effective protection
at a reduced cost.
An alternative approach to protect memories is the use of
built-in current sensors (BICS) that are able to detect the occur-
rence of errors by detecting changes in the current, as proposed
ARGYRIDES et al.: MATRIX CODES FOR RELIABLE AND COST EFFICIENT MEMORY CHIPS
in [16] and [17]. The sensors are placed in the columns of the
memory block and they detect unexpected current variations on
each of the memory bit positions.
The protection can be optimized with protection codes that
are tailored to the specific problem of a memory protected that
suffers MBUs. This is the objective of this paper in which such
codes are proposed.
Another major issue in the design of memories for new tech-
nologies is to cope with defects. As reported in [18], the yield
is decreasing while the technology is scaling. Many different
techniques have been proposed based on the use of redundant
elements to replace the defective ones. These techniques vary
from those applied during the manufacturing process, in the test
phase, to the use of built-in circuits that are able to repair the
memory chips even during normal operation in the field, with
different tradeoffs in terms of cost and speed.
In this paper, a high level method for detection and correc-
tion of multiple faults is proposed. This method is based on
combining Hamming codes and Parity codes in a matrix format
so the detection and correction of multiple faults is achieved.
The fault detection/correction coverage, mean-error-to-fail
(METF) and reliability in terms of mean-time-to-fail (MTTF)
of the proposed approach are analyzed and compared to those
of Reed–Muller code and Hamming code. The results show
that the proposed approach can detect and correct multiple
faults more than Hamming code but slightly less than the
Reed–Muller code but with higher MTTF results compared
to Reed–Muller ones in most of the cases. However, the area
and power consumption of the proposed method are 25%
and 21% better than the Reed–Muller code, respectively. We
also introduce different metrics for comparing the protection
methods for their correction and detection coverage as well
as their cost while incorporated into a memory chip for the
improvement of the yield. Based on the experimental results,
the detection/correction coverage of our proposed method is
better than Reed–Muller and provides better yield results with
respect to the cost of the methods. This paper is an extension
of [19]. In this paper, we show results based on memory chip
simulation while the results of [19] were portrayed using
experiment and analytical results based on the codeword’s
coverage. Also in this version we discuss different codeword
organization. Additionally a yield and cost per chip analysis
are presented here and METF results are portrayed as well.
The remainder of this paper is organized as follows. Section II
provides some background and related work. The matrix code
(MC) is introduced in Section III. Experimental study based on
fault injection and reliability analysis based on the METF of
the proposed method are provided in Section IV. Section V ex-
plains the area and power consumption analysis of the proposed
method. The yield and cost per chip analysis are portrayed in
Section VI, and finally Section VII concludes this paper.
II. BACKGROUND AND RELATED WORK
Concurrent error detection (CED) is one of the major ap-
proaches for transient errors mitigation. In its simpler forms,
CED allows only the detection of errors, requiring the use of ad-
ditional techniques for error correction. Nevertheless, the imple-
mentation of CED usually requires sometimes the duplication of
421
the area of circuit to be protected. One of the simpler examples
of CED is called duplication with comparison [20]–[22], which
duplicates the circuit to be protected and compares the results
generated by both copies to check for errors. This technique im-
poses an area overhead higher than 100%, and when an error is
detected the outputs of the circuit must be recomputed.
Hamming codes and odd weight codes are largely used to
protect memories against SEU because of their efficient ability
to correct single upsets with a reduced area and performance
overhead [23]. The Hamming code implementation is composed
by a combinational block responsible to code the data (encoder
block), inclusion of extra bits in the word that indicate the Parity
(extra latches or flip-flops) and another combinational block re-
sponsible for decoding the data (decoder block). The encoder
block calculates the parity bit, and it can be implemented by a
set of two-input XOR gates. The decoder block is more complex
than the encoder block, because it needs not only to detect the
fault, but it must also correct it. It is basically composed by the
same logic used to compose the Parity bits plus a decoder that
will indicate the bit address that contains the upset. The decoder
block can also be composed of a set of two-input XOR gates and
some AND and INVERTER gates. In [23], studies show the area
efficiency of using Hamming code to protect memories. How-
ever, it does not cope with multiple upsets. Consequently, more
complex correcting codes must be investigated.
The Reed–Muller code [12], [24] is another protection code
that is able to detect and correct more errors than a Hamming
code and is suitable for tolerating multiple upsets in SRAM
memories. Although this type of protection code is more effi-
cient than Hamming code in terms of multiple error detection
and correction, the main drawback of this protection code is its
high area and power penalties (since encoding and decoding cor-
recting circuitry in this code is more complex than for a Ham-
ming code). Hence, a low-overhead error detection and correc-
tion code for tolerating multiple upset is required.
Many different techniques have been proposed, all of them
based on the use of redundant elements to replace defective
ones. Those techniques vary from those applied during the man-
ufacturing process, in the test phase, to the use of built-in circuits
able to repair the memory chips even during normal operation in
the field, with different tradeoffs in terms of cost and speed. No
matter when the chip repair is performed, those techniques rely
in a few basic redundancy schemes. For instance, in redundant
rows or redundant columns approach, only redundant rows (or
redundant columns) are included in the memory array and are
used to replace defective rows (or defective columns) detected
during test. Also known as 1-D redundancy, the main advan-
tage of this approach is that its implementation is very straight-
forward, requiring no complex redundant rows (or columns) al-
location algorithms. However, its repair efficiency can be low,
since a defective column (row) containing multiple defective
cells cannot be replaced by a single redundant row (column)
[25]–[27].
Both redundant rows and columns can be incorporated into
the memory array, which will be more efficient than having ei-
ther one especially in the case of multiple faulty cells exist in the
2-D memory array. The main drawback of this approach is that
the optimal redundancy allocation problem becomes NP-com-
plete [28], [29]. Although many heuristic algorithms have been
422 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 3, MARCH 2011

proposed to solve this problem, it is still difficult to develop

on-chip implementations for these algorithms. Due to the high
bandwidth requirement of today’s system-on-chip (SoC) de-
signs, we usually have long bit lines and word lines for em-
bedded memories. The repair efficiency will decrease since an
entire (and long) redundant row (column) is required to repair Fig. 1. 32-bit logical organization of MCs.
a faulty row (column) containing only a small number of faulty
cells. Examples of such techniques are presented in [28]–[33].
Another method is called divide by half. By using this ap- the horizontal check bits, are the vertical parity bits.
proach (apart from the redundant rows and columns that are in- Hamming codes are applied for each row. For an 8-bit data, 5
corporated into the memory array) while manufacturing, if there Hamming check bits are required, so 5 check bits are added at
are more defects than the ones that may be mitigated using ad- the end of the 8 data bits.
ditional redundancy, the most significant bit (of the address) is The check bits are calculated as follows:
ignored in order to use one half of the chip (upper part or lower
part). When a faulty cell is detected, we can use a redundant (1)
row or a redundant column to replace. Due to the high band- (2)
width requirement of current SoC designs, embedded memories
usually have long bit and word lines, which decreases the repair (3)
efficiency, since an entire (and long) redundant row (column) is (4)
required to repair a defective row (column) containing only a (5)
small number of defective cells. Both for 1-D and 2-D redun-
dancy approaches, when the number of defective cells in the Accordingly, we calculate all check bits for all rows using
array exceeds the repair capability through the use of redun- and , where is the
dant elements, the last alternative before discarding the defec- number of check bits per row, is the row number where is
tive chip is try to use it as a downgraded version of memory. For the corresponding check bit’s position in the first row and is
example, when all remaining defective cells are located in one the corresponding data bit’s position in this first row.
half of the array, the other half can still be used as a memory with For the parity row we use the following formula:
reduced capacity. This is done by permanently setting the most
significant bit of the addresses either to 0 or 1, depending on (6)
which part of the memory is to be used. However, in most cases
the remaining defective cells are evenly distributed across the where is column number from 0 to 7 for eight parity bits.
whole array, and not clustered in one half of the array, making A Hamming decoder is used to decode each row. Decoding is
this technique useless. Examples of such techniques are pre- done in two steps. First, the horizontal check bits are calculated
sented in [34], [35]. More recently another divide by half tech- using the saved data bits and compared with the saved horizontal
nique to cope with this problem has been proposed [36], that check bits. This procedure is called syndrome bit generation
divides memory chip by half using a set of multiplexer and de- and is called syndrome bit of check bit . Second, using
multiplexer. This technique provides better yield results com- syndrome bits , the single error detection (SED)/double error
pared to the other techniques but this technique like the other detection (DED)/no error (NE) signals are generated for each
techniques have a important drawback, they do not provide soft row. If DED is activated (double error is detected in a row), we
error tolerance and in the presence of soft errors will fail. use the vertical syndrome bits and the saved value of the bit
In order to improve the efficiency of repairing embedded we can correct any single or double erroneous bits in each row
memories, a novel redundancy mechanism to cope not only using (7)
with defects but as well as with transients is required. Our
technique, in comparison with the previous techniques, dra- (7)
matically reduces the cost per chip while improving the overall
systems reliability. where is the erroneous bit, the decoder output corre-
sponding to the erroneous bit , is the DED signal of row
III. MATRIX CODES and the syndrome parity of the corresponding parity of
The proposed detection/correction scheme is called MCs the bit, e.g., for , we have .
since the protection bits are used in a matrix format. The It is important to mention that if more than two errors are
-bit code word is divided into subwords of width (i.e., present in the code word, MCs can correct two errors in any row
). A matrix is formed where and assuming that we have only one error in other rows. If only two
represent the numbers of rows and columns, respectively. errors occur, they these can be corrected without any restriction.
For each of the rows, the check bits are added for single Algorithm 1 shows the procedure of detection and correction
error correction/double error detection. Another bits are in the proposed Matrix method which is applied on a code word
added as vertical parity bits. We explain the basic technique , where and are the check bits and the parity bits that
by considering a 32-bit word length memory, which is divided are calculated using the saved data bits in the memory. These
into a matrix format as shown in Fig. 1, where and are then compared with saved in memory check bits and parity
, through are the data bits, through are bits to calculate the syndrome bits and .
ARGYRIDES et al.: MATRIX CODES FOR RELIABLE AND COST EFFICIENT MEMORY CHIPS 423

The read and write procedure for the memory with error
correcting technique can be explained as follows. First each
word in the modules is segmented into multiple bit segments.
Then each bit segment is encoded to bit segment which
contains data bits and check bits. Algorithms 2
and 3 show the procedure for reading/writing words from/to a
Fig. 2. MCs—32 bits. memory, respectively.

Algorithm 2 Algorithm MEMORY READ

Algorithm 1 MATRIX code verification algorithm (X: data) 1: Read the word which contains the desired bits.
2: Correct for any errors.
1: Read the saved data bits of X 3: Route the desired bits on the tree to the root node
2: Generate check bits using saved data bits
3: Generate syndrome bits of check bits Algorithm 3 Algorithm MEMORY WRITE
4: Generate parity bits using saved data bits
5: Generate syndrome bits of parity bits 1: Read the word which includes the desired bit.
6: Correct every saved bit if it is erroneous using (7)
7: Output the corrected word 2: Check for errors and correct them (if any)
3: Compare the value of the bit to be written against the value
Let us give an example of the Matrix method. Suppose the stored in the memory.
codeword “10111001 01100111 11001100 11011100” is saved
4: if bits are different then
to the memory. Check bits will be equal to “11101
01111 10100 01001” and according to parity equations, parity 5: Recompute the check bits based on this new value.
bits will be equal to “1100 1110”. The physical layout
6: Write back the data and the newly computed check bits
of this codeword with check and parity bits is shown in Fig. 2.
Suppose that while reading the codeword from the memory 7: else
and are erroneous. changed from 1 to 0 and from
8: Write back the data and the newly computed check bits
0 to 1. Using the decoding algorithm one can easily correct the
two erroneous bits. This procedure is shown in Example 1. With 9 end if
this technique we can correct any kind of single or double errors
in each row. IV. EXPERIMENTAL STUDY AND RELIABILITY ESTIMATION

Example 1 The procedure of error detection/correction in A. Detection and Correction Coverage

Matrix code In order to estimate the error detection and correction
coverage of the proposed technique, we use a fault injection
1: Read the saved method. Without loss of generality, we consider the coverage of
the proposed technique for a 32-bit data word since the protec-
tion code can be applied on each data word of a given memory.
2: Calculate check bits using saved data bits: The size of a word is assumed to be 32 bits. Both single and
'' multiple faults were injected. For each number of bits in the
3: Generate syndrome bits for check bits: case of multiple fault injection, about one million experiments
'' were conducted. The obtained values are shown in Fig. 3. For
4: Generate parity bits using saved data bits: each protection code, there are two lines for fault detection and
'' correction coverage. The horizontal axis shows the number of
5: Generate syndrome bits of parity bits: faulty bits in a codeword. As the number of faulty bits increases,
'' the fault detection or correction coverage decreases. As can be
6: Correct every saved bit if it is erroneous using (7) observed from this figure, the fault detection and correction
7: coverage of the matrix and Reed–Muller methods are better
8: than Hamming code. It is also shown that the matrix method
9: Initial Value has the ability to provide coverage for multiple faults, though, it
10: is less than the Reed–Muller code for three simultaneous faults
11: in the same codeword.
12: Initial Value
13: Output the B. Reliability Estimation
A memory chip protected with the proposed technique,
Reed–Muller codes and Hamming Codes have been also de-
424 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 3, MARCH 2011
Fig. 3. Detection and correction coverage of different techniques.
Fig. 4. 32 bits codeword.
scribed using C language. Random faults were thrown into the
memory and the METF for each technique was calculated. The
METF of each technique was calculated using 15000 trials
for each memory size, for more details, refer to [37]. We have
used two different codeword sizes, 32 and 64 bits. The results
are portrayed in Figs. 4 and 5. “Matrix Codes A” and “Matrix
Codes B” denote two different word organizations of the pro-
posed technique for each codeword. For the 32-bit codeword
we used two organizations “Matrix Codes A” we have
and and for “Matrix Codes B” and . For
the 64-bit codeword, “Matrix Codes A” we have and
and for “Matrix Codes B” and . The
improvement for 32-bit codeword is more than 10% compared
to Reed–Muller codes.
Using the results obtained from METF and the (8) we can
obtain the MTTF of these techniques. The MTTF results for the
Fig. 5. 64 bits codeword.
TABLE I
MTTF IN DAYS OF PROPOSED TECHNIQUE FOR  = 10 , wordsize = 32
TABLE II
MTTF IN DAYS OF PROPOSED TECHNIQUE FOR  = 10 , wordsize = 64
32-bit and 64-bit codewords for fault rate ( is the
number of bit upsets per day) are portrayed in Tables I and II,
respectively. The MTTF of the “Matrix Codes B” for 2 Mb is
50% increased compared to Reed–Muller Codes.
(8)
The redundant bits required for these techniques are por-
trayed in Table III. The extra required for redundant bits for
MCs are 78% and 125% for “Matrix Codes A” and “Matrix
Codes B” respectively and 100% for Reed–Muller Codes in
32 bits codeword. For 64 bits codeword the required bit for
Matrix Codes 62.5% and 75% for “Matrix Codes A” and
“Matrix Codes B,” respectively. The required redundant bits for
Reed–Muller Codes are 100%. The results of the Tables I–III
will be discussed further in the following section for cost
analysis.
ARGYRIDES et al.: MATRIX CODES FOR RELIABLE AND COST EFFICIENT MEMORY CHIPS 425

TABLE III
REQUIRED REDUNDANT BITS

TABLE IV
AREA, POWER, AND DELAY ANALYSIS

V. IMPLEMENTATION AND COST ANALYSIS

All methods described in the previous section are coded in
VHDL. The results reported here are for a register file, how-
ever the design is generic in datapath width. The design was
simulated using ModelSim and was tested for functionality by
giving various inputs. The outputs from the VHDL coded ar-
chitecture are validated against a standard MATLAB output.
The architectures were synthesized using the Synopsys tools in
0.18- m technology. Synopsys design power was used to esti-
mate the power consumption. Table IV shows the area, power,
and critical path delay of different protection schemes. The area,
power, and delay overheads of the proposed method are 53%,
57%, and 10%, compared to those of the Hamming code, re-
spectively. However, these overheads are less than the overhead
imposed by the Reed-Muller code. Note that, although Ham-
ming code has less overhead compared to the proposed method
and Reed-Muller, it can detect only two errors and correct one
error as depicted in Fig. 3 before.
In order to compare the efficiency of error detection and cor-
rection of the protection codes with respect to the implementa-
tion overheads, we provide a new metric. We call this new metric
correction coverage per cost (CCC) and calculate it as follows:
(9)
where is defined by
(10)
Designers would prefer detection coverage and the cost of de-
tection method to take high and low values, respectively. This
implies that designs should have high a value of the new metric
detection coverage per cost.
Fig. 6 shows the CCC metric against the number of faults.
Note that the Hamming code is not included in this analysis as
there is no any correction when the number of faults is more than
one. The proposed matrix method has better coverage per cost
than the Reed–Muller code. Thus, based on the results given
in Table IV and Fig. 6, the matrix method is better suited for
low-power and high-performance applications.
Fig. 6. Correction coverage per cost for Reed–Muller and matrix codes versus
number of faults in memory.
TABLE V
MTTF PER COST, FOR 32-bit CODEWORD
TABLE VI
MTTF PER COST, FOR 64-bit CODEWORD
We have also introduced another metric for further compar-
ison of the efficiency of the memory using the proposed tech-
niques. We refer to this metric as “MTTF per Cost”. As Cost
we define the redundant bits that are required to implement the
specific technique per code word as in Table III. In this metric
we can see the MCs perform better than Reed–Muller Codes.
These results are portrayed in Tables V and VI.
From Tables V and VI, we can see that the MCs with 64-bit
codeword is always performing better than Reed–Muller codes.
For a 32-bit codeword, we can see that the technique with higher
number of redundant bits is performing better than Reed–Muller
codes for smaller memory sizes than 128-Mbits.
VI. YIELD AND COST PER CHIP ANALYSIS
Traditional memory repair techniques for yield improvement
rely only on the addition of redundant rows and columns, which
are then used to replace defective ones in the fabricated chip
when necessary. As the number of redundant rows and columns
is increased to allow higher repair capability, the fabrication
yield also increases. However, since full size rows or columns
must be used to replace defective ones, which usually contain
426 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 3, MARCH 2011

only a few cells, this technique also increases the fabrication

cost. Moreover, when all redundant rows and columns are ex-
hausted, only a few chips can be used with degraded capacity
by setting the most significant address bit to a constant value,
due to the scattered distribution of defects in the array.
The technique proposed in this paper aims to reduce the cost
per chip and increase yield by using coding techniques that al-
lows you to save some of the faulty memory chips with small
defects instead of traditional redundant rows and columns. In the
analysis of yield and cost per chip presented here, the following
assumptions have been adopted for the following simulations.
1) All defective memory chips have only spot defects, and no
global defects, which are those defects affecting complete
sections of a chip or wafer. For traditional techniques,
when no redundant rows/columns are included in the
chip, any single spot defect will result in the chip being
discarded.
2) A 1024 32 bits memory array is used for area calcula-
tion, which has been obtained by modeling the chips in C
programming language.
3) Each wafer can hold 1000 chips without any redundancy.
If redundant rows/columns are included on the chip, the
number of chips per wafer is reduced. For example, if we
add two redundant rows and two columns in each memory
array the number of chips per wafer will be 969. (This is
used only for the cost per chip.)
A. Yield Analysis
In order to confirm the yield benefits provided by our tech-
nique, we have performed several simulations of a production
run for 1000 chips, with different numbers of defects per array
and different quantities of redundant rows and columns in each
run compared to our technique. In the yield analysis, the con-
sidered number of defects per chip in each simulated produc-
tion run has been randomly distributed in the array, and simu-
lations have been performed assuming the following scenario:
1) chips are repaired using the coding techniques (Reed–Muller
and matrix) and chips with remaining defects after all redundant
elements have been allocated are discarded. For each different
simulation run, the yield has been calculated by dividing the ef-
fective number of chips that were considered good for sale after
repair in each case by the total number of chips that are pro-
duced 1000 in our simulations. Using this criteria we evaluated
the effectiveness of the proposed approach and calculated the
yield for each technique.
B. Cost per Chip Analysis
In order to confirm the cost benefits provided by our tech-
nique, we have performed several simulations of a production
run for 1000 chips, with different numbers of defects per array
and using the same coding techniques. In the cost analysis, the
considered number of defects per chip in each simulated pro-
duction run has been randomly distributed in the array, and sim-
ulations have been performed assuming two different scenarios:
2) chips are repaired using the coding techniques (Reed–Muller
Codes and Matrix Codes) and chips with remaining defects after
all redundant elements have been allocated are discarded. For
each different simulation run, the relative cost per chip has been
Fig. 7. Relative cost per chip for scenario 2).
calculated by dividing total number of chips that could be pro-
duced in the ideal scenario where no redundancy is used and
no chips have defects (1000 in our simulations) by the effective
number of chips that were considered good for sale after repair
in each case. Using this criteria to evaluate the effectiveness of
the proposed approach, for the ideal scenario the relative cost
per chip would be , while in a case where
only 750 working chips are left after repair the relative cost per
chip would be
(11)
This means a 33% cost overhead when compared to the ideal
scenario. For scenario 2), 32 different runs have been simulated,
with the number of defects per chip varying from 0 to 15, with
increments of 1. The results of the simulations are shown in the
chart of Fig. 7, where one can see that even when no defects are
found in the chips, the use of redundant rows and columns in-
creases to relative cost per chip, when compared to the ideal sce-
nario. This happens because in the simulations a constant wafer
capacity has been considered, which means that, when redun-
dant elements are added, the total number of chips per wafer de-
creases, when compared to the ideal scenario. In our case using
the coding techniques we increase the size of the chip by 53%
and 100% for matrix and Reed–Muller codes respectively. It is
obvious that if we reduce the cost per chip, the more benefits we
obtain.
As said before, both “Yield” and “Cost per Chip” are both
important in the design of memory chips. Using both results
we for both of the techniques we evaluate the “Yield per Cost”
metric (YIC) as shown as follows with equal of both:
(12)
The results of this metric are shown in Fig. 8. In all cases (i.e.,
regardless of the number of faults), the memory with embedded
Matrix codes shows better yield per cost than the one with the
Reed–Muller code. The improvement provided by the proposed
ARGYRIDES et al.: MATRIX CODES FOR RELIABLE AND COST EFFICIENT MEMORY CHIPS
Fig. 8. Yield per cost.
Matrix method in YIC can reach up to 300% as in the case of
15 defects per chip.
VII. CONCLUSION
This paper presented a high level error detection and correc-
tion method called MC. The proposed protection code combines
Hamming code and Parity code, so that multiple errors can be
detected and corrected. The fault-injection based experimental
results show that the proposed Matrix method provides detec-
tion and correction coverage somewhere in between the Ham-
ming and Reed–Muller codes. However, the Hamming code is
not adequate for more than two errors and the Reed–Muller
imposes significant area and power consumption compared to
the proposed method. Cost analysis showed that the proposed
method is significantly better than the Reed–Muller code in both
the detection/correction coverage per cost and yield per cost.
Future research will be conducted for the further improve-
ment of the reliability of the proposed technique and the reduc-
tion of the overheads.
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Costas Argyrides (S’07–M’10) received the B.Sc.
degree in informatics and computer science from
Moscow Power Engineering Institute-Technical
University (MPEI-TU), Moscow, Russia, with
distinction and has entered the list of top 10 students
of the MPEI-TU, and the M.Sc. degree in advanced
computing and the Ph.D. degree in computer science
from the University of Bristol (UoB), Bristol, U.K.
Currently he is a Postdoctoral Research Associate
with the Department of Computer Science, UoB.
Prior to this, he served as a Research Assistant with
the Universities of Warwick and Cambridge. He is the author or coauthor of
more than 30 technical papers. His research interests include fault-tolerant
computer systems, software fault tolerance, reliability improvement, error
correcting codes, algorithmic based fault tolerance and nanotechnology-based
designs.
Dr. Argyrides was a recipient of the Best Paper Award for his paper “Re-
liability Aware Yield Improvement Technique for Nanotechnology Based Cir-
cuits” with C. Lisboa, L. Carro, and D. K. Pradhan presented at the 22nd Sym-
posium on Integrated Circuits and Systems Design SBCCI 2009.
Dhiraj K. Pradhan (S’70–M’72–SM’80–F’88) is
currently a Professor with the Department of Com-
puter Science, University of Bristol, Bristol, U.K.
Previously, he was a Professor with the Department
of Electrical and Computer Engineering, Oregon
State University, Corvallis, and held the COE En-
dowed Chair Professorship in Computer Science
with Texas A&M University, College Station, where
he also served as the founder of the Laboratory of
Computer Systems, and he held a professorship at
the University of Massachusetts, Amherst, where
he also served as a coordinator of computer engineering. He also worked at
the University of California, Berkeley, Oakland University, Rochester, MI,
and the University of Regina, Saskatchewan, Canada. He was also a Visiting
Professor with Stanford University, Stanford, CA. In the past, he worked as
a Staff Engineer with IBM. More recently, he served as the founding CEO
of Reliable Computer Technology, Inc. He continues to serve as an Editor of
prestigious journals, including IEEE transactions. He has also served as the
general chair and program chair for various major conferences. He is also the
inventor of two patents, one of which was licensed to Mentor Graphics and
Motorola. The verification tool, Formal Pro, by Mentor Graphics is based on
his patent. He has contributed to VLSI computer-aided design and test, as well
as to fault-tolerant computing, computer architecture, and parallel processing
research, with major publications in journals and conferences spanning more
than 30 years. During this long career, he has been well funded by various
agencies in Canada, the United States of America, and the United Kingdom.
He is also the coauthor and editor of various books, including Fault-Tolerant
Computing: Theory and Techniques, volumes I and II (Prentice-Hall, 1986),
Fault-Tolerant Computer Systems Design (Prentice-Hall, 1996; second print,
2003), IC Manufacturability: The Art of Process and Design Integration (IEEE
Press, 2000), Practical Design Verification (Cambridge University Press,
2009), and Fault and Defect Tolerance in Nanotechnology Circuits (Cambridge
University Press, 2009). His research interests include low power designs,
soft-error protection and variability issues.
Dr. Pradhan is a fellow of the ACM and the Japan Society for the Promo-
tion of Science. He was a recipient of the Humboldt Prize in Germany, the Ful-
bright-Flad Chair in Computer Science in 1997, Best Paper Awards including
the 1996 IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems Best Paper Award, with W. Kunz, on “Recursive Learning: A New
Implication Technique for Efficient Solutions to CAD Problems Test, Verifica-
tion and Optimization.”
Taskin Kocak received B.S. degrees in electrical and
electronic engineering, and in physics (as a double
major) from Bogazici University, Istanbul, Turkey,
in 1996, and the M.S. and Ph.D. degrees in electrical
and computer engineering from Duke University,
Durham, NC, in 1998 and 2001, respectively.
He is currently an Associate Professor and
Chairman of the Computer Engineering Department,
Bahcesehir University, Istanbul, Turkey. Previously,
he was a Senior Lecturer (associate Professor) with
the Electrical and Electronic Engineering Depart-
ment, University of Bristol, U.K. (2007–2009). Prior to that he was an Assistant
Professor with the Department of Computer Engineering, University of Central
Florida, Orlando (2001–2007). Before joining the academia, he worked as a De-
sign Engineer with Mitsubishi Electronic America’s Semiconductor Division
in Raleigh-Durham, NC (1998–2000). His research interests include computer
networks and communications, and hardware design (computer architecture
and VLSI). His research activities have produced over 85 peer-reviewed
publications, including 29 journal papers, and have been supported by both
American and British funding agencies and companies, including Northrop
Grumman, Toshiba Research Europe, Great Western Research, ClearSpeed
Technology, and U.K. Engineering and Physical Sciences Research Council.
He founded and organized the Advanced Networking and Communications
Hardware Workshop series (2004–2006) which were supported by both IEEE
and ACM. He is the founding Editor-In-Chief of the ICST Transactions on
Network Computing. He also served as an associate editor for the Computer
Journal (2007–2009). He is currently serving as a guest editor for special issues
of the ACM Journal on Emerging Technologies in Computing Systems and
EURASIP Journal on Wireless Communications and Networking.