RT8901 Richtek

®
RT8901
35V Gate Pulse Modulator for LCD Panels

General Description Features
The Gate Pulse Modulator (GPM) is specially designed  Flicker Compensation Circuit
for the application of gate driver in TFT LCD panels. The  Reduction of Coupling Effect Between Gate Line
GPM is controlled by frame signals from timing controller and Pixel
to modulate the Gate-On voltage that acts a flicker  Programmable Power Sequence for Gate Driver IC
compensation circuit to reduce the coupling effect between  Operation from 20V to 35V Positive Supply Input
gate lines and pixels. It also can delay the Gate-On voltage  Adjustable Output Delay Time
while power-on for achieving a correct power-on-sequence  RoHS Compliant and 100% Lead (Pb)-Free
for gate driver ICs. Both of the delay time for flicker
compensation and power-on-sequence are programmable Applications
by external resistors and capacitors.
 TFT-LCD Panels
Ordering Information
RT8901 Typical Application Circuit
4
Package Type VCD CD VGH 1 VGH
S : SOP-8 RT8901 C1
VFLK 8 VFLK 1µF
Lead Plating System R2
33k 2
P : Pb Free VDPM 6
VDPM
VGHM VGHM
R1 C2
G : Green (Halogen Free and Pb Free) 3 1.2k 1.5nF
C3 RE
Note : 100pF
Richtek products are : 7

GND R5A 200k
5
VD VAVDD
 RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020. R5B
20k
 Suitable for use in SnPb or Pb-free soldering processes.
Figure 1. Typical Application Circuit for Mode A and

Marking Information
Mode C
RT8901GS
RT8901GS : Product Number
RT8901 YMDNN : Date Code C4
100pF
GSYMDNN 4
VGH 1
CD VGH
RT8901 C1
VFLK 8 VFLK 1µF
R2
33k 2
6 VGHM VGHM
VDPM
Pin Configurations VDPM R1
1.2k
C2
C3 3 1.5nF
RE
(TOP VIEW) 100pF
7
GND 5 R5A 200k
VGH 8 VFLK VD VAVDD
VGHM 2 7 GND
RE 3 6 VDPM R5B
20k
CD 4 5 VD
SOP-8 Figure 2. Typical Application Circuit for Mode B
Copyright © 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS8901-03 October 2013 www.richtek.com

1
RT8901
Timing Diagram
VGH
VREF
VDPM 0V
CD VCD = 5V
High
VFLK Low
VGH
VGHM 10VD
0V
Duty is controlled by VFLK Discharging Time

is controlled by R1
Figure 3. Timing Sequence of Mode A
VGH
VREF
VDPM 0V
0.9VDD
CD VREF
VFLK
VGH
VGHM 10VD
0V
Duty is controlled by VFLK and C4 Discharging Time

is controlled by R1
Figure 4. Timing Sequence of Mode B
VGH
VREF
VDPM 0V
CD VCD = 3.3V
High
VFLK Low
VGH
VGHM 10VD
0V
Duty is controlled by VFLK Discharging Time

is controlled by R1
Figure 5. Timing Sequence of Mode C
www.richtek.com DS8901-03 October 2013

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RT8901
Functional Pin Description
Pin No. Pin Name Pin Function
1 VGH Power Supply Input.
2 VGHM Switch output directly drives the power supply of Gate Driver IC.
Source of the internal high-voltage MOSFET P2 connect to a resistor from this pin
3 RE
to ground.
VGHM Discharging Delay Input. For mode selection and VGHM discharging delay
4 CD
time setting.
5 VD VGHM Low-Level Regulation Set-Point Input. The voltage level is 10VD.
High-Voltage Switch Delay Input. Connect a capacitor from VDPM to GND to set
6 VDPM
the delay time. The internal current source is 5μA.
7 GND Ground.
8 VFLK Control Signal Input Pin. VFLK is produced from timing controller in LCD module.
Function Block Diagram
VDD VREF
Regulator VGH
5µA VDD
- P1
VDPM +
VDD VGHM
Logic
50µA Control 9R
- Circuit P2
CDO + +
CD
-
R
Q3 RE
VFLK GND VD

3
RT8901
Absolute Maximum Ratings (Note 1)
 VGH, VGHM, RE to GND ------------------------------------------------------------------------------------------------ −0.3V to 40V
 VFLK, VDPM, VD, CD to GND ----------------------------------------------------------------------------------------- −0.3V to 6.5V
 Output Current Source from VGH (Pulse Width <500ns with period >2.5μs) ------------------------------ 1A
 Output Current (rms value), R1 = 0Ω -------------------------------------------------------------------------------- 133mA
 Power Dissipation, PD @ TA = 25°C
SOP-8 ------------------------------------------------------------------------------------------------------------------------ 0.833W
 Package Thermal Resistance (Note 2)
SOP-8, θJA ------------------------------------------------------------------------------------------------------------------ 120°C/W
SOP-8, θJC ----------------------------------------------------------------------------------------------------------------- 30°C/W
 Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
 Junction Temperature ---------------------------------------------------------------------------------------------------- 150°C
 Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------- 2kV
MM (Machine Model) ----------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)

 Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VGH = +30V, GND = 0V, TA = 25°C, unless otherwise specified.)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Supply Voltage VVGH 20 -- 35 V
Input Supply Current IVGH CD = VDPM = 5V, VVFLK = 5V -- 0.5 1.5 mA
Adjustable VGHM Falling fVFLK = 25kHz, VGHM at Low, VGHM
10VD 3 -- V GH V
Regulation Voltage with 1.5nF, R1 = 1.2k
VFLK Threshold Logic- High VVFLK_H 1.5 -- 5.5
V
Voltage Logic- Low VVFLK_L 0 -- 0.4
VFLK Input Leakage Current ILeak VVFLK = 0V or High 1 1 μA
R1 = 1.2k, VGHM with 1.5nF,
VFLK to VGHM Rising
tPLH VVFLK = 0 to 3V, measure -- 100 200 ns
Propagation Delay
VVFLK = 1.5V to 10% VGHM
CD = 5V, R1 = 1.2k, VGHM with
VFLK to VGHM Falling
tPHL 1.5nF , VVFLK = 3 to 0V, measure -- 100 200 ns
Propagation Delay at Mode A
CD = 3.3V, R1 = 1.2k, VGHM with
VFLK to VGHM Falling
tPHL 1.5nF , VVFLK = 3 to 0V, measure -- 260 -- ns
Propagation Delay at Mode C
Operation Frequency f OSC -- -- 300 kHz
VDPM Voltage Threshold VDPM_H VDPM High Logic Threshold 2.4 2.5 2.6 V
CD Mode A Operation Range VCD_A -- 5 -- V

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RT8901
Parameter Symbol Test Conditions Min Typ Max Unit
CD Mode B Voltage Threshold VCD_THB 2.4 2.5 2.6 V
CD Mode C Operation Range VCD_C 3 -- 3.6 V
Connect VDPM to GND,
VDPM Charge Current IVDPM 4 5 6 μA
VVGH = 30V, VVFLK = 5V
Connect CD to GND,
CD Charge Current ICD 40 50 60 μA
VVGH = 30V, VVFLK = 0V
VGH Switch On Resistance RP1 VVGH = 30V/-20mA at VVFLK = 5V -- 15 30 
RE Switch On Resistance RP2 VVGH = 30V/+20mA at VVFLK = 0V -- 15 30 
CD Switch On Resistance RQ3 ICD = +1mA at VVFLK = 5V -- 1 -- k
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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RT8901
Typical Operating Characteristics
Supply Current vs. Supply Voltage Supply Current vs. Temperature
495 600
490 500
Supply Current (uA)
Supply Current (uA)

485 400
480 300
475 200
470 100
VVDPM = VCD = VVFLK = 5V VVDPM = VCD = VVFLK = 5V

465 0
20 22 24 26 28 30 -40 -25 -10 5 20 35 50 65 80 95 110 125
Supply Voltage (V) Temperature (°C)
VDPM Charge Current vs. Temperature CD Charge Current vs. Temperature

6 55
5.75 53.5
VDPM Charge Current (uA)
CD Charge Current(uA)
5.5 52
5.25 50.5
5 49
4.75 47.5
4.5 46
4.25 44.5
4 43
3.75 41.5
VVGH = 30V, VVFLK = 0V VVGH = 30V, VVFLK = VCD = 5V
3.5 40
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)
VFLK Threshold vs. Temperature CD Threshold vs. Temperature

1.5 3
1.3 2.8
VFLK Threshold (V)
CD Threshold (V)
Rising
1.1 2.6
Rising
Falling
0.9 2.4
Falling
0.7 2.2
VVDPM = VCD = 5V, VVGH = 30V VVDPM = 5V, VVGH = 30V

0.5 2
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature ( °C )

6
RT8901
VGHM Start Waveform VGHM Falling Regulation Voltage
VVFLK
(2V/Div)
VVFLK
(2V/Div)
VVGHM
(10V/Div)
VVDPM VVGH = 0V to 30V, VCD = 5V VVGHM VVGH = 30V, VCD = 5V

(5V/Div) VVD = 0V, fVFLK = 50kHz
(10V/Div) VVD = 1.6V, fVFLK = 50kHz
Time (25μs/Div) Time (2.5μs/Div)
Mode A VGHM Propagation Delay Mode A VGHM Propagation Delay
VVFLK VVFLK
(2V/Div) (2V/Div)
VVGHM VVGHM
(10V/Div) (10V/Div)
VVGH = 30V, VCD = 5V VVGH = 30V, VCD = 5V
VVFLK = 0V to 3V VVFLK = 3V to 0V
Time (25μs/Div) Time (50ns/Div)
Mode C VGHM Propagation Delay Mode C VGHM Propagation Delay
VVFLK VVFLK
(2V/Div) (2V/Div)
VVGHM VVGHM
(10V/Div) (10V/Div)
VVGH = 30V, VCD = 3.3V VVGH = 30V, VCD = 3.3V
VVFLK = 0V to 3V VVFLK = 3V to 0V
Time (25ns/Div) Time (100ns/Div)

7
RT8901
Applications Information
The GPM consists of two high-voltage MOSFETs which The voltage on the VDPM linearly rises because of the
include P1 between VGH and VGHM and P2 between constant-charging current. When VDPM goes above VREF,
VGHM and RE. The switch-control block is enabled when the switch control block is enabled.
VDPM exceeds VREF and then P1 and P2 are controlled
by VFLK and CD. There are three different modes of Output Current Maximum Rating (rms value)
operation (see the Typical Application Circuit and Timing The GPM output current is RMS value and the RMS current
Diagram). boundary depends on ambient temperature with fixed P1
and P2 on-resistance. In figure 6, the test condition is
Activate the Mode A by connecting CD to 5V. When VFLK
VGH = 30V with R1 = 0Ω and R1 = 43Ω. The boundary is
is logic high, P1 turns on and P2 turns off, VGHM is
located at 125°C junction temperature for safe operation
connected to VGH. When VFLK is logic low, P1 turns off
in SOP-8 package.
and P2 turns on, VGHM is connected to RE, and VGHM
is discharged through the resistor between RE and GND. RMS
RMSCurent
Currentvs.
vs.Ambient
Ambient Temperature
Temperature
P2 turns off and stops discharging VGHM when VGHM 180
reaches 10 times the voltage of the VD pin. 160 R1 = 43Ω
When CD is connected with a capacitor, the switch control 140

RMS Current (mA)
block works in the Mode B. The rising edge of the VFLK 120
R1 = 0Ω
will turns on P1 and turns off P2, connecting VGHM to 100
VGH. An internal N-MOSFET Q3 between CDO and GND 80
is also turned on to discharge the external capacitor 60
between CD and GND. The falling edge of VFLK turns off
40
Q3, and an internal 50μA current source starts charging
20
the CD capacitor. Once VCD exceeds VREF, the switch
0
control circuit turns off P1 and turns on P2, connecting 0 20 40 60 80 100 120 140
VGHM to RE. VGHM is discharged through the resistor
Ambient Temperature (°C)
connected between RE and GND. P2 turns off and stops
discharging VGHM when VGHM reaches 10 times the Figure 6. Output Current Maximum Rating vs. Ambient
voltage of the VD pin. Temperature with R1 = 0Ω and R1 = 43Ω
Activate the Mode C by connecting CD to 3.3V. P1 will be
turned on, P2 will be turned off and Q3 will be turned on Thermal Considerations
respectively when VFLK is high. When VFLK is low, Q3 For continuous operation, do not exceed absolute
will be turned off and CDO will be pull to the same voltage maximum operation junction temperature. The maximum
level as CD through a 1kΩ resistor. P1 and P2 will be turn power dissipation depends on the thermal resistance of
off and on respectively when comparator detects CDO IC package, PCB layout, the rate of surroundings airflow
voltage is greater than 2.5V. VGHM is discharged through and temperature difference between junction to ambient.
the resistor connected between RE and GND. P2 turns The maximum power dissipation can be calculated by
off and stops discharging VGHM when VGHM reaches 10 following formula :
times the voltage of VD pin.
PD(MAX) = ( TJ(MAX) - TA ) / θJA
The timing of enabling the switch control block can be
Where T J(MAX) is the maximum operation junction
adjusted with an external capacitor connected between
temperature, TA is the ambient temperature and the θJA is
VDPM and GND. An internal 5μA current source starts
the junction to ambient thermal resistance.
charging the VDPM capacitor if all internal power is ready.

8
RT8901
For recommended operating conditions specification, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance θJA is layout dependent. For
SOP-8 package, the thermal resistance θJA is 120°C/W
on the standard JEDEC 51-7 four layers thermal test board.
The maximum power dissipation at TA =25°C can be
calculated by following formula :
PD(MAX) = ( 125°C - 25°C ) / (120°C/W) = 0.833W for
SOP-8 package
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. The Figure 7 of derating curves allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation allowed.
1.0
Four Layers PCB
Maximum Power Dissipation (W)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0 15 30 45 60 75 90 105 120 135
Ambient Temperature (°C)
Figure 7. Derating Curve

9
RT8901
Outline Dimension
H
A
J B
C
I
D
Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.050 0.254 0.002 0.010
J 5.791 6.200 0.228 0.244
M 0.400 1.270 0.016 0.050
8-Lead SOP Plastic Package
Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
10

RT8901 Richtek

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®

35V Gate Pulse Modulator for LCD Panels

Richtek products are : 7

Figure 1. Typical Application Circuit for Mode A and

SOP-8 Figure 2. Typical Application Circuit for Mode B

DS8901-03 October 2013 www.richtek.com

Duty is controlled by VFLK Discharging Time

Figure 3. Timing Sequence of Mode A

Duty is controlled by VFLK and C4 Discharging Time

Figure 4. Timing Sequence of Mode B

Duty is controlled by VFLK Discharging Time

www.richtek.com DS8901-03 October 2013

Function Block Diagram

DS8901-03 October 2013 www.richtek.com

Recommended Operating Conditions (Note 4)

www.richtek.com DS8901-03 October 2013

DS8901-03 October 2013 www.richtek.com

Supply Current (uA)

VVDPM = VCD = VVFLK = 5V VVDPM = VCD = VVFLK = 5V

VDPM Charge Current vs. Temperature CD Charge Current vs. Temperature

VFLK Threshold vs. Temperature CD Threshold vs. Temperature

VVDPM = VCD = 5V, VVGH = 30V VVDPM = 5V, VVGH = 30V

www.richtek.com DS8901-03 October 2013

VGHM Start Waveform VGHM Falling Regulation Voltage

VVDPM VVGH = 0V to 30V, VCD = 5V VVGHM VVGH = 30V, VCD = 5V

Time (25μs/Div) Time (2.5μs/Div)

Mode A VGHM Propagation Delay Mode A VGHM Propagation Delay

Time (25μs/Div) Time (50ns/Div)

Mode C VGHM Propagation Delay Mode C VGHM Propagation Delay

Time (25ns/Div) Time (100ns/Div)

DS8901-03 October 2013 www.richtek.com

reaches 10 times the voltage of the VD pin. 160 R1 = 43Ω

When CD is connected with a capacitor, the switch control 140

www.richtek.com DS8901-03 October 2013

Figure 7. Derating Curve

DS8901-03 October 2013 www.richtek.com

Dimensions In Millimeters Dimensions In Inches

8-Lead SOP Plastic Package

Richtek Technology Corporation

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