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Instrumentation Amplifier
AD624
FEATURES FUNCTIONAL BLOCK DIAGRAM
Low Noise: 0.2 V p-p 0.1 Hz to 10 Hz
Low Gain TC: 5 ppm max (G = 1) 50⍀
–INPUT
Low Nonlinearity: 0.001% max (G = 1 to 200)
High CMRR: 130 dB min (G = 500 to 1000) G = 100
AD624
Low Input Offset Voltage: 25 V, max 225.3⍀
Low Input Offset Voltage Drift: 0.25 V/ⴗC max G = 200 4445.7⍀
124⍀
Gain Bandwidth Product: 25 MHz VB 10k⍀
G = 500 SENSE
Pin Programmable Gains of 1, 100, 200, 500, 1000 80.2⍀
20k⍀ 10k⍀
No External Components Required RG1
20k⍀ 10k⍀ OUTPUT
Internally Compensated RG2
10k⍀
REF
50⍀
+INPUT
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD624–SPECIFICATIONS (@ V = ⴞ15 V, R = 2 k⍀ and T = +25ⴗC, unless otherwise noted)
S L A
–2– REV. C
AD624
Model AD624A AD624B AD624C AD624S
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
REFERENCE INPUT
RIN 16 20 24 16 20 24 16 20 24 16 20 24 kΩ
IIN 30 30 30 30 µA
Voltage Range ± 10 ± 10 ± 10 ± 10 V
Gain to Output 1 1 1 1 %
TEMPERATURE RANGE
Specified Performance –25 +85 –25 +85 –25 +85 –55 +125 °C
Storage –65 +150 –65 +150 –65 +150 –65 +150 °C
POWER SUPPLY
Power Supply Range ⴞ6 ⴞ15 ⴞ18 ⴞ6 ⴞ15 ⴞ18 ⴞ6 ⴞ15 ⴞ18 ⴞ6 ⴞ15 ⴞ18 V
Quiescent Current 3.5 5 3.5 5 3.5 5 3.5 5 mA
NOTES
1
VDL is the maximum differential input voltage at G = 1 for specified nonlinearity, V DL at other gains = 10 V/G. V D = actual differential input voltage.
1
Example: G = 10, V D = 0.50. VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production unit at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
REV. C –3–
AD624–Typical Characteristics
20 20 30
15 15
20
+25ⴗC
10 10
10
5 5
0 0 0
0 5 10 15 20 0 5 10 15 20 10 100 1k 10k
SUPPLY VOLTAGE – ⴞV SUPPLY VOLTAGE – ⴞV LOAD RESISTANCE – ⍀
Figure 1. Input Voltage Range vs. Figure 2. Output Voltage Swing vs. Figure 3. Output Voltage Swing vs.
Supply Voltage, G = 1 Supply Voltage Load Resistance
8.0 16 40
AMPLIFIER QUIESCENT CURRENT – mA
14 30
INPUT BIAS CURRENT – ⴞnA
10 10
4.0 8 0
6 –10
2.0 4 –20
2 –30
0 0 –40
0 5 10 15 20 0 5 10 15 20 –125 –75 –25 25 75 125
SUPPLY VOLTAGE – ⴞV SUPPLY VOLTAGE – ⴞV TEMPERATURE – ⴗC
Figure 4. Quiescent Current vs. Figure 5. Input Bias Current vs. Figure 6. Input Bias Current vs.
Supply Voltage Supply Voltage Temperature
16
–1
14
0
⌬VOS FROM FINAL VALUE – V
INPUT BIAS CURRENT – ⴞnA
12
1
500
10
GAIN – V/V
2 100
8
3 10
6
4
1
4
5
2
6
0 0
0 5 10 15 20 7 1 10 100 1k 10k 100k 1M 10M
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
INPUT VOLTAGE – ⴞV FREQUENCY – Hz
WARM-UP TIME – Minutes
Figure 7. Input Bias Current vs. CMV Figure 8. Offset Voltage, RTI, Turn Figure 9. Gain vs. Frequency
On Drift
–4– REV. C
AD624
–140 30 160
G = 500
–VS = –15V dc+
0 0 0
1 10 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10 100 1k 10k 100k
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz
Figure 10. CMRR vs. Frequency RTI, Figure 11. Large Signal Frequency Figure 12. Positive PSRR vs.
Zero to 1k Source Imbalance Response Frequency
1000
100 G = 10
10 1000
80
G = 100
G = 100, 1000
60
G = 1000
40 1 100
G=1
20
0 0.1 10
10 100 1k 10k 100k 1 10 100 1k 10k 100k 0.1 1 10 100 10k 100k
FREQUENCY – Hz FREQUENCY – Hz
FREQUENCY – Hz
Figure 13. Negative PSRR vs. Figure 14. RTI Noise Spectral Figure 15. Input Current Noise
Frequency Density vs. Gain
–12 TO 12
1% 0.1% 0.01%
–8 TO 8
–4 TO 4
OUTPUT
STEP –V
4 TO –4
8 TO –8
1% 0.1% 0.01%
12 TO –12
0 5 10 15 20
SETTLING TIME – s
Figure 16. Low Frequency Voltage Figure 17. Low Frequency Voltage Figure 18. Settling Time, Gain = 1
Noise, G = 1 (System Gain = 1000) Noise, G = 1000 (System Gain =
100,000)
REV. C –5–
AD624
–12 TO 12 0.1%
1% 0.01%
–8 TO 8
–4 TO 4
OUTPUT
STEP –V
4 TO –4
8 TO –8
1% 0.01%
0.1%
12 TO –12
0 5 10 15 20
SETTLING TIME – s
Figure 19. Large Signal Pulse Figure 20. Settling Time Gain = 100 Figure 21. Large Signal Pulse
Response and Settling Time, G = 1 Response and Settling Time,
G = 100
–12 TO 12 1% 0.1%
0.01%
–8 TO 8
–4 TO 4
OUTPUT
STEP –V
4 TO –4
8 TO –8
0.01%
1% 0.1%
12 TO –12
0 5 10 15 20
SETTLING TIME – s
Figure 22. Range Signal Pulse Figure 23. Settling Time Gain = 1000 Figure 24. Large Signal Pulse
Response and Settling Time, Response and Settling Time,
G = 500 G = 1000
–6– REV. C
AD624
10k⍀ 1k⍀ 10k⍀
1% 10T 1%
+VS VOUT
INPUT
20V p-p 100k⍀
1%
RG1
G = 100
G = 200
AD624
G = 500
1k⍀ 500⍀ 200⍀
0.1% 0.1% 0.1% RG2
–VS
REV. C –7–
AD624
directly proportional to gain i.e., input offset as measured at Table I.
the output at G = 100 is 100 times greater than at G = 1.
Temperature
Output offset is independent of gain. At low gains, output offset Gain Coefficient Pin 3
drift is dominant, while at high gains input offset drift domi- (Nominal) (Nominal) to Pin Connect Pins
nates. Therefore, the output offset voltage drift is normally
specified as drift at G = 1 (where input effects are insignificant), 1 –0 ppm/°C – –
while input offset voltage drift is given by drift specification at a 100 –1.5 ppm/°C 13 –
high gain (where output offset effects are negligible). All input- 125 –5 ppm/°C 13 11 to 16
related numbers are referred to the input (RTI) which is to say 137 –5.5 ppm/°C 13 11 to 12
that the effect on the output is “G” times larger. Voltage offset 186.5 –6.5 ppm/°C 13 11 to 12 to 16
vs. power supply is also specified at one or more gain settings 200 –3.5 ppm/°C 12 –
and is also RTI. 250 –5.5 ppm/°C 12 11 to 13
333 –15 ppm/°C 12 11 to 16
By separating these errors, one can evaluate the total error inde-
375 –0.5 ppm/°C 12 13 to 16
pendent of the gain setting used. In a given gain configura-
500 –10 ppm/°C 11 –
tion both errors can be combined to give a total error referred to
624 –5 ppm/°C 11 13 to 16
the input (R.T.I.) or output (R.T.O.) by the following formula:
688 –1.5 ppm/°C 11 11 to 12; 13 to 16
Total Error R.T.I. = input error + (output error/gain) 831 +4 ppm/°C 11 16 to 12
Total Error R.T.O. = (Gain × input error) + output error 1000 0 ppm/°C 11 16 to 12; 13 to 11
As an illustration, a typical AD624 might have a +250 µV out- Pins 3 and 16 programs the gain according to the formula
put offset and a –50 µV input offset. In a unity gain configura-
40k
tion, the total output offset would be 200 µV or the sum of the RG =
two. At a gain of 100, the output offset would be –4.75 mV G −1
or: +250 µV + 100 (–50 µV) = –4.75 mV. (see Figure 29). For best results RG should be a precision resis-
tor with a low temperature coefficient. An external RG affects both
The AD624 provides for both input and output offset adjust- gain accuracy and gain drift due to the mismatch between it and
ment. This optimizes nulling in very high precision applications the internal thin-film resistors R56 and R57. Gain accuracy is
and minimizes offset voltage effects in switched gain applica- determined by the tolerance of the external RG and the absolute
tions. In such applications the input offset is adjusted first at the accuracy of the internal resistors (±20%). Gain drift is determined
highest programmed gain, then the output offset is adjusted at by the mismatch of the temperature coefficient of RG and the tem-
G = 1. perature coefficient of the internal resistors (–15 ppm/°C typ),
and the temperature coefficient of the internal interconnections.
GAIN
+VS
The AD624 includes high accuracy pretrimmed internal
–INPUT
gain resistors. These allow for single connection program-
RG1
ming of gains of 1, 100, 200 and 500. Additionally, a variety 1.5k⍀
of gains including a pretrimmed gain of 1000 can be achieved OR 2.105k⍀ AD624 VOUT
through series and parallel combinations of the internal resis- 1k⍀
tors. Table I shows the available gains and the appropriate RG2 REFERENCE
pin connections and gain temperature coefficients. +INPUT
–VS G = 40.000 + 1 = 20 ⴞ20%
The gain values achieved via the combination of internal 2.105
resistors are extremely useful. The temperature coefficient of the Figure 29. Operating Connections for G = 20
gain is dependent primarily on the mismatch of the temperature
coefficients of the various internal resistors. Tracking of these The AD624 may also be configured to provide gain in the out-
resistors is extremely tight resulting in the low gain TCs shown put stage. Figure 30 shows an H pad attenuator connected to
in Table I. the reference and sense lines of the AD624. The values of R1,
R2 and R3 should be selected to be as low as possible to mini-
If the desired value of gain is not attainable using the inter- mize the gain variation and reduction of CMRR. Varying R2
nal resistors, a single external resistor can be used to achieve will precisely set the gain without affecting CMRR. CMRR is
any gain between 1 and 10,000. This resistor connected between determined by the match of R1 and R3.
+VS
INPUT +VS
OFFSET R1
–INPUT 10k⍀ NULL –INPUT 6k⍀
RG1 RG1
R2
G = 100 G = 100 5k⍀
AD624 VOUT VOUT
G = 200 G = 200 AD624
G = 500 RL
G = 500
OUTPUT
RG2 SIGNAL RG2
+INPUT COMMON
+INPUT R3
–VS –VS 6k⍀
(R2||20k⍀) + R1 + R3)
Figure 28. Operating Connections for G = 200 G=
(R2||20k⍀) (R1 + R2 + R3) || RL 2k⍀
–8– REV. C
AD624
NOISE +VS
LOAD G = 200
100⍀
RG2 AD624 VOUT
–VS TO AD711
POWER
REFERENCE
SUPPLY
GROUND +INPUT
–VS
a. Transformer Coupled
Figure 32. Shield Driver, G ≥ 100
+VS
+VS
–INPUT
AD712 RG1
100⍀
AD624
AD624 VOUT
LOAD 100⍀
–VS RG2
REFERENCE
+INPUT
–VS TO
POWER –VS
SUPPLY
GROUND Figure 33. Differential Shield Driver
b. Thermocouple
REV. C –9–
AD624
GROUNDING “inside the loop” of an instrumentation amplifier to provide the
Many data-acquisition components have two or more ground required current without significantly degrading overall perfor-
pins which are not connected together within the device. These mance. The effects of nonlinearities, offset and gain inaccuracies
grounds must be tied together at one point, usually at the sys- of the buffer are reduced by the loop gain of the IA output
tem power supply ground. Ideally, a single solid ground would amplifier. Offset drift of the buffer is similarly reduced.
be desirable. However, since current flows through the ground
wires and etch stripes of the circuit cards, and since these paths REFERENCE TERMINAL
have resistance and inductance, hundreds of millivolts can be The reference terminal may be used to offset the output by up
generated between the system ground point and the data acqui- to ± 10 V. This is useful when the load is “floating” or does not
sition components. Separate ground returns should be provided share a ground with the rest of the system. It also provides a
to minimize the current flow in the path from the most sensitive direct means of injecting a precise offset. It must be remem-
points to the system ground point. In this way supply currents bered that the total output swing is ± 10 volts, from ground, to
and logic-gate return currents are not summed into the same be shared between signal and reference offset.
return path as analog signals where they would cause measure-
+VS
ment errors (see Figure 34).
SENSE
VIN+
ANALOG P.S. DIGITAL P.S.
+15V C –15V C +5V
AD624
REF LOAD
VIN–
0.1 0.1 0.1 0.1
F F F F 1F 1F 1F
–VS
X1 SENSE
AD624
+INPUT
RL R1
VIN– +VX–
(REF) IL
AD624
V–
–INPUT
AD711
Figure 35. AD624 Instrumentation Amplifier with Output REF
A2
Current Booster
VX VIN 40.000 LOAD
Typically, IC instrumentation amplifiers are rated for a full IL =
R1
=
R1
1+
RG
± 10 volt output swing into 2 kΩ. In some applications, how-
ever, the need exists to drive more current into heavier loads. Figure 37. Voltage-to-Current Converter
Figure 35 shows how a current booster may be connected
–10– REV. C
AD624
50⍀
–IN 1 16
OUTPUT
50⍀ OFFSET G = 100 G = 200 G = 500
+IN 2 80.2⍀ 15 TRIM K1 K2 K3
NC
3 14 R2
4445.7⍀ 10k⍀
INPUT
OFFSET 4 13
TRIM 20k⍀ VB 20k⍀ 225.3⍀ RELAY
SHIELDS
R1 5 12
10k⍀ 10k⍀ 10k⍀ 124⍀
10k⍀
6 11
+5V
10k⍀
–VS 7 10 K1 K2 K3
AD624 D1 D2 D3
+VS 8 9 OUT
C1 C2
1F
35V
ANALOG K1 – K3 =
COMMON THERMOSEN DM2C
4.5V COIL
D1 – D3 = IN4148 INPUTS A
GAIN Y0
RANGE B
74LS138 Y1 7407N
DECODER BUFFER 10F
GAIN TABLE Y2 DRIVER
A B GAIN
0 0 100
0 1 500
1 0 200 +5V
1 1 1
LOGIC
COMMON
By establishing a reference at the “low” side of a current setting symmetrical bipolar transmission is ideal in this application. The
resistor, an output current may be defined as a function of input multiplying DAC’s advantage is that it can handle inputs of
voltage, gain and the value of that resistor. Since only a small either polarity or zero without affecting the programmed gain.
current is demanded at the input of the buffer amplifier A2, the The circuit shown uses an AD7528 to set the gain (DAC A) and
forced current IL will largely flow through the load. Offset and to perform a fine adjustment (DAC B).
drift specifications of A2 must be added to the output offset and
drift specifications of the IA.
(+INPUT) 50⍀
–IN 1 16
OUTPUT
PROGRAMMABLE GAIN (–INPUT) 50⍀ OFFSET
+IN 2 15 NULL
Figure 38 shows the AD624 being used as a software program- 80.2⍀
TO –V
mable gain amplifier. Gain switching can be accomplished with 3 14 10k⍀
INPUT 4445.7⍀
mechanical switches such as DIP switches or reed relays. It OFFSET
4 13
should be noted that the “on” resistance of the switch in series NULL 20k⍀ VB 20k⍀
225.3⍀
with the internal gain resistor becomes part of the gain equation 10k⍀ 5 12
10k⍀ 10k⍀
and will have an effect on gain accuracy. 124⍀
6 11
10k⍀
A significant advantage in using the internal gain resistors in a 10k⍀
–VS 7 10
programmable gain configuration is the minimization of thermo-
AD624
couple signals which are often present in multiplexed data +VS 8 9 VOUT
acquisition systems. 1F
35V
If the full performance of the AD624 is to be achieved, the user 10pF VSS VDD GND
must be extremely careful in designing and laying out his circuit
+VS
to minimize the remaining thermocouple signals.
The AD624 can also be connected for gain in the output stage. 39.2k⍀ 1k⍀
Figure 39 shows an AD547 used as an active attenuator in the AD711 28.7k⍀ 1k⍀
–VS
output amplifier’s feedback loop. The active attenuation pre- 316k⍀ 1k⍀
sents a very low impedance to the feedback resistors therefore AD7590
minimizing the common-mode rejection ratio degradation.
Another method for developing the switching scheme is to use a A1 A2 A3 A4 WR
DAC. The AD7528 dual DAC which acts essentially as a pair of
switched resistive attenuators having high analog linearity and Figure 39. Programmable Output Gain
REV. C –11–
AD624
50⍀ In many applications complex software algorithms for autozero
+INPUT
(–INPUT) applications are not available. For these applications Figure 42
provides a hardware solution.
G = 100
AD624
225.3⍀
+VS
G = 200 4445.7⍀ VB
124⍀
10k⍀ 15 16 RG1
G = 500
80.2⍀ 14
20k⍀ 10k⍀
RG1 AD624 VOUT
VOUT 13 0.1F LOW 9 10
RG2 CH
20k⍀ LEAKAGE
10k⍀
10k⍀ RG2
1k⍀
50⍀
–INPUT –VS 12 11
(+INPUT) AD542
+VS
1/2
AD712
DAC A
VDD
DATA DB0 VSS AD7510DIKD
INPUTS DB7 256:1 GND
CS AD7528 A1 A2 A3 A4
WR 200s
DAC A/DAC B 1/2 ZERO PULSE
DAC B AD712
Figure 42. Autozero Circuit
The microprocessor controlled data acquisition system shown in
Figure 43 includes includes both autozero and autogain capabil-
Figure 40. Programmable Output Gain Using a DAC ity. By dedicating two of the differential inputs, one to ground
and one to the A/D reference, the proper program calibration
AUTOZERO CIRCUITS cycles can eliminate both initial accuracy errors and accuracy
In many applications it is necessary to provide very accurate errors over temperature. The autozero cycle, in this application,
data in high gain configurations. At room temperature the offset converts a number that appears to be ground and then writes
effects can be nulled by the use of offset trimpots. Over the that same number (8 bit) to the AD624 which eliminates the
operating temperature range, however, offset nulling becomes a zero error since its output has an inverted scale. The autogain
problem. The circuit of Figure 41 shows a CMOS DAC operat- cycle converts the A/D reference and compares it with full scale.
ing in the bipolar mode and connected to the reference terminal A multiplicative correction factor is then computed and applied
to provide software controllable offset adjustments. to subsequent readings.
+VS
–INPUT
RG2
RG1 VREF
G = 100 AD583
AD624 VOUT VIN
G = 200 AD7507 AD624 AD574A
G = 500 AGND
RG2
+INPUT RG1
–VS A0 A2
39k⍀ VREF EN A1 –VREF
–VS 20k⍀ 20k⍀
AD589 +VS R3
20k⍀ R5
RFB 20k⍀
MSB AD7524
OUT1 +VS 1/2 LATCH
DATA C1 R4 10k⍀
INPUTS LSB AD712 1/2
10k⍀ 1/2
AD7524 5k⍀ AD712
AD712 DECODE
CS
OUT2
1/2
WR AD712 R6
5k⍀ CONTROL
–VS
GND
MICRO-
ADDRESS BUS PROCESSOR
Figure 41. Software Controllable Offset
–12– REV. C
AD624
WEIGH SCALE Figure 45 is an example of an ac bridge system with the AD630
Figure 44 shows an example of how an AD624 can be used to used as a synchronous demodulator. The oscilloscope photo-
condition the differential output voltage from a load cell. The graph shows the results of a 0.05% bridge imbalance caused by
10% reference voltage adjustment range is required to accom- the 1 Meg resistor in parallel with one leg of the bridge. The top
modate the 10% transducer sensitivity tolerance. The high trace represents the bridge excitation, the upper middle trace is
linearity and low noise of the AD624 make it ideal for use in the amplified bridge output, the lower-middle trace is the out-
applications of this type particularly where it is desirable to put of the synchronous demodulator and the bottom trace is the
measure small changes in weight as opposed to the absolute filtered dc system output.
value. The addition of an autogain/autotare cycle will enable the This system can easily resolve a 0.5 ppm change in bridge
system to remove offsets, gain errors, and drifts making possible impedance. Such a change will produce a 6.3 mV change in the
true 14-bit performance. low-pass filtered dc output, well above the RTO drifts and noise.
+15V +15V The AC-CMRR of the AD624 decreases with the frequency of
NOTE 2
the input signal. This is due mainly to the package-pin capaci-
R3
+10V 10V ⴞ10% 10⍀ tance associated with the AD624’s internal gain resistors. If
100⍀
+5V R1 AD707 2N2219 AC-CMRR is not sufficient for a given application, it can be
30k⍀ trimmed by using a variable capacitor connected to the amplifier’s
AD584 SCALE
+2.5V R2 RG2 pin as shown in Figure 45.
20k⍀ ERROR
ADJUST
VBG
R3 1kHz +VS
10k⍀ BRIDGE
EXCITATION
10k⍀
RG1
–INPUT 1k⍀ 1k⍀
SENSE +10V FULL
G500 SCALE
OUTPUT 1k⍀ AD624C
G200 G = 1000
AD624 A/D 1k⍀
G100 CONVERTER
OUT 1M⍀ RG2
RG2
R5
3M⍀ REFERENCE 4–49pF
CERAMIC ac –VS
+INPUT BALANCE
R4
10k⍀ GAIN = 500 CAPACITOR
ZERO R7
100k TRANSDUCER
ADJUST
(FINE) ⍀ SEE NOTE 1
MODULATION
R6 INPUT
100k⍀ 2.5k⍀
ZERO ADJUST
(COARSE)
PHASE
SHIFTER BA
NOTES
1. LOAD CELL TEDEA MODEL 1010 10kG. OUTPUT 2mV/Vⴞ10%. 2.5k⍀
2. R1, R2 AND R3 SELECTED FOR AD584. OUTPUT 10V ⴞ10%.
B
5k⍀
Figure 44. AD624 Weigh Scale Application
10k⍀ MODULATED
AC BRIDGE OUTPUT
10k⍀ SIGNAL
Bridge circuits which use dc excitation are often plagued by –VS VOUT
–V
errors caused by thermocouple effects, l/f noise, dc drifts in the
electronics, and line noise pickup. One way to get around these CARRIER
INPUT AD630 +VS
problems is to excite the bridge with an ac waveform, amplify COMP
REV. C –13–
AD624
ERROR BUDGET ANALYSIS +VS
Effect on Effect on
Absolute Absolute Effect
AD624C Accuracy Accuracy on
Error Source Specifications Calculation at TA = +25ⴗC at TA = +85ⴗC Resolution
Gain Error ± 0.1% ± 0.1% = 1000 ppm 1000 ppm 1000 ppm –
Gain Instability 10 ppm (10 ppm/°C) (60°C) = 600 ppm _ 600 ppm –
Gain Nonlinearity ± 0.001% ± 0.001% = 10 ppm – – 10 ppm
Input Offset Voltage ± 25 µV, RTI ± 25 µV/20 mV = ± 1250 ppm 1250 ppm 1250 ppm –
Input Offset Voltage Drift ± 0.25 µV/°C (± 0.25 µV/°C) (60°C)= 15 µV
15 µV/20 mV = 750 ppm – 750 ppm –
Output Offset Voltage1 ± 2.0 mV ± 2.0 mV/20 mV = 1000 ppm 1000 ppm 1000 ppm –
Output Offset Voltage Drift1 ± 10 µV/°C (± 10 µV/°C) (60°C) = 600 µV
600 µV/20 mV = 300 ppm – 300 ppm –
Bias Current–Source ± 15 nA (± 15 nA)(5 Ω ) = 0.075 µV
Imbalance Error 0.075 µV/20mV = 3.75 ppm 3.75 ppm 3.75 ppm –
Offset Current–Source ± 10 nA (± 10 nA)(5 Ω) = 0.050 µV
Imbalance Error 0.050 µV/20 mV = 2.5 ppm 2.5 ppm 2.5 ppm –
Offset Current–Source ± 10 nA (10 nA) (175 Ω) = 1.75 µV
Resistance Error 1.75 µV/20 mV = 87.5 ppm 87.5 ppm 87.5 ppm –
Offset Current–Source ± 100 pA/°C (100 pA/°C) (175 Ω) (60°C) = 1 µV
Resistance–Drift 1 µV/20 mV = 50 ppm – 50 ppm –
Common-Mode Rejection 115 dB 115 dB = 1.8 ppm × 5 V = 9 µV
5 V dc 9 µV/20 mV = 444 ppm 450 ppm 450 ppm –
Noise, RTI
(0.1 Hz–10 Hz) 0.22 µV p-p 0.22 µV p-p/20 mV = 10 ppm _ – 10 ppm
Total Error 3793.75 ppm 5493.75 ppm 20 ppm
NOTE
1
Output offset voltage and output offset voltage drift are given as RTI figures.
–14– REV. C
AD624
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16 9
0.310 (7.87)
0.220 (5.59)
1 8
0.320 (8.13)
PIN 1 0.290 (7.37)
0.840 (21.34) MAX 0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX 0.150
0.200 (5.08) (3.81)
0.125 (3.18) MAX
0.015 (0.38)
0.023 (0.58) 0.100 0.070 (1.78) SEATING
(2.54) PLANE 0.008 (0.20)
0.014 (0.36) 0.030 (0.76)
BSC
REV. C –15–
–16–
PRINTED IN U.S.A. C805d–0–7/99