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Data

UE distance to base station UE dis


Period start time ws Cell size Avg UE dist 0-78m 78-156m 156-312m
LTE_1340A LTE_1339A LTE_1341A LTE_1342A LTE_1343A
08.11.2018 4G_LDG 15.000 1.170
08.12.2018 4G_LDG 15.000 1.176
08.13.2018 4G_LDG 15.000 1.142

Page 1
Data

UE distance distribution in 2.1km cells


312-468m 468-624m 624-780m 780-1092m 1092-1404m 1404-1794m 1794-2262m
LTE_1344A LTE_1345A LTE_1346A LTE_1347A LTE_1349A LTE_1350A LTE_1351A

Page 2
Data

UE distance distribution in 5km cells


+2262m 0-0.5km 0.5-1.0km 1.0-1.5km 1.5-2.0km 2.0-2.7km 2.7-3.4km 3.4-4.1km
LTE_1352A LTE_1353A LTE_1354A LTE_1355A LTE_1357A LTE_1359A LTE_1360A LTE_1361A

Page 3
Data

cells UE distance distribution in 10km


4.1-4.8km 4.8-5.6km +5.6km 0-1.0km 1.0-2.0km 2.0-3.0km 3.0-4.0km 4.0-5.3km
LTE_1362A LTE_1363A LTE_1364A LTE_1365A LTE_1366A LTE_1367A LTE_1368A LTE_1369A

Page 4
Data

tance distribution in 10km cells U


5.3-6.9km 6.9-8.6km 8.6-9.5km 9.5-11.1km +11.1km 0-1.5km 1.5-3.0km 3.0-4.5km
LTE_1370A LTE_1371A LTE_1372A LTE_1373A LTE_1374A LTE_1375A LTE_1376A LTE_1377A
83.02 13.29 2.75
82.04 14.12 2.93

Page 5
Data

UE distance distribution in 15km cells


4.5-6.0km 6.0-8.0km 8.0-10.4km 10.4-12.9km 12.9-14.6km 14.6-16.6km +16.6km
LTE_1378A LTE_1379A LTE_1380A LTE_1381A LTE_1382A LTE_1383A LTE_1384A
0.68 0.11 0.09 0.06 0.00 0.00 0.00
0.65 0.12 0.07 0.06 0.00 0.00 0.01

Page 6
Data

UE distance distribution in 30km cells


0-3.0km 3.0-6.0km 6.0-9.0km 9.0-12km 12-16km 16-21km 21-26km 26-33km
LTE_1385A LTE_1386A LTE_1387A LTE_1388A LTE_1389A LTE_1390A LTE_1391A LTE_1392A

Page 7
Data

UE distance distribution in 60km cells


+33km 0-6.0km 6.0-12km 12-15km 15-18km 18-24km 24-32km 32-41km
LTE_1393A LTE_1394A LTE_1395A LTE_1396A LTE_1397A LTE_1398A LTE_1399A LTE_1400A

Page 8
Data

cells UE distance distribution in 100km cells


41-52km 52-63km +63km 0-10km 10-20km 20-30km 30-40km 40-53km
LTE_1401A LTE_1402A LTE_1403A LTE_1404A LTE_1405A LTE_1406A LTE_1407A LTE_1408A

Page 9
Data

istribution in 100km cells


53-69km 69-87km 87-105km +105km
LTE_1409A LTE_1410A LTE_1411A LTE_1412A

Page 10
Documentation

Report Title RSLTE058 - Timing advance


NOP Report Release Version RSLTE LTE16
RS Report Release Version 5.4.1
Report ID rslte_LTE16/reports/RSLTE058.xml
Report Description Timing advance
Start Time 08.11.2018 00:00:00
End Time 08.14.2018 00:00:00
Objects Level: WS_RSLTE-LNBTS-2; 4G_LDG ('4G_LDG')
Object Aggregation Level PLMN/WS_LNBTS
Time Aggregation Level day
Threshold none
Data Source pmrPool
Advanced Filter none

KPI ID KPI Alias KPI Title


LTE_1340a Cell size Expected cel
LTE_1339a Avg UE dist Average UE
LTE_1341a 0-78m % UEs with d
LTE_1342a 78-156m % UEs with d
LTE_1343a 156-312m % UEs with d
LTE_1344a 312-468m % UEs with d
LTE_1345a 468-624m % UEs with d
LTE_1346a 624-780m % UEs with d
LTE_1347a 780-1092m % UEs with d
LTE_1349a 1092-1404m % UEs with d
LTE_1350a 1404-1794m % UEs with d
LTE_1351a 1794-2262m % UEs with d
LTE_1352a +2262m % UEs with
LTE_1353a 0-0.5km % UEs with d
LTE_1354a 0.5-1.0km % UEs with d
LTE_1355a 1.0-1.5km % UEs with d
LTE_1357a 1.5-2.0km % UEs with d
LTE_1359a 2.0-2.7km % UEs with d
LTE_1360a 2.7-3.4km % UEs with d
LTE_1361a 3.4-4.1km % UEs with d
LTE_1362a 4.1-4.8km % UEs with d
LTE_1363a 4.8-5.6km % UEs with d
LTE_1364a +5.6km % UEs with
LTE_1365a 0-1.0km % UEs with d
LTE_1366a 1.0-2.0km % UEs with d
LTE_1367a 2.0-3.0km % UEs with d
LTE_1368a 3.0-4.0km % UEs with d
LTE_1369a 4.0-5.3km % UEs with d
LTE_1370a 5.3-6.9km % UEs with d
LTE_1371a 6.9-8.6km % UEs with d
LTE_1372a 8.6-9.5km % UEs with d
LTE_1373a 9.5-11.1km % UEs with d
LTE_1374a +11.1km % UEs with

Page 11
Documentation

LTE_1375a 0-1.5km % UEs with d


LTE_1376a 1.5-3.0km % UEs with d
LTE_1377a 3.0-4.5km % UEs with d
LTE_1378a 4.5-6.0km % UEs with d
LTE_1379a 6.0-8.0km % UEs with d
LTE_1380a 8.0-10.4km % UEs with d
LTE_1381a 10.4-12.9km % UEs with d
LTE_1382a 12.9-14.6km % UEs with d
LTE_1383a 14.6-16.6km % UEs with d
LTE_1384a +16.6km % UEs with
LTE_1385a 0-3.0km % UEs with d
LTE_1386a 3.0-6.0km % UEs with d
LTE_1387a 6.0-9.0km % UEs with d
LTE_1388a 9.0-12km % UEs with d
LTE_1389a 12-16km % UEs with d
LTE_1390a 16-21km % UEs with d
LTE_1391a 21-26km % UEs with d
LTE_1392a 26-33km % UEs with d
LTE_1393a +33km % UEs with
LTE_1394a 0-6.0km % UEs with d
LTE_1395a 6.0-12km % UEs with d
LTE_1396a 12-15km % UEs with d
LTE_1397a 15-18km % UEs with d
LTE_1398a 18-24km % UEs with d
LTE_1399a 24-32km % UEs with d
LTE_1400a 32-41km % UEs with d
LTE_1401a 41-52km % UEs with d
LTE_1402a 52-63km % UEs with d
LTE_1403a +63km % UEs with
LTE_1404a 0-10km % UEs with d
LTE_1405a 10-20km % UEs with d
LTE_1406a 20-30km % UEs with d
LTE_1407a 30-40km % UEs with d
LTE_1408a 40-53km % UEs with d
LTE_1409a 53-69km % UEs with d
LTE_1410a 69-87km % UEs with d
LTE_1411a 87-105km % UEs with d
LTE_1412a +105km % UEs with

Page 12
Documentation

KPI Formul Unit


lmac_ext.av[km]
lmac_ext.ue[km]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]

Page 13
Documentation

100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]

Page 14
Report Execution

Cache handler
Evaluation method
Init duration
Sql generation
Execution duration
Load from cache
Create tmp Tables
Drop tmp Tables
Load data db
Load data and write to cache

Start Time
2018-08-14 13:56:48.610

2018-08-14 13:56:48.640

Page 15
Report Execution

2018-08-14 13:56:48.789

Page 16
Report Execution

2018-08-14 13:56:52.756

2018-08-14 13:56:52.767

Page 17
Report Execution

com.nokia.oss.qengine.support.CacheAwareEngine
tmp tables(1)
0.341
0.046
4.393
none
4.158
none
none
none

End Time Note Sql


2018-08-14 13:56:48.640 executing sql extra step
create global temporary table jf_lnbts_2

select
"plmn".co_gid "plmn_gid",
"vloflnbtsparent".co_gid "vloflnbts
"vloflnbtsparent".co_mr_gid "vlo
"lnbts".co_gid "lnbts_gid",
"lnbts".co_mr_gid "lnbts_mr_gid
from
utp_common_objects "plmn",
utp_common_objects "vloflnbtsp
utp_common_objects "lnbts"
where
"plmn".co_oc_id = 16 and
( "vloflnbtsparent".co_oc_id = 31
"vloflnbtsparent".co_parent_gid =
"lnbts".co_oc_id = 3129 and
"lnbts".co_parent_gid = "vloflnbts
2018-08-14 13:56:48.788 creating tmp table: jf_LMAC2_1445267551
create global temporary table jf_LMAC
select
a.period_start_time,
g.ws,
SUM(TIMING_ADV_BIN_1) TIMING_A
SUM(TIMING_ADV_BIN_2) TIMIN
SUM(TIMING_ADV_BIN_3) TIMIN
SUM(TIMING_ADV_BIN_4) TIMIN
SUM(TIMING_ADV_BIN_5) TIMIN
SUM(TIMING_ADV_BIN_6) TIMIN
SUM(TIMING_ADV_BIN_7) TIMIN
SUM(TIMING_ADV_BIN_8) TIMIN
SUM(TIMING_ADV_BIN_9) TIMIN
SUM(TIMING_ADV_BIN_10) TIM
SUM(TIMING_ADV_BIN_11) TIM
SUM(TIMING_ADV_BIN_12) TIM

Page 18
Report Execution

SUM(TIMING_ADV_BIN_13) TIM
SUM(TIMING_ADV_BIN_14) TIM
SUM(TIMING_ADV_BIN_15) TIM
SUM(TIMING_ADV_BIN_16) TIM
SUM(TIMING_ADV_BIN_17) TIM
SUM(TIMING_ADV_BIN_18) TIM
SUM(TIMING_ADV_BIN_19) TIM
SUM(TIMING_ADV_BIN_20) TIM
SUM(TIMING_ADV_BIN_21) TIM
SUM(TIMING_ADV_BIN_22) TIM
SUM(TIMING_ADV_BIN_23) TIM
SUM(TIMING_ADV_BIN_24) TIM
SUM(TIMING_ADV_BIN_25) TIM
SUM(TIMING_ADV_BIN_26) TIM
SUM(TIMING_ADV_BIN_27) TIM
SUM(TIMING_ADV_BIN_28) TIM
SUM(TIMING_ADV_BIN_29) TIM
SUM(TIMING_ADV_BIN_30) TIM
from
( select distinct g.ws_gid, g.ws fro
w.setname ws, leg.la_co_gid ws
from
w_manual_sets w,
utp_legacy leg
where
w.int_id = leg.la_int_id) g ) g ,
(
select
trunc( p.period_start_time, 'dd' )
t."vloflnbtsparent_gid" vloflnbtspar
t."lnbts_gid" lnbts_gid,
g.ws ws,
SUM(TIMING_ADV_BIN_1) TIM
SUM(TIMING_ADV_BIN_2) TIMIN
SUM(TIMING_ADV_BIN_3) TIMIN
SUM(TIMING_ADV_BIN_4) TIMIN
SUM(TIMING_ADV_BIN_5) TIMIN
SUM(TIMING_ADV_BIN_6) TIMIN
SUM(TIMING_ADV_BIN_7) TIMIN
SUM(TIMING_ADV_BIN_8) TIMIN
SUM(TIMING_ADV_BIN_9) TIMIN
SUM(TIMING_ADV_BIN_10) TIM
SUM(TIMING_ADV_BIN_11) TIM
SUM(TIMING_ADV_BIN_12) TIM
SUM(TIMING_ADV_BIN_13) TIM
SUM(TIMING_ADV_BIN_14) TIM
SUM(TIMING_ADV_BIN_15) TIM
SUM(TIMING_ADV_BIN_16) TIM
SUM(TIMING_ADV_BIN_17) TIM
SUM(TIMING_ADV_BIN_18) TIM

Page 19
Report Execution

SUM(TIMING_ADV_BIN_19) TIM
SUM(TIMING_ADV_BIN_20) TIM
SUM(TIMING_ADV_BIN_21) TIM
SUM(TIMING_ADV_BIN_22) TIM
SUM(TIMING_ADV_BIN_23) TIM
SUM(TIMING_ADV_BIN_24) TIM
SUM(TIMING_ADV_BIN_25) TIM
SUM(TIMING_ADV_BIN_26) TIM
SUM(TIMING_ADV_BIN_27) TIM
SUM(TIMING_ADV_BIN_28) TIM
SUM(TIMING_ADV_BIN_29) TIM
SUM(TIMING_ADV_BIN_30) TIM
from
( select distinct g.ws_gid, g.ws fr
w.setname ws, leg.la_co_gid ws
from
w_manual_sets w,
utp_legacy leg
where
w.int_id = leg.la_int_id) g ) g ,
jf_lnbts_2_1410667861 t,
noklte_ps_lmac_lnbts_day p
where
g.ws_gid = t."lnbts_gid" and g.w
and period_start_time >= to_dat
and period_start_time < to_date
and t."lnbts_gid" = p.lnbts_id
group by
trunc( p.period_start_time, 'dd' ),
t."vloflnbtsparent_gid",
t."lnbts_gid",
g.ws
)a
where
g.ws_gid = a.lnbts_gid and g.ws in ( '4
group by
a.period_start_time,
g.ws
2018-08-14 13:56:52.755 creating tmp table: jf_LMAC_ext_1425049700
create global temporary table jf_LMAC
select
trunc( p.period_start_time, 'dd' )
g.ws ws,
AVG(TIMING_ADV_SET_INDEX
AVG(decode(TIMING_ADV_SET_
AVG(DECODE((TIMING_ADV_BI
from
(select
w.setname ws, leg.la_co_gid ws
from

Page 20
Report Execution

w_manual_sets w,
utp_legacy leg
where
w.int_id = leg.la_int_id) g ,
jf_lnbts_2_1410667861 t,
NOKLTE_PS_LMAC_MNC1_RA
where
g.ws_gid = t."lnbts_gid" and g.w
and period_start_time >= to_dat
and period_start_time < to_date
and t."lnbts_gid" = p.lnbts_id
group by
trunc( p.period_start_time, 'dd' ),
g.ws
2018-08-14 13:56:52.767 creating tmp table: jf_ALLTABLES_1431423225
create global temporary table jf_ALLTA
select
period_start_time,
ws
from
(
(
select
period_start_time, TO_CHAR(ws)
from
jf_LMAC2_1445267551
)
UNION
(
select
period_start_time, TO_CHAR(ws)
from
jf_LMAC_ext_1425049700
)
)p
2018-08-14 13:56:53.2 report from tmp tables
select
ALLTABLES.period_start_time,
ALLTABLES.ws,
1 WS_DUMMY,
to_number(lmac_ext.avg_tim_adv
to_number(lmac_ext.ue_dist_avg
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext

Page 21
Report Execution

to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext

Page 22
Report Execution

to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
from
dual
,
jf_ALLTABLES_1431423225 ALLTA
jf_LMAC2_1445267551 LMAC2,
jf_LMAC_ext_1425049700 LMAC_
where
1=1
and ALLTABLES.period_start_tim
and ALLTABLES.period_start_tim

order by
2,1,3

Page 23
Report Execution

al temporary table jf_lnbts_2_1410667861 on commit preserve rows as

".co_gid "plmn_gid",
btsparent".co_gid "vloflnbtsparent_gid",
nbtsparent".co_mr_gid "vloflnbtsparent_mr_gid",
.co_gid "lnbts_gid",
".co_mr_gid "lnbts_mr_gid"

ommon_objects "plmn",
ommon_objects "vloflnbtsparent",
ommon_objects "lnbts"

".co_oc_id = 16 and
lnbtsparent".co_oc_id = 3128 or "vloflnbtsparent".co_oc_id = 739 ) and
nbtsparent".co_parent_gid = "plmn".co_gid and
".co_oc_id = 3129 and
".co_parent_gid = "vloflnbtsparent".co_gid
MAC2_1445267551
al temporary table jf_LMAC2_1445267551 on commit preserve rows as

G_ADV_BIN_1) TIMING_ADV_BIN_1,
TIMING_ADV_BIN_2) TIMING_ADV_BIN_2,
TIMING_ADV_BIN_3) TIMING_ADV_BIN_3,
TIMING_ADV_BIN_4) TIMING_ADV_BIN_4,
TIMING_ADV_BIN_5) TIMING_ADV_BIN_5,
TIMING_ADV_BIN_6) TIMING_ADV_BIN_6,
TIMING_ADV_BIN_7) TIMING_ADV_BIN_7,
TIMING_ADV_BIN_8) TIMING_ADV_BIN_8,
TIMING_ADV_BIN_9) TIMING_ADV_BIN_9,
TIMING_ADV_BIN_10) TIMING_ADV_BIN_10,
TIMING_ADV_BIN_11) TIMING_ADV_BIN_11,
TIMING_ADV_BIN_12) TIMING_ADV_BIN_12,

Page 24
Report Execution

TIMING_ADV_BIN_13) TIMING_ADV_BIN_13,
TIMING_ADV_BIN_14) TIMING_ADV_BIN_14,
TIMING_ADV_BIN_15) TIMING_ADV_BIN_15,
TIMING_ADV_BIN_16) TIMING_ADV_BIN_16,
TIMING_ADV_BIN_17) TIMING_ADV_BIN_17,
TIMING_ADV_BIN_18) TIMING_ADV_BIN_18,
TIMING_ADV_BIN_19) TIMING_ADV_BIN_19,
TIMING_ADV_BIN_20) TIMING_ADV_BIN_20,
TIMING_ADV_BIN_21) TIMING_ADV_BIN_21,
TIMING_ADV_BIN_22) TIMING_ADV_BIN_22,
TIMING_ADV_BIN_23) TIMING_ADV_BIN_23,
TIMING_ADV_BIN_24) TIMING_ADV_BIN_24,
TIMING_ADV_BIN_25) TIMING_ADV_BIN_25,
TIMING_ADV_BIN_26) TIMING_ADV_BIN_26,
TIMING_ADV_BIN_27) TIMING_ADV_BIN_27,
TIMING_ADV_BIN_28) TIMING_ADV_BIN_28,
TIMING_ADV_BIN_29) TIMING_ADV_BIN_29,
TIMING_ADV_BIN_30) TIMING_ADV_BIN_30

t distinct g.ws_gid, g.ws from (select


name ws, leg.la_co_gid ws_gid

anual_sets w,

id = leg.la_int_id) g ) g ,

( p.period_start_time, 'dd' ) period_start_time,


nbtsparent_gid" vloflnbtsparent_gid,
_gid" lnbts_gid,

TIMING_ADV_BIN_1) TIMING_ADV_BIN_1,
TIMING_ADV_BIN_2) TIMING_ADV_BIN_2,
TIMING_ADV_BIN_3) TIMING_ADV_BIN_3,
TIMING_ADV_BIN_4) TIMING_ADV_BIN_4,
TIMING_ADV_BIN_5) TIMING_ADV_BIN_5,
TIMING_ADV_BIN_6) TIMING_ADV_BIN_6,
TIMING_ADV_BIN_7) TIMING_ADV_BIN_7,
TIMING_ADV_BIN_8) TIMING_ADV_BIN_8,
TIMING_ADV_BIN_9) TIMING_ADV_BIN_9,
TIMING_ADV_BIN_10) TIMING_ADV_BIN_10,
TIMING_ADV_BIN_11) TIMING_ADV_BIN_11,
TIMING_ADV_BIN_12) TIMING_ADV_BIN_12,
TIMING_ADV_BIN_13) TIMING_ADV_BIN_13,
TIMING_ADV_BIN_14) TIMING_ADV_BIN_14,
TIMING_ADV_BIN_15) TIMING_ADV_BIN_15,
TIMING_ADV_BIN_16) TIMING_ADV_BIN_16,
TIMING_ADV_BIN_17) TIMING_ADV_BIN_17,
TIMING_ADV_BIN_18) TIMING_ADV_BIN_18,

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Report Execution

TIMING_ADV_BIN_19) TIMING_ADV_BIN_19,
TIMING_ADV_BIN_20) TIMING_ADV_BIN_20,
TIMING_ADV_BIN_21) TIMING_ADV_BIN_21,
TIMING_ADV_BIN_22) TIMING_ADV_BIN_22,
TIMING_ADV_BIN_23) TIMING_ADV_BIN_23,
TIMING_ADV_BIN_24) TIMING_ADV_BIN_24,
TIMING_ADV_BIN_25) TIMING_ADV_BIN_25,
TIMING_ADV_BIN_26) TIMING_ADV_BIN_26,
TIMING_ADV_BIN_27) TIMING_ADV_BIN_27,
TIMING_ADV_BIN_28) TIMING_ADV_BIN_28,
TIMING_ADV_BIN_29) TIMING_ADV_BIN_29,
TIMING_ADV_BIN_30) TIMING_ADV_BIN_30

ct distinct g.ws_gid, g.ws from (select


name ws, leg.la_co_gid ws_gid

anual_sets w,

id = leg.la_int_id) g ) g ,
ts_2_1410667861 t,
e_ps_lmac_lnbts_day p

_gid = t."lnbts_gid" and g.ws in ( '4G_LDG' )


eriod_start_time >= to_date('2018/08/11 00:00:00', 'yyyy/mm/dd hh24:mi:ss')
eriod_start_time < to_date('2018/08/14 00:00:00', 'yyyy/mm/dd hh24:mi:ss')
"lnbts_gid" = p.lnbts_id

( p.period_start_time, 'dd' ),
nbtsparent_gid",

a.lnbts_gid and g.ws in ( '4G_LDG' ) and a.ws = g.ws

MAC_ext_1425049700
al temporary table jf_LMAC_ext_1425049700 on commit preserve rows as

( p.period_start_time, 'dd' ) period_start_time,

TIMING_ADV_SET_INDEX) TIMING_ADV_SET_INDEX,
ecode(TIMING_ADV_SET_INDEX ,1,2.1 ,2,5 ,3,10 ,4,15 ,5,30 ,6,60 ,7,100 ,NULL)) AVG_TIM_ADV_INDEX,
ECODE((TIMING_ADV_BIN_1+TIMING_ADV_BIN_2+TIMING_ADV_BIN_3+TIMING_ADV_BIN_4+TIMING_ADV_BIN_5+TIM

name ws, leg.la_co_gid ws_gid

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Report Execution

anual_sets w,

id = leg.la_int_id) g ,
ts_2_1410667861 t,
LTE_PS_LMAC_MNC1_RAW p

_gid = t."lnbts_gid" and g.ws in ( '4G_LDG' )


eriod_start_time >= to_date('2018/08/11 00:00:00', 'yyyy/mm/dd hh24:mi:ss')
eriod_start_time < to_date('2018/08/14 00:00:00', 'yyyy/mm/dd hh24:mi:ss')
"lnbts_gid" = p.lnbts_id

( p.period_start_time, 'dd' ),

LLTABLES_1431423225
al temporary table jf_ALLTABLES_1431423225 on commit preserve rows as

_start_time, TO_CHAR(ws) ws

C2_1445267551

_start_time, TO_CHAR(ws) ws

C_ext_1425049700

BLES.period_start_time,

mber(lmac_ext.avg_tim_adv_index) LTE_1340a,
mber(lmac_ext.ue_dist_avg) LTE_1339a,
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin

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Report Execution

mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin


mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin

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mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin


mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin

ABLES_1431423225 ALLTABLES,
C2_1445267551 LMAC2,
C_ext_1425049700 LMAC_ext

LTABLES.period_start_time = LMAC2.period_start_time (+) and ALLTABLES.ws = LMAC2.ws (+)


LTABLES.period_start_time = LMAC_ext.period_start_time (+) and ALLTABLES.ws = LMAC_ext.ws (+)

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Report Execution

_ADV_INDEX,
BIN_4+TIMING_ADV_BIN_5+TIMING_ADV_BIN_6+TIMING_ADV_BIN_7+TIMING_ADV_BIN_8+TIMING_ADV_BIN_9+TIMING

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Report Execution

2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6


2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6

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2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6


2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6

Page 32
Report Execution

2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6


2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6

Page 33
Report Execution

_8+TIMING_ADV_BIN_9+TIMING_ADV_BIN_10+ TIMING_ADV_BIN_11+TIMING_ADV_BIN_12+TIMING_ADV_BIN_13+TIMI

Page 34
Report Execution

_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi


_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi

Page 35
Report Execution

_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi


_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi

Page 36
Report Execution

_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi


_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi

Page 37
Report Execution

_12+TIMING_ADV_BIN_13+TIMING_ADV_BIN_14+TIMING_ADV_BIN_15+TIMING_ADV_BIN_16+TIMING_ADV_BIN_17+TIM

Page 38
Report Execution

c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b


c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b

Page 39
Report Execution

c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b


c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b

Page 40
Report Execution

c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b


c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b

Page 41
Report Execution

N_16+TIMING_ADV_BIN_17+TIMING_ADV_BIN_18+TIMING_ADV_BIN_19+TIMING_ADV_BIN_20+ TIMING_ADV_BIN_21+

Page 42
Report Execution

dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l


dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l

Page 43
Report Execution

dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l


dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l

Page 44
Report Execution

dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l


dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l

Page 45
Report Execution

BIN_20+ TIMING_ADV_BIN_21+TIMING_ADV_BIN_22+TIMING_ADV_BIN_23+TIMING_ADV_BIN_24+TIMING_ADV_BIN_25

Page 46
Report Execution

5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim


5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim

Page 47
Report Execution

5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim


5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim

Page 48
Report Execution

5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim


5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim

Page 49
Report Execution

V_BIN_24+TIMING_ADV_BIN_25+TIMING_ADV_BIN_26+TIMING_ADV_BIN_27+TIMING_ADV_BIN_28+TIMING_ADV_BIN_

Page 50
Report Execution

2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_


2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_

Page 51
Report Execution

2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_


2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_

Page 52
Report Execution

2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_


2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_

Page 53
Report Execution

DV_BIN_28+TIMING_ADV_BIN_29+TIMING_ADV_BIN_30),0,NULL, (DECODE(TIMING_ADV_SET_INDEX, 1,(39*TIMING_A

Page 54
Report Execution

adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +


adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +

Page 55
Report Execution

adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +


adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +

Page 56
Report Execution

adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +


adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +

Page 57
Report Execution

V_SET_INDEX, 1,(39*TIMING_ADV_BIN_1+117*TIMING_ADV_BIN_2+195*TIMING_ADV_BIN_3+273*TIMING_ADV_BIN_4+

Page 58
Report Execution

25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim


25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim

Page 59
Report Execution

25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim


25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim

Page 60
Report Execution

25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim


25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim

Page 61
Report Execution

N_3+273*TIMING_ADV_BIN_4+351*TIMING_ADV_BIN_5+429*TIMING_ADV_BIN_6+507*TIMING_ADV_BIN_7+585*TIMING

Page 62
Report Execution

c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_


c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing

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c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing


c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12) / (lmac2.timin
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing

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c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing


c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30) / (lmac2.timin
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30) / (lmac2.timin

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MING_ADV_BIN_7+585*TIMING_ADV_BIN_8+663*TIMING_ADV_BIN_9+741*TIMING_ADV_BIN_10+819*TIMING_ADV_BIN

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Report Execution

ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +


ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin
iming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin

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iming_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23) / (lmac2.timing_adv_b


iming_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin
timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15) / (lmac2.timing_adv_bi
iming_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin
iming_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin
timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
iming_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin
iming_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin
timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_
iming_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin
iming_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29) / (lmac2.timing_adv_b
timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin
iming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin

Page 68
Report Execution

iming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin


iming_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin
iming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
iming_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4

Page 69
Report Execution

_BIN_10+819*TIMING_ADV_BIN_11+897*TIMING_ADV_BIN_12+975*TIMING_ADV_BIN_13+1053*TIMING_ADV_BIN_14+1

Page 70
Report Execution

n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...


n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
dv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
dv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...

Page 71
Report Execution

v_bin_23) / (lmac2.timing_adv_bin_1 + lmac2.timing_ad...


v_bin_28 + lmac2.timing_adv_bin_29) / (lmac2.timing_a...
bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
v_bin_15) / (lmac2.timing_adv_bin_1 + lmac2.timing_ad...
v_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv...
v_bin_28 + lmac2.timing_adv_bin_29) / (lmac2.timing_a...
bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_b...
v_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv...
v_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv...
bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
v_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_...
v_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv...
v_bin_29) / (lmac2.timing_adv_bin_1 + lmac2.timing_ad...
bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
dv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
v_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv...
bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
dv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...

Page 72
Report Execution

v_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv...


_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_b...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
dv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
v_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv...
_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_b...

Page 73
Report Execution

3+1053*TIMING_ADV_BIN_14+1131*TIMING_ADV_BIN_15+1209*TIMING_ADV_BIN_16+1287*TIMING_ADV_BIN_17+1365*

Page 74
Report Execution

87*TIMING_ADV_BIN_17+1365*TIMING_ADV_BIN_18+1443*TIMING_ADV_BIN_19+1521*TIMING_...

Page 75
Report Execution

Page 76

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