Documente Academic
Documente Profesional
Documente Cultură
(Autonomous)
Dundigal, Hyderabad - 500 043
I. COURSE OVERVIEW
In this course students will learn digital system fundamental applications. Topics include: logic gates; logic
system design using gate combinations and VHDL (Very High Speed Integrated Circuit Hardware
Description Language); Combinational Circuits; flip-flop theory; shift register theory; counter theory;
VHDL for combinational and sequential circuits. This course is intended to describe the memories like
SRAM and DRAM cells and their opertions along with their timing diagrams.
V. ASSESSMENT METHODOLOGIES–DIRECT:
TERM PAPER
Proficiency
Program Outcomes Level
assessed by
PO1 Engineering knowledge: Apply the knowledge of
mathematics, science, engineering fundamentals, and an
S Assignments.
engineering specialization to the solution of complex
engineering problems.
PO2 Problem analysis: Identify, formulate, review research
literature, and analyze complex engineering problems
H Design
reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
PO3 Design/development of solutions: Design solutions for
complex engineering problems and design system
components or processes that meet the specified needs with S
Mini Project
appropriate consideration for the public health and safety,
and the cultural, societal, and environmental considerations.
PO4 Conduct investigations of complex problems: Use research-
based knowledge and research methods including design of
Open ended
experiments, analysis and interpretation of data, and synthesis S
experiments
of the information to providevalid
conclusions.
PO5 Modern tool usage: Create, select, and apply appropriate
techniques, resources, and modern engineering and IT tools
S Mini Project
including prediction and modeling to complex engineering
activities with an understanding of the limitations.
PO6 The engineer and society: Apply reasoning informed by the
contextual knowledge to assess societal, health, safety, legal
N
and cultural issues and the consequent responsibilities --
relevant to the professional engineering practice.
PO7 Environment and sustainability: Understand the impact of
the professional engineering solutions in societal and
N
environmental contexts, and demonstrate the knowledge of, --
and need for sustainable development.
PO8 Ethics: Apply ethical principles and commit to professional
ethics and responsibilities and norms of the engineering N
--
practice.
PO9 Individual and team work: Function effectively as an
individual, and as a member or leader in diverse teams, and S Project Work
in multidisciplinary settings.
PO10 Communication: Communicate effectively on complex
engineering activities with the engineering community and
with society at large, such as, being able to comprehend and
N
write effective reports and design documentation, make
Seminars
effective presentations, and give and receive clear
instructions.
PO11 Project management and finance: Demonstrate knowledge
and understanding of the engineering and management
principles and apply these to one‟s own work, as a member N
--
and leader in a team, to manage projects and in
multidisciplinary environments.
PO12 Life-long learning: Recognize the need for, and have the
preparation and ability to engage in independent and life- S --
long learning in the broadest context of technological change.
Proficiency
Program Specific Outcomes Level Assessed
by
PSO 1 Professional Skills: An ability to understand the basic concepts
in Electronics & Communication Engineering and to apply them
Lectures and
to various areas, like Electronics, Communications, Signal S
Assignments
processing, VLSI, Embedded systems etc., in the design and
implementation of complex systems.
PSO 2 Problem-Solving Skills: An ability to solve complex
Electronics and communication Engineering problems, using
S Tutorials
latest hardware and software tools, along with analytical skills
to arrive cost effective and appropriate solutions.
PSO 3 Successful Career and Entrepreneurship: An understanding
of social-awareness & environmental-wisdom along with ethical
responsibility to have a successful career and to sustain passion S Guest lectures
and zeal for real-world applications using optimal resources as
an Entrepreneur.
XI. SYLLABUS:
TEXTBOOKS:
1 John F.Wakerly, “Digital Design Principles & Practices”, 3rd Edition, 2005, PHI/ Pearson Education
Asia,
2 J. Bhasker, “VHDL Primer”, Pearson Education / PHI, 3rd Edition. Pearson Higher Education
REFERENCES:
1 Charles H. Roth Jr., “Digital System Design Using VHDL”, PWS Publications, 1998.
2 Alan B. Marcovitz, “Introduction to Logic Design”, TMH, 2nd Edition, 2005.
3 Stephen Brown, ZvonkoVransesic, “Fundamentals of Digital Logic with Verilog Design”, TMH, 2003.
4 Cypress Semiconductors Data Book (Download from website).
5 K. Lalkishore, “Linear Integrated Circuit Applications”, Pearson Educations 2005.
Lecture
Topic Outcomes Topics to be covered Reference
No.
1. Understand thelogic family, Introduction to Logic Family, MOS transistor T1: 3.3
Operation of MOS transistor operation
2. Understand the functioning of CMOS logic and voltage levels, CMOS T1: 3.3
CMOS inverter Inverter
3. Design and analyze CMOS NAND CMOS NAND and NOR gates T1: 3.3.4
and NOR gates
4. Design and analyze CMOS AOI and CMOS AOI, OAI logic T1: 3.3.7
OAI gates
5. Design and analyze CMOS AND CMOS AND & OR gates T1: 3.3.7
andOR gates
6. Design and analyze CMOS XOR and CMOS XOR and XNOR gates T1: 3.3.7
XNOR gates
7. Understand the characteristics of CMOS steady state electrical behavior, CMOS T1: 3.4
CMOS circuit dynamic Electrical behavior
8. Familiar about various CMOS logic CMOS logic families, Diode Logic T1: 3.8-3.9
families
9. Design and analyze TTL NAND gates TTL NAND Gate T1: 3.10
10. Design and analyze TTL NOR gates TTL NOR Gate, CMOS/TTL interfacing, Low T1: 3.10. 3.12
voltage CMOS logic and interfacing
11. Understand ECL logic, comparision Emitter Coupled Logic, Comparison of logic T1:3.14
of logic families families, Familiarity withstandard 74XX and
CMOS 40XX series-ICs – Specifications.
12. Understand the design flow of Design flow, Program structure, types and R5: 8.5-8.6
VHDL constants
13. Understand functions, procedures, Functions and Procedures, R5: 8.5-8.6
libraries and packages Libraries and packages
14. Understand structural design Structural design elements with example T1: 6.1-6.2
elements
15. Understand dataflow design elements Data flow design elements with example T1: 6.1-6.2
16. Understand behavioural design Behavioral design elements with example T1: 6.3
elements
17. Understand time dimension, Time dimension and simulation synthesis T1: 6.3
simulation and synthesis
18. Design and implementation of 74x139 Decoder and VHDL model T1: 5.4.3
decoder
19. Design and implementation of 74x138 Decoder and VHDL model T1: 5.4.4
decoder
20. Design and implementation of 74x148 encoders and VHDL model T1: 5.5.2
encoder
21. Design and implementation of three Three state devices and VHDL model T1: 5.6
state devices
22. Design and implementation of Multiplexers and VHDL model T1: 5.7
multiplexers
23. Design and implementation of Multiplexers and VHDL model T1: 5.7
multiplexer
24. Design and implementation of Demultiplexers and VHDL model T1: 5.7
demultiplexer
25. Design and implementation of code Code Converters and VHDL model T1: 5.7
converters
26. Design and implementation of parity EX-OR gates and parity circuits, comparators T1: 5.8, 5.9
circuits and comparators and VHDL model
27. Design and implementation of adders HA, FA adders and FA using HA and VHDL T1:5.10
model
28. Design and implementation of CLA CLA adder and VHDL model T1: 5.10
adder
29. Design and implementation of Subtractors, FS using FA and VHDL model, T1: 5.10
subtractors ALUs and VHDL model
30. Design and implementation of Combinational multipliers T1: 5.11
multiplier
31. Design and implementation of Combinational multipliers VHDL model T1: 5.11
multiplier
32. Design and implementation of barrel Barrel shifter T1: 6.1.1
shifter
33. Design and implementation of barrel Barrel shifter VHDL model T1: 5.1.2
shifter
34. Design and implementation of Comparators, floating-point encoder and T1: 5.1.3
comparators, encoders VHDL model
35. Design and implementation of dula Dual parity encoder and VHDL model T1: 5.13
parity encoder
36. Design and implementation of Latches & flip-flops and VHDL model T1: 7.2
latches and flipflops
37. Realize Flip flops from latches Realization of Lathes and Flip Flops, PLD and T1: 7.2
VHDL model
38. Design and implementation of Synchronous counters and VHDL model T1: 8.4
counters
39. Design and implementation of Asynchronous counters and VHDL model T1: 8.4
counters
40. Design and implementation of Shift register and VHDL model T1:8.5
registers
41. Understand synchrounous design Synchronous design methodology. T1:8.7-8.8
methodology Impediments to synchronous design
42. Understand ROMs structure ROMs Internal structure T1:8.6
43. Understand 2D decoding mechanism 2D-decoding ROMs, Commercial types, T1: 8.2
in RAMs timing and applications R5: 4.4
44. Understand static RAM internal Static RAM internal structure, T1: 8.2
structure R5: 4.4
45. Understand SRAM timing diagram SRAM timing Standard SRAMS, synchronous T1: 8.9
SRAMS R6: 4.5
46. Understand DRAM internal structure Dynamic RAM internal structure T1: 8.12-8.13
47. Understand DRAM timing diagram DRAM timing T1: 10.6
48. Familiar about Cypress devices Synchronous DRAMs Familiarity with T1: 10.4
Component Data Sheets –Cypress CY6116,
CY7C1006, Specifications