®

CA3160, CA3160A

Data Sheet October 2002 FN976.4

4MHz, BiMOS Operational Amplifier with Features

MOSFET Input/CMOS Output • MOSFET Input Stage Provides:
The CA3160A and CA3160 are integrated circuit operational - Very High ZI = 1.5TΩ (1.5 x 1012Ω) (Typ)
amplifiers that combine the advantage of both CMOS and - Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation
bipolar transistors on a monolithic chip. The CA3160 series are . . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation
frequency compensated versions of the popular CA3130 • Common-Mode Input Voltage Range Includes
series. Negative Supply Rail; Input Terminals Can Be Swung
Gate protected P-Channel MOSFET (PMOS) transistors are 0.5V Below Negative Supply Rail
used in the input circuit to provide very high input • CMOS Output Stage Permits Signal Swing to Either (or
impedance, very low input current, and exceptional speed Both) Supply Rails
performance. The use of PMOS field effect transistors in the
input stage results in common-mode input voltage capability Applications
down to 0.5V below the negative supply terminal, an • Ground Referenced Single Supply Amplifiers
important attribute in single supply applications.
• Fast Sample Hold Amplifiers
A complementary symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10mV of • Long Duration Timers/Monostables
either supply voltage terminal (at very high values of load • High Input Impedance Wideband Amplifiers
impedance), is employed as the output circuit.
• Voltage Followers (e.g., Follower for Single Supply
The CA3160 Series circuits operate at supply voltages D/A Converter)
ranging from 5V to 16V, or ±2.5V to ±8V when using split • Wien-Bridge Oscillators
supplies, and have terminals for adjustment of offset voltage
for applications requiring offset null capability. Terminal • Voltage Controlled Oscillators
provisions are also made to permit strobing of the output • Photo Diode Sensor Amplifiers
stage.

The CA3160A offers superior input characteristics over

Pinout
those of the CA3160. CA3160
(PDIP)
TOP VIEW
Ordering Information
TEMP. PKG. OFFSET NULL 1 8 STROBE
PART NUMBER RANGE (oC) PACKAGE NO.
INV.
2 - 7 V+
INPUT
CA3160AE -55 to 125 8 Ld PDIP E8.3
NON-INV. +
3 6 OUTPUT
INPUT
CA3160E -55 to 125 8 Ld PDIP E8.3
V- 4 5 OFFSET NULL

NOTE: CA3160 Series devices have an on-chip frequency

compensation network. Supplementary phase compensation or
frequency roll-off (if desired) can be connected externally between
Terminals 1 and 8.

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
 CA3160, CA3160A

Absolute Maximum Ratings Thermal Information

Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . .+16V Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .8V PDIP Package . . . . . . . . . . . . . . . . . . . 115 N/A
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Output Short Circuit Duration (Note 2). . . . . . . . . . . . . . . . Indefinite Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Short Circuit may be applied to ground or to either supply.

Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

CA3160 CA3160A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Input Offset Voltage |VIO| VS = ±7.5V - 6 15 - 2 5 mV

Input Offset Current |IIO| VS = ±7.5V - 0.5 30 - 0.5 20 pA

Input Current II VS = ±7.5V - 5 50 - 5 30 pA

Large-Signal Voltage Gain AOL VO = 10VP-P , RL = 2kΩ 50 320 - 50 320 - kV/V

94 110 - 94 110 - dB

Common-Mode Rejection Ratio CMRR 70 90 - 80 95 - dB

Common-Mode Input-Voltage Range VlCR 0 -0.5 to 12 10 0 -0.5 to 12 10 V

Power-Supply Rejection Ratio PSRR ∆VIO/∆VS, VS = ±7.5V - 32 320 - 32 150 µV/V

Maximum Output Voltage VOM+ RL = 2kΩ 12 13.3 - 12 13.3 - V

VOM- - 0.002 0.01 - 0.002 0.01 V

VOM+ RL = ∞ 14.99 15 - 14.99 15 - V

VOM- - 0 0.01 - 0 0.01 V

Maximum Output Current IOM+ VO = 0V (Source) 12 22 45 12 22 45 mA

IOM- VO = 15V (Sink) 12 20 45 12 20 45 mA

Supply Current (Note 3) I+ VO = 7.5V, R L = ∞ - 10 15 - 10 15 mA

VO = 0V, R L = ∞ - 2 3 - 2 3 mA

Input Offset Voltage Temperature Drift ∆VIO/∆T - 8 - - 6 - µV/oC

Electrical Specifications For Design Guidance, VSUPPLY = ±7.5V, TA = 25oC, Unless Otherwise Specified

CA3160 CA3160A
PARAMETER SYMBOL TEST CONDITIONS TYP TYP UNITS
Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or ±22 ±22 mV
Terminals 4 and 1
Input Resistance RI 1.5 1.5 TΩ
Input Capacitance CI f = 1MHz 4.3 4.3 pF
Equivalent Input Noise Voltage eN BW = 0.2MHz RS = 1MΩ 40 40 µV
RS = 10MΩ 50 50 µV
Equivalent Input Noise Voltage eN RS = 100Ω 1kHz 72 72 nV/√Hz
10kHz 30 30 nV/√Hz

2
 CA3160, CA3160A

Electrical Specifications For Design Guidance, VSUPPLY = ±7.5V, TA = 25oC, Unless Otherwise Specified (Continued)

CA3160 CA3160A
PARAMETER SYMBOL TEST CONDITIONS TYP TYP UNITS
Unity Gain Crossover Frequency fT 4 4 MHz
Slew Rate SR 10 10 V/µs
Transient Response Rise and Fall Time tr CL = 25pF, RL = 2kΩ, (Voltage Follower) 0.09 0.09 µs
Overshoot OS 10 10 %
Settling Time tS CL = 25pF, RL = 2kΩ, (Voltage Follower) 1.8 1.8 µs
To <0.1%, VIN = 4VP-P

Electrical Specifications For Design Guidance, V+ = +5V, V- = 0V, TA = 25oC, Unless Otherwise Specified

CA3160 CA3160A

PARAMETER SYMBOL TEST CONDITIONS TYP TYP UNITS

Input Offset Voltage VIO 6 2 mV

Input Offset Current IIO 0.1 0.1 pA

Input Current Il 2 2 pA

Common-Mode Rejection Ratio CMRR 80 90 dB

Large Signal Voltage Gain AOL VO = 4VP-P , RL = 5kΩ 100 100 kV/V

100 100 dB

Common-Mode Input Voltage Range VlCR 0 to 2.8 0 to 2.8 V

Supply Current I+ VO = 5V, RL = ∞ 300 300 µA

VO = 2.5V, RL = ∞ 500 500 µA

Power Supply Rejection Ratio PSRR ∆VIO/∆V+ 200 200 µV/V

NOTE:
3. ICC typically increases by 1.5mA/MHz during operation.

Block Diagram

7 V+
8mA
200µA 1.35mA 200µA (NOTE 4) NOTES:
0mA 4. Total supply voltage (for indicated voltage
(NOTE 5)
BIAS CKT. gains) = 15V with input terminals biased so
that Terminal 6 potential is +7.5V above
Terminal 4.
5. Total supply voltage (for indicated voltage
gains) = 15V with output terminal driven to
+ either supply rail.
3 OUTPUT
AV ≈
INPUT AV ≈ 5X AV ≈ 30X 6
6000X
2
-

4 V-

CC
5 1 8 STROBE
COMPENSATION
OFFSET (WHEN DESIRED)
NULL

3
 CA3160, CA3160A

Schematic Diagram
BIAS CURRENT CURRENT SOURCE “CURRENT SOURCE 7 V+
FOR Q6 AND Q7 LOAD” FOR Q11

Q1 Q2 Q3

D1
Z1 Q4 Q5
D2
8.3V
D3
R1 D4
40kΩ

R2
5kΩ

INPUT STAGE SECOND

D5 D7 STAGE
D6
NON-INV.
INPUT OUTPUT
STAGE Q8
3
+ Q6 Q7
2kΩ OUTPUT
2
- 30
6
INV. INPUT R3 R4 pF
1kΩ 1kΩ

Q11 Q12
Q9 Q10

R5 R6
1kΩ 1kΩ

5 1 SUPPLEMENTARY 8 4
OFFSET NULL COMP IF DESIRED STROBING

NOTE: Diodes D5 Through D7 Provide Gate Oxide Protection For MOSFET Input Stage.

Application Information
Circuit Description
Refer to the Block Diagram of the CA3160 series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3160 series circuits are
ideal for single supply operation. Three class A amplifier
stages, having the individual gain capability and current
consumption shown in the Block Diagram provide the total
gain of the CA3160. A biasing circuit provides two potentials
for common use in the first and second stages. Terminals 8
and 1 can be used to supplement the internal phase
compensation network if additional phase compensation or
frequency roll-off is desired. Terminals 8 and 4 can also be
used to strobe the output stage into a low quiescent current
state. When Terminal 8 is tied to the negative supply rail
(Terminal 4) by mechanical or electrical means, the output
potential at Terminal 6 essentially rises to the positive supply-
rail potential at Terminal 7. This condition of essentially zero
current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load
resistance presented to the amplifier is very high (e.g., when
the amplifier output is used to drive MOS digital circuits in
comparator applications).
Input Stage - The circuit of the CA3160 is shown in the
Schematic Diagram. It consists of a differential-input stage
using PMOS field-effect transistors (Q6, Q7) working into a
mirror-pair of bipolar transistors (Q9, Q10) functioning as load
resistors together with resistors R3 through R6. The mirror-
pair transistors also function as a differential-to-single-ended
converter to provide base drive to the second-stage bipolar
transistor (Q11). Offset nulling, when desired, can be effected
by connecting a 100,000Ω potentiometer across Terminals 1
and 5 and the potentiometer slider arm to Terminal 4.
Cascode-connected PMOS transistors Q2, Q4, are the
constant-current source for the input stage. The biasing circuit
for the constant-current source is subsequently described.
The small diodes D5 through D7 provide gate-oxide protection
against high-voltage transients, including static electricity
during handling for Q6 and Q7.
Second-Stage - Most of the voltage gain in the CA3160 is
provided by the second amplifier stage, consisting of bipolar

4
 CA3160, CA3160A
transistor Q11 and its cascode-connected load resistance
provided by PMOS transistors Q3 and Q5. The source of bias
potentials for these PMOS transistors is described later. Miller
Effect compensation (roll off) is accomplished by means of the
30pF capacitor and 2kΩ resistor connected between the base
and collector of transistor Q11. These internal components
provide sufficient compensation for unity gain operation in
most applications. However, additional compensation, if
desired, may be used between Terminals 1 and 8.
Bias-Source Circuit - At total supply voltages, somewhat
above 8.3V, resistor R2 and zener diode Z1 serve to establish a
voltage of 8.3V across the series-connected circuit, consisting
of resistor R1, diodes D1 through D4, and PMOS transistor Q1.
A tap at the junction of resistor R1 and diode D4 provides a
gate-bias potential of about 4.5V for PMOS transistors Q4 and
Q5 with respect to Terminal 7. A potential of about 2.2V is
developed across diode-connected PMOS transistor Q1 with
respect to Terminal 7 to provide gate bias for PMOS transistors
Q2 and Q3. It should be noted that Q1 is “mirror-connected” to
both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to
be identical, the approximately 200µA current in Q1 establishes
a similar current in Q2 and Q3 as constant-current sources for
both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener diode
Z1 becomes nonconductive and the potential, developed
across series-connected R1, D1 - D4, and Q1, varies directly
with variations in supply voltage. Consequently, the gate bias
for Q4, Q5 and Q2, Q3 varies in accordance with supply-
voltage variations. This variation results in deterioration of the
power-supply-rejection ratio (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about
4.5V results in seriously degraded performance.
Output Stage - The output stage consists of a drain-loaded
inverting amplifier using CMOS transistors operating in the
Class A mode. When operating into very high resistance loads,
the output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain is
dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 17. Typical op amp
loads are readily driven by the output stage. Because large-
signal excursions are non-linear, requiring feedback for good
waveform reproduction, transient delays may be encountered.
As a voltage follower, the amplifier can achieve 0.01%
accuracy levels, including the negative supply rail.
Offset Nulling
Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer's total range.
5
Input Current Variation with Common Mode Input
Voltage
As shown in the Electrical Specifications, the input current for
the CA3160 Series Op Amps is typically 5pA at TA = 25oC
when Terminals 2 and 3 are at a common-mode potential of
+7.5V with respect to negative supply Terminal 4. Figure 23
contains data showing the variation of input current as a
function of common-mode input voltage at TA = 25oC. These
data show that circuit designers can advantageously exploit
these characteristics to design circuits which typically require
an input current of less than 1pA, provided the common-mode
input voltage does not exceed 2V. As previously noted, the
input current is essentially the result of the leakage current
through the gate-protection diodes in the input circuit and,
therefore, a function of the applied voltage. Although the finite
resistance of the glass terminal-to-case insulator of the metal
can package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate-
protection network functions as if it is connected to Terminal 4
potential, and the metal can case of the CA3160 is also
internally tied to Terminal 4, input Terminal 3 is essentially
“guarded” from spurious leakage currents.
Input-Current Variation with Temperature
The input current of the CA3160 Series circuits is typically 5pA
at 25oC. The major portion of this input current is due to
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor junction device, including op
amps with a junction-FET input stage, the leakage current
approximately doubles for every 10oC increase in temperature.
Figure 24 provides data on the typical variation of input bias
current as a function of temperature in the CA3160.
In applications requiring the lowest practical input current and
incremental increases in current because of “warm-up” effects,
it is suggested that an appropriate heat sink be used with the
CA3160. In addition, when “sinking” or “sourcing” significant
output current the chip temperature increases, causing an
increase in the input current. In such cases, heat-sinking can
also very markedly reduce and stabilize input current variations.
Input Offset Voltage (VIO) Variation with DC Bias
vs Device Operating Life
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magnitude
of the change is increased at high temperatures. Users of the
CA3160 should be alert to the possible impacts of this effect if
the application of the device involves extended operation at
high temperatures with a significant differential DC bias voltage
applied across Terminals 2 and 3. Figure 25 shows typical data
pertinent to shifts in offset voltage encountered with CA3160
devices in metal can packages during life testing. At lower
temperatures (metal can and plastic) for example at 85oC, this
change in voltage is considerably less. In typical linear
applications where the differential voltage is small and
symmetrical, these incremental changes are of about the same
 CA3160, CA3160A

magnitude as those encountered in an operational amplifier
employing a bipolar transistor input stage. The 2V differential
voltage example represents conditions when the amplifier
output state is “toggled”, e.g., as in comparator applications.
Power Supply Considerations
Because the CA3160 is very useful in single supply
applications, it is pertinent to review some considerations
relating to power supply current consumption under both
single and dual supply service. Figures 1A and 1B show the
CA3160 connected for both dual and single supply operation.
Dual-supply operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q8 and Q12 are driven
increasingly positive with respect to ground, current flow
through Q12 (from the negative supply) to the load is
increased and current flow through Q8 (from the positive
supply) decreases correspondingly. When the gate terminals
of Q8 and Q12 are driven increasingly negative with respect
to ground, current flow through Q8 is increased and current
flow through Q12 is decreased accordingly.
voltages. Figure 17 shows the voltage transfer characteristics
of the output stage for several values of load resistance.
Wideband Noise
From the standpoint of low-noise performance considerations,
the use of the CA3160 is most advantageous in applications
where in the source resistance of the input signal is on the
order of 1MΩ or more. In this case, the total input-referred
noise voltage is typically only 40µV when the test circuit
amplifier of Figure 2 is operated at a total supply voltage of
15V. This value of total input-referred noise remains
essentially constant, even though the value of source
resistance is raised by an order of magnitude. This
characteristic is due to the fact that reactance of the input
capacitance becomes a significant factor in shunting the
source resistance. It should be noted, however, that for values
of source resistance very much greater than 1MΩ, the total
noise voltage generated can be dominated by the thermal
noise contributions of both the feedback and source resistors.

Single supply operation: Initially, let it be assumed that the 7 V+

3 +
value of RL is very high (or disconnected), and that the input- Q8
terminal bias (Terminals 2 and 3) is such that the output
CA3160
terminal (No. 6) voltage is at V+/2, i.e., the voltage-drops OUTPUT
Q12 6
across Q8 and Q12 are of equal magnitude. Figure 18 shows STAGE
typical quiescent supply-current vs supply voltage for the
RL
CA3160 operated under these conditions.
2 - 4
Since the output stage is operating as a Class A amplifier, the
V- NEGATIVE
supply current will remain constant under dynamic operating 8 SUPPLY
conditions as long as the transistors are operated in the linear
FIGURE 1A. DUAL POWER SUPPLY OPERATION
portion of their voltage-transfer characteristics (see Figure 17).
If either Q8 or Q12 are swung out of their linear regions toward
cutoff (a non-linear region), there will be a corresponding
reduction in supply-current. In the extreme case, e.g., with
V+
Terminal 8 swung down to ground potential (or tied to ground),
NMOS transistor Q12 is completely cut off and the supply 7
3 +
current to series connected transistors Q8, Q12 goes Q8
essentially to zero. The two preceding stages in the CA3160, CA3160
however, continue to draw modest supply-current (see the OUTPUT
6
Q12 STAGE
lower curve in Figure 18) even though the output stage is
strobed off. Figure 1A shows a dual-supply arrangement for the RL
output stage that can also be strobed off, assuming RL = ∞, by 2 - 4
pulling the potential of Terminal 8 down to that of Terminal 4.

Let it now-be assumed that a load resistance of nominal value 8

(e.g., 2kΩ) is connected between Terminal 6 and ground in the

FIGURE 1B. SINGLE POWER SUPPLY OPERATION
circuit of Figure 1B. Let it further be assumed again that the
FIGURE 1. CA3160 OUTPUT STAGE IN DUAL AND SINGLE
input-terminal bias (Terminals 2 and 3) is such that the output
POWER SUPPLY OPERATION
terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q8
must now supply quiescent current to both RL and transistor
Q12, it should be apparent that under these conditions the
supply current must increase as an inverse function of the RL
magnitude. Figure 20 shows the voltage-drop across PMOS
transistor Q8 as a function of load current at several supply

6
 CA3160, CA3160A

+7.5V

0.01µF
RS
7
3 +
1MΩ NOISE
CA3160 6 VOLTAGE
OUTPUT
2 - 4
30.1kΩ
0.01
µF
-7.5V

BW (3dB) = 200kHz 1kΩ

TOTAL NOISE VOLTAGE
(INPUT REFERRED = 40µV (TYP)

FIGURE 2. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR

WIDEBAND NOISE MEASUREMENTS

Typical Performance Curves

+7.5V

0.01µF
7
3 +
10kΩ
CA3160 6

2 - 4
2kΩ
0.01
µF
-7.5V
25pF
2kΩ
SIMULATED
LOAD
BW (-3dB) = 4MHz CAPACITANCE
SR = 10V/µs 0.1µF

FIGURE 3A.

Top Trace: Output Signal

Top Trace: Output
Center Trace: Difference Signal 5mV/Div.
Bottom Trace: Input
Bottom Trace: Input Signal
FIGURE 3B. SMALL SIGNAL RESPONSE FIGURE 3C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME
FIGURE 3. DUAL SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS

7
 CA3160, CA3160A

Typical Applications +15V

Voltage Followers
0.01µF
Operational amplifiers with very high input resistances, like 7
3
the CA3160, are particularly suited to service as voltage +
10kΩ
followers. Figure 3 shows the circuit of a classical voltage CA3160 6

follower, together with pertinent waveforms using the CA3160 2 - 4

in a split-supply configuration. 5
1
A voltage follower, operated from a single supply, is shown in
Figure 4 together with related waveforms. This follower circuit OFFSET
ADJUST
is linear over a wide dynamic range, as illustrated by the
reproduction of the output waveform in Figure 4B with input-
2kΩ
signal ramping. The waveforms in Figure 4C show that the
follower does not lose its input-to-output phase-sense, even BW (-3dB) = 4MHz
SR = 10V/µs 0.1µF
though the input is being swung 7.5V below ground potential.
This unique characteristic is an important attribute in both FIGURE 4A.
operational amplifier and comparator applications. Figure 4C
also shows the manner in which the COS/MOS output stage
permits the output signal to swing down to the negative
supply-rail potential (i.e., ground in the case shown). The
digital-to-analog converter (DAC) circuit, described in the
following section, illustrates the practical use of the CA3160 in
a single supply voltage follower application.

9-Bit CMOS DAC

A typical circuit of a 9-bit Digital-to-Analog Converter (DAC) (see
Note 6) is shown in Figure 5. This system combines the concepts
of multiple-switch CMOS lCs, a low-cost ladder network of
discrete metal-oxide-film resistors, a CA3160 op amp connected
as a follower, and an inexpensive monolithic regulator in a simple
single power-supply arrangement. An additional feature of the
Top Trace: Output
DAC is that it is readily interfaced with CMOS input logic, e.g.,
Bottom Trace: Input
10V logic levels are used in the circuit of Figure 5.
The circuit uses an R/2R voltage-ladder network, with the output- FIGURE 4B. OUTPUT WAVEFORM WITH GROUND REFERENCE
potential obtained directly by terminating the ladder arms at SINE WAVE INPUT
either the positive or the negative power supply terminal. Each
CD4007A contains three inverters, each inverter functioning as a
single-pole double-throw switch to terminate an arm of the R/2R
network at either the positive or negative power-supply terminal.
The resistor ladder is an assembly of 1% tolerance metal-oxide
film resistors. The five arms requiring the highest accuracy are
assembled with series and parallel combinations of 806,000Ω
resistors from the same manufacturing lot.
A single 15V supply provides a positive bus for the CA3160
follower amplifier and feeds the CA3085 voltage regulator. A
“scale-adjust” function is provided by the regulator output control,
set to a nominal 10V level in this system. The line-voltage
regulation (approximately 0.2%) permits a 9-bit accuracy to be
maintained with variations of several volts in the supply. The
flexibility afforded by the CMOS building blocks simplifies the
design of DAC systems tailored to particular needs. FIGURE 4C. OUTPUT SIGNAL WITH INPUT SIGNAL RAMPING
NOTE:
FIGURE 4. SINGLE SUPPLY VOLTAGE FOLLOWER WITH
6. “Digital-to-Analog Conversion Using the Intersil CD4007A
ASSOCIATED WAVEFORMS. (E.G., FOR USE IN
COS/MOS lC”, Application Note AN6080.
SINGLE SUPPLY D/A CONVERTER; SEE
FIGURE 9 IN AN6080)

8
 CA3160, CA3160A

10V LOGIC INPUTS

+10.010V
14
LSB MSB
9 8 7 11 6 5 4 3 2 1
6 3 10 6 3 10 6 3 10
2
CD4007A CD4007A CD4007A
“SWITCHES” “SWITCHES” “SWITCHES”

9 13 1 12 13 1 12 13 1 12
806K
7 8 5 8 5 8 5
1% (2) (4) (8)
4 806K 402K 200K 100K 806K 806K
1% 1% 1% 1% 1% 1% 806K 806K 806K
1% 1% 1%

806K 750K +15V

806K 10K
1% 1% 1%
PARALLELED 7
RESISTORS
REQUIRED OUTPUT + 3
VOLTAGE
REGULATOR CA3160 VOLTAGE
62 BIT RATIO-MATCH 6 FOLLOWER
+15V
1 Standard 4 - 2
2 1 +10.010V
2 ±0.1% 5
CA3085 8 LOAD 1
3 ±0.2%
3 6 22.1K 100K
7 1% 4 ±0.4% OFFSET
4 NULL
5 ±0.8% 2K
+ 2µF 1K REGULATED
VOLTAGE
- 25V 0.001µF ADJUST 6-9 ±1% ABS. 0.1µF
3.83K
1%

FIGURE 5. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3160

Error-Amplifier in Regulated Power Supplies
The CA3160 is an ideal choice for error-amplifier service in
regulated power supplies since it can function as an error-
amplifier when the regulated output voltage is required to
approach zero.
The circuit shown in Figure 6 uses a CA3160 as an error
amplifier in a continuously adjustable 1A power supply. One
of the key features of this circuit is its ability to regulate down
to the vicinity of 0V with only one DC power supply input.
An RC network, connected between the base of the output
drive transistor and the input voltage, prevents “turn-on
overshoot”, a condition typical of many operational
amplifier regulator circuits. As the amplifier becomes
operational, this RC network ceases to have any influence
on the regulator performance.
Precision Voltage-Controlled Oscillator
The circuit diagram of a precision voltage-controlled oscillator is
shown in Figure 7. The oscillator operates with a tracking error
in the order of 0.02% and a temperature coefficient of
0.01%/oC. A multivibrator (A1) generates pulses of constant
amplitude (V) and width (T2). Since the output (Terminal 6) of
A1 (a CA3130) can swing within about 10mV of either supply-
rail, the output pulse amplitude (V) is essentially equal to V+.
The average output voltage (EAVG = V T2/T1) is applied to the
non-inverting Input terminal of comparator A2 via an integrating
network R3, C2. Comparator A2 operates to establish circuit
conditions such that EAVG = V1. This circuit condition is
accomplished by feeding an output signal from Terminal 6 of A2
through R4, D4 to the inverting terminal (Terminal 2) of A1,
thereby adjusting the multivibrator interval, T3.
Voltmeter With High Input Resistance
The voltmeter circuit shown in Figure 8 illustrates an
application in which a number of the CA3160 characteristics
are exploited. Range-switch SW1 is ganged between input
and output circuitry to permit selection of the proper output
voltage for feedback to Terminal 2 via 10kΩ current-limiting
resistor. The circuit is powered by a single 8.4V mercury
battery. With zero input signal, the circuit consumes
somewhat less than 500µA plus the meter current required
to indicate a given voltage. Thus, at full scale input, the total
supply current rises to slightly more than 1500µA.
Function Generator
A function generator having a wide tuning range is shown in
Figure 9. The adjustment range, in excess of 1,000,000/1, is
accomplished by a single potentiometer. Three operational
amplifiers are utilized: a CA3160 as a voltage follower, a
CA3080 as a high speed comparator, and a second
CA3080A as a programmable current source. Three variable
capacitors C1, C2, and C3 shape the triangular signal
between 500kHz and 1MHz. Capacitors C4, C5, and the
trimmer potentiometer in series with C5 maintain essentially
constant (+10%) amplitude up to 1MHz.

9
 CA3160, CA3160A

2N6385
3 POWER DARLINGTON SHORT-CIRCUIT CURRENT
40V INPUT LIMIT ADJUSTMENT
+ 2 1Ω

10kΩ OUTPUT
0.2µF 0V TO 35V
TURN AT 1A
2.4kΩ ON
1W 1kΩ
DELAY

100kΩ 1.5kΩ 1 2N2102

1W 1kΩ
+
1N914 56pF 43kΩ 100µF
-
2.2kΩ 8
+ 7 10kΩ
100µF + 5µF
25V 2kΩ + 3
-
CA3086 - 6 CA3160
10 11 2 1
2N2102 - 2
5
1
9 3 8.2kΩ
8 7 5 12 14 10kΩ 4

6 4 13 4.7kΩ

1kΩ
50kΩ 100kΩ

62kΩ 0.01µF
- -

Hum and Noise Output <250µVRMS; Regulation (No Load to Full Load) <0.005%; Input Regulation <0.01%/V

FIGURE 6. VOLTAGE REGULATOR CIRCUIT (0.1V TO 35V AT 1A)

T2 T3
VCO CONTROL VOLTAGE (VI)
V (0V - 10V)
fO
(SENSITIVITY = 1kHz/V)
+15V T1
D1
10K
1M
0.01µF
+15V
R5 100K +15V
100K D2
0.1
7 µF 2 7
3 + -
R6 MULTI- EAVG = V T2/T1
C1 VIBRATOR 6 COMPARATOR 6
100K 500pF CA3130 R3 CA3160
2 - 1M +
4 3 4
5
C2 1 0.01µF
D3 0.01µF R7
100K
R1 R2 D5
D4 182K 10K R4

D1 - D5 = 1N914 3K

FIGURE 7. VOLTAGE CONTROLLED OSCILLATOR

10
 CA3160, CA3160A

BATTERY
TEST
300V 300V OFF ON
100MΩ
100V 100V
3 POSITION
30V 30V SLIDE SWITCH
1.02 9.9kΩ +
10V 10V 500
MΩ µF
-
M
+9V BATTERY
BATTERY 0-1mA
SW1A 3V SW1B
3V 7 3V CAL.
3 500Ω
+ 2.7kΩ
INPUT 1V 1V 22MΩ 300V
0.001µF CA3160 6
300V 300V 100V
2 - 300V
100V 100V
4 820Ω 200Ω
100V 30V
5
30V 30V 1 30V 10V
1V CAL.
10V 10V 3V
10V SW1D
100kΩ SW1C 3V 1V

1V 300mV
ZERO
ADJUST 9kΩ
9.1kΩ 100mV
300mV
100mV 30mV
900Ω
10kΩ 10mV
30mV

10mV 100Ω

FIGURE 8. HIGH INPUT RESISTANCE DC VOLTMETER

20pF

8.2kΩ CENTERING THRESHOLD

BUFFER 100kΩ DETECTOR
VOLTAGE FOLLOWER +7.5V
+7.5V -7.5V +7.5V
VOLTAGE-CONTROLLED 0.9 - 7pF +7.5V
C1 430pF 30kΩ
CURRENT SOURCE
HIGH
7 FREQ.
SHAPE 0.1µF 6.8MΩ
7
3 + 5
6.2kΩ
1kΩ CA3080A 6 3 + 7
10kΩ
2 - 10-80pF
4 - 60pF CA3160 6 2 -
4 C3
1kΩ
5 C2 2 - CA3080 6
2MΩ +
-7.5V 3
4
-7.5V
SYMMETRY 4.7kΩ EXTERNAL
SWEEPING INPUT 10kΩ
-7.5V 100kΩ +7.5V 0.1µF

-7.5V
C4 50kΩ 2-1N914
4 - 60pF
MAX FREQ
SET MIN FREQ.SET 2kΩ
C5
+7.5V -7.5V HIGH FREQ 15 - 115pF
10kΩ 6.2kΩ 500Ω 500Ω LEVEL
FREQ ADJUST
ADJUST

FIGURE 9A. 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR: 1Hz to 1MHz

11
 CA3160, CA3160A

NOTE: A square wave signal modulates the external sweeping input to NOTE: The bottom trace is the sweeping signal and the top trace is the
produce 1Hz and 1MHz, showing the 1,000,000/1 frequency range of actual generator output. The center trace displays the 1MHz signal via
the Function Generator. delayed oscilloscope triggering of the upper swept output signal.

FIGURE 9B. TWO-TONE OUTPUT SIGNAL FROM THE FUNCTION FIGURE 9C. TRIPLE-TRACE OF THE FUNCTION GENERATOR
GENERATOR SWEEPING TO 1MHz

FIGURE 9. 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR: 1Hz to 1MHz

5.1kΩ 1N914

+15V 470pF
STAIRCASE
+15V OUTPUT
100 100
kΩ kΩ 1MΩ +15V +15V
7 STEP HEIGHT
ADJUST
4 - 60pF 7
3 +
8.2kΩ 7
100 6
kΩ CA3130 2 - 10kΩ
2 - CA3160 6 3 +
8 1N914
+15V CA3130 6
15 - 115pF 3 + 2kΩ
FREQ
ADJUST
4
4
2 - 8
1.5
MΩ 4

MULTIVIBRATOR CHARGE INTEGRATOR

COMMUTATING HYSTERESIS SWITCH
NETWORK

51kΩ
MULTIVIBRATOR RETRACE INHIBIT +15mV TO +10V

100kΩ

FIGURE 10A. STAIRCASE GENERATOR CIRCUIT

12
 CA3160, CA3160A

Terminals 2 and 4 of the CA3160 at ground potential, the

CA3160 input is operated in the “guarded mode”. Under this
operating condition, even slight leakage resistance present
between Terminals 3 and 2 or between Terminals 3 and 4
STAIRCASE would result in zero voltage across this leakage resistance,
OUTPUT
2V STEPS
thus substantially reducing the leakage current.

If the CA3160 is operated with the same voltage on input

Terminals 3 and 2 as on Terminal 4, a further reduction in
the input current to the less than one picoampere level can
COMPARATOR
be achieved as shown in Figure 23.
OSCILLATOR
To further enhance the stability of this circuit, the CA3160
can be operated with its output (Terminal 6) near ground,
Top Trace: Staircase Output 2V Steps thus markedly reducing the dissipation by reducing the
Center Trace: Comparator supply current to the device.
Bottom Trace: Oscillator
FIGURE 10B. STAIRCASE GENERATOR WAVEFORM The CA3140 stage serves as a X100 gain stage to provide
FIGURE 10. STAIRCASE GENERATOR CIRCUIT
the required plus and minus output swing for the meter and
feedback network. A 100-to-1 voltage divider network
Staircase Generator consisting of a 9.9kΩ resistor in series with a 100Ω resistor
Figure 10 shows a staircase generator circuit utilizing three sets the voltage at the 10GΩ resistor (in series with Terminal
CMOS operational amplifiers. Two CA3130s are used; one 3) to ±30mV full-scale deflection. This 30mV signal results
as a multivibrator, the other as a hysteresis switch. The third from ±3V appearing at the top of the voltage divider network
amplifier, a CA3160, is used as a linear staircase generator. which also drives the meter circuitry.

Picoammeter Circuit By utilizing a switching technique in the meter circuit and in

the 9.9kΩ and 100Ω network similar to that used in voltmeter
Figure 11 is a current-to-voltage converter configuration
circuit shown in Figure 8, a current range of 3pA to 1nA full
utilizing a CA3160 and CA3140 to provide a picoampere
scale can be handled with the single 10GΩ resistor.
meter for 13pA full scale meter deflection. By placing

10GΩ
+15V
1MΩ
10pF
0.1µF +15V
10MΩ 7
3 + 7
CA3160 6 2 -
2 10kΩ
- CA3140 6
4
5 3 +
1 9.9kΩ 5.6kΩ
560kΩ 4
100kΩ 0.1µF
500Ω
9.1kΩ 100Ω
M 500-0-500µA
-15V -15V

FIGURE 11. CURRENT-TO-VOLTAGE CONVERTER TO PROVIDE A PICOAMMETER WITH ±3pA FULL SCALE DEFLECTION

13
 CA3160, CA3160A

+15V 100kΩ +15V

2200pF

30pF
+15V
0.1µF 0.1µF
7
1MΩ 39kΩ 8.2Ω
3 + 0.1µF
CA3160 6 2 7
- 7
2 - 1N914
8 CA3080A 6 2 -
4
5 3 + CA3140 6
1 1MΩ
4 100kΩ
3 +
100kΩ 0.1µF 5 4
8.2kΩ DROOP 0.1µF
OFFSET 9.1kΩ 27kΩ ZERO 39kΩ
VOLTAGE ADJUST
ADJUST 500µA

STROBE INPUT
SAMPLE = 15V
2kΩ HOLD = 0V

FIGURE 12A. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V

SAMPLED
OUTPUT SAMPLED
OUTPUT
0V-

INPUT INPUT 0V-

SIGNAL

SAMPLING SAMPLING
PULSES PULSES

Top Trace: Sampled Output Top Trace: Sampled Output

Center Trace: Input Signal Center Trace: Input Signal
Bottom Trace: Sampling Pulses Bottom Trace: Sampling Pulses
FIGURE 12B. SAMPLE AND HOLD WAVEFORM FIGURE 12C. SAMPLE AND HOLD WAVEFORM
FIGURE 12. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V

Single Supply Sample-and-Hold System hold mode. Even with 320mV at the amplifier bias circuit
Figure 12 shows a single supply sample-and-hold system terminal (5) at least 1100pA of output current will be
using a CA3160 to provide a high input impedance and an available.
input voltage range of 0V to 10V. The output from the input
Wien Bridge Oscillator
buffer integrator network is coupled to a CA3080A. The
A simple, single supply Wien Bridge oscillator using a
CA3080A functions as a strobeable current source for the
CA3160 is shown in Figure 13. A pair of parallel-connected
CA3140 output integrator and storage capacitor. The
1N914 diodes comprise the gain-setting network which
CA3140 was chosen because of its low output impedance
standardizes the output voltage at approximately 1.1V. The
and constant gain-bandwidth product. Pulse “droop” during
500Ω potentiometer is adjusted so that the oscillator will
the hold interval can be reduced to zero by adjusting the
always start and the oscillation will be maintained.
100kΩ bias-voltage potentiometer on the positive input of
Increasing the amplitude of the voltage may lower the
the CA3140. This zero adjustment sets the CA3080A output
threshold level for starting and for sustaining the oscillation,
voltage at its zero current position. In this sample-and-hold
but will introduce more distortion.
circuit it is essential that the amplifier bias current be
reduced to zero to minimize output signal current during the

14
 CA3160, CA3160A

Operation with Output Stage Power Booster

R3 +15V
The current sourcing and sinking capability of the CA3160
R1 51kΩ
100kΩ
C2 0.1 OUTPUT output stage is easily supplemented to provide power-boost
51pF 7 µF f = 100kHz
2% THD AT 1.1VP-P capability. In the circuit of Figure 14, three CMOS transistor-
3 +
pairs in a single CA3600 lC array are shown parallel-connected
CA3160 6
with the output stage in the CA3160. In the Class A mode of
R2 2 -
CA3600E shown, a typical device consumes 20mA of supply
100kΩ 4
current at 15V operation. This arrangement boosts the current-
2kΩ
C1 handling capability of the CA3160 output stage by about 2.5X.
10-80 2-1N914
pF
The amplifier circuit in Figure 14 employs feedback to
0.01µF
establish a closed-loop gain of 20dB. The typical large-
680Ω signal-bandwidth (-3dB) is 190kHz.
1
f= 500Ω
2 π √(R1 || R2) C1 R3 C2

FIGURE 13. SINGLE SUPPLY WEIN BRIDGE OSCILLATOR

+15V

0.01µF 14 2 11
1MΩ
1µF CA3600
- + QP1 QP2 QP3

680kΩ
3 +
13 1
CA3160 6
INPUT
2 - 500µF
1µF 2kΩ 8 6 3 10 12
50Ω
4 100mW
AT 10%
THD
8 5
A = 20dB
LARGE SIGNAL QN1 QN2 QN3
BW (-3dB) = 190kHz

7 4 9
20kΩ

FIGURE 14. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3160

15
 CA3160, CA3160A

Typical Performance Curves

120 150

OPEN LOOP PHASE (DEGREES)

VS = ±±7.5V 0 RL = 2kΩ
TA = 25oC
OPEN LOOP VOLTAGE GAIN (dB)

OPEN LOOP VOLTAGE GAIN (dB)

100 50 140
100
130
80 φ OL 150
200
120
60
110
40
CL = 30pF 100
RL = 2kΩ
20
90

0 80
101 102 103 104 105 106 107 108 -100 -50 0 50 100
FREQUENCY (Hz) TEMPERATURE (oC)

FIGURE 15. OPEN LOOP VOLTAGE GAIN AND PHASE SHIFT FIGURE 16. OPEN LOOP GAIN vs TEMPERATURE
vs FREQUENCY

15.0
17.5 TA = 25oC
OUTPUT VOLTAGE [TERMS. 4 AND 6] (V)

V+ = 15V, V- = 0V
RL = ∞
QUIESCENT SUPPLY CURRENT (mA)
TA = 25oC
15 12.5 V- = 0
RL = 5kΩ
2kΩ
12.5 10.0
1kΩ BALANCED
500Ω VO = V+/2
10
7.5
7.5
5.0
HIGH VO = V+
5 OR LOW VO = V-
2.5
2.5

0 0
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 6 8 10 12 14 16 18
GATE VOLTAGE [TERMINALS 4 AND 8] (V) POSITIVE SUPPLY VOLTAGE (V)

FIGURE 17. VOLTAGE TRANSFER CHARACTERISTICS OF FIGURE 18. QUIESCENT SUPPLY CURRENT vs SUPPLY
CMOS OUTPUT STAGE VOLTAGE

16
 CA3160, CA3160A

Typical Performance Curves (Continued)

VOLTAGE DROP ACROSS PMOS OUTPUT STAGE

14 50
VO = V+ / 2 V- = 0V V+ = 15V
QUIESCENT SUPPLY CURRENT (mA)

V- = 0 TA = 25oC
12 10 10V
5V
10

TRANSISTOR (Q8) (V)

TA = -55oC 1
8 25oC
125oC
6 0.1

4
0.01
2

0 0.001
0 2 4 6 8 10 12 14 16 18 0.001 0.01 0.1 1 10 100
POSITIVE SUPPLY VOLTAGE (V) MAGNITUDE OF LOAD CURRENT (mA)

FIGURE 19. QUIESCENT SUPPLY CURRENT vs SUPPLY FIGURE 20. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR
VOLTAGE (Q8) vs LOAD CURRENT
VOLTAGE DROP ACROSS NMOS OUTPUT STAGE

1000
50 TA = 25oC
V- = 0V VS = ±7.5V
TA = 25oC V+ = 15V
10
10V
TRANSISTOR (Q12) (V)

5V
100
1
EN (nV/√Hz)

0.1
10

0.01

0.001 1
0.001 0.01 0.1 1 10 100 1 101 102 103 104 105
MAGNITUDE OF LOAD CURRENT (mA) FREQUENCY (Hz)

FIGURE 21. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR FIGURE 22. EQUIVALENT NOISE VOLTAGE vs FREQUENCY
(Q12) vs LOAD CURRENT

17
 CA3160, CA3160A

Typical Performance Curves (Continued)

10 4000
TA = 25oC VS = ±7.5V

1000
7.5
INPUT VOLTAGE (V)

INPUT CURRENT (pA)

V+ 15V
TO
5V 100
5 7
2
PA CA3160 6

3
2.5 10
4 8
VIN
0V
TO
V- -10V
0 1
-1 0 1 2 3 4 5 6 7 -80 -60 -40 -20 0 20 40 60 80 100 120 140
INPUT CURRENT (pA) TEMPERATURE (oC)

FIGURE 23. INPUT CURRENT vs COMMON MODE VOLTAGE FIGURE 24. INPUT CURRENT vs TEMPERATURE

7
DIFFERENTIAL DC VOLTAGE
6 (ACROSS TERMINALS 2 AND 3) = 2V
OFFSET VOLTAGE SHIFT (mV)

OUTPUT STAGE TOGGLED

5
TA = 125oC FOR
METAL CAN PACKAGES
4

2 DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
1 OUTPUT VOLTAGE = V+ / 2

0
0 500 1000 1500 2000 2500 3000 3500 4000
TIME (HOURS)

FIGURE 25. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT vs OPERATING LIFE

18
 CA3160, CA3160A

Dual-In-Line Plastic Packages (PDIP)

N
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C B1 0.045 0.070 1.15 1.77 8, 10
L
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.355 0.400 9.01 10.16 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES: E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between
e 0.100 BSC 2.54 BSC -
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6

3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7
2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated
N 8 8 9
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru- Rev. 0 12/93
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be per-
pendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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19
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