1.

Given the two binary numbers X = 10101M3 and Y = 1000011, perform the subtraction
(a) X - Y and @) Y - X by using 2's complements and 1’s complements.

2. Do the following conversion probIems:

(a) Convert decimal 27.3 15 to binary.
@) Cdcculate the binary equivalent of 2/3 out to eight places.Then convert from binary to decimal.
(c) Convert the binary result in (b) into hexadecimal. Then convert the d to decimal.

3. Repsent the decimal number 5.137 in a) BCD. (b) excess-3 code. c) 2421 code. and d) a
6311 code.

4. Find the complement of the functions F1 = x'yz' + xty'z and 6 = x(y'z’ + yz) By applying
DeMorgm's theroms as many times as necessary.

5. Express the Boolean function F = A + B'C as a sum of mintem.

6. Express the Boolean function F = xy + x'z as a sum of maxterms

7. Convert each of the following expressions into sum of product and product ofsum: -, (a) (A’ + C)(B + C'D)
(b) x' + x(x + y’)(y + z’)

8.Simplify the following boolean function into (a) sum-of-products form and b. product of sums
F(A,B,C,D)= ∑(0,1,2,5,8,9,10)

9. Implement the following Boolean function with NAND gates:

F(X,Y,z) = (1,2,3,4,5,7 )

10. Design the circuit for 3-bit even parity generator and 4-bit even parity checker.

11. Simplify the following Boolean expression using three variable k-map:
(a) F(x,y,z) = xy + x'y'z' + x'yz' (b) F(x,y.z) = x'y' + yz + x'yz'
(c)F(x, y, r) = x'y + yz' + y'z' (d) F(x, y, z) = xyz + x'y'e + xy'z'

12. Simplify the following Boolean expression using four variable k-map (a) w'z + xz + x'y + wx'z
(b) C'D + A'B'C + ABC' + AE'C
(cp AB'C + B'C'D' + BCD + ACD' + A'B'C + A'BC'D
(d) xyz + wy + wxy' + x'y

13.

14. Impkmat tke following four Boolean uxpradons with three half adders -
li ..
D=ABC
E - A'BC + AB'C
F = ABC' + (A' + B')C
G = ABC

15. Construct 4x16 decoder from 3x8 decoder

16. construct 1:8 demux from 2 to 4 decoder

17.construct full subtractor using 1 to 8 demultiplexer

18.Implement Full adder using a decoder

19. Design a four bit priority encoder.

20. Desing 4 to 1 line multiplexer using logic gates.

21.Implement F(A,B,C,D)=∑(1,3,4,11,12,13,14,15) USING 8X1 MUX

22.Implement 4 to 1 mux using 2 to 4 decoder and tri state gates.

23.Draw the logic diagram of a two to four line decoder using (a)NOR gates only and (b) NAND gates only

24. construct 4 to 16 deocder with 2 to 4 line deocders

25.Construct 5 to 32 line decoder using 3 to 8 decoder and 2 to 4 line decoders.

26.Construct a 16x1 Multiplexers using 8x1 and 2x1 multiplexers.

27.Design a combinational circuit to convert from binary to excess 3 code.

28. Write the difference bw combinational and synchronous circuits.

29. Write the difference bw latches and flip flops.

30. Write general block diagrams of mealy and more state machines.

31.Implement JK flip flop using 2to1 multiplexer and D flip flop.

32.Write the circuit diagram of a) PISO b)PIPO

33.Convert D F/F to JK F/F

34.Design a three bit binary counter using T flip flops

35.Write the differences bw ripple counter and synchronous counter

36. Design a mod-5 ripple counter

37. Write the differences bw Asynchronous reset and synchronous reset.

38. Design a Mealy FSM to detect the sequence 1011 and implement using D F/F

39.Explain the FIFO and LIFO concept.

40.Implement 9x1 mux using 2x1

41.Desing moore state machine to detect the sequence 1010.

42. Desing moore state machine to detect the sequence 10101.

43.How race condition is prevented in master slave configuration. Explain.

44. Explain race condition in JK flip flops.

45.An 8x1 multiplexer has inputs A,B and C connected to the selections inputs S2,S1 and S0, respectively. The data
inputs I0 through I7 are as follows
(a) I1=I2-I7=0; I3=I5=I; I0=I4=D; and I6=D’;
(b) I1=I2=0; I3=I7=1; I4=I5=D; and I0=I6=D’;

46. Implement the following equations with a 4 X 1 multiplexer and external gates
(a)F(A,B.C.D) = X(1,3,4,11,12,13,14,15)
(b) f(A.8.C.D) = T(1,2,4,7,8,9,10,11,13,15)

47.Write the block diagram and expressions of the 4 bit carry lookahead adder.

48.Write the block diagram of BCD adder using Binary adder.

49.Design positive edge triggered and negative edge triggered D F/F using multiplexer.

50.Design master slave D F/F using multiplexer.