Frederick University c oe

Computer Engineering Faculty

Freshman Computer Engineering

(ACOE101)

Experiment #2

Logic Gate Input Expansion

Student’s Name:
Semester: Date:

Assessment:

Assessment Point Weight Grade

Methodology and correctness of results
Discussion of results
Participation
Assessment Points’ Grade:

Comments:
ACOE101: Freshman Computer Engineering Experiment # 2

Experiment #2:
Logic Gate Input Expansion

Objectives:
The objectives of this experiment are to:
1. investigate how a logic gate with many inputs can be implemented using gates
with less inputs,
2. examine how to handle unused inputs of logic gates.

Discussion:
The basic logic gates (Figure 1) found in integrated circuits have a limited small
number of inputs, usually two, three or four. In many applications there is a need for
logic gates with more inputs. A number of logic gates can be combined to form a
logic gate with more inputs. Figure 1b shows how a 3-input AND gate can be
implemented using two 2-input AND gates. Figure 1c and 1d show how a 4-input
AND gate can be implemented using three 2-input AND gates. Figure 1f shows how
a 3-input OR gate can be implemented using two 2-input OR gates. Figure 1g and
1h show how a 4-input OR gate can be implemented using three 2-input OR gates.

(i) NOT AND OR EX-OR

A A A
(ii) A X X X X
B B B

(iii) X=A X=AB X=A+B X=A+B

A X A B X A B X A B X
(iv) 0 1 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 1 1 0 1 1
1 0 0 1 0 1 1 0 1
1 1 1 1 1 1 1 1 0

Figure 1: Basic Logic Gates

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ACOE101: Freshman Computer Engineering Experiment # 2

(a) (b) (c) (d)

(e) (f) (g) (h)

Figure 2: Logic Gate Input Expansion

In many applications there are gates available with more inputs that the required
ones. The extra inputs must be connected in such a way not to change the function
of the logic gate. The unused inputs are usually connected directly to logic 1, a logic
0, or to another input of the same gate. Figure 2 shows how the unused inputs of
logic gates can be connected.

+5V

(a) (b) (c) (d)

+5V

(e) (f) (g) (h)

Figure 3: Unused inputs of logic gates

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ACOE101: Freshman Computer Engineering Experiment # 2

Procedure:
Exercise 1:
(a) Place the 7408 and the 7432 ICs on the breadboard and make the connections
shown in figure 4. Turn on the Digital Lab Trainer power.

L7 L6 L5 L4 L3 L2 L1 L0

+5V Gnd

+5V +5V

Gnd Gnd

A B C D E F G H I J K L A B C D E F G H I J K L
1 14 1 14
Vcc

Vcc
1 1
2 13 2 13
2 2
3 12 3 12
3 3

7432
7408

4 11 4 11
4 4
5 10 5 10
5 5
6 9 6 9
6 6
GND

GND
7 8 7 8
7 7

8 8

9 9

1 1 1 1 1 1 1 1

P1 P2 0 0 0 0 0 0 0 0

S7 S6 S5 S4 S3 S2 S1 S0

Figure 4.

(b) Go through all possible states of the switches S7, S6, S5, S4, S3 and S2 and
fill up table 1. Use number 1 to represent the ON state of the LEDs and number
0 to represent the OFF state.

S7 S6 S5 L7 S4 S3 S2 L3
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1

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ACOE101: Freshman Computer Engineering Experiment # 2

1 1 0 1 1 0
1 1 1 1 1 1
(a) (b)

Table 1.
Exercise 2:
(a) Turn off the Digital Lab Trainer power. Place the 7400 and the 7486 ICs on the
breadboard and make the connections shown in Figure 5. Turn on the Digital
Lab Trainer power.

(b) Go through all possible states of the switches S7, S6, S5, S4, S3 and S2 and
fill up table 2. Use number 1 to represent the ON state of the LEDs and number
0 to represent the OFF state.

S7 S6 S5 L7 S4 S3 S2 L3
0 0 0 0 0 0
0 0 1 0 0 1

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ACOE101: Freshman Computer Engineering Experiment # 2

0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1
(a) (b)

Table 2.

L7 L6 L5 L4 L3 L2 L1 L0

+5V Gnd

+5V +5V

Gnd Gnd

A B C D E F G H I J K L A B C D E F G H I J K L
1 14
Vcc

Vcc
1 1
2 13
2 2
3 12
3 3
7486
7400

4 11
4 4
5 10
5 5
6 9
6 6
GND

GND

7 8
7 7

8 8

9 9

1 1 1 1 1 1 1 1

P1 P2 0 0 0 0 0 0 0 0

S7 S6 S5 S4 S3 S2 S1 S0

Figure 5.

Questions
1. Discuss the results of exercise 1 (Table 1)

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ACOE101: Freshman Computer Engineering Experiment # 2

2. Discuss the results of exercise 2 (Table 2)

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