Cisco Router Architecture

601601
1094_06F9_c4
1094_06F9_c1
1094_06F9_c4 © 1999, Cisco
© 1999, Systems,
Cisco Inc. Inc.
Systems, 1 1
Cisco Router Architecture
Session 601
601
1094_06F9_c4 © 1999, Cisco Systems, Inc. 2
Copyright © 1998, Cisco Systems, Inc. All rights reserved. Printed in USA.
Presentation_ID.scr 1
Agenda
• Router Fundamentals
• Layered Switching
• Router Architectures/Switching Paths
• Optimized Network Design
• Troubleshooting
601
Router Fundamentals
601
What Is a Router?
• Routers perform OSPF, EIGRP,BGP

Static Routes, Etc…
two main functions List of Reachable
Networks
• Control path
routines
• Data path control
(switching)
Packet Packet
Layer 3
Frame Packet Switch Frame
Frame Packet
Layer 2 Encapsulation
TTL-1
Layer 3 Checksum
601
Routers (Operationally)
• Maintain/manipulate routing information

Listen for updates/update neighbors
• Classify packets for manipulation/queuing/permit-deny, etc.
Compare packets to classification lists and perform control
• Perform Layer 3 switching

Create outbound Layer 2 encapsulation
Layer 3 checksum
TTL/hop count update
• Management/billing (statistics)
Interface statistics—Netflow export
Telnet, SNMP, ping, trace route, HTTP
601
Router Functionality
• Run routing protocols

• Maintain routing tables
• Check for CLI commands
• Increment accounting counters
System Level Tasks • ICMP
Control Plane • Queue packets, etc…
CPU
Data Plane Layer 1: Retime, Regenerate Signal

Packet Switching Layer 2: Rewrite Header and CRC
Layer 3: Decrement TTL and CRC Rewrite
601
Routers
(Layer 3 Packet Functionally)
• (Attempt to) switch packets
Layer 3 switching based on routing information
• (Attempt to) transmit packets

Access outbound media
• Manipulate packets
Change contents of packet (CAR/NAT/compression/encryption)
• Consume packets
Routing protocol updates etc…/services
advertisements(SAP)/ICMP/SNMP
• Generate packets
Routing protocol packets/SAPs/ICMP/SNMP
Tunnels—GRE, IPSec, DLSw etc…
601
Generic Router
Architectures
601
Shared Memory
CPU CPU Memory

Routing Table
Shared Memory
Shared Bus Electrical Limitations Limit of

Shared Bus Switches <= 20 Gbps
Interface
Interface
Interface
Interface
Thus 10 Gbps/No. Line Cards =

Max Line Rate
601
SM Data Path (Conventional)
CPU CPU Memory

Routing Table
Shared Memory
Shared Bus
Interface
Interface
Interface
Interface
One Packet/Switching Cycle

601
SM Data Path
(Distributed Processors)
CPU Memory
CPU Routing Table
CPU
Interface
CPU
Interface
CPU
Interface
CPU
Shared Memory Interface
601
Cross Bar Data Path
CPU Memory
CPU Routing Table
CPU
i/p Interface
CPU
Interface
o/p CPU
Interface
CPU
Interface
601
Cross Bar Data Path
CPU Memory
CPU Routing Table
CPU
Interface
Bit Slicing Allows CPU
Multiple Switching
Fabrics Interface
CPU
Interface
CPU
Interface
601
Cisco Router
Components
601
General Router Hardware
Flash CPU
NVRAM
Bus
ROM RAM
Interface
System Bus
Interface Interface Interface

Network Network Network
Controller Controller Controller
601
Software Components
• ROM monitor • Device microcode

Startup diagnostic code Part of Cisco IOS that deals
Contains exception handling with network controllers
Microcode deals with modular
• RxBoot
interface processors
Host mode Operating System
• Configuration register
Used for downloading full
Cisco IOS® 16 Bits, specifies router
startup parameters
• Cisco IOS
• Configuration file
Internetwork operating
system Startup-config: Contains
configuration info
Contains process scheduler,
memory manager, parser Running-config: Currently
active configuration
Also contains protocol-
specific code for packet
handling
601
Memory Usage
Boot Flash PCMCIA Flash
RxBoot Cisco IOS File CPU
NVRAM Cisco IOS RAM

Exec Main I/O
Startup-Config
Config Reg. Running Routing System
config Table Buffers
ROM
Data Layer 2/3 Interface
ROM Monitor Structures Cache Buffers
601
Cisco Router Buffers
and Queues
601
Router Interface Buffers
• Interface FIFO
A very small amount of buffer memory (for large MTUs not
even one packet in size) used to store bits as they arrives from
the wire and are dealt with by the interface driver
These buffers are NOT configurable
• Interface Rx and Tx RING
On some platforms these buffers are used by the interface
driver for reception and transmission of packets
Each interface has a FIFO Rx/Tx Ring
Inbound (Rx) they are used to store a packet until an
Interface buffer is available. Outbound (Tx) until the
interface can transmit to the wire
They can exist on the interface card or in shared memory
These buffers are NOT normally configurable
601
Router Internal Buffers
• Buffer Headers
These data structures containing information about related buffer
(e.g. location pointers, size, etc.). They are mostly located in main
processor memory for all buffers. In some cases headers or particle
headers may be stored in shared I/O memory for speed
The purpose of buffer headers is to keep track of buffers and
enqueue them for various processes
• Shared or main memory system buffers

These buffers are used when packets are bound for the processor
for either consumption or process switching
System buffers are sized as small (104), middle (600), big (1,524),
very big (4,520), large (5,024), and huge (18,024)
The total number of buffers depends on available DRAM
System buffers can grow or Trim on demand and can
be configured
These buffers are public. All interfaces can use them
601
Router Internal Buffers

• Shared memory interface buffers
These buffers are used to store packets between the interface driver
and the switching path (not process switching) software
(e.g optimum switching)
These buffers are allocated at startup or after OIR. The number of
buffers depends on the speed and MTU of the interfaces available
These buffers are Interface specific
• Shared memory interface particle buffers

Used as Packet buffers on some platforms and VIP cards
Particle Buffers are located in Shared I/O Memory
Their size is 512 bytes (or 128 byte multicast/broadcast)
The incoming packets are “scattered” into 512 byte particles and
then “gathered” into a contiguous packets for transmission”
601
Contiguous Buffers
• Contiguous buffers
Contiguous buffers (older platforms as well as RSP/RSM)
store packets in buffers sized with respect to the interface
media MTU and speed
The amount of buffers is based on grouping the MTUs of the
interfaces e.g. Ethernet = 1500b MTU, Token Ring/FDDI =
4500b MTU
Let’s assume we have 6 Ethernet and 2 FDDI = 2 buffer pools.
(all the Ethernet I/f share the 1500b pool and all the FDDI
share the 4500b pool)
Based on the aggregate bandwidth we get: Ethernet =
(60/60+200) = 23% and FDDI = (200/60+200) = 77%
We then apportion the available buffers (let’s say it’s a 7K SP)
(.23*504K)/1500 = 79 buffers and (.77*504K)/4500 = 88 Buffers
Therefore, 79/6 = 12 buffers/Ethernet interface and
88/2 = 44 buffers/FDDI interface
601
Contiguous Buffers
• Contiguous buffers
Packet buffers (contiguous) can be wasteful in terms of
memory (Frames are rarely all full size), but more importantly
are not as efficient as particles when it comes to packet
replication
In contiguous buffers the packets is treated as a whole,
therefore to create a replication of the packet with a different
output header requires a completely new packet to be created
1500 4500
Ethernet Interface FDDI Interface

Buffer Pool Buffer Pool
601
Particles vs. Contiguous Buffers
• On some newer platforms (36xx, 72xx, 71xx, VIP2) packet memory is

allocated in “particles”. Particles are either 1024b (36xx), 512b or 128b
chunks of memory
• Packets are divided into particle size blocks and stored in free particles
• Particles have an associated Particle Buffer header which stores
information as to which particles constitute an entire frame
and or an?
I/P Buffer Particle Headers
Header
Packet Memory
Divided Into
Particles
O/P Buffer
Particle Headers Header
601
Particles vs. Contiguous Buffers
• We have the ability to “clone” particle buffer headers

• This allows us to “replicate” a packets particles a number of times
without actually replicating the packet itself for every outbound
interface. This significantly improved multicast performance
I/P Buffer Particle Headers

Header
New Header Packet Memory

Divided into
New Header Particles
Particle O/P Buffer

Headers Header
Cloned
O/P Buffer
Particle
Headers Header
601
Types of Queues
• System interface queues
Input hold queues
Used to queue packets in system buffers for process switching
These queues are based in Main Processor Memory
The size of Input Hold queue is configurable per interface basis
Use “Show Interface” to look at Input Queue statistics
Output hold queues
These queues are used for packets in System buffers after they
have been process switched and are waiting to be transmitted by
the interface driver
These queues exist in main processor memory
The size of input hold queue is configurable per interface basis
Use “Show Interface” to look at output queue statistics
601
Types of Queues
• Interface Queues
Receive Queues
The queues are used for incoming packets that wait in
interface buffers for Fast Switching code
Receive queue usually has a size limit (called RQL) which
is calculated based upon various factors
By default the RQL = Total buffers in a pool/no. interfaces
in that pool
(If for any reason this results in less than 16KB of buffers
RQL= 16384/MTU)
Transmit Queues
These queues are used for outgoing packets that wait in
interface buffers for transmission by outgoing interface
driver code
Transmit queue usually has a size limit (called TQL) which
601
is calculated based upon various factors
Router Operating
System Details
601
Cisco IOS Image and File Storage
• BOOT ROM
EPROM used for startup diagnostic code and ROM
monitor (read only) and to load Cisco IOS
• NVRAM
Used to store startup configuration (rewritable).
Configuration register settings
• PCMCIA FLASH
Portable storage of Cisco IOS image, configuration
files etc… (rewritable)
• FLASH
Onboard storage of full Cisco IOS (rewritable). In
some cases Cisco IOS execution
601
Operational Storage
• DRAM
Used to store loaded Cisco IOS, running
configuration, route tables, switching caches,
processor and switched packets
• SRAM
Used on platforms to deal with high-speed
switching and high-speed interfaces
• FIFO
First-In, First-Out memory used for interface
buffering (not queued—circular buffer or RING)
601
Elements of Execution
• ROM MONITOR (System Bootstrap, or Bootstrap code)

Hardware configuration and system diagnostics performed at
system startup
• RxBOOT (Boot Helper image, Helper Cisco IOS, or
Bootstrap Image)
A Subset of the Cisco IOS, used when a valid Cisco IOS image is not
present allowing a user to download a full Cisco IOS image from
the network
• Cisco IOS
Cisco IOS normally resides in Flash or PCMCIA Flash card and is loaded
into processor memory (DRAM) for execution
In some platforms it may also run from Flash memory to save DRAM
• ROUTER CONFIG
The Startup configuration is stored in NVRAM and a copy is loaded in
DRAM at startup
601
Configuration Register Function
• Force the system into the bootstrap program

• Select a boot source and default boot filename
• Recognition of break signal from console
• Control broadcast addresses
• Set the console terminal baud rate
• Load operating software from ROM
• Enable booting from a Trivial File Transfer
Protocol (TFTP) server
601
Router Startup
ROM Monitor
Diagnostic Check, Console Setup, Memory Sizing, Config
Register Check
Loads Rxboot, or Stays in ROMMON [rommon>]
RxBoot
Builds Basic Data Structures, Interface Setup, Host Mode
Functionality, Startup-Config Check
loads Cisco IOS, or Stays in RxBoot [router(boot)>]
Cisco IOS
Interface Setup, Router Functionality, Allocate Buffers,
Loads Startup-Config
Boot Process Complete [router>]
601
How Routers Receive
and Transmit Packets
601
Receiving Packet
Packet
Packet on
on
Shared Memory Buffer Headers 11 Interface
Interface
Process
Scheduler 22
Interface
Interface Driver
Driver
Code
Code
66 55 44 22 Discard Frame
CPU 33 33 Frame
Fail Update Frame
Frame Check
Check errors, e.g.
“Runt, Giant, CRC”
x
OK
No Discard Frame
11 Assign
Assign aa Free
Free
44 Increment
Buffer
Buffer Header
Header “Overrun”
If CPU Too Slow
Interface Yes
FIFO Buffer No Increment “No
Increment “Ignore”
R
Free
Free Buffer
Buffer 55 Header
Header Available
Available Buffer”
*Drop Packet*
Yes Return to Scheduled
Move
Move Packet
Packet toto Processes
66
Shared
Shared Memory
Memory
601
Receiving a Packet
(Process Switching)
Classify
Classify
System Memory Packet
Packet
IP Process
Input Hold
Queue Fast Cache Yes Go to
Can
Can the
the Packet
Packet
77 Be
Be Fast
Fast Switched
Switched FastSwitching
99 77
No
Assign
Assign System
System Buffer
Buffer
88 Return
Return Packet
Packet Buffer
Buffer
88 88 to
to Free
Free List
List
CPU If “Input Hold Queue”
System
System Buffers
Buffers Enqueue
99 Enqueue Packet
Packet Full, *Drop Packet*
for
for Process
Process Switching
Switching Increment “Input
Queue Drop”
Rx
Rx Interrupt
Interrupt
Complete
Complete How Is This
Return
Return CPU
CPU to
to Box Related?
Interface Rx Interrupt Scheduled
Scheduled Tasks
Tasks
FIFO
Buffer
601
Transmitting a Packet
(Process Switching)
System Memory
Output Hold Queue Forwarding
Forwarding
Decision
Decision
11
11
Write
Write New
New
10
10 Header
Header Over
Over
10
10 Old
Old Header
Header
12
12
CPU
System
System Buffers
Buffers 11
Packet
Packet Is
Is Enqueued
Enqueued How Is this
11 in
in for
for Output
Output I/f
I/f in
in
Output
Output Hold
Hold Queue
Queue
Box Related?
Packet
Packet Is
Is If Output Hold Queue Is
Interface 12
12 Transmitted
Transmitted Full, Packet Is Dropped
With an “Output Queue
FIFO Drop”
Buffer
601
Transmitting a Packet
(Fast Switching)
Classify
Classify
Fast Cache Packet
Packet
Packet Memory
Go to
88 77 Yes FastSwitching
77 Can
Can the
the Packet
Packet be
be
TQL Fast
Fast Switched
Switched
i/p 99 o/p Obtain Output

88 Header From
10
10 CPU Fast Cache
Packet Buffers If No Output Buffer
Available Drop Packet Rewrite Header
With and Move
11 “Output Buffer Failure” Buffer Header
11 99
Note: If or Move Packet
Interface “Transmit Buffer to Output
Backing-Store” Interface Buffer
FIFO Is Enabled the Packet
Buffer Will Be Moved to
Enqueue Packet
System Buffers and De-
10
10 for Interface
queued as with Process Transmit Queue
Switching
An Output Buffer Swap
Is Incremented
11 Transmit Packet
11
601
Packet Switching
“Processes” and
“Functions”
601
Processes and Functions
• Process switching is a collection of functions based
on a particular protocol that is being switched
• The Scheduler gives processor time to each “Process”
which may call a number of “Functions” before the
“Process” is complete
• Each “Process” is run to completion unless a higher-
priority “Process” is invoked. The original “Process” is
suspended until such time as the higher-priority
“Process” is completed at which time the original
“Process” will continue to be run
IP Input Compression
Compression Encryption
Encryption I/P
I/P ACLs
ACLs CAR
CAR Completed
Process Functions
601
• For Fast and ½ Fast Switching there is no concept of a

“Input Process”
• The Fast Switching code, invoked after an Rx Interrupt,
calls various functions, independently as defined by the
configuration file for an interface or protocol
• Some features are run in Rx Interrupt mode, but the
packets are moved to system buffers depending on the
requirements of the feature (e.g. NAT)
MLPPP NAT IPSec
Function Calls
Rx Interrupt
601
• Dequeuing is the function used when a packet
has been process switched and needs to be
passed to the output interface, or when an
interface has “fancy” queuing enabled and again
packets are stored in system buffers until they
are dequeued (based on queuing mechanism)
System
System Buffers
Buffers Output
Output Hold
Hold Q
Q
Shared System Memory

(DRAM)
Output I/f
Packet
Packet Buffers
Buffers
“Fancy”
“Fancy” Queued
Queued
Shared Packet Memory Packets
Packets
(SRAM)
601
• In the case of “fancy” queuing being applied to an

interface, the Output Hold Queue represents either the (4)
Priority, (>16) Custom or (>256) Weighted Fair queues
• In Process switching this is a FIFO queue by default
Process Switching Priority Queuing Custom Queuing
L N M H 0 1 2 3 Output Hold Q
FIFO
601
Process Switching
Dequeue
Dequeue Packet
Packet from
from
IP Process Input Input
Input Hold
Hold Queue
Queue
Hold Queue
Yes
Input Processing Compressed
Compressed Decompress Packet
No
Yes
System Memory
Encrypted
Encrypted Decrypt Packet
No
Deny
Input
Input ACL
ACL *Drop Packet*
Permit Conform/Not Conform
CPU CAR
CAR CAR Action
No
Is
Is TTL>0
TTL>0 *Drop Packet*
Yes
TTL=TTL-1
TTL=TTL-1
Yes
NAT Out->In NAT
NAT Transform
Transform
Attempt
Attempt to
to
Forward
Forward Packet
Packet
= Packet Compared To Access

List in Configuration
601
Process Switching
IP Process Output
Hold Queue
Yes
Output Processing Broadcast
Broadcast Broadcast Packet
No Yes
Policy
Policy Route
Route Policy Route
System Memory
No Yes
NAT
NAT Transform
Transform In->Out
CPU No
Look
Look Up
Up Route
Route Route Table
Deny
Output
Output ACL
ACL *Drop Packet*
Permit
Yes
Encryption
Encryption Encrypt Packet
Yes
Compression
Compression Compress Packet
= Packet Compared To Access

List in Configuration
601
How Routers Make
Switching Decisions
601
Routing Tables
• Forwarding information populated by IGPs

and EGPs
RIP, OSPF, Statics, EIGRP etc…
c3620#sh ip route
Codes: C - connected, S - static, I - IGRP, R - RIP, M - mobile, B - BGP
D - EIGRP, EX - EIGRP external, O - OSPF, IA - OSPF inter area
N1 - OSPF NSSA external type 1, N2 - OSPF NSSA external type 2
E1 - OSPF external type 1, E2 - OSPF external type 2, E - EGP
i - IS-IS, L1 - IS-IS level-1, L2 - IS-IS level-2, * - candidate default
U - per-user static route, o - ODR
Gateway of last resort is 0.0.0.0 to network 0.0.0.0
1.0.0.0/24 is subnetted, 2 subnets

C 1.1.1.0 is directly connected, Ethernet0/0
C 1.1.2.0 is directly connected, Loopback1
10.0.0.0/24 is subnetted, 1 subnets
C 10.64.217.0 is directly connected, Ethernet0/1
S* 0.0.0.0/0 is directly connected, Ethernet0/1
601
Adjacency Information
• Discovered in various ways including

ARP protocol
c3620#sh arp
Protocol Address Age (min) Hardware Addr Type Interface
Internet 1.1.1.1 - 0010.7b1f.4a61 ARPA Ethernet0/0
Internet 1.1.1.5 118 00a0.c903.6077 ARPA Ethernet0/0
Internet 32.97.105.46 153 0000.0caa.2350 ARPA Ethernet0/1
Internet 1.1.1.6 4 00a0.c903.6064 ARPA Ethernet0/0
601
A Cached Table of Forwarding

and Adjacency Information
• Initialized after a packet has been

successfully Process Switched and
*Can* be cached…
c3620#sh ip ca verb
IP routing cache 3 entries, 516 bytes
232 adds, 229 invalidates, 0 refcounts
Minimum invalidation interval 2 seconds, maximum interval 5 seconds,
quiet interval 3 seconds, threshold 0 requests
Invalidation rate 0 in last second, 0 in last 3 seconds
Prefix/Length Age Interface Next Hop

1.1.1.5/32-24 21:07:47 Ethernet0/0 1.1.1.5 14 00A0C903607700107B1F4A610800
1.1.1.151/32-24 00:06:22 Ethernet0/0 1.1.1.151 14 000039542C0800107B1F4A610800
171.69.0.0/16-0 01:16:08 Ethernet0/1 171.69.10.34 14 00000CAA235000107B1F4A620800
601
Finding an Entry in a Table
• We could look sequentially through each entry until
we find the one we are looking for
• This could end up being very time consuming and
(unless the tables were sorted inversely with time)
probably end up with the most useful entries (i.e. the
most recent ones) at the end
• Also it is possible that a more specific and more
optimized entry maybe missed if we take the first one
we find sequentially
Prefix/Length Age Interface Next Hop
1.1.1.5/32 20:50:18 Ethernet0/0 1.1.1.5
1.1.1.151/32 00:08:20 Ethernet0/0 1.1.1.151
171.68.0.0/16 00:43:59 Ethernet0/1 171.70.10.70 This would come first
171.68.1.0/24 00:08:39 Ethernet0/2 171.68.11.34 This is more specific
199.2.54.0/24 00:03:54 Ethernet0/1 199.2.54.193
601
How Binary Trees Help Us

Speed up Performance
Linear List Look-Up
Find X=4
X=n 1
X=n 2
X=n 3 This Is OK for Small Tables of
X=n 4 ü Information Where the Maximum
5 Look up Time Is the Number on
6 Entries in the List
7
8
9
601
Speed up Performance
Binary List Look-Up
Find X=4
Find Midpoint Find Midpoint
of the List of the List
1 1 An Entry in a Table W/2 Billion
Entries Will Take 32 Iterations
3 3
4 4 4 ü
6 If X= -> L, Found,
8 If X< -> L, look in first half of the list,
else look in the second half
9
11
If X= -> L, Found,
If X< -> L, look in first half of the list,
else look in the second half Or…
601

Speed-Up Performance
Binary List Look-Up
Find X=4
LHS RHS
This Is a Node
Compare X to Root Node 6 (In This Case the Root Node)
If X = RN Done
If X < RN Search in LHS
If X > RN Search in RHS 3 9
1 4 8 11
Look-Up Time = (Max = Logn, Where N=no. Nodes)
601
Cisco Router Internals
(Low-Mid Range)
601
Low-End Systems
Main DRAM Shared DRAM

Cisco IOS Switch Contiguous System Buffers
(Not 1600/2500) Cache (Small, Large, Huge, Etc.)
Running Routing Public, Dynamic, Configurable
Config Tables
Data Buffer Contiguous Interface Buffers
Structures Headers Private, Static, Configurable
Particle Based in 7200 (512 B) 3600
SRAM 7200 (Npe150/200)
(1524 B), Nonconfigurable
Particle-based
Interface Buffer. Tx and Rx Descriptor Rings
Tx and Rx Rings
(3 Hi BW PA Only), Private, Circular Linked Lists
Nonconfigurable
601
Cisco 1000/2500 Family
601
Cisco 100x Series
CPU Boot ROM

M 68360
Console
CPU Bus
I/O Buses SCC NVRAM
Serial PCMCIA
CSU/DSU
BRI S/T, U Ethernet DRAM
601
Cisco 160x Series
WIC WIC Slot Boot ROM
NVRAM
CPU
CPU Bus
M 68360 PCMCIA
Console
I/O Buses SCC
DRAM
Serial SIMM
CSU/DSU On Board
BRI S/T, U Ethernet DRAM
601
Cisco 25xx Series
WIC WIC Slots Dual

2524, 2525 UART
Async M 68030 Boot ROM
CPU Bus
Mgmt Card
System Bus
2509-2512
2517-2519 NVRAM
Hub Ports
Daughter and
2505, 2507 PCMCIA
Hub Cards Sys Ctrl
2516
ASIC
Flash
Ether/TR
On Board DRAM
WAN Intf DRAM SIMM
601
Cisco 3600 Family
601
Cisco 36x0 Series

PCI Bus 1 PCI Bus 2
Network PCI
Modules Bridge Dual
R 4700 UART
PCI Bus 0
Network Boot ROM

PCI CPU Bus
I/O Bus
Modules Bridge NVRAM

Sys Ctrl
GT 64010 Flash
PCMCIA
DRAM
601
Cisco 4000 Family
601
Cisco 4000 and 4000M
Dual
Control Bus
UART
NIMs
M 68030 Boot ROM
CPU Bus
NVRAM
DBus
Sys Ctrl Flash /

Logic
EPROM
Shared Main
DRAM DRAM
601
Cisco 4500 and 4700
Layer 2 R 4600
Control Bus
Cache R 4700 Dual
NIMs 4700 Only UART
CPU Bus
Boot ROM
I/O Bus
DBus
Other Sys Ctrl NVRAM

Logic ASICs
Power Flash
Supply Shared Main
DRAM DRAM Boot Flash
601
Low-Mid Router Comparison
CPU PROCESSOR TYPE CLOCK CPU Bus INTERFACES Layer 2 CACHE
4000 M68030 CISC 40 MHz 32 bit NIM -
4000M M68030 CISC 40 MHz 32 bit NIM -
4500 R4600 RISC 100 MHz 64 bit NIM -

4xxx
4500M R4600 RISC 100 MHz 64 bit NIM -
4700 R4700 RISC 133 MHz 64 bit NIM 512 KB
4700M R4700 RISC 133 MHz 64 bit NIM 512 KB
3620 R4700 RISC 80 MHz 64 bit NM,WIC,VIC -

36XX
3640 R4700 RISC 100 MHz 64 bit NM,WIC,VIC -
25xx M68360 CISC 20 MHz 32 bit Built in -
17xx ????? ????? ?????? BI,WIC,VIC -

?????
160x M68360 CISC 33 MHz 32 bit BI,WIC,VIC -
100x M68360 CISC 25 MHz 32 bit Built in -
601
High-End Systems
Main DRAM
Cisco IOS Switch CPU
(Not 1600/2500) Cache
Running Routing RP
RSP
Configuration Tables SP/SSP
Data Buffer
SRAM
Structures Headers
Contiguous System Buffers Contiguous Interface Buffers
Public, Dynamic, Configurable Shared, Static, Nonconfigurable
DRAM IProc SRAM VIP Micro PA

Processor Network
Microcode Particle Based VIP
Micro Controllers
256 B Cisco
Local Buff Processor DRAM
Local Buffs IOS
PA
Tx and Network
Tx and Rx Distributed Network
Rx Rings Controllers Cache
Rings Controllers
601
Cisco 7200/7500 Family
601
Cisco 720x Series
PA 5 PCI Bridge PCI Bridge PA 6
PCI Bus 1
PCI Bus 2
I/O Controller CPU

PCI PCI
Fast Ether PCMCIA Midplane NPE
Bridge Bridge
SRAM
PCI Bus 0
! NPE-100
Dual Sys Ctrl
CPU Bus
Boot ROM GT 64010 R 4700
UART
R 5000
I/O Bus Layer 2
Cache
NVRAM Boot Flash EEPROM DRAM
NPE-200
601
Cisco 70x0—RP and SP/SSP
SP/SSP RP
Bit Slice Multi Bus I/O M 68040
I/O Ctrl
Multi Bus
EEPROM Proc. Intf Logic Devices
Local Bus CPU Bus
CxBus Intf Diag Bus Multi Bus Diag Bus DRAM

SRAM DMA Logic Intf Logic Intf Logic Intf Logic
Diag Bus
Cx Bus
Fan
Cx Bus
Tray Intf Proc. Intf Proc.
Arbiter
601
Cisco 70x0—RSP7000
CI Board Dual RSP7K

DRAM Sys Ctrl
UART
ASICs R 4600
EEPROM Boot ROM
I/O Bus
NVRAM CPU Bus
Envm Register
Logic FPGA
PCMCIA MemD Ctrl SRAM
Diag Bus Diag Bus ASICs
Intf Logic Boot Flash FPGA QA ASIC
Diag Bus
Cx Bus
Fan Cx Bus
Tray IP/VIP IP / VIP Arbiter
601
Cisco 75xx Series
Dual RSP Sys Ctrl DRAM R 4600

UART R 4700
ASICs Layer 2
Boot ROM Cache R 5000
I/O Bus
NVRAM CPU Bus

Register
FPGA
PCMCIA MemD Ctrl SRAM
Diag Bus ASICs
Boot Flash FPGA QA ASIC
Diag Bus
Cy Bus 0 Cy Bus 1
Cy Bus
IP/VIP IP/VIP IP/VIP IP/VIP
Arbiter
601
Cisco 75xx Series—VIP
VIP DRAM DRAM Ctrl R 4600

PCI Bus 2 ASICs R 4700
PCI R 5000
PA Bridge 2
PCI Bus 0
CPU Bus
Boot ROM
Packet Bus
I/O Ctrl Layer 2
PCI Bus 1
SRAM ASIC Cache

PA PCI
Bridge 1 PMA CYA
ASICs EEPROM
ASICs
CBus Diag Bus
601
High End Router Comparison

Layer 2
CPU PROCESSOR TYPE CLOCK CPU Bus INTERFACES
CACHE
RSP1 R4600 RISC 100 MHz 64 bit IP,VIP1,VIP2 -
RSP2 R4600/R4700 RISC 100 MHz 64 bit IP,VIP1,VIP2 -
RSP4 R5000 RISC 200 MHz 64 bit IP,VIP1,VIP2 512 KB

7500
VIP2-15 R4700 RISC 100 MHz 64 bit PA 512 KB
NPE100 R4700 RISC 150 MHz 64 bit PA,IO -FE 512 KB

7200
RP M68040 RISC 40 MHz 32 bit IP, VIP1 -

7000
RP M68040 RISC 40 MHz 32 bit IP, VIP1 -
RSP7K R4600 RISC 100 MHz 64 bit IP, VIP1,VIP2 -
601
GSR Family
601
1094_06F9_c4
GSR Switch Fabric
Switch Fabric Cards
CPU I/f CPU I/f
CPU I/f CPU I/f
CPU I/f CPU I/f
CPU CPU I/f

I/f
CPU CPU I/f

I/f
CPU CPU
RP RP
Clock and Scheduler Cards

601
GSR Throughput
Each Card can Switch 15Gbps

Transceivers
CPU I/f
CPU
RP
1.25Gbps per Trace

601
GSR RP
DRAM SRAM
FIA SLI Tranciever
Layer 2 R5000 Tiger CSAR
Cache CPU Asic FIA SLI Tranciever
R5000 CPU Executes Cisco IOS Software —200mhz RISC
I/O BUS Processor
Layer 2 CACH—512KB Write through Data and Instruction Cache
Ethernet NVRAM TIGER ASIC Connects RP to DRAM, CSAR I/O Bus
DRAM Memory for Main Storage Supporing up to 256MB

PCMCIA
CSAR Segments and Reassembles Packets
Console Boot
SAR SRAM Provides a Cache for the CSAR
ROM
Flash SIMM FABRIC INTERFACE ASICS Manage Cisco Cells to and from
the Fabric
SLI ASICS Encode Packets for Transmission on the Fabric
8B/10B Encoding Similar to Gigabit Ethernet or FDDI
601
GSR Switch
Processor Configurations
Mode CSC SFC Bandwidth Clock Redundancy Fabric Redundancy
Entry Level 1 0 622Mbps none none
Redundant Entry 2 0 622Mbps 1:1 1:1
High BW 1 3 2.4Gbps none none

High BW 2 2 2.4Gbps 1:1 none
Redundant High BW 2 3 2.4Gbps 1:1 1:N
601
GSR Interface Card
Tx Rx
512Kb
512Kb 512Kb
512Kb
Processor
Burst
Burst Burst
Burst
Buffer
Buffer Buffer
Buffer
SQE
16-64MB
16-64MB 16-64MB
16-64MB CPU I/f
Buffer
Buffer Buffer
Buffer
Memory
Memory Memory
Memory
Fabric Interface
601
Head of Line Blocking (HOL)
Blocked (grrrrr!!)
601
Output Queue
CPU
C C C B
Interface A
Delayed/
Dropped
B
Interface
Congested C
Interface
Shared Memory
601
“Lane Control”
B
A D C
B B
A C A C
D D
A B C
D
601
All Destinations Have a Lane

B
A D C
B B
A C A C
D D
A B C No interface
(Outbound) Can
affect another
Interface
D
601
Virtual Input Queuing
CPU
FIFO C C C
FIFO B
Interface A
Delayed/
Dropped
B
Interface
Congested C
Interface
Shared Memory
601
Virtual Input Queue
CPU
FIFO C C C
Queue
FIFO
Scheduler
Interface A
B
B
Interface
Congested C
Interface
Shared Memory
601
Please Complete Your
Evaluation Form
Session 601
601
1094_06F9_c4
601

Cisco Router Architecture

Încărcat de

Informații document

Descriere originală:

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Cisco Router Architecture

Încărcat de

Drepturi de autor:

Formate disponibile

601601

Cisco Router Architecture

• Routers perform OSPF, EIGRP,BGP

• Maintain/manipulate routing information

• Perform Layer 3 switching

• Run routing protocols

Data Plane Layer 1: Retime, Regenerate Signal

• (Attempt to) transmit packets

CPU CPU Memory

Shared Bus Electrical Limitations Limit of

Thus 10 Gbps/No. Line Cards =

CPU CPU Memory

One Packet/Switching Cycle

Shared Memory Interface

Cross Bar Data Path

General Router Hardware

Interface Interface Interface

• ROM monitor • Device microcode

Boot Flash PCMCIA Flash

RxBoot Cisco IOS File CPU

NVRAM Cisco IOS RAM

Router Interface Buffers

• Shared or main memory system buffers

Router Internal Buffers

• Shared memory interface particle buffers

Ethernet Interface FDDI Interface

• On some newer platforms (36xx, 72xx, 71xx, VIP2) packet memory is

Particles vs. Contiguous Buffers

• We have the ability to “clone” particle buffer headers

I/P Buffer Particle Headers

New Header Packet Memory

Particle O/P Buffer

Cisco IOS Image and File Storage

• ROM MONITOR (System Bootstrap, or Bootstrap code)

• Force the system into the bootstrap program

i/p 99 o/p Obtain Output

Processes and Functions

• For Fast and ½ Fast Switching there is no concept of a

MLPPP NAT IPSec

Shared System Memory

Processes and Functions

• In the case of “fancy” queuing being applied to an

Process Switching Priority Queuing Custom Queuing

= Packet Compared To Access

= Packet Compared To Access

• Forwarding information populated by IGPs

Gateway of last resort is 0.0.0.0 to network 0.0.0.0

1.0.0.0/24 is subnetted, 2 subnets

• Discovered in various ways including

A Cached Table of Forwarding

• Initialized after a packet has been

Prefix/Length Age Interface Next Hop

How Binary Trees Help Us

How Binary Trees Help Us

Look-Up Time = (Max = Logn, Where N=no. Nodes)

Main DRAM Shared DRAM

Cisco 100x Series

CPU Boot ROM

I/O Buses SCC NVRAM

WIC WIC Slot Boot ROM

Cisco 25xx Series

WIC WIC Slots Dual