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A Thesis
In
Electrical Engineering
MASTER OF SCIENCE
IN
ELECTRICAL ENGINEERING
Approved
Mark Sheridan
Dean of the Graduate School
May, 2015
Copyright 2015, Benjamin Hall
Texas Tech University, Benjamin Hall, May 2015
ACKNOWLEDGMENTS
This thesis may have a single author, but it took an entire team to accomplish
everything I have been able to do. First, I would thank my family. No matter how
difficult life or school got, they always were there to support me and lift me up, not to
mention paying for school. Through my undergrad to my graduate work, my mother,
Hamide Hall, father, Andrew Hall, and Sister Rachel Hall have continued to inspire
me and encourage me to do my best. Without them I do not know where I would be.
Next I would like to thank my committee, Dr. Richard Gale and Dr. Brian
Nutter, for giving me the opportunity to teach this class as my thesis. The advisement
and teachings from Dr. Gale have been invaluable in my studies as a test engineer. I
also appreciate the incredible chance Dr. Nutter took on me by giving me the reins to
my own class.
I would also like to thank the incredible members at National Instruments that
have donated not only equipment, but also their time to helping me in everything
related to the STS. I would especially like to thank Corby Bryan for all the time and
effort he put into training and supporting me ever since I showed any interest in the
semiconductor field.
Finally, I would like to thank the amazing faculty at the Texas Tech University
Department of Electrical and Computer Engineering. Richard Woodcock has been
instrumental in providing me with the equipment needed and lending me his wisdom
from his years in the semiconductor field. Jackie Charlebois and Janet McKelvey have
provided me with the resources needed for my class and have consistently supported
and encouraged me. Not to mention they have been a source of entertainment on
difficult days.
No one person is worth more than the other. All I have accomplished requires
each and every person that I have mentioned, and so many more I did not. Without
any one of them, I could not be where I am and do what I do. Thank you all so much.
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TABLE OF CONTENTS
ACKNOWLEDGMENTS .................................................................................................... ii
ABSTRACT ..................................................................................................................... iv
LIST OF FIGURES ........................................................................................................... v
LIST OF ABBREVIATIONS .............................................................................................. vi
INTRODUCTION OF SEMICONDUCTOR TEST SYSTEM..................................................... 1
1.1 Background of Semiconductor Testing at Texas Tech ................................... 1
1.2 The Semiconductor Testing System ................................................................ 1
I. COURSE DEVELOPMENT ............................................................................................. 4
2.1 Motivation ....................................................................................................... 4
2.2 Expected Learning Outcomes ......................................................................... 4
II. COURSE CURRICULUM ............................................................................................. 6
3.1 Probability and Statics .................................................................................... 6
3.1.1 Central Limit Theorem ............................................................................................ 6
3.1.2 Process Capability .................................................................................................. 7
3.1.2 Repeatability and Reproducibility ........................................................................... 9
3.2 Solid State Physics ........................................................................................ 11
3.3 Testing Strategies .......................................................................................... 12
3.3.1 Continuity.............................................................................................................. 13
3.3.2 Leakage Current ................................................................................................... 14
3.3.3 Power Consumption ............................................................................................. 15
3.3.4 Voltage Output High/Voltage Output Low ............................................................ 15
3.3.5 Functionality ......................................................................................................... 17
3.3.6 Test Plan Development ........................................................................................ 17
3.4 Pin Map and Pin Map Application Program Interface .................................. 18
3.4.1 Pin Map Creation .................................................................................................. 19
3.4.2 Pin Map API Definitions ........................................................................................ 21
3.4.3 Using the Pin Map ................................................................................................ 25
3.5 TestStand and Semiconductor Multi Test Step ............................................. 25
3.5.1 Semiconductor Multi Test ..................................................................................... 26
IV. COURSE EVAUATION ............................................................................................. 29
4.1 Assessment .................................................................................................... 29
4.1.1 Fall Semester Assessment................................................................................... 29
4.1.2 Spring Semester Assessment .............................................................................. 29
4.2 Instructor Evaluation ..................................................................................... 30
4.3 Future Work .................................................................................................. 32
V. CONCLUSION ........................................................................................................... 33
BIBLIOGRAPHY ............................................................................................................ 34
A SYLLABUS ................................................................................................................. 35
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ABSTRACT
The Program for Semiconductor and Product Engineering (PSPE) at Texas
Tech University strives to prepare students for a job in the semiconductor field. One
crucial partner with PSPE is National Instruments (NI), who has donated a state of the
art Automated Test Equipment (ATE) called the Semiconductor Test System (STS).
This thesis discusses the development of curriculum for ECE 5332: Advanced
Modular Testing Methods for Integrated Circuits, which focuses on training students
on how to properly utilize the STS for their own projects. With the STS becoming an
industry standard, students from Texas Tech will be on the forefront of the advances
being made in the semiconductor field.
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LIST OF FIGURES
1 Semiconductor Test System [1] .................................................................................. 2
2 Different STS Sizes [1] ............................................................................................... 3
3 Ideal Process Capability [2] ........................................................................................ 7
4 Gaussian Distribution with Spec Limits [2] ................................................................ 8
5 Guarbanding Test Limits [2] ..................................................................................... 10
6 Forward Biased P-N Junction [3].............................................................................. 11
7 Forward Biased P-N Junction [3].............................................................................. 12
8 Continuity on a Single Pin [5]................................................................................... 13
9 Leakage Current Test on SMU [5] ............................................................................ 14
10 Power Consumption Test [5] .................................................................................. 15
11 VOH/VOL Test [6] ................................................................................................. 16
12 Overall Pin Map Schema [5] ................................................................................... 19
13 DUT Pin Schema [5] ............................................................................................... 20
14 Instrument Definition Schema [5] ........................................................................... 20
15 Site Definition Schema [5] ...................................................................................... 20
16 Pin Connection Schema [5]..................................................................................... 21
17 Pin Map API Location [5] ....................................................................................... 22
18 Get All NI-HSDIO Instrument Names VI [5] ......................................................... 23
19 Correlation Between Get All NI-HSDIO Instrument Names VI and
Pin Map [5] .......................................................................................... 23
20 Get Pin Names VI [5] .............................................................................................. 24
21 Pins To NI-HSDIO Sessions VI [5] ........................................................................ 24
22 Publish Data VI [5] ................................................................................................. 24
23 Using the Pin Map API [4] ..................................................................................... 25
24 TestStand Sequence [5] ........................................................................................... 26
25 Semiconductor Multi Test Setup [5] ....................................................................... 27
26 TestStand Test Limits in Excel [5].......................................................................... 28
27 Semiconductor Multi Test Options Tab [5] ............................................................ 28
28 Course and Instructor Evaluation Average Results ................................................ 31
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LIST OF ABBREVIATIONS
ATE – Automated Test Equipment
NI – National Instruments
PXI – PCI eXtensions for Instrumentation (also used in National Instrument’s part
names)
VI – Virtual Instrument
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CHAPTER I
The Program for Semiconductor and Product Engineering (PSPE) at Texas Tech
University primarily focuses on instructing students in the different methods for
semiconductor testing. Through this program, students are prepared for an industrial
test or product engineering job. To accomplish this, the students take specific classes
with a focus on semiconductor devices which are associated with a lab component
where students get hands on experience testing various devices utilizing similar
instruments used at semiconductor companies.
The PSPE lab mostly uses bench equipment, but most companies use Automated
Test Equipment (ATE) when it comes to device manufacturing. NI recently started to
shift into the world of semiconductor ATEs in the form of the Semiconductor Test
System (STS). The STS is a system released in August of 2014 that uses one or
multiple PXIs to perform the full spectrum of DC and parametric tests on
semiconductor devices. The system comes packaged with the new Semiconductor
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Module and PinMap drivers for NI LabVIEW and TestStand, programming languages
used to interface the various equipment used in the PXI. The following figure shows
how the STS incorporates the PXI and LabVIEW.
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The STS comes in three different sizes; T1, T2, and T4 (Figure 1.2). The
different sizes dictate the number of PXI chassis that can fit into one system. The
PSPE lab received a T4, which is capable of holding four 18-slot PXI chassis.
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CHAPTER II
COURSE DEVELOPMENT
2.1 Motivation
Within the PSPE lab, the task of training new students on all the equipment had
been left to former students. Though many of the students were able to learn how to
properly use the equipment, there was still a gap between the fully experienced
students and the ones with limited training. At times, students trusted word of mouth
on the proper method to set up a test, which sometimes meant students were doing an
unnecessary amount of work to accomplish a simple task. One such incident is when a
student requested an updated version of switching software to make 124 connections
on a 12 pin device.
With a brand new system introduced to the lab, a former training class was needed
to bridge the gap and ensure all students were properly trained to use the STS. The
class also prepares students with test methods used in industry allowing them to find a
job in the semiconductor field with companies that use the STS.
In the process of developing the course, a few items had to be completed. First, the
course objective needed to be identified. When considering the objective, the
motivation was taken into high consideration. The final objective was identified as
“To develop the skills needed for industry test standards”. Next, the syllabus had to be
developed. A copy of the syllabus can be found in Appendix A. When considering the
syllabus, the Expected Learning Outcomes (ELO) were identified as the following:
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2. Reconfigure and sequence test programs in the ATE environment using Test
Stand
6. Summarize test results and present process and test capability analyses
Finally, students with a desire to pursue jobs in the semiconductor field had to be
identified. These students had to have a motivation to learn a brand new system from
the ground up and be willing to help their peers. Fortunately, ten students with these
traits were identified for the first offering of the class in the fall 2014 semester. Their
work then motivated a class of thirty-five for the spring 2015 semester.
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CHAPTER III
COURSE CURRICULUM
The first part of the course focuses on probability and statistics, with a stronger
emphasis on the latter. First, the difference between probability and statics has to be
understood. Probability is using the known population to predict the outcome of a
sample. For example, if a bag of marbles contains three red marbles, two green
marbles, and five blue marbles, probability is used to predict the likelihood that one
red, one green, and one blue marble will be selected. Typically, test engineers do not
rely on probability, and instead utilize statistics.
The Central Limit Theorem (CLT) states that in the limit of a large number of
samples (< 30), the distribution of a random variable will tend toward a Gaussian
distribution, or bell curve. In the field of test engineering, the number of samples, n, is
the number of measurements taken. Theses measurement values follow the behavior
of a Gaussian and are characterized by two main values, the mean (Formula 3.1) and
standard deviation (Formula 3.2).
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(1)
(2)
The mean is the average value of all samples. It is the expected and most
probable value whenever a measurement is taken. The standard deviation is the
measurement of the dispersion of the uncertainty of the measured quantity about the
mean. [2]
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(3)
Cp is the ratio of the range of passing values and the process capability [2].
The larger the Cp, the more stable the process. Any value less than 2 indicates a
process stability issue.
The Process Capability Index, or Cpk, is the process capability with respect to
the centering between specifications limits [2]. When considering only one side of the
specification limits, Cpk can be calculated by the appropriate value in Equation 4. A
Cpk of equal to or greater than 1.5 is needed in order to achieve 6σ.
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(4)
When given a two sided specification, both values in Equation 4 are calculated
and the lower of the two values is taken or the Cpk can be calculated using Equation 5.
C pk C p (1 k ) (5)
Where k is calculated using Equation 6 in which T is the target value and µ is
the mean of the distribution. It is important to note that if T=µ, the distribution is
centered on the mean and therefore Cp=Cpk.
T
k (6)
0.5USL LSL
3.1.2 Repeatability and Reproducibility
After considering the variation in the process of the device, the variation of the
instruments must be considered. This brings up the difference between accuracy and
precision. The accuracy of an instrument is its ability to get close to the expected
value. The precision of the instrument is its ability to get close to the same values after
multiple measurements. However, the measurements themselves are not necessarily
accurate. The precision of the instrument is also described as its repeatability and
reproducibility.
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(7)
When considering the repeatability of the instrument, it is important to
implement gaurdbanding, which is a technique used to tighten the test limits to
compensate for the uncertainty of the instrument. Gaurdbanding involves defining a
upper and lower test limit that is tighter on the graph (Figure 5) by ±ɛ as defined in
equation 6.
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First, the I-V curve (Figure 3.2) of diode is studied to understand the proper
flow of current when the device is in different states. The first state is the Forward
Current state in which the device is open allowing current to flow. While in the
Forward Current state, the depletion region of the diode is small. The next state is the
Reverse Blocking state. In this state, the diode is in reverse bias and is blocking
current. The depletion region in the blocking state is large compared to the forward
state. Finally, there is the Reverse Breakdown state. After a threshold of voltage is
reached, the depletion region is too large and current starts to sink through the device.
This is a dangerous state to be in as the current is not limited and can damage the
device.
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3.3.1 Continuity
Continuity is thought to be the bread and butter of testing. It is always the first
test performed for several different reasons. First, continuity is used to detect the
electrostatic discharge (ESD) diodes present in all devices. The diodes are imperative
to protect the device from being damaged in case of static discharge. Since it is known
that all devices have ESD protection diodes on each pin, other than VDD and GND,
continuity is also used to ensure there are proper connections between the device
under test (DUT) and the instruments being used.
The diodes presented in the device are connected from a pin on the device to
VDD and one to GND. To perform a continuity test, all pins must first be grounded.
Next, a current is applied to a single pin on the DUT. When detecting the Vcc diode,
current is sourced. This puts the diode connected to GND in reverse bias which blocks
the current and the diode connected to Vcc in forward bias allowing the current to
flow out the power pin to ground. When detecting the GND diode, the current is sunk.
This puts the VDD diode in reverse bias which blocks the current and the diode
connected to GND in forward bias allowing current to flow to ground. When detecting
either diode, the voltage drop is measured, and is typically around 550 and 750 mV.
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The input to a CMOS device has high impedance that theoretically allows no
current to flow. In practicality, whenever a voltage is applied, there is a small amount
of current that “leaks” from the pin. Leakage current can detect physical defects, such
as metal filaments that can cause shorts, and an issue in the process of the DUT that
can cause a failure later down the line. This failure is known as infinite mortality [2].
Leakage current can also cause DC offsets which can affect customer applications.
Typically leakage current is less than 1 µA [4]. At times, output pins may have high
impedance and in that case the leakage current should be measured at the output as
well.
When performing a leakage current test, first ensure the DUT is powered on by
connecting VDD to a voltage source. Next, DC voltage is forced on the pin being
tested. The value of the voltage is depends on the type of device being tested. If it is an
analog device, the measurement is taken at the VDD voltage level, and at 0 V. If it is a
digital device, the voltage is set to the input voltage thresholds, VIH and VIL.
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The Power Consumption test is used to detect catastrophic failures in the DUT.
As the name implies, the test measures the DUT’s power consumption under normal
operating conditions. Depending on the DUT, the test may need to be performed
multiple times in the different states of the device.
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(VOH) is the minimum voltage required for output HI at load current. VOH is
measured when the input pins are set to output a HI. For example, in the case of an
AND gate, if the inputs are both set to 1, the value of VOH is the voltage at the time of
the device outputs a 1. When performing VOH, it is important to have a sinking
current acting as a load. If the pins are unable to source enough current to match or
exceed the sinking current, the output voltage will decrease which indicates poor
output circuitry.
Voltage Output Low (VOL) is the maximum voltage required for an output LO
at load current. VOL is measured when the input pins are set to output a LO. In the
case of an AND gate, if the inputs are both 0, the value of VOL is the voltage at the
time the device output is 0. When performing VOL, it is important to have a constant
current sourcing into the output pin to act as the driving circuitry of another chip. If
the pin is unable to sink more current than is being source, the output voltage will be
significantly higher than 0 V. It is important to note the VOH ≠ VOL in order for the
device to not falsely switch between HIGH and LO with the presence of noise.
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circuitry for VOL [6]. When setting the input levels, 3.3 V is used for an input of 1
and 0 V is used for an input of 0. Different values may be specified in the data sheet
and should be used in place of the typical values.
3.3.5 Functionality
To perform a functionality test, the engineer must first understand how the
device is intended to operate. From there, either the HSDIO or SMU is used to force
the operation of the DUT. Typically an SMU is used for analog devices and an
HSDIO is used for digital devices. An SMU should always be used to power on the
device. When measuring the output, a simple indicator can be used to display a HI or
LO for digital chips. For an analog output, the voltage can be measured and displayed
to ensure proper functionality.
Before performing any test, a Test Plan should first be developed. The
intention of the Test Plan is to help guide the engineer while performing the tests. The
Test Plan is also used when anyone that is not familiar with the particular device
attempts to performs tests on said device. The Test Plan should include enough
information about the device that anyone could familiarize themselves enough to
perform all the tests described in the Test Plan. The following is a simple breakdown
of the items considered when developing a Test Plan:
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The final item of defending reasons for each decision is essential in the Test
Plan. All choices made have pros and cons. It is important that trade off studies be
made when it comes to considering items like instruments being used and number of
times to perform each test.
The Pin Map and Pin Map Application Program Interface (API) are essential
parts of testing using the STS. The Pin Map is used to make connections from the
DUT directly to the instruments being used. The Pin Map is created as an XML file
utilizing a specific schema. Within this file the following are defined [5] (Figure 3.7):
• Tester Resources
• Pins o DUT
• System pins
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DUT pins and system pins are defined first on the schema (Figure 3.7). Each
pin is defined by its name and associated with a single DUT. The pin name can be
anything, but it is best to use the name in the data sheet to avoid confusion. DUT pins
are associated with each test site where as system pins are associated with all test sites.
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Once all parameters are defined, it is time to make the connections of each pin
to the device resource. When defining the connection, start with the pin to connect.
Next, define the site the pin is connected to. Then, define the desired instrument.
Finally, define the instrument channel to complete the pin connection. Ensure all
names and numbers are the same as the definitions previously defined.
The Pin Map API is the connection between the created Pin Map and the test
program in LabVIEW. It can be found under TestStand Semiconductor Module menu
in the Functions tab (Figure 3.11) on the block diagram. The Pin Map API comes
complete with VI’s for NI-HSDIO, NI-DCPower, Radio Frequency instruments, and
Switching instruments. It also includes a “Get Pin Names” VI and a Publish Data VI.
Both are essential in programming the various tests and being able to view the data
from the tests after they are executed.
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Figure 19 Correlation Between Get All NI-HSDIO Instrument Names VI and Pin Map
[5]
The “Get Pin Names” VI (Figure 3.14) takes the SMC and outputs all the pin
names as defined in the Pin Map. There are separate outputs for DUT Pins and System
Pins. The output is a 1D array of strings. This array is then used as the input to the
“Pins to NI-HSDIO (or DCPower) Sessions” (Figure 3.15) to develop the channel list
needed for the HSDIO VI’s.
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The Pin Map API allows for several changes when programming a test. First,
the instrument name resource is defined by the Pin Map API and it no longer a control
or constant. Next, the instrument channels no longer are hard defined, but instead
defined by the Pin Map API. The initialization and closing of the HSDIO sessions also
no longer need to be defined as they will be done in a separate VI. Finally, the output
measurement is not a simple indicator, but instead reported using the “Publish Data”
VI with the pin name associated to each value.
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Within the sequence, there are three test groups: Setup, Main, and Cleanup.
Setup contains steps that initialize the instruments that will be used. Main contains all
the steps of the tests that are to be performed. Cleanup contains all steps that reset and
close down all the devices initialized in Setup.
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The High Limit and Low Limit are values as defined by the engineer, typically
found in the data sheet. These values are used to determine if the pin pass or failed.
When defining the limits, only put a numerical value into the field. Next, select the
scaling factor from the drop down menu, and finally input the unit being measured.
The limit fields will automatically be populated by the scaling factor and unit.
When defining the test permeates, some engineers may find it more convenient
to use a program such as Microsoft Excel to more quickly define each test. To do so,
simply go to the Semiconductor Module tab at the top of TestStand and select “Export
Test Limits from [Sequence Name]”. From there the engineer can open the test limits
in Excel and edit it as they wish. It is important to stick with the format of the opened
file (Figure 3.19). It is suggested to define at least one limit before exporting the file to
edit. Once complete, select “Import Test Limits to [Sequence name]”
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CHAPTER IV
COURSE EVAUATION
4.1 Assessment
In the fall 2014 semester, ten students were enrolled in the course. With that
being the case, the ELO’s were met using a project based approach. First, an exam to
demonstrate the ability to design tests in LabVIEW using NI-HSDIO to meet ELO’s 1,
3, 4, and 5. The average for the first exam was a 90. A final project was assigned to
use the STS ATE to perform all tests discussed in class using TestStand, TSM, and
LabVIEW on a logic gate. The final exam was designed to meet ELO’s 1-6. The
average of the final exam was an 87. Two Quizzes were also given to meet ELO’s 5
and 6. The class average of both quizzes was a 95. The final average in the class was a
94, with all students earning an A for the semester.
The spring semester had thirty-five students enrolled in the course. After the
lengthy amount of time to arrange the first exam project for only ten students, it was
clear another assessment model had to be developed. First, two quizzes and a written
exam were administered to meet ELO’s 4-6. The class average for the written exam
was an 87. The class average of both quizzes was an 86. After the first exam, quizzes
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were given daily in class to meet ELO’s 1-3. Because the material was brand new to
the students, the quiz answers were discussed in class and the student received a
participation grade. The same final project was assigned to the spring semester class to
meet ELO’s 1-6. The project is still in works and the results are pending.
In the fall semester, students enrolled in the course took a course and instructor
evaluation survey. The students were was three questions:
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4
Question 1
3 Question 2
Question 3
2
0
Strongly Agree Agree Neutral Disagree Strongly
Disagree
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The course had proven quite popular to students wishing to learn advanced
methods in semiconductor testing and it continually requested to be taught another
semester since some students were unable to take it when offered. Currently, a student
from the fall 2014 semester is tutoring the class. His knowledge and ability to assist
the students in the spring 2015 semester had prepared him to take over instructor the
course in the fall 2015 semester. The course has also brought more attention to the
structure of the semiconductor testing curriculum at Texas Tech. Students are
requesting a stronger emphasis on equipment training mixed with testing theory. The
PSPE faculty and senior students are in works to incorporate the hands on training into
the curriculum.
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CHAPTER V
CONCLUSION
The technological world is always changing, and it is the goal of academia to
prepare students for all the changes. With the introduction of brand new state of the art
equipment, it is the responsibility of instructors to introduce and train students so they
can be prepared for new industry standards. The STS is just one piece of technology
students will be tasked to use when they move onto their jobs into the semiconductor
field. The main focus of the PSPE is to bridge the gap between academia and industry.
It is also the focus of this course to give students a chance to learn new equipment
being quickly adopted by their field, and give them a leg up in the job market. One
student from the fall 2014 semester landed an interview based on their work with the
STS.
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BIBLIOGRAPHY
[1] “NI Semiconductor Test Systems – National Instruments.” [Online] Available:
http://www.ni.com/pdf/niweek/us/STS_Flyer.pdf
http://en.wikibooks.org/wiki/Analogue_Electronics/pn_Junctions
https://learn.sparkfun.com/tutorials/diodes/real-diode-characteristics
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APPENDIX A
SYLLABUS
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