CSE205 - Computer Architecture and

Organization (CAO)

INTERRUPTS

Jimmy Mathew
Assistant Professor Senior,
School of Computing Science & Engineering (SCSE),
VIT University, India
Email: jimmym@vit.ac.in / Office: SJT-313-A08
 Reference textbooks
• [1] W. Stallings, “Computer organization and architecture”, Prentice-
Hall, 8th edition, 2009.

• [2] M. M. Mano, “Computer System Architecture”, Prentice-Hall, 3rd

Edition, 1992.

• [3] J. P. Hayes, “Computer system architecture”, McGraw Hill, 3rd

Edition, 2002.

• [4] John L. Hennessy and David A. Patterson, “Quantitative Approach –

Computer Architecture”, Morgan Kaufmann Publishers, 5th edition, 2011.

CAO Chapter 1.6 JMW VIT-U 2

 INTERRUPTS – FEATURES, TYPES

CAO Chapter 1.6 JMW VIT-U 3

 Interrupts
• Interrupts – Signal from external world

• Maskable Vs Non-maskable

• Hardware interrupts Vs software interrupts

• Processor sleep – wakeup using interrupts

• Button press

• Emergency shut down switch

• Burglar alarm

• “Embedded system is driven by interrupts”

CAO Chapter 1.6 JMW VIT-U 4

 Interrupts
• Three terms: Interrupt latency, interrupt response, interrupt recovery

CAO Chapter 1.6 JMW VIT-U 5

 Interrupts
• INTR pin

• Context save

• Interrupt vector table

• Interrupt Service Routine

• ISR execution

• Context restore

• Nested interrupts

CAO Chapter 1.6 JMW VIT-U 6

 Interrupts
• Interrupts have assigned priority

• NMI – Non Maskable Interrupt – the highest priority interrupt

• A group of devices may have same priority (For example: Multiple channels of
DMA)

• A microcontroller may have up to 255 priority levels

CAO Chapter 1.6 JMW VIT-U 7

 Interrupts
• Level triggered interrupts

• Edge triggered interrupts

CAO Chapter 1.6 JMW VIT-U 8

CSE205 - Computer Architecture and
Organization (CAO)

INTERRUPTS

Jimmy Mathew
Assistant Professor Senior,
School of Computing Science & Engineering (SCSE),
VIT University, India
Email: jimmym@vit.ac.in / Office: SJT-313-A08

1
1
 Reference textbooks
• [1] W. Stallings, “Computer organization and architecture”, Prentice-
Hall, 8th edition, 2009.

• [2] M. M. Mano, “Computer System Architecture”, Prentice-Hall, 3 rd

Edition, 1992.

• [3] J. P. Hayes, “Computer system architecture”, McGraw Hill, 3 rd

Edition, 2002.

• [4] John L. Hennessy and David A. Patterson, “Quantitative Approach –

Computer Architecture”, Morgan Kaufmann Publishers, 5 th edition, 2011.

CAO Chapter 1.6 JMW VIT-U 2

2
2
 INTERRUPTS – FEATURES, TYPES

CAO Chapter 1.6 JMW VIT-U 3

3
3
 Interrupts
• Interrupts – Signal from external world

• Maskable Vs Non-maskable

• Hardware interrupts Vs software interrupts

• Processor sleep – wakeup using interrupts

• Button press

• Emergency shut down switch

• Burglar alarm

• “Embedded system is driven by interrupts”

CAO Chapter 1.6 JMW VIT-U 4

4
4
 Interrupts
• Three terms: Interrupt latency, interrupt response, interrupt recovery

CAO Chapter 1.6 JMW VIT-U 5

5
5
 Interrupts
• INTR pin

• Context save

• Interrupt vector table

• Interrupt Service Routine

• ISR execution

• Context restore

• Nested interrupts

CAO Chapter 1.6 JMW VIT-U 6

6
6
 Interrupts
• Interrupts have assigned priority

• NMI – Non Maskable Interrupt – the highest priority interrupt

• A group of devices may have same priority (For example: Multiple channels of
DMA)

• A microcontroller may have up to 255 priority levels

CAO Chapter 1.6 JMW VIT-U 7

7
7
 Interrupts
• Level triggered interrupts

• Edge triggered interrupts

CAO Chapter 1.6 JMW VIT-U 8

8
8