IEEE Instrumentation and Measurement

Technology Conference
Budapest, Hungary, May 21-23,2001

Low power implementation of a Sigma Delta decimation filter for cardiac

applications
L. Ascari, A. Pierazzi, C. Morandi
Dip. Ingegneria dell’hformazione
University of Parma, Viale delle Scienze 181/A, 43100 Parma, ITALY
Ph. +39-0521-905814, Fax. +39-0521-905822, E-mail: ascari@ieee.org

Abstract - This paper reports on two main issues: low power architectures
for decimation filters, and simulation toolsfor their RTL-level power estima-
tion.
The final aim is the design of a decimator filter for a CA ADC, used in a
pacemaker: in this field of application, the main request is a lowest power
consumption, in order to preserve the batteries.
First, state-of-the-art designs arepresented, in order to choose the most suit-
able architectures for this purpose.
Matlab was used to achieve the desired performances, in terms of EA or-
der and sampling frequency, and to find the decimation ratio. Up to now
three architectures were selected and implemented (at RTL level): the clas-
sic Hogenauer’s CIC (Cascade of Integrators Comb) structure and two
polyphase M u h Stage Multi Rate structures. All the topologies were im-
plemented in AHDL language and simulated in CADENCE environment,
to obtain a comparison in terms of the power dissipation, by adding for ev-
ery block a power estimation feature. The results of these simulations are
reported.
KEYWORDS
Power estimation, EA decimation, low power design.
I. INTRODUCTION
Power dissipation is an issue of great concem in body im-
plantable devices, such Pacemakers. The less current absorp-
tion, the longer the mean time between battery change: if this
is not so much important for extemal devices, like hearing aids,
it’s essential for internal circuits, like pacemakers.
This paper deals with the acquisition and digitization of car-
diac signal. Thanks to the narrow bandwidth of cardiac sig-
nals (50-150 Hz), oversampling techniques are advantageous
in terms of Signal to Quantization Noise ratio; in fact there are
many other noticeable features that make these techniques in-
teresting, like the possibility of using common and cheap digi-
tal components instead of more expensive and accurate analog
ones.
The chosen ADC is a EA Converter: it is formed by two main
blocks: the modulator and the decimator. The modulator has a
third order CRFBD (Cascade of Resonators, FeedBack form,
Delaying quantizer) architecture [?I; it oversamples the input
signal at fs = 8192Hz, producing a two level digital output.
The high frequency signal coming from the modulator will be
converted into a multilevel signal at lower frequency by the
decimator: fs decreases by 16 times, reaching the value of
512Hz and the amplitude resolution increases from 1 bit to
10 bits.
In this work the attention is focused on the decimator circuit,
being that the modulator has been designed at Padua University
( his power consumption is 1.4pW) E?]. The decimator is the
most area and power consuming subsystem in the converter.
Designers have the choice among many different architectures
implementing the same decimator, having very different per-
formances in terms of circuit complexity, area occupation and
power dissipation. So the choice of the architecture is a deli-
cate task.
A method allowing a first rough quantitative estimation of the
power dissipation of a certain architecture would be of great
help in this phase. The designer could compare different archi-
tectures and implement at circuital level only the best one.
This work presents such a method, applied on three architec-
tures: the classic Hogenauer’s CIC (Cascade of Integrators
Comb) architecture and two Polyphase (PP) ones.
11. PRELIMINARIES
A. Architectures
The transfer function of a typical sinck decimator is:
This function can be implemented by means of single rate sin-
gle stage filters, but this solution is indicated only for low Deci-
mation factors D and low filter order k ; for higher D and k , cir-
cuit complexity and power consumption increase fast: in fact,
all the parts into the filter operate at high frequency (fg).
A better solution is the use of multi-stage multi-rate archi-
tectures. They are based on the commutative rule: a generic

02001 IEEE
0-7803-6646-8/01/$10.00

750
H ( z D )is equivalent to a system consisting of a downsam- sine4 2048Hz sine4 512Hz
pler, whose decimation factor is D, followed by the trans-
): : :(: :
fer function H ( z ) . In this way, H ( z ) ’= can be
split in two sections: a cascade of k integrators implement-
ing H I ).( = (&)‘ and a cascade of k combs implement-
ing H~(z) = (1 - 2-l)’. The integrator and comb sections In this way, considering only one of the two decimation stages:
are separated by a downsampler, with a decimation factor D.
This is the’Hogenauer’s CIC architecture [?I. Its main posi- H ( Z ) = (1 +~ - l ) ~ ~ - 7 ~
(i+
tive characteristics are the high regularity and the absence of
multipliers and storage elements; but when the filter order or which can be implemented using the commutative rule, bring-
the decimation factor become high, these drawbacks appear: ing to the configuration of fig. 3:
the intemal word-length of the integrator section is large and
power consumption increases because this section operates at
high input oversampling frequency and with large word-length;
another effect is that the highest sampling rate is limited by the
high word-length, but not in this case, being the frequencies Figure 3. Principle of implementation of a s2nc4 block
involved very low.
By using polyphase decomposition, the block (1 + z-1)4 can
Hogenauer’s CIC decimation filter structure is represented in be expressed as:
fig. 1.
+ +
(1 z - ’ ) ~ = (1 62-2 z - ~ ) zP1(4 + + + 4z-’)
+
= E1(z2) Y 1 E 2 ( z 2 ) .

In this way E l ( z ) and E2(z) can be implemented, at a lower

frequency, instead of E1(z2) and E2(z2). To limit power
consumption in the realization of El (2) and E2 ( z ) ,multipli-
ers must be avoided, and substituted by shift-and-add opera-
tions. For instance, the coefficient 6 has been implemented as
+ +
4 2 = 22 2, by means of one “add” and two “shift”. In fig.
4 the architecture of the proposed decimator is reported.

Figure 1. Realization of Hogenauer’s CIC decimator with integrator and

comb sections. fie
I

Out@512Hz

Better results in terms of power consumption are obtained us-

ing multirate architectures. Starting from the same Transfer
Function, but performing different manipulations, we arrived
at the architectures described below.

A. 1 First Polyphase structure

First of all, recursive path are eliminated, expressing H ( z ) in

a “non recursive” form:
D-1 -n
H(z)= (Cn=o 1 Figure 4. Architecture of our low power decimator.
= (1 + .-1)’(1+ z-2)‘ . . . . . (1 + .-2+’)k
A.2 Second Polyphase structure
where D = 2 M .

The decimation factor must be 16 and was implemented by the Starting from ~ ( z=) = (1 + 2-1 + 2 - 2 + z - ~ ) ~ ,
cascade of two sinc4 stages, each having a decimation factor in some passages we arrive at:
of 4: as a consequence, D=4. The scheme of the decimator is
reported in fig. 2.
~ ( z=)~ ~ ( + Z - ~ E ~ ( +Z ~z -) ’ E ~ ( z ~+) z - ~ E ~ ( z ~ )
2 ~ )

75 1
where
The corresponding architecture is reported in fig. 5.
In @ 8192 Hz
sinc4 sinc4
Out @ 512 Hz
Each of FIR filters El(z), E2(z), E3(z),E4(z), was imple-
mented using the rules presented in the previous paragraph to
reduce power consumption: no multipliers were used, coeffi-
cients were implemented as sum of power-of-two numbers; in
addition, a technique known as Substructure Sharing was in-
troduced in this architecture: simply speaking, it consists of
the re-use of part of the circuitry involved in the realization of
a multiplicative coefficient, to implement another coefficient.
As an example, the structure of E3(z) was reported here, in
fig.6. In order to obtain the coefficient 44 we have multiplied
Figure 6. Architecture of the FIR filter E 3 ( z ) .
by 4 the output of the structure used for the coefficient 10, and
added 4 to it. This is the so-called “Substructure Sharing”.
In this second Polyphase architecture, registers and adders
work at a rate 2 times slower than in the first one, because
of the downsampling by 4 at the input. On the other side, the
number of filters to be implemented ( E i ( z ) )has increased. It’s
a difficult task to preview which of the last two architectures
consumes the less. That’s why a system to compare their per-
formances in advance is important.
B. Low Level Implementation
Substantial power savings can be made also in the low-level
implementation of the previous architectures. At first, the logic
chosen to implement adders must be presented.
-
Being the fact that glitches are responsible of a wasteful power
consumption, we looked for logic families not allowing glitch
propagation. We focused our attention on dynamic precharge-
evaluation CMOS logic, using a 4-phase clock. Effectively,
glitches don’t propagate, but the slow clock rates at which the
decimator must work cause high-level voltage droop; the re-
fresh rate is not high enough.
So we decided to use a static CMOS logic, which isn’t afflicted
by the problems of dynamic logics at low rates.
B . l Glitches
The filter being designed has a clocked architecture, which
means that glitches don’t cause wrong outputs; their effect is
nevertheless a great increase in power dissipation. The solu-
tion adopted to this problem is the use of clocked adders: if
an adder performs the sum in correspondence of a rising clock
edge, the following adder is sinchronized with the subsequent
falling clock edge, when its input are stabilized. An example is
..
reported in fig.7, in which a possible implementation of E4(z)
is represented.
g&
Figure 7. Architecture of the FIR filter E4(z).
A consequence of this choice is that delay elements of 0.5 and
1.5 clock periods are to be designed, in order to preserve the
correct synchronization.
Another effect is that simpler adder architectures can be used:
in fact we can adopt a minimal covering of the Karnaugh map,
using a minor number of transistors. Glitches don’t have the
possibility to propagate across the structure, thanks to the tim-
ing of adders and delay elements.
FIR filters El(z), E2(z),E 3 ( z ) ,E4(z) have different laten-
cies, so attention must be posed on synchronization of their
outputs before the final adders (see fig.5): the final architecture
is reported in fig.8.
752
 In @ 8192 Hz
sinc4
Out @ 512 Hz
Figure 8. Second Polyphase architecturewith added delay elements for
synchronization.
The total latency of the architecture implementing sinc4 block
is 3Tck, where Tck is the clock period.
B.2 Adders
Referring to the last two architectures, the first block has a
characteristic that allows saving much power: its input is a one-
bit word. This means that many adders can be eliminated and
substituted by ad-hoc wiring solutions. As an example, let’s
consider the block implementing E3(z) in the last architecture
(see fig.9). As it can be seen from the figure, only 2 adders are
-
C. Power Consumption Estimate
A number of different approaches to estimate power consump-
tion were developed by others ([?I [?I). Here several of them
are presented, focusing the attention on those referring to Reg-
ister Transfer abstraction level. At this level the primitives are
functional blocks, such as adders, multipliers, registers. The
difficulty in estimating power in this case stems from the fact
that the gate, circuit and layout level details of the design may
not have been specified yet. The strategies proposed for RT-
level power estimation can be divided in two classes: analytical
and empirical methods [?I.
C. 1 Analytical Methods
Analytical methods attempt to relate power consumption of a
particular RTL description to fundamental quantities that de-
scribe the physical capacitance and activity of a design. Con-
cepts belonging to these procedures are gate equivalents (GE),
used in the technique called CES (Chip Estimation System),
Entropy, used by Najm [?] as an estimate of the activity of a
cell, Area, as an estimate of the capacitance.
These methods have the advantage of requiring little informa-
tion as input; on the other hand, no timing information enter the
calculation and, therefore, glitching power isn’t accounted for.
In CMOS, power dissipation is highly dependent on switching
and glitching activity. Therefore, power predictions based on
these techniques may not have a strong relation to real hard-
ware. To solve these problems empirical methods can be used.
C.2 Empirical Methods

These methods measure the power consumption of existing im-

plementations and produce a model based on those measure-
ments. This approach is best suited for library-based approach,
~ ~ i , ~ ~ ~ ~ ~ ! - ! ! ~ it’s
but - not, necessary,
~ ~ if a~ ballpark
~ .estimate- ~of the power can
-. .._
- -.- -,.
~ ..
be acceptable. This category of models can be divided in those
assuming fixed signal activity and those trying to take into ac-
count the dependence of the circuit activity on the input sig-
nals. Power Factor Approximation (PFA) method belongs to
the first group, while ESP method belongs to the second one
[?I. The latter divides total power in a fixed component and
in a component proportional to the number of bit transitions of
the input vector.
Figure 9. To realize E 3 ( z ) ,only a one-bit adder and one 5-bits adder (both
with carry-out) are necessary.
111. RESULTS

necessary (S3 and S4) of the four represented: moreover, in the
case of S3, even if the words to be added are 6-bits long, a 1-bit
adder with carry out is sufficient; in the case of S4, bacause of
the particular configuration of the input words, a 5-bits adder
with carry out is required.
These optimizations can be operated only in the first block: in
fact the input word-length of the second block is higher (see
fig.4 and 5).
A very simple tool to compare power dissipation for different
architectures was implemented. It was applied on all the struc-
tures mentioned above.
In fact the high efficiency in terms of power consumption of
the Polyphase realization is clear and doesn’t need any proof,
because of the elimination of recursive loops, the reduction of
the high frequency operating circuitry, the slightly increasing
of the internal word-length. In such a case the power estimate

753
is useless; nevertheless its importance grows fast in case of
comparison of slightly different architectures as in the case of
the second and third structure.
In this case it would be interesting to know in advance which
architecture is the less consuming, in order to concentrate de-
sign efforts over it: optimizations and trade-offs could be in-
troduced very early in the design flow. The “power estimator”
will help in such a choice. Another advantage of architecture-
level tools over lower level ones is the simulation speed, due to
the lower model complexity of the former [?I.
A. Power Dissipation Estimate
The approach to power simulation is simpler than those listed
in section 11-C; it takes ideas from several of them, as it at-
tempts to take into account the switching and glitching activ-
ity, the word-length in the different blocks, the activation rate
of the blocks. The main topic is relative comparisons between
architectures, not in the absolute value of power consumption.
For this reason, capacitances are eliminated from the calcu-
lus, preferring a simple “activity” measure of the system under
test. This is a measure of the computational complexity of the
architecture.
Let’s examine a simple block: it has inputs and output: the
output is a function of the history of inputs values. Every tran-
sition of the input and the output is considered, to obtain the
estimated power request. Such method was used in case of
adders, shift registers and so on, but not for multipliers.
Power consumption of multiplication blocks was neglected be-
cause every coefficient is decomposed in the sum of power-of-
two coefficients, which are implemented by bit-shifts. Further-
more the shifts are only ideal, because in practice it will be suf-
ficient to connect the bit-line inputs to the following adder in
the correct position. Moreover, power consumption of adders
in the second and third architecture is computed accordingly
with the real word-lengths: for example, referring to fig.9, S1
and S2 don’t absorb any current, whereas S3 and S4 absorb a
current proportional to 1 and 5 bit respectively.
An approximate estimate of the “activity” of the designed ar-
chitecture is obtained; the rate at which the different blocks
operate, and glitch activity are taken into account.
The formula used to compute activity until time T is:
where A stands for “activity”, as defined above, and N is the
total number of blocks in the architecture. To clarify this con-
cept, let’s take a 4-bits adder, as reported in fig. 10. The inputs
+
at t = i and t = i 1 are reported, as well as the correspond-
ing outputs. The arrows indicate the positions of changing bits.
154
During this clock period 4 bit change, and this is the quantity
we have considered as an activity indication in this time step.
A counter stores all these changes in all the adders and reg-
isters of the structure under test, during all the simulation pe-
riod. The structure letting the counter work has been embed-
ded in the AHDL code describing adders and regiters: the en-
tering words (whose length is passed to the block as parame-
ter) are logically XORed with the corresponding previous ones
(stored in local variables), as well as the output word, and then
ones are counted and stored. This is repeated at each clock
edge by which the block is activated. The language in which
blocks were implemented was SpectreHDL and simulations
took place in CADENCE SpectreS.
t=i+l
vv
00 11 0110
v ’
t=i 1001 0100
. . . . -
t=i
t=i+l 10 Power=2+1+1=L
1 10 1
1
Figure 10. Example of the implemented Activity estimation tool, applied to a
4-bits adder.
One problem of this test procedure is that results are highly
pattern-dependent. Nevertheless this is not a real problem be-
cause of the physical characteristics of a general EA modu-
lated signal, consisting of a high-rate sequence of Is and Os.
In fig. 11 are reported the results for all the architectures men-
tioned above. As expected, the complexity levels of the CIC
architecture and the Polyphase architectures are very different;
between the two Polyphase structures, the last is the less con-
suming one.
IV. NOVELTIES
This work tends to compare similar low-power architectures
for decimator filters at Register Transfer Level, from a power-
consumption point of view. Keeping the decimation factor
and the high-level structure (fig. 2) of the filter fixed, several
tradeoffs between lowering filter operating frequency and filter
complexity can be rapidly compared.
A fast but accurate evaluation of computational power con-
sumption for decimation filters at RTL was presented, espe-
cially in case of similar low-power multi-rate solutions.
An approximate estimation of the activity, according the rate at
which the different blocks operate, comprehending the glitch
activity, is obtained.
 References
a: Activity-Polyphose2 o : Activity-Polyphasel
60K - : Activity-CIC [l] R. Schreier, The Delta-Sigma Tooboz 5.1. A n a l o g B vices Inc,
April 1998.
[2] A.Gerosa, A.Novo, and A.Neviani, “h -paver sensing and dig-
50K
itization of cardiac signals based on sigmadel ta conversion,”
Proceedings of the 2000 International Symposium on Low Power
40K Electronics and Design, Jul y 2000
,--. [3] Y Gao,L . Jia, and R e n h u n e n y h -complexity high-speed
30K decimation fi ters,” Proceedings of the 8th International Sym-
v posium on Integrated Circuits, Devices and Systems (ISIC’SS),
20K Septemher 1 999.
[4] F. N.Ngm,“ A survey of pKer esti mation techniques in tisi
10K circuits,” IEEE ’Bansactions on Very Large Scale Integration
( V L S I ) S y s t q s vol. 2,Decenber 1 994.
[5] PLandmaIfyi gh-level pwer esti mation,” Proceedings of the
0.0 International Symposium on Low Power Electronics and De-
0.0 30m 60m 90m
time ( s ) sign, August 1996.
[6] PE . Landmadow-Power Archi tectural Design Methodologies
PhD thesi s, UC EM ey, 1994.

Figure 11. Comparison between the computational complexity of the three

architectures considered: Hogenauer’s CIC (“CIC”), Polyphase1 and
Polyphase2; the input signal rate is 1OOps.

755