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ERRATA
Please e-mail comments and errors to milos@cs.ucla.edu
(page 109): Figure 4.23: Reorder the outputs (z_3 on top, etc.)
(page 138): Figure 5.18: Change c' to c at the bottom line with a transistor and in the expression
for z which should read z = ((a+b) + c)' = (a+b)c'
(page 238): Figure 8.45: The outputs should be labeled with z_1 and z_0
(page 392): Exercise 13.2: Change ``x" to ``a" and ``y" to ``w"
(page 396, line 7): Exercise 13.14: Move the right parenthesis after ``... details".
(page 393): Exercise 13.5: Correct the subscript of z on the left-hand side of the equation: it should be i+1
(page 428): Exercise 14.2: Exchange ``j" and ``i" in the expression for T
(page 431): Exercise 14.10: Replace ``Section 14.4.5" with ``Example 14.3"; ``adder" with ``ALU"
(page 432): Exercise 14.12: Move line with ``i:=i+1" after END IF;
(page 433): Exercise 14.13: Add a reset line to the module; also
(page 498, line 25): Correct ``thruth table" to ``truth table"; move after line 45
Errata corrected in the third printing
(page 58): Exercise 2.50: Eliminate the hint
(page 93): Figure 4.7(b): Add ``x1x0" at the output of the rightmost NAND gate
(page 102, line 8): Change the sentence ``Due to ..." to ``We illustrate the computation of the delay for the
path"
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(page 138): In Figure 5.18, change the rightmost expression for w to ... = (a+c)(b+c')
(page 186): In Figure 7.16: the bit strings under states S4, S5, and S6 should be in bold
(page 275): In caption for Figure 9.39: ``Exercise 9.24" change to ``Exercise 9.23"
(page 303, paragraph 8, line 2): Change ``6 x 4" to ``8 x 6"
(page 306): In Figure 10.20: the module in the middle: ``Binary Decoder" change to ``Binary Encoder"
(page 311,paragraph 1, line 6): Change ``... in Chapters 12 ... `` to ``... Chapter 13 to ..."
(page 335): Exercise 11.12: should refer to Exercise 11.11 and not to Exercise 11.10
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