GITAM UNIVERSITY

(Declared as Deemed to be University U/S 3 of UGC Act, 1956)

REGULATIONS & SYLLABUS

OF

M.Tech. (VLSI Design)

(w.e.f 2008 -09 admitted batch)

Gandhi Nagar Campus, Rushikonda

VISAKHAPATNAM – 530 045
Website: www.gitam.edu
 REGULATIONS
(w.e.f. 2008-09 admitted batch)

1.0 ADMISSIONS

1.1 Admissions into M.Tech (VLSI Design) programme of GITAM University are governed
by GITAM University admission regulations.

2.0 ELIGIBILTY CRITERIA

2.1 A pass in B E / B Tech / AMIE or equivalent in ECE / EIE / EEE / CSE / IT/ICE

2.2 Admissions into M.Tech will be based on the following:

(i) Score obtained in GAT (PG), if conducted.

(ii) Performance in Qualifying Examination / Interview.

The actual weightage to be given to the above items will be decided by the authorities
before the commencement of the academic year. Candidates with valid GATE score shall
be exempted from appearing for GAT (PG).

3.0 STRUCTURE OF THE M.Tech. PROGRAMME

3.1 The Programme of instruction consists of:

(i) A core programme imparting to the student specialization of engineering branch

concerned.
(ii) An elective programme enabling the students to take up a group of departmental
courses of interest to him/her.
(iii) Carry out a technical project approved by the Department and submit a report.

3.2 Each academic year consists of two semesters. Every branch of the M.Tech programme
has a curriculum and course content (syllabi) for the subjects recommended by the Board
of Studies concerned and approved by Academic Council.

3.3 Project Dissertation has to be submitted by each student individually.

4.0 CREDIT BASED SYSTEM

4.1 The course content of individual subjects - theory as well as practicals – is expressed in
terms of a specified number of credits. The number of credits assigned to a subject
depends on the number of contact hours (lectures & tutorials) per week.

4.2 In general, credits are assigned to the subjects based on the following contact hours per
week per semester.

One credit for each Lecture hour.

One credit for two hours of Practicals.
Two credits for three (or more) hours of Practicals.
 4.3 The curriculum of M.Tech programme is designed to have a total of 70 -85 credits for the
award of M.Tech degree. A student is deemed to have successfully completed a particular
semester’s programme of study when he / she earns all the credits of that semester i.e., he
/ she has no ‘F’ grade in any subject of that semester.

5.0 MEDIUM OF INSTRUCTION

The medium of instruction (including examinations and project reports) shall be English.

6.0 REGISTRATION

Every student has to register himself/herself for each semester individually at the time specified by
the College / University.

7.0 CONTINUOUS ASSESSMENT AND EXAMINATIONS

7.1 The assessment of the student’s performance in each course will be based on continuous
internal evaluation and semester-end examination. The marks for each of the component
of assessment are fixed as shown in the Table 2:

Table 2: Assessment Procedure

S.No. Component of Marks allotted Type of Scheme of Examination

assessment Assessment
(i) Two mid semester
examinations shall be
conducted for 10 marks each.
(ii) Two quizzes shall be
40 Continuous conducted for 5 marks each.
evaluation (iii) 5 marks are allotted for
1 Theory assignments.
(iv) 5 marks are allotted for
attendance
The semester-end examination
Semester-end in theory subjects will be for a
60 examination maximum of 60 marks.
Total 100
(i) 40 marks are allotted for
record work and regular
performance of the student in
the lab.
Continuous (ii) One examination for a
2 Practicals 100 evaluation maximum of 20 marks shall be
conducted by the teacher
handling the lab course at the
middle of the semester
(iii) One examination for a
maximum of 40 marks shall be
conducted at the end of the
semester (as scheduled by the
Head of the Department
concerned).
 (i) 50 marks are allotted for
continuous evaluation of the
project work throughout the
3 Project work 100 Project evaluation semester by the guide.
(ii) 50 marks are allotted for the
presentation of the project work
& viva-voce at the end of the
semester.*
Comprehensive 100 marks are allotted for
Viva 100 Viva-voce comprehensive viva to be
5 conducted at the end of
programme.*
* Head of the Department concerned shall appoint two examiners for conduct of the examination.

8.0 REAPPEARANCE

8.1 A Student who has secured ‘F’ Grade in any theory course / Practicals of any semester
shall have to reappear for the semester end examination of that course / Practicals along
with his / her juniors.

8.2 A student who has secured ‘F’ Grade in Project work shall have to improve his report and
reappear for viva – voce Examination of project work at the time of special examination
to be conducted in the summer vacation after the last academic year.

9.0 SPECIAL EXAMINATION

9.1 A student who has completed the stipulated period of study for the degree programme
concerned and still having failure grade (‘F’) in not more than 5 courses ( Theory /
Practicals), may be permitted to appear for the special examination, which shall be
conducted in the summer vacation at the end of the last academic year.

9.2 A student having ‘F’ Grade in more than 5 courses ( Theory/practicals ) shall not be
permitted to appear for the special examination.

10.0 ATTENDANCE REQUIREMENTS

10.1 A student whose attendance is less than 75% in all the courses put together in any
semester will not be permitted to attend the end - semester examination and he/she will
not be allowed to register for subsequent semester of study. He /She has to repeat the
semester along with his / her juniors.

10.2 However, the Vice Chancellor on the recommendation of the Principal / Director of the
University college / Institute may condone the shortage of attendance to the students
whose attendance is between 66% and 74% on genuine medical grounds and on payment
of prescribed fee.

11.0 GRADING SYSTEM

11.1 Based on the student performance during a given semester, a final letter grade will be
awarded at the end of the semester in each course. The letter grades and the
corresponding grade points are as given in Table 3.
 Table 3: Grades & Grade Points

Grade Grade points Absolute Marks

O 10 90 and above
A+ 9 80 – 89
A 8 70 – 79
B+ 7 60 – 69
B 6 50 – 59
C 5 40 – 49
F Failed, 0 Less than 40

11.2 A student who earns a minimum of 5 grade points (C grade) in a course is declared to
have successfully completed the course, and is deemed to have earned the credits
assigned to that course. However, a minimum of 24 marks is to be secured at the semester
end examination of theory courses in order to pass in the theory course.

12.0 GRADE POINT AVERAGE

12.1 A Grade Point Average (GPA) for the semester will be calculated according to the
formula:
Σ[Cx G]
GPA = ----------------
ΣC
Where
C = number of credits for the course,
G = grade points obtained by the student in the course.

12.2 Semester Grade Point Average (SGPA) is awarded to those candidates who pass in all the
subjects of the semester.

12.3 To arrive at Cumulative Grade Point Average (CGPA), a similar formula is used
considering the student’s performance in all the courses taken in all the semesters
completed up to the particular point of time.

12.4 The requirement of CGPA for a student to be declared to have passed on successful
completion of the M.Tech programme and for the declaration of the class is as shown in
Table 4.

Table 4: CGPA required for award of Degree

Distinction ≥ 8.0*
First Class ≥ 7.0
Second Class ≥ 6.0
Pass ≥ 5.0

* In addition to the required CGPA of 8.0, the student must have necessarily passed all the courses of
every semester in first attempt.
13.0 ELIGIBILITY FOR AWARD OF THE M.Tech DEGREE

13.1 Duration of the programme:

A student is ordinarily expected to complete the M Tech. programme in four semesters of
two years. However a student may complete the programme in not more than four years
including study period.

13.2 However the above regulation may be relaxed by the Vice Chancellor in individual cases
for cogent and sufficient reasons.

13.3 Project dissertation shall the submitted on or before the last day of the course. However,
it can be extended up to a period of 6 months maximum, with the written permission of
the Head of the Department concerned.

13.4 A student shall be eligible for award of the M.Tech degree if he / she fulfils all the
following conditions.

a) Registered and successfully completed all the courses and projects.

b) Successfully acquired the minimum required credits as specified in the curriculum
corresponding to the branch of his/her study within the stipulated time.
c) Has no dues to the Institute, hostels, Libraries, NCC / NSS etc, and
d) No disciplinary action is pending against him / her.

13.5 The degree shall be awarded after approval by the Academic Council.
 RULES
1. With regard to the conduct of the end-semester examination in any of the practical courses of the
programme, the Head of the Department concerned shall appoint one examiner from the
department not connected with the conduct of regular laboratory work, in addition to the teacher
who handled the laboratory work during the semester.

2. In respect of all theory examinations, the paper setting shall be done by an external paper setter
having a minimum of three years of teaching experience. The panel of paper setters for each
course is to be prepared by the Board of Studies of the department concerned and approved by the
Academic Council. The paper setters are to be appointed by the Vice Chancellor on the basis of
recommendation of Director of Evaluation / Controller of Examinations.

3. The theory papers of end-semester examination will be evaluated by two examiners. The
examiners may be internal or external. The average of the two evaluations shall be considered for
the award of grade in that course.

4. If the difference of marks awarded by the two examiners of theory course exceeds 12 marks, the
paper will have to be referred to third examiner for evaluation. The average of the two nearest
evaluations of the three shall be considered for the award of the grade in that course.

5. Panel of examiners of evaluation for each course is to be prepared by the Board of Studies of the
department concerned and approved by the Academic Council.

6. The examiner for evaluation should possess post graduate qualification and a minimum of three
years teaching experience.

7. The appointment of examiners for evaluation of theory papers will be done by the Vice
Chancellor on the basis of recommendation of Director of Evaluation / Controller of
Examinations from a panel of examiners approved by the Academic Council.

8. Project work shall be evaluated by two examiners at the semester end examination. One examiner
shall be internal and the other be external. The Vice Chancellor can permit appointment of second
examiner to be internal when an external examiner is not available.

9. The attendance marks (maximum 5) shall be allotted as follows:

Percentage of Attendance Marks

76% to 80% 1
81% to 85% 2
86% to 90% 3
91% to 95% 4
96% to 100% 5
 SYLLABUS
M.Tech (VLSI Design)
Programme Code: EPRVD 200801
I Semester
Course Name of the Course Credits Hours per Continuous Semester End Total
Code Week Evaluation Examination Marks
EPRVD101 VLSI Technology* 4 4L 40 60 100
EPRVD102 Digital IC Design 4 4L 40 60 100
EPRVD103 Digital Logic Design* 4 4L 40 60 100
EPRVD104 Analog IC Design* 4 4L 40 60 100
EPRVD121 4 4L 40 60 100
EPRVD122 Elective-I
EPRVD123
EPRVD124
EPRVD125
EPRVD111 Technical Seminar I 2 2L 100 - 100
EPRVD112 HDL Programming and EDA 2 6P 100 - 100
Tools Laboratory
Total 24 25 400 300 700
Elective-1
EPRVD121 : Digital Signal Processing
EPRVD122 : Microcontrollers and Applications
EPRVD123 : Wireless Communications and Networks
EPRVD124 : DSP Processors and Architectures
EPRVD125 : Semiconductor Device Modeling

II semester
Course Name of the Course Credits Hours Continuous Semester Total
Code per Week Evaluation End Marks
Examination
EPRVD201 Analog System Design* 4 4L 40 60 100
EPRVD202 Advanced Digital IC Design 4 4L 40 60 100
EPRVD203 VLSI Physical Design* 4 4L 40 60 100
EPRVD204 Digital Systems Testing and 4 4L 40 60 100
Testability*
EPRVD231 4 4L 40 60 100
EPRVD232 Elective –II
EPRVD233
EPRVD234
EPRVD211 Technical Seminar-II 2 2L 100 -- 100
EPRVD212 VLSI Design Laboratory 2 6P 100 - 100
EPRVD213 Comprehensive Viva Voce 2 -- -- 100 100
Total 26 25 400 400 800
Elective-II
EPRVD231: Operating Systems
EPRVD232: Advanced Computer Architecture
EPRVD233: Image and Video Processing
EPRVD234: Communication Networks
EPRVD235: Advanced Digital Signal Processing
 M.Tech (VLSI Design)

III Semester

Course Code Name of the Credits Continuous Semester End Total

Course Evaluation Examination Marks
EPRVD311 Project Work 8 50 50 100
Total 8 50 50 100

IV Semester

Course Name of the Credits Continuous Semester Total

Code Course Evaluation End Marks
Examination
EPRVD411 Project work 16 50 50 100

Total 16 50 50 100

Total Credits 74
 M.Tech (VLSI Design) I Semester

VLSI Technology

Course Code: EPRVD101 Credits: 4 Hours: 4 per week

UNIT I
Introduction : Semiconductor materials, Semiconductor Devices, Semiconductor process
technology, Basic fabrication steps. Crystal Growth : Silicon Crystal Growth from melt,
Silicon Float-Zone Process, GaAs Crystal Growth Techniques, Material Characterization.

UNIT II
Silicon Oxidation : Thermal oxidation, Impurity Redistribution during oxidation, masking
properties of silicon dioxide, oxide quality, oxide thickness characterization.
Photolithography : Optical lithography, Next-Generation lithographic.

UNIT III
Etching : Wet chemical etching, Dry etching. Diffusion : Basic Diffusion Process, Extrinsic
Diffusion, Lateral Diffusion.

UNIT IV
Ion Implantation : Range of Implanted ions, Implant Damage and annealing, Implantation-
related Process. Film Deposition : Epitaxial growth techniques, Structures and defects in
epitaxial layers, Dielectric deposition, Polysilicon deposition, Metallization.

UNIT V
Process Integration : Passive Components, Bipolar Technology, MOSFET technology,
MESFET technology, MEMS technology. IC Manufacturing : Electrical testing, Packaging.

Text Books:

1. Gary S. May, Simon M. Sze, Fundamentals of Semiconductor Fabrication, John Wiley

Inc., 2004.

Reference Books:

1. C.Y. Chang and S.M.Sze (Ed), ULSI Technology, McGraw Hill Companies Inc, 1996.
2. S.K. Ghandhi, VLSI Fabrication Principles, John Wiley Inc., New York, 1983.
3. S.M. Sze (Ed), VLSI Technology, 2nd Edition, McGraw Hill, 1988
4. The Science and Engineering of Microelectronic Fabrication, Stephen Cambell, Oxford
University Press, 2001.
 M.Tech (VLSI Design) I Semester

Digital IC Design

Course Code: EPRVD102 Credits: 4 Hours: 4 per week

UNIT-I
Introduction: Historical Perspective, Issues in Digital Integrated Circuit Design, Quality Metrics of a Digital
Design - Cost of an Integrated Circuit, Functionality and Robustness, Performance, Power and Energy
Consumption – The Manufacturing Process - Introduction, Manufacturing CMOS Integrated Circuits, The Silicon
Wafer, Photolithography, Some Recurring Process Steps Simplified CMOS Process Flow, Design Rules — The
Contract between Designer and Process Engineer

UNIT-II
Devices: Introduction, The Diode, A First Glance at the Diode — The Depletion Region, Static Behavior,
Dynamic, or Transient, Behavior, The Actual Diode—Secondary Effects, The SPICE Diode Model, The
MOS(FET) Transistor, A First Glance at the Device, The MOS Transistor under Static Conditions, Dynamic
Behavior, The Actual MOS Transistor—Some Secondary Effects, SPICE Models for the MOS Transistor – Wire:
Introduction, A First Glance, Interconnect Parameters — Capacitance, Resistance, and Inductance, Capacitance,
Resistance, Inductance

UNIT-III
The CMOS Inverter: Introduction, The Static CMOS Inverter — An Intuitive Perspective, Evaluating the
Robustness of the CMOS Inverter: The Static Behavior, Switching Threshold, Noise Margins, Robustness
Revisited, Performance of CMOS Inverter: The Dynamic Behavior, Computing the Capacitances, Propagation
Delay: First-Order Analysis, Propagation Delay from a Design Perspective, Power, Energy, and Energy-Delay,
Dynamic Power Consumption, Static Consumption, Perspective: Technology Scaling and its Impact on the
Inverter Metrics

UNIT-IV
Designing Combinational Logic Gates in CMOS: Introduction, Static CMOS Design, Complementary CMOS,
Ratioed Logic, Pass-Transistor Logic, Dynamic CMOS Design, Dynamic Logic: Basic Principles, Speed and
Power Dissipation of Dynamic Logic, Issues in Dynamic Design, Cascading Dynamic Gates, Perspectives, How to
Choose a Logic Style, Designing Logic for Reduced Supply Voltages

UNIT-V
Designing Sequential Logic Circuits: Introduction, Timing Metrics for Sequential Circuits, Classification of
Memory Elements, Static Latches and Registers, The Bistability Principle, Multiplexer-Based Latches Master-
Slave Edge-Triggered Register, Low-Voltage Static Latches, Static SR Flip-Flops—Writing Data by Pure Force,
Dynamic Latches and Registers, Dynamic Transmission-Gate Edge-triggered Registers C2MOS—A Clock-Skew
Insensitive Approach, True Single-Phase Clocked Register (TSPCR), Pipelining: An approach to optimize
sequential circuits, Latch- vs. Register-Based Pipelines, NORA-CMOS—A Logic Style for Pipelined Structures,
Non-Bistable Sequential Circuits, The Schmitt Trigger, Monostable Sequential Circuits, Astable Circuits,
Perspective: Choosing a Clocking Strategy

Text Books :

1. Jan M. Rabaey Anantha Chandrakasan, & Borivoje Nikolic, Digital Integrated Circuits – A design
perspective, Second Edition, PHI, 2003

Reference Books:
1. S. M. Kang & Y. Leblebici, CMOS Digital Integrated Circuits, Third Edition, McGraw Hill, 2003.
2. Jackson & Hodges, Analysis and Design of Digital Integrated circuits. 3rd Ed. TMH Publication, 2005.
3. Ken Martin, Digital Integrated Circuit Design, Oxford Publications, 2001.
4. Sedra and Smith, Microelectronic Circuits 5/e, Oxford Publications, 2005.
 M.Tech (VLSI Design) I Semester

Digital Logic Design

Course Code: EPRVD103 Credits: 4 Hours: 4 per week

UNIT I
Review of Logic Design Fundamentals: Combinational Logic / Boolean Algebra and Algebraic Simplification
Karnaugh Maps / Designing with NAND and NOR Gates / Hazards in Combinational Circuits / Flip-Flops and
Latches / Mealy Sequential Circuit Design / Design of a Moore Sequential Circuit / Equivalent States and
Reduction of State Tables / Sequential Circuit Timing / Tristate Logic and Busses

UNIT II
Introduction to VHDL: Computer-Aided Design / Hardware Description Languages / VHDL Description of
Combinational Circuits / VHDL Modules / Sequential Statements and VHDL Processes / Modeling Flip-Flops
Using VHDL Processes / Processes Using Wait Statements / Two Types of VHDL Delays: Transport and Inertial
Delays / Compilation, Simulation, and Synthesis of VHDL Code / VHDL Data Types and Operators / Simple
Synthesis Examples / VHDL Models for Multiplexers / VHDL Libraries / Modeling Registers and Counters Using
VHDL Processes / Behavioral and Structural VHDL / Variables, Signals, and Constants / Arrays / Loops in VHDL
/ Assert and Report Statements

UNIT III
Introduction to Programmable Logic Devices: Brief Overview of Programmable Logic Devices / Simple
Programmable Logic Devices (SPLDs) / Complex Programmable Logic Devices (CPLDs) / Field-Programmable
Gate Arrays (FPGAs) Design Examples: BCD to 7-Segment Display Decoder / A BCD Adder / 32-Bit Adders /
Traffic Light Controller / State Graphs for Control Circuits / Scoreboard and Controller / Synchronization and
Debouncing / A Shift-and-Add Multiplier / Array Multiplier / A Signed Integer/Fraction Multiplier / Keypad
Scanner / Binary Dividers

UNIT IV
SM Charts and Microprogramming: State Machine Charts / Derivation of SM Charts / realization of SM Charts
/ Implementation of the Dice Game / Microprogramming / Linked State Machines

UNIT V
Designing with Field Programmable Gate Arrays: Implementing Functions in FPGAs / Implementing Functions
Using Shannon’s Decomposition / Carry Chains in FPGAs / Cascade Chains in FPGAs / Examples of Logic Blocks
in Commercial FPGAs / Dedicated Memory in FPGAs / Dedicated Multipliers in FPGAs / Cost of
Programmability / FPGAs and One-Hot State Assignment / FPGA Capacity: Maximum Gates Versus Usable Gates
/ Design Translation (Synthesis) / Mapping, Placement, and Routing

Text Books :

1. Charles Roth, Lizy Kurian John, Principles of Digital System Design using VHDL, Cengage Learning, 2009.

Reference Books:

1. John F. Wakerly, Digital Design Principles and Practices, Pearson Education, 2002..
2. Digital Systems Design using VHDL by Charles Roth, Cengage Learning, 1998.
3. Michael Ciletti, Advanced Digital Design using Verilog HDL, Prentice Hall Publications, 2006
4. P.K.Chan & S. Mourad, Digital Design Using Field Programmable Gate Array, Prentice Hall (Pte) 1994.
5. S.Trimberger, Field Programmable Gate Array Technology, Kluwer Academic Publications ,1994.
6. J. Old Field, R.Dorf, Field Programmable Gate Arrays, John Wiley & Sons, Newyork, 1995.
7. S.Brown, R.Francis, J.Rose, Z.Vransic, Field Programmable Gate Array, Kluwer Pubications, 1992.
8. S.Brown, R.Francis, J.Rose, Z.Vransic, Fundamentals of Digital Logic with Verilog Design, Kluwer Pubishers,
1992.
9. FPGA Based system Design, Wayve Woldf, Pearson Education
 M.Tech (VLSI Design) I Semester

Analog IC Design

Course Code: EPRVD104 Credits:4 Hours: 4 per week

UNIT I
Basic MOS Device Physics: General Considerations, MOSFET as a Switch, MOSFET Structure, MOS
Symbols, MOS I/V Characteristics, Threshold Voltage, Derivation of I/V Characteristics, Second-Order
Effects, MOS Device Models, MOS Device Layout, MOS Device Capacitances, MOS Small-Signal Model,
MOS SPICE models, NMOS versus PMOS Devices, Long-Channel versus Short-Channel Devices.

UNIT II
Single-Stage Amplifiers, Basic Concepts , Common-Source Stage, Common-Source Stage with Resistive
Load ,CS Stage with Diode-Connected Load, CS Stage with Current-Source Load, CS Stage with Triode
Load, CS Stage with Source Degeneration, Source Follower, Common-Gate Stage, Cascode Stage, Folded
Cascode, Choice of Device Models.

UNIT III
Differential Amplifiers, Single-Ended and Differential Operation. Basic Differential Pair, Qualitative
Analysis, Quantitative Analysis, Common-Mode Response, Differential Pair with MOS Loads, Gilbert
Cell, Passive and Active Current Mirrors, Basic Current Mirrors, Cascode Current Mirrors, Active
Current Mirrors, Large-Signal Analysis, Small-Signal Analysis, Common-Mode Properties

UNIT IV
Frequency Response of Amplifiers, General Considerations, Miller Effect, Association of Poles with
Nodes, Common-Source Stage, Source Followers, Common-Gate Stage, Cascode Stage, Differential Pair
Feedback General Considerations, Properties of Feedback Circuits, Types of Amplifiers, Feedback
Topologies, Voltage-Voltage Feedback, Current-Voltage Feedback, Voltage-Current Feedback, Current-
Current Feedback, Effect of Loading, Two-Port Network Models, Loading in Voltage-Voltage Feedback,
Loading in Current-Voltage Feedback, Loading in Voltage-Current Feedback, Loading in Current-Current
Feedback, Summary of Loading Effects, Effect of Feedback on Noise

UNIT V
Operational Amplifiers, General Considerations , Performance Parameters, One-Stage Op Amps, Two-
Stage Op Amps , Gain Boosting , Comparison , Common-Mode Feedback . Input Range Limitations,
Slew Rate, Power Supply Rejection, Noise in Op Amps Stability and Frequency Compensation General
Considerations, Multipole Systems, Phase Margin, Frequency Compensation, Compensation of Two-Stage
Op Amps, Slewing in Two-Stage Op Amps, Other Compensation Techniques.

Text Books:
1. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001.

Reference Books
1. P. R. Gray & R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley, 1993.
2. R. Gregorian and Temes, Analog MOS Intgrated Circuits for Signal Processing, Wiley, 1986.
3. Ken Martin, Analog Integrated Circuit Design, Wiley Publications, 2002.
4. Sedra and Smith, Microelectronic Circuits 5/e, Oxford Publications, 2001
5. B.Razavi, Fundamentals of Microelectronics, Wiley Publications, 2008
 M.Tech (VLSI Design) I Semester

Digital Signal Processing

Course Code: EPRVD121 Credits: 4 Hours: 4 per week

UNIT-I
Discrete-Time Signals And Systems - Discrete-Time Signals, Discrete-Time Systems, Analysis of
Discrete-Time Linear Time-Invariant systems, Discrete-Time Systems Described by Difference
Equations, Implementation of Discrete-Time Systems

UNIT-II
Frequency Analysis Of Signals And Systems: The z-Transform, Properties of the z-Transform,
Analysis of Linear Time Invariant Systems in the z-Domain, Frequency Analysis of Continuous-Time
Signals, Frequency Analysis of Discrete-Time Signals, Frequency-Domain Characteristics of Linear
Time-Invariant Systems, Frequency Response of LTI Systems

UNIT-III
The Discrete Fourier Transform: Its Properties And Applications - Frequency Domain Sampling:
The Discrete Fourier Transform, Properties of the DFT, Linear Filtering Methods Based on the DFT,
Frequency Analysis of Signals Using the DFT, The Discrete Cosine Transform, Efficient Computation
of the DFT: FFT Algorithms Applications of FFT Algorithms

UNIT-IV
Implementation Of Discrete-Time Systems: Structures for the Realization of Discrete-Time
Systems, Structures for FIR Systems, Structures for IIR Systems, Representation of Numbers,
Quantization of Filter Coefficients, Round-Off Effects in Digital Filters, Quantization Effects in the
Computation of the DFT

UNIT-V
Design Of Digital Filers: General Considerations, Design of FIR Filters, Design of IIR Filters From
Analog Filters Frequency Transformations

Text Books
1. Digital Signal Processing : Principles, Algorithms and Applications - Proakis, J.Gard and
D.G.Manolakis, Fourth Edn.,,PHI, 1996.

Reference Books:
1. Discrete Time Signal Processing – A.V. Oppenheim and R.W. Schaffer, PHI, 1989.
2. Fundamentals of Digital Signal Processing – Robert J. Schilling & Sandra L. Harris, Thomson,
2005
3. Digital Signal Processing – S. Salivahanan et al., TMH, 2000.
4. Digital Signal Processing – Thomas J. Cavicchi, WSE, John Wiley, 2004.
5. Digital Signal Processing by A.V.Opperheim & R.W.Schafer, PHI Publications
 M.Tech (VLSI Design) I Semester

Microcontrollers and Applications

Course Code: EPRVD 122 Credits: 4 Hours: 4 per week

Unit-I
THE 8051 MICROCONTROLLERS: Microcontrollers and embedded processors,
Overview of the 8051 family, 8051 ASSEMBLY LANGUAGE PROGRAMMING,
JUMP, LOOP, AND CALL INSTRUCTIONS

Unit-II: I/OPORT PROGRAMMING, 8051 ADDRESSING MODES, 8051

PROGRAMMING IN C, Data types and time delay in 8051 C, I/O programming in 8051
C, Logic operations in 8051 C, Accessing code ROM space in 8051 C

Unit-III: 8051 HARDWARE CONNECTION AND INTEL HEX FILE, 8051 TIMER
PROGRAMMING, 8051 SERIAL PORT PROGRAMMING, INTERRUPTS
PROGRAMMING, ADC, DAC SENSOR INTERFACING, 8051 INTERFACING TO
EXTERNAL MEMORY

Unit-IV
PIC Microcontrollers
PIC Microcontroller Families, PIC16X8XX Architecture, Peripherals, PIC18F
architecture, Peripherals etc

Unit-V
ARM 32 Bit MCUs : Introduction to 16/32 Bit processors – ARM architecture and
organization – ARM / Thumb programming model – ARM / Thumb instruction set –
Development tools.

Text Books
1. PIC Microcontroller and Embedded Systems – Using Assembly and C, Mazidi and
Mazidi, Pearson Education, 2008
2. The 8051 Microcontroller and Embedded Systems – Using Assembly and C, Mazidi and
Mazidi, 2nd Edition, Pearson Education, 2002.
3. Rajkamal, Microcontrollers, Pearson Education, 2002.

Reference Books:
1. Microcontrollers (Theory & Applications) – A.V. Deshmuk, WTMH, 2005.
2. Design with PIC Microcontrollers – John B. Peatman, Pearson Education, 2005.
3. Michael Bates, Programming with 8-bit PIC Microcontrollers, Elsevier Publications,
2004.
 M.Tech (VLSI Design) I Semester

Wireless Communications and Networks

Course Code: EPRVD123 Credits: 4 Hours: 4 per week

UNIT-I
Multiple Access Techniques for Wireless Communication: Introduction, FDMA, TDMA, Spread
Spectrum, Multiple access, SDMA, Packet radio, Packet radio protocols, CSMA protocols, Reservation
protocols. Introduction to Wireless Networking: Introduction, Difference between wireless and fixed
telephone networks, Development of wireless networks, Traffic routing in wireless networks.

UNIT-II
Wireless Data Services: CDPD, ARDIS, RMD, Common channel signaling, ISDN, BISDN and ATM,
SS7, SS7 user part, signaling traffic in SS7.

UNIT-III
Mobile IP and Wireless Access Protocol: Mobile IP Operation of mobile IP, Co-located address,
Registration, Tunneling, WAP Architecture, overview, WML scripts, WAP service, WAP session protocol,
wireless transaction, Wireless datagram protocol.

UNIT-IV
Wireless LAN Technology: Infrared LANs, Spread spectrum LANs, Narrow bank microwave LANs,
IEEE 802 protocol Architecture, IEEE802 architecture and services, 802.11 medium access control, 802.11
physical layer. Blue Tooth, Overview, Radio specification, Base band specification, Links manager
specification, Logical link control and adaptation protocol. Introduction to WLL Technology.

UNIT-V
Mobile Data Networks: Introduction, Data oriented CDPD Network, GPRS and higher data rates, Short
messaging service in GSM, Mobile application protocol. Wireless ATM & HiPER LAN: Introduction,
Wireless ATM, HIPERLAN, Adhoc Networking and WPAN,GSM, WCDMA, OFDM etc.

Text Books

1. Wireless Communication and Networking – William Stallings, PHI, 2003.

2. Wireless Communications, Principles, Practice – Theodore, S. Rappaport, PHI, 2nd Edn., 2002.

Reference Books

1. Wireless Digital Communications – Kamilo Feher, PHI, 1999.

2. Principles of Wireless Networks – Kaveh Pah Laven and P. Krishna Murthy, Pearson Education, 2002.
 M.Tech (VLSI Design) I Semester

DSP Processors and Architectures

Course Code: EPRVD 124 Credits: 4 Hours: 4 per week

UNIT-I
Introduction to digital signal processing ,the sampling process,Discrte time sequences, discrete fourier
transform and FFT, Linear time –invariant systems, digital filters, decimation and Interpolation,analysys
and design tool for DSP systems,MATLAB,DSP using MATLAB.

UNIT-II
Computational accuracy IN DSP Implementations: number formats for signals and coefficients in
DSP systems, Dynamic Range and Precision, Sources of error in DSP implementations, A/D conversion
errors, DSP computational errors.D/A conversion errors, compensating filter.

UNIT-III
Architectures for Programmable DSP Devices : basic architectural features,DSP computational
building blocks. Bus architecture and memory, data addressing capabilities, address generation unit,
programmability and program execution, speed issues, features for external interfacing.

UNIT-IV
Execution Control and Pipelining: hard ware looping, Interrupts stacks, relative branch support,
pipelining and performance, Pipeline depth, interlocking, branching effects, Interrupt effects, Pipeline
programming models.

UNIT-V
Interfacing Memory and Peroipherals to Programmable DSP devices: Memory space oragnisation
,External bus interfacing signals,Memory interface,parallel I/O interface,programmable I/O,Interrupt and
I/O,direct memory access. Muilti channel buffered serial port (McBSP), McBSP programming.

Text Books

1. Digital Signal Processing- Avtar Singh and S. Srinivasan, Thompson Publications, 2004.
2. DSP processor fundamentals,Archtecture & Features-Lapsley et al. S. Chand & Co.2000

Reference Books:
1. Digital signal processors, Archtecture, programming and applications- B. venkata ramani and M.
Bhaskar, TMH, 2004.
2. Sen. M. Kuo, Real-Time Digital Signal Processing: Implementations and Applications 2/e, Wiley
Publications, 2006
3. Rulph Chassaing, Digital Signal Processing with C6713 and C6416 DSK, 2/e Wiley Publications,
2005
 M.Tech (VLSI Design) I Semester

Semiconductor Device Modeling

Course Code: EPRVD 125 Credits: 4 Hours: 4 per week

UNIT I
Basic Device Physics : Electrons and holes in silicon, p-n junction, MOS capacitor, High-
field effects.

UNIT II
MOSFET Devices : Long-channel MOSFETs, Short-channel MOSFETs. CMOS Device
Design : MOSFET Scaling, Threshold voltage, MOSFET channel length.

UNIT III
CMOS Performance Factors : Basic CMOS circuit elements, Parasitic elements, Sensitivity
of CMOS delay to device parameters, Performance factors of advanced CMOS devices.

UNIT IV
Bipolar Devices : n-p-n Transistors, Ideal current-voltage characteristics, Characteristics of a
typical n-p-n transistor, Bipolar device models for circuit and time-dependent analyses,
Breakdown voltages.

UNIT V
Bipolar Device Design : Design of the emitter design, Design of the base region, Design of
the collector design, Modern bipolar transistor structures.

Text Books

1. Yuan Taur, Tak.H.Ning, Fundamentals of Modern VLSI Devices, Cambridge University

Press, 1998

Reference Books

1. Donald Neamen, Semiconductors Physics and Devices, Tata Mc Graw Hill, 2003
2. Tyagi, Introduction to Semiconductor Materials and Devices, Wiley Publications, 2002.
3. Semiconductor Devices, Basic Principles Jasprit Singh, Wiley Publications, 2001
4. S.M. Sze (Ed), Physics of Semiconductor Devices, 2nd Edition, Wiley Publications, 1998
5. Analysis and Design of Analog Integrated Circuits 4/e, Paul R. Gray, Paul J. Hurst,
Robert G Meyer, 2001, Wiley Publications
6. Physics of Semiconductor Devices 3/e S. M. Sze, Wiley Publications, 2007.
 M.Tech (VLSI Design) I Semester

Technical Seminar - I

Course Code: EPRVD111 Credits: 2 Hours : 2 per week

Student during the Technical Seminar should cover topics not covered in the
curriculum mainly related to applications of VLSI Design
Viz.

Wireless Communications, Wireless Networks, Communication Networks,

Telephone Networks, Computer Organization, Microprocessors, Microcontrollers,

Embedded Systems, Digital Signal Processing, Digital Signal Compression,

Multimedia, Computer Architecture, Device Modeling, VLSI Fabrication, Low

Power VLSI Design, Design for Yield, Design for Manufacturability, Sub Nanometer

Design issues, Logic Synthesis, Physical Design, Selected Topics from IEEE Journals

etc
 M.Tech (VLSI Design) I Semester

HDL Programming and EDA Tools Laboratory

Course Code: EPRVD112 Credits: 2 Hours : 3 per week

This laboratory course shall be carried out in two 3-Hour sessions per week.
Session-I: Digital IC Design
Experiments shall be carried out using Tanner/Mentor Graphics/Cadence/Xilinx
Tools

1. Introduction to SPICE (Operating Point Analysis, DC Sweep, Transient Analysis, AC

Sweep, Parametric Sweep, Transfer Function Analysis)
2. Modeling of Diodes, MOS transistors, Bipolar Transistors etc using SPICE.
3. An Overview of Tanner EDA Tool/MicroWind/Electric/ Magic/LTSpice
4. I-V Curves of NMOS and PMOS Transistors
5. DC Characteristics of CMOS Inverters (VTC, Noise Margin)
6. Dynamic Characteristics of CMOS Inverters (Propagation Delay, Power Dissipation)
7. Schematic Entry/Simulation/ Layout of CMOS Combinational Circuits
8. Schematic Entry/Simulation/ Layout of CMOS Sequential Circuits
9. High Speed and Low Power Design of CMOS Circuits

Session-II: HDL Programming

Modeling and Functional Simulation of the following digital circuits (with Xilinx/ ModelSim
tools) using VHDL/Verilog Hardware Description Languages

1. Part – I Combinational Logic: Basic Gates, Multiplexer, Comparator, Adder/ Substractor,

Multipliers, Decoders, Address decoders, parity generator, ALU

2. Part – II Sequential Logic: D-Latch, D-Flip Flop, JK-Flip Flop, Registers, Ripple Counters,
Synchronous Counters, Shift Registers ( serial-to-parallel, parallel-to-serial), Cyclic Encoder /
Decoder.

3. Part – III Memories and State Machines: Read Only Memory (ROM), Random Access
Memory (RAM), Mealy State Machine, Moore State Machine, Arithmetic Multipliers using
FSMs
4. Part-IV: FPGA System Design: Demonstration of FPGA and CPLD Boards, Demonstration of
Digital design using FPGAs and CPLDs. Implementation of UART/Mini Processors on
FPGA/CPLD
 M.Tech (VLSI Design) II Semester

Analog System Design

Course Code: EPRVD201 Credits: 4 Hours: 4 per week

Unit- I
Noise Analysis and Modeling: Statistical Characteristics of Noise, Noise Spectrum, Amplitude
Distribution, Correlated and Uncorrelated Sources, Types of Noise, Thermal Noise, Flicker Noise,
Representation of Noise in Circuits, Noise in Single-Stage Amplifiers, Common-Source Stage, Common-
Gate Stage, Source Followers, Cascode Stage, Noise in Differential Pairs, Noise in Op-Amps, Noise
Bandwidth.

Unit-II
Active and Passive Filter Design (Elementary Treatment): General Considerations, Filter
Characteristics, Classification of Filters, Filter Transfer Function, Problem of Sensitivity, First-Order
Filters, Second-Order Filters, Special Cases, RLC Realizations, Active Filters, Sallen and Key Filter,
Integrator-Based Biquads, Biquads Using Simulated Inductors, Approximation of Filter Response,
Butterworth Response, Chebyshev Response
Comparators: Characterization of a Comparator, Two-Stage, Open-Loop Comparators, Other Open-Loop
Comparators, Improving the Performance of Open-Loop Comparators, Discrete-Time Comparators, High-
Speed Comparators

Unit-III
Introduction to Switched-Capacitor Circuits General Considerations, Sampling Switches, MOSFETS as
Switches , Speed Considerations, Precision Considerations , Charge Injection Cancellation, Switched-
Capacitor Amplifiers , Unity-Gain Sampler/Buffer, Noninverting Amplifier, Precision Multiply-by-Two
Circuit, Switched-Capacitor Integrator, Switched-Capacitor Common-Mode Feedback

Unit-IV
OSCILLATORS General Considerations , Ring Oscillators, LC Oscillators , Crossed-Coupled Oscillator
Colpitts Oscillator, One-Port Oscillators, Voltage-Controlled Oscillators, Tuning in Ring Oscillators,
Tuning in LC Oscillators, Mathematical Model of VCOs. Phase-Locked Loops Simple PLL , Phase
Detector, Basic PLL Topology, Dynamics of Simple PLL, Charge-Pump PLLs, Problem of Lock
Acquisition, Phase/Frequency Detector and Charge Pump, Basic Charge-Pump PLL, Nonideal Effects in
PLLs , PFD/CP Nonidealities, Jitter in PLLs , Delay-Locked Loops, Applications, Frequency
Multiplication and Synthesis, Skew Reduction, Jitter Reduction

Unit –V
Digital-To-Analog and Analog-To-Digital Converters: Introduction and Characterization of Digital-
Analog Converters, Parallel Digital-Analog Converters, Extending the Resolution of Parallel Digital-
Analog Converters, Serial Digital-Analog Converters, Introduction and Characterization of Analog-Digital
Converters, Serial Analog-Digital Converters, Medium-Speed Analog-Digital Converters
High-Speed Analog-Digital Converters, Oversampling Converters

Text Books
1. B. Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw Hill Publications, 2002
2. Allen Holberg, CMOS Analog Circuit Design, Oxford Publications, 2002
3. B.Razavi, Fundamentals of Microelectronics, Wiley Publications, 2008
Reference Books:
1. Baker, Li, Boyce, CMOS Mixed Circuit Design, Wiley Publications, 2002
2. Baker, Li, Boyce, CMOS Circuit Design Layout and Simulation, IEEE Press, 2000
3. David A Johns, Ken Martin, Analog Integrated Circuit Design, Wiley Publications, 2003
 M.Tech (VLSI Design) II Semester

Advanced Digital IC Design

Course Code: EPRVD202 Credits: 4 Hours: 4 per week

UNIT-I
Implementation Strategies for Digital ICs: Introduction, From Custom to Semicustom and
Structured Array Design Approaches, Custom Circuit Design, Cell-Based Design Methodology,
Standard Cell, Compiled Cells, Macrocells, Megacells and Intellectual Property, Semi-Custom Design
Flow, Array-Based Implementation Approaches, Pre-diffused (or Mask-Programmable) Arrays, Pre-
wired Arrays, Perspective—The Implementation Platform of the Future

UNIT-II
Coping with Interconnect: Introduction, Capacitive Parasitics, Capacitance and Reliability—Cross
Talk, Capacitance and Performance in CMOS, Resistive Parasitics, Resistance and Reliability—Ohmic
Voltage Drop, Electromigration, Resistance and Performance—RC Delay

UNIT-III
Timing Issues in Digital Circuits: Introduction, Timing Classification of Digital Systems,
Synchronous Interconnect, Mesochronous interconnect, Plesiochronous Interconnect, Asynchronous
Interconnect, Synchronous Design — An In-depth Perspective, Synchronous Timing Basics, Sources
of Skew and Jitter, Clock-Distribution Techniques, Synchronizers and Arbiters, Synchronizers—
Concept and Implementation, Arbiters, Clock Synthesis and Synchronization Using a Phase-Locked
Loop, Basic Concept, Building Blocks of a PLL

UNIT-IV
Designing Arithmetic Building Blocks: Introduction, Datapaths in Digital Processor Architectures,
The Adder, The Binary Adder: Definitions, The Full Adder: Circuit Design Considerations, The
Binary Adder: Logic Design Considerations, The Multiplier, The Multiplier: Definitions, Partial-
Product Generation, Partial Product Accumulation, Final Addition, Multiplier Summary, The Shifter,
Barrel Shifter, Logarithmic Shifter

UNIT-V
Designing Memory and Array Structures: Introduction, Memory Classification, Memory
Architectures and Building Blocks, The Memory Core, Read-Only Memories, Nonvolatile Read-Write
Memories, Read-Write Memories (RAM), Contents-Addressable or Associative Memory (CAM),
Memory Peripheral Circuitry, The Address Decoders, Sense Amplifiers, Voltage References,
Drivers/Buffers, Timing and Control

Text Books :

1. Jan M. Rabaey Anantha Chandrakasan, & Borivoje Nikolic, Digital Integrated Circuits – A design
perspective, Second Edition, PHI, 2003

Reference Books:

1. S. M. Kang & Y. Leblebici, CMOS Digital Integrated Circuits, Third Edition, McGraw Hill, 2003.
2. Jackson & Hodges, Analysis and Design of Digital Integrated circuits. 3rd Ed. TMH Publication, 2005.
3. Ken Martin, Digital Integrated Circuit Design, Oxford Publications, 2001.
4. Sedra and Smith, Microelectronic Circuits 5/e, Oxford Publications, 2005.
 M.Tech (VLSI Design) II Semester

VLSI Physical Design

Course Code: EPRVD 203 Credits: 4 Hours: 4 per week

Unit - I
Algorithmic Graph Theory and Computational Complexity – Terminology, Data Structures for the
Representation of Graphs, Computational Complexity, Examples of Graph Algorithms, Depth-first Search,
Breadth-first Search, Dijkstra's Shortest-path Algorithm, Prim's Algorithm for Minimum Spanning Trees -
Tractable and Intractable Problems, Combinatorial Optimization Problems, Decision Problems, Complexity
Classes, NP-completeness and NP-hardness

Unit - II
Simulation - General Remarks on VLSI Simulation, Gate-level Modeling and Simulation, Signal Modeling,
Gate Modeling, Delay Modeling, Connectivity Modeling, Compiler-driven Simulation
Event-driven Simulation, Switch-level Modeling and Simulation, Connectivity and Signal Modeling,
Simulation Mechanisms,

Unit - III
Logic Synthesis and Verification , Introduction to Combinational Logic Synthesis, Basic Issues and
Terminology, A Practical Example, Binary-decision Diagrams, ROBDD Principles, ROBDD Implementation
and Construction, ROBDD Manipulation, Variable Ordering, Applications to Verification, Applications to
Combinatorial Optimization, Two-level Logic Synthesis, Problem Definition and Analysis, A Heuristic
Based on ROBDDs, High-level Synthesis, Hardware Models for High-level Synthesis, Hardware for
Computations, Data Storage, and Interconnection, Data, Control, and Clocks, Internal Representation of the
Input Algorithm, Allocation, Assignment and Scheduling, Some Scheduling Algorithms, Some Aspects of
the Assignment Problem, High-level Transformations

Unit - IV
Layout Compaction, Design Rules, Symbolic Layout, Problem Formulation, Algorithms for Constraint-
graph Compaction, A Longest-path Algorithm for DAGs, The Longest Path in Graphs with Cycles, The
Liao- Wong Algorithm, The Bellman-Ford Algorithm, Discussion: Shortest Paths, Longest Paths and Time
Complexity, Other Issues Placement and Partitioning, Circuit Representation, Wire-length Estimation,
Types of Placement Problem, Placement Algorithms, Constructive Placement, Iterative Improvement,
Partitioning, The Kernighan-Lin Partitioning Algorithm.

Unit - III
Floorplanning, Floorplanning Concepts, Terminology and Floorplan Representation, Optimization
Problems in Floorplanning, Shape Functions and Floorplan Sizing Routing, Types of Local Routing
Problems, Area Routing, Channel Routing, Channel Routing Models, The Vertical Constraint Graph,
Horizontal Constraints and the Left-edge Algorithm Channel Routing Algorithms, Introduction to Global
Routing, Standard-cell Layout, Building-block Layout and Channel Ordering, Algorithms for Global
Routing, Problem Definition and Discussion, Efficient Rectilinear Steiner-tree Construction, Local
Transformations for Global Routing

Text Books
1. Algorithms for VLSI Design Automation, S.H.Gerez, WILEY Student Edition, John wiley & Sons (Asia)
Pvt. Ltd., 1999.
Reference Books
1. Majid Sarrafzadeh and C. K. Wong, An Introduction to VLSI Physical Design, McGraw Hill, 1996.
2. Naveed Sherwani, Algorithms for VLSI Physical Design Automation, 3rd ed., Kluwer Academic Pub.,
1999
3. Computer Aided Logical Design with Emphasis on VLSI – Hill & Peterson, Wiley, 1993.
4. Modern VLSI Design: Systems on silicon – Wayne Wolf, Pearson Education Asia, 2nd Edition, 1998
 M.Tech (VLSI Design) II Semester

Digital Systems Testing and Testability

Course Code: EPRVD204 Credits: 4 Hours: 4 per week

UNIT-I
Introduction to Test and Design for Testability (DFT) Fundamentals. Modeling: Modeling
digital circuits at logic level, register level and structural models. Levels of modeling. Logic
Simulation: Types of simulation, Delay models, Element evaluation, Hazard detection, Gate
level event driven simulation.

UNIT-II
Fault Modeling – Logic fault models, Fault detection and redundancy, Fault equivalence and
fault location. Single stuck and multiple stuck – Fault models. Fault simulation applications,
General techniques for Combinational circuits.

UNIT-III
Testing for single stuck faults (SSF) – Automated test pattern generation (ATPG/ATG) for
SSFs in combinational and sequential circuits, Functional testing with specific fault models.

UNIT-IV
Design for testability – testability trade-offs, techniques. Scan architectures and testing –
controllability and absorbability, generic boundary scan, full integrated scan, storage cells for
scan design. Board level and system level DFT approaches. Boundary scans standards.
Compression techniques – different techniques, syndrome test and signature analysis.

UNIT-V
Built-in self-test (BIST) – BIST Concepts and test pattern generation. Specific BIST
Architectures – CSBL, BEST, RTS, LOCST, STUMPS, CBIST, CEBS, RTD, SST, CATS,
CSTP, BILBO. Brief ideas on some advanced BIST concepts and design for self-test at board
level.

Text Books
1. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable
Design, Piscataway, New Jersey: IEEE Press, 1994. Revised printing.

Reference Books
1. M. L. Bushnel and V. D. Agarwal, Essentials of Testing for Digital, Memory and Mixed
– Signal VLSI Circuits, Boston: Kluwer Academic Publishers, 2000.
 M.Tech (VLSI Design) II Semester

Operating Systems

Course Code: EPRVD 231 Credits: 4 Hours: 4 per week

UNIT-I
Computer System and Operating System Overview: Overview of Computer System hardware –
Instruction execution – I/O function – Interrupts – Memory hierarchy – I.O Communication
techniques. Operating System Objectives and functions – Evaluation of operating System – Example
Systems.

UNIT-II
Process Description – Process Control –Process States- Process and Threads - Examples of Process
description and Control. Concurrency : Principles of Concurrency – Mutual Exclusion – Software and
hardware approaches – semaphores – Monitors – Message Passing – Readers Writers Problem.
Principles of Deadlock – deadlock prevention, detection and avoidance dining philosophers problem
– example Systems.

UNIT-III
Memory Management : Memory Management requirements – loading programmes in to main
memory – virtual memory – hardware and Control structures – OS Software – Examples of Memory
Management.

UNIT-IV
Uniprocessor Scheduling : Types of Scheduling – Scheduling algorithms – I/O management and Disc
Scheduling – I/o devices – organization – of I/O function – OS design issues – I/O buffering – Disk
I/O – disk scheduling Policies – examples System.

UNIT-V
File Management and Security : Overview of file management – file organization and access – File
Directories – File sharing – record blocking – secondary Storage Management – example system.
Security : Security threats – Protection – intruders – Viruses – trusted System. Case studies of Linux,
Unix, Windows XP, VxWorks

Text Books
1. Operating System Principles- Abraham Silberchatz, Peter B. Galvin, Greg Gagne 7th Edition,
John Wiley.

Reference Books
1. Operating Systems’ – Internal and Design Principles Stallings, Fifth Edition–2005, Pearson
Education/PHI
2. Operating System A Design Approach-Crowley,TMH.
3. Modern Operating Systems, Andrew S Tanenbaum 2nd edition Pearson/PHI
 M.Tech (VLSI Design) II Semester

Advanced Computer Architecture

Course Code: EPRVD 232 Credits: 4 Hours: 4 per week

UNIT-I
Fundamentals of Computer Design : technology trends, cost Measuring and reporting, performance
quantitative principles of computer design, Instruction set principles and examples, classifying
instruction set, memory addressing ,type and size of operands, addressing modes for signal processing,
Operations in the instruction set ,instruction for control ,encoding an instruction set.

UNIT-II
Instruction Level Parallelism, Over coming hazards, reducing branch costs, High performance
instruction delivery, hardware based speculation ,Limitation of LIP,ILP software approach, compiler
techniques, static branch Protection VLIW approach.

UNIT-III
Memory hierarchy design, cache performance, reducing cache misses penalty and Miss rate, virtual
memory, protection and examples of VM

UNIT-IV
Multi processors and thread level parallelism, symmetric shared memory architectures, distributed
shared memory, synchronization, and multi threading

UNIT-V
Storage systems, types, Buses, RAID errors and failures, bench marking a storage device, designing a
I/O system

Text Books
1. Computer Architecture a quantitative approach 3rd edition John L. Hennessy & David A Patterson
Morgan Kuffman,2002
2. Computer Architecture a quantitative approach 4th edition John L. Hennessy & David A Patterson
Morgan Kuffman,2005

Reference Books
1. Computer Architecture and Parallel Processing- Kaui Hwang and A. Briggs International Edition
Mc graw hill
2. Advanced Computer Architecture, Dezso Sima,terence Fountain ,peter Kacsuk Pearson
Education.
 M.Tech (VLSI Design) II Semester

Image and Video Processing

Course Code: EPRVD233 Credits: 4 Hours: 4 per week

UNIT-I
Digital image fundamentals – image acquisition, representation, visual perception,
quality measures, sampling and quantization, basic relationship between pixels,
imaging geometry, color spaces

UNIT-II
Two dimensional systems – properties, analysis in spatial, frequency and transform
domains. Image transforms - DFT, DCT, Sine, Hadamard, Haar, Slant, KL transform,
Wavelet transform.

UNIT-III
Image enhancement – point processing, spatial filtering, Image restoration – inverse
filtering, de-blurring Image compression – lossless and lossy compression techniques,
standards for image compression – JPEG, JPEG200

UNIT-IV
Image segmentation – feature extraction, region oriented segmentation, descriptors,
morphology, Image recognition

UNIT-V
Video spaces, analog and digital video interfaces, video standards. Video processing
– display enhancement, video mixing, video scaling, scan rate conversion, Video
compression – motion estimation, intra and interframe prediction, perceptual coding,
standards - MPEG, H.264

Text Books
1. R. C. Gonzalez and R E Woods, Digital Image Processing, Pearson Education, 2002
2. Keith Jack, Video Demystified, Fifth Edition, LLH, 2001

Reference Books

1. A K Jain, Fundamentals of Digital Image Processing:, Pearson Education,1989

2. W Pratt, Digital Image Processing, Wiley, 2001
3. Al Bovik, Handbook of Image and Video Processing, Academic Press, 2000
 M.Tech (VLSI Design) II Semester

Communication Networks

Course Code: EPRVD 234 Credits: 4 Hours: 4 per week

Unit - I
Communication Networks and Services, Evolution of Network Architecture and Services, Future
Network Architectures and Their Services, Key Factors in Communication Network Evolution.
Applications and Layered Architectures - Examples of Protocols. Services and Layering. The
OSI Reference Model
Overview of TCP/IP Architecture. Network Management Overview

Unit - II
Digital Transmission Fundamentals. Characterization of Communication Channels,
Fundamental Limits in Digital Transmission, Line Coding, Modems and Digital Modulation,
Properties of Media and Digital Transmission Systems, Error Detection and Correction. Circuit-
Switching Networks - Multiplexing,
Circuit Switches, the Telephone Network, Signaling, Cellular Telephone Networks

Unit - III
Peer-to-Peer Protocols and Data Link Layer - Peer-to-Peer Protocols - Peer-to-Peer Protocols
and Service Models, ARQ Protocols and Reliable Data Transfer Service, Data Link Controls,
Framing, HDLC Data Link Control. Medium Access Control Protocols and Local Area
Networks, Medium Access Control Protocols, Multiple Access Communications, Random
Access, Channelization, Local Area Networks
LAN Protocols, Ethernet and IEEE 802.3 LAN Standard, Wireless LANs and IEEE 802.11
Standard, LAN Bridges

Unit - IV
Packet-Switching Networks, Network Services and Internal Network Operation, Packet
Network Topology Datagrams and Virtual Circuits, Routing in Packet Networks, Shortest-Path
Routing, ATM Networks,

Unit – V
TCP-IP and ATM Networks - TCP/IP, the Internet Protocol, IPv6, User Datagram Protocol,
Transmission Control Protocol, and Mobile IP, ATM Networks, ATM Signaling,

Text Books:
1. Communication Networks- Leon Garcia Widjaja, TMH, 2000.

Reference Books:

1. ATM fundamentals-N.N. Biswas,Advenrture books publishers,1998

2. Data Networks, Robert Gallagher, PHI Publications
3. Computer Networks, A.To down approach featuring the Internet Kurose Pearson Education.
4. Data Communications & Networking, Forozam 4th Edition TMH Publication.
5. An Engineering Approach to Computer Networking, S. Keshav, Pearson Education, 2000
 M.Tech (VLSI Design) II Semester

Advanced Digital Signal Processing

Course Code: EPRVD 235 Credits: 4 Hours: 4 per week

UNIT-I
Multirate Digital Signal Processing – Introduction, Decimation by a Factor D, Interpolation by a Factor I,
Sampling Rate Conversion by a Rational Factor I/D, Implementation of Sampling Rate Conversion,
Multistage Implementation of Sampling Rate Conversion, Applications of Sampling Rate Conversion,
Digital Filter Banks Two-Channel Quadrature Mirror Filter Bank.

UNIT-II
Linear Prediction And Optimum Linear Filters - Random Signals, Correlation Functions and Power
Spectra, Innovations Representation of a Stationary Random Process, Forward and Backward Linear
Prediction, Solution of the Normal Equations Wiener Filters for Filtering and Prediction.

UNIT-III
Adaptive Filters - Applications of Adaptive Filters, Adaptive Direct-Form FIR Filters-The LMS
Algorithm, Adaptive Direct-Form FIR Filters-RLS Algorithms.

UNIT-IV
Power Spectrum Estimation - Estimation of Spectra from Finite-Duration Observations of Signals,
Nonparametric Methods for Power Spectrum Estimation, Parametric Methods for Power Spectrum
Estimation.

UNIT-V
Wavelet Theory: Introduction to time frequency analysis, Short-time Fourier transform, Continuous time
wavelet transform, Discrete wavelet transform, Construction of wavelets. Multi resolution analysis,
Application of wavelet theory to signal de noising, image and video compression.

Text Books
1. Digital Signal Processing : Principles, Algorithms and Applications - Proakis, J.Gard and
D.G.Manolakis, Fourth Edition, PHI, 2006.
2. Insight into Wavelets, Ramachandran and Soman, Prentice Hall Publications, 2003

Reference Books

1. P.P. Vaidyanathan, Multirate systems and Filter banks, Prentice Hall, 1993
2. V. Oppenheim and R.W.Schafer, Discrete time Signal Processing, PHI 1994
3. S.J. Orfanidis, Optimum Signal Processing, McGraw Hill, 1989.
4. Wavelet Transforms: Introduction to Theory and Applications, Raghuveer M Rao, Ajit S, Bopardikar,
Pearson Education 2000.
 M.Tech (VLSI Design) II Semester

Technical Seminar - II

Course Code: EPRVD211 Credits: 2 Hours: 2 per week

Student during the Technical Seminar should cover topics not covered in the
curriculum mainly related to applications of VLSI Design
Viz.

Wireless Communications, Wireless Networks, Communication Networks,

Telephone Networks, Computer Organization, Microprocessors, Microcontrollers,

Embedded Systems, Digital Signal Processing, Digital Signal Compression,

Multimedia, Computer Architecture, Device Modeling, VLSI Fabrication, Low

Power VLSI Design, Design for Yield, Design for Manufacturability, Sub Nanometer

Design issues, Logic Synthesis, Physical Design etc

 M.Tech (VLSI Design) II Semester

VLSI Design Laboratory

Course Code: EPRVD 212 Credits: 2 Hours: 3 per week

This Laboratory Course takes two 3-Hour Sessions per week.

Session-I: Analog IC Design

Experiments shall be carried out using Tanner/Mentor Graphics/Cadence Tools

1. Design and Simulation of Single Stage Amplifiers (Common Source, Source

Follower, Common Gate Amplifier)
2. Design and Simulation of Single Stage Amplifiers (Cascode Amplifier, Folded
Cascode Amplifier)
3. Design and Simulation of a Differential Amplifier (with Resistive Load, Current
Source Biasing)
4. Design and Simulation of Basic Current Mirror, Cascode Current Mirror
5. Analysis of Frequency response of various amplifiers (Common Source, Source
Follower, Cascode, Differential Amplifier
6. Schematic/Simulation/Layout of amplifiers, current mirrors
7. Design/Simulation/Layout of Telescopic Operational Amplifier/ Folded
Cascode Operational Amplifier
8. Design/Simulation of other analog building blocks (comparators, oscillators,
PLLs, switched capacitor circuits)

Session-II: ASIC Design

Experiments shall be carried out using Mentor Graphics/Cadence Tools

1. Part-I: Backend Design

Schematic Entry/ Simulation / Layout/ DRC/PEX/Post Layout Simulation of
CMOS Inverter, NAND Gate, OR Gate, Flip Flops, Register Cell, Half Adder, Full
Adder Circuits

2. Part-II: Semicustom Design

HDL Design Entry/ Logic Simulation, RTL Synthesis, Place & Route, DFT, STA Power
Analysis of Medium Scale Combinational, Sequential Circuits

3. Part-III: High Speed/Low Power CMOS Design

Designing combinational/sequential CMOS circuits for High Speed
Designing combinational/sequential CMOS circuits for Low Power
 M.Tech (VLSI Design) III Semester

Project Work

Course Code: EPRVD311 Credits: 8

M.Tech (VLSI Design) IV Semester

Project Work

Course Code: EPRVD411 Credits: 16