ETIN20 - Digital IC design (Fall 2018)

v.1.0.0

1 Home assignments
1. Read section 1.3 and chapter 5 in text book. When doing this lab, you should know what
Voltage Transfer Characteristic (VTC) is and its different properties like switching thresh-
old, noise margins and etc.

2. Read 5.3.3. What is “process variation” and a “process corner”.

3. Familiarize yourself with the tools used in Lab 0 so you can demonstrate the following to
a TA at the start of the Lab.

• Create a new Library.

• Create a new Schematic.
• Instantiate an NMOS and PMOS transistor to create a Low Power Low-Vt Inverter.
• Perform a DC simulation and measure the current drained from a DC source.

2 Lab1: Design of a CMOS Inverter

In this lab, we will design and verify a CMOS Inverter using a schematic. Later we will draw the
layout and perform a parasitic extraction to understand the effects of parasitics such as capaci-
tance and resistance on the transient characteristics of the inverter. Even though all experiments
are performed on a simple inverter, the results are applicable to other CMOS combinatonial gates
as well.

2.1 Inverter Schematic

The first step is the creation of a library in which the design will be stored. Follow the steps
described in Lab 0 and create a library named lab1. Create a new cellview called inv_schematic
or any other suitable name. In the Schematic Editor, instantiate an NMOS transistor ‘nhvtlp’
from the library ‘cmos065’ with the view ‘symbol’ as shown in Fig 1. Note that the default
dimensions of the device is minimum with a width of 135 nm and a length of 60 nm. Place the
selected transistor in the schematic editor window. The inverter has two transistors, one NMOS
and the other one is a PMOS. Place the PMOS tranistor in the editor by performing the steps
described above and choose ‘phtvlp’.

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 Figure 1: Nmos transistor selection

Perform the proper connection using a wire and the final schematic will look as shown in Fig
2. Since we are going to create a custom inverter, we will need to create a ‘Symbol view’. In
order to generate a symbol view and to enable connectivity to other cells, either standard cells,
or custom cells when building up a bigger design, ‘Pins’ are needed. The pins as seen in the
this figure are generated by pressing the [p] button on the keyboard. In the new pop up window
provide the name of the pin, select the direction of the pin and then connect it will the wire that
corresponds to the signal as shown in the Fig 3. For the source voltage, add the pins in the same
manner, the only difference being that instead of selecting input or output exclusively, select the
‘inputoutput’ option in the ‘Direction’ tab.

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 Figure 2: Inverter schematic

Figure 3: Pin connections for schematic

Now the schematic is ready, however, it needs to be verified to make sure that no errors are
present. In order to do this, perform a check and save, and observe the output in the ‘CIW’
(command interface window). If there are no errors or warnings proceed to create a symbol for
the inverter.
• Click on the ‘Create’ tab on the Schematic Editor
• Selecting ‘Cell view’ and then ‘From Cell view’ as shown in the Fig 4
• In the pop up window ‘Cell view from Cell view’, fill in the appropriate details and press
‘OK’

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 Figure 4: Creating a symbol view from schematic

In the ‘Symbol generation options’ pop up window, provide the layout of the pins for the
symbol as shown in the Fig 5. The final symbol will look like the Fig 6. In this symbol you can
write the name of the symbol by using labels. Press [l] key to add the labels.

Figure 5: Symbol generation options

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 Figure 6: Symbol View of the Inverter

2.2 Inverter Testbench Schematic

To test the inverter, a new schematic needs to be created for the testbench. Create a new cell view
in the same library where the inverter is present, and name it as ‘inv_tb’. In this schematic add
the instance of the created inverter, as shown in the Fig 7.

Figure 7: Add Inverter instance to a testbench

The signal generator to generate a pulse train to be used as our inverter input is added using
the add instance function, by choosing the ‘analogLib’ library. Copy the options from the Fig

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8. Similarly add the supply source voltage by choosing the ‘vdc’ instance from ‘analogLib’,
interconnect it properly and finally, add ’VDC’ as the ’DC voltage’. Floating wires will produce
a warning when saving the schematic. To prevent this problem, you can select ’noConn’ sym-
bol from ’basic’ library and connect it to the floating nets where required. The final testbench
schematic will look like the Fig 9. Do not forget to save all the schematics.

Figure 8: Adding the vpulse instance for input generation

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 Figure 9: Complete testbench for simulation

Now in the schematic window drop down menu click on ‘Launch’ tab and then click on the
ADE-L option, a new window will pop up. Add the variable from the schematic as shown using
the ‘Copy from Cellview’ option and provide the values to the variable as shown in the Fig 10.

Figure 10: Updating variables for simulation

Click on the ‘Analysis’ tab and then click on ‘Choose’. In the pop up window select ‘DC’,
’Save DC Operating Point’, select ’Design Variable’ and specify the variable name that we want
to sweep. VPulse is a source that has both DC and transient properties. The transient information
is not used during the DC simulation and DC information is not used during transient simulation.
In this part, we select the DC variable 0 vi_DC0 to sweep from 0 to 1[V].

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 Figure 11: DC simulation setup

In ADE menu, choose ’outputs’, ’to be plotted’ to select the signals to be plotted after simu-
lations. By doing this, the schematic window will be selected automatically. Now you can click
on interesting signals that you want to plot, as shown in Fig 12. You can select both current
and voltages. Selecting nodes of the devices (small rectangles used to interconnect the devices)
will measure the current, while selecting the wires and labels will measure the voltage. Clicking
on any device will result in selecting all the currents going in and from the device. In case of
selecting any unwanted signal, select it and click on the cross icon in right menu on ADE.

Figure 12: Choosing signals to be plotted

The final step to run the simulation is to save the model files for simulation, which is required
just once when you start a new simulation. In this part, you should decide about the process

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corner that will be used to set the corresponding models and parameters during simulation. In
order to do this, click on the ArtistKit tab and then select TT (typical/typical), No, and DK
(design kit) option on the new pop up window as shown in the Fig 13. During chip production,
different steps in the manufacturing process of the chip might result in variations in transistor
parameters. To produce a robust design, the cells should be simulated in presence of various
process variations. The effects of these variations are taken into account by selecting different
parameters. In our present testbench, we use the TT option, meaning that both the NMOS and
PMOS transistors are simulated in the "typical" process corner without local variations expected
during the process. STMicroelectronics provides a set of model files for the transistors that
enables for simulations in different process corners with or without local variations and are used
for this testbench. Local variations can be added, but we disable that option for this simple
testbench. Save Model file!

Figure 13: Setting up simulation corners

Click on the Simulation, then on Netlist and Run, to run the simulations as shown in Fig 14.

Figure 14: Netlist and simulation run

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 Once the simulation is completed you will see a plot, where the signals are plotted against
0 vi_DC0 .

Assignment:
1. What is switching threshold (VM ) of the inverter?
The manual method to find the VIL and VIH , is to use the markers ’a’ (hover the mouse over
the waveform and press ’a’ key) and ’b’ (hover the mouse over the waveform and press ’b’
key) and find the points that give the slope=-1.

2. Find the noise margins of the inverter.

3. In ADE window, change the plotting mode to append. In the "Artist kit" window, change
the corners to FS (fast NMOS, slow PMOS) and SF (slow NMOS, fast PMOS) and repeat
the simulation for each case. How are VM and noise margins affected?

4. Extract the VM for each case and discuss your results with TA.
Discussion: Which process corner "TT, FF, FS, SF, SS" gives the best "VM "? Discuss the
result with TA and think about which corner gives shortest rise time, fall time and propagation
delay? Which process corner gives the lowest leakage current?

2.2.1 Timing calculations

Change the testbench according to the Fig 15, by instantiating three inverter cells.

Figure 15: Load test for inverter

Change the corners back to TT and change the analyse type from ’DC’ to ’tran’ (transient).
Set the stop time to 10n and run the simulation. In the plot window, using the ‘a’ and ‘b’ markers
find the rise time, fall time and propagation delay.
Now increase the load by 10X, by changing the instance name to I8<9:0> as shown in Fig 16.
This connects the cells in parallel which essentially means that load of the inverter increases by
10x. The final schematic of the load is shown in Fig 17. Once these changes are performed, run
the simulations to observe the effects on the timing behaviour.

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 Figure 16: Load scaling

Figure 17: Schematic section of the load

2.3 Parametric sweep

In this section you will learn to do parametric sweeps on the inverter. The procedure is similar
to the one performed in Lab 0. As an example, a parametric sweep on the transistor ‘VDC’ is
shown here. However, you are to perform a parametric sweep on the width and length of
the transistor too. In order to this, the first step is to change the default size of the transistors
that was used in the ‘Inv’. Open the schematic, select the transistors for which you are going
to change the width parameter. Press the [q] key on the keyboard, a pop up window will show
you all the properties of the transistor. Now instead of the default value, write the name of the
variable that will then be used for the sweep as shown in the Fig 18. Do not forget to add the
variable in the Analog environment window as described before, you will see the variable as
shown in Fig 18. The parametric analysis tool is placed in the tab of tools as shown in Fig 18,
click on it.

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 Figure 18: Parametric analysis with variable transistor width

The tool is invoked in a new window, select the variable that you want to perform the sweep
on, specify the range and the steps as shown in Fig 19 and start the sweep as shown in Fig 20.

Figure 19: Variable selection

Figure 20: Sweep start

You will see multiple plots after the simulations ends, you can pick and choose the pair of
input and outputs that you want to analyse by selecting them and using the right click to get the
option of ‘Move to’ –> ‘New Window’, as shown in Fig 21

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 Figure 21: Parametric analysis with VDC

2.4 Assignment
- Run a parametric transient analysis with the supply voltage VDC with 10X load. Limit the
simulation count to less than 10. How the timing is affected by supply voltage? How you
can connect this effect to ID of transistors in inverter?

- Run a parametric DC analysis with the width of the PMOS[Wp] to obtain different Voltage
transfer characteristic VTC. Set the supply voltage to 1[V] and limit the simulation count
to less than 10. Which size gives a balanced inverter?

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3 Lab1:Layout design of an inverter
In this section of the manual, you will find instructions on creating a layout for a CMOS inverter.
We will use the layout to extract parasitic parameters and will compare the transient characteris-
tics of the inverter schematic with that of the layout.

3.1 Home assignments

• Sketch a layout of a CMOS inverter. Mark clearly all the layers you will need

3.1.1 Layout creation

To begin,
• Goto the Library manager and create a new Cellview in the library where you have the
inverter schematic

• Choose the View name to be ‘Layout’ and Application as ‘Layout L’ as shown in Fig. 22

Figure 22: Creating a layout

This opens the Virtuoso Layout Editing tool which will be used to design the layout of the
inverter.
• Click on ‘Launch’ and select ‘Layout XL’

• In the bottom left of the Layout Editing tool, you will now see some new icons. These
icons will help you pick the layout of the PMOS and NMOS transistors from the schematic
created in the previous section. Hover the mouse over one of the icons and you will see
the function of the button

• Click on the icon which says ‘Generate selected from source’

• Choose the NMOS and PMOS transistors in the Schematic Editor window by holding
down the shift key and using the mouse buttons.

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 • Move the mouse over to the Layout Editor and now you can place the layout views of the
PMOS and NMOS transistors

• Zoom in and Zoom out to fit the view you prefer and use the [f] key to fit the drawing to
the whole screen area

• If the transistors appear as red boxes, press ‘shift+F’ key which enables one to view all the
layers in the layout.

Examine the PMOS and NMOS transistors. Notice that there only the Gate, Source and Drain
terminals present. The substrate connections need to be made by hand.
Next step is to connect the transistors

• All available layers, including metals and poly are available on the left hand side of the
Layout editor in the Layers window as shown in Fig 23.

• To connect terminals of the transistor use the ‘M1 drawing’ layer

• The ‘M1 pin’ layer will be used to make connections to the input, output, vdd and the
ground pins

• Use the ‘PO drawing’ layer to connect the poly layers of the two transistors

Figure 23: Available drawing layers

To draw connections,

• Click on ‘Create’, then on ‘Shape’ and choose ‘Rectangle’. The shortkey is [r]

• Click on the diagonal corners where you want to add for instance a rectangle in M1

• Another alternate method is Create->Shape->Path. The shortkey is [p].

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. Test both methods to see which you prefer. To simplify the drawing it is possible to zoom using
View->Zoom [z]. You can also use the right mouse button by holding it down and selecting an
area where you want to zoom in.
Notice that there is no ‘N-Well’ around the PMOS. Add the ‘N-Well’ by choosing the right
layer called ‘NW’ around the PMOS. To connect the substrates to the right voltages we will need
to create some ‘Via’s. This can be done by Create->Via or by pressing the [v] key. Choose the
NTAP and PTAP to connect the appropriate substrates. Make sure you choose atleast 4 in the
columns option when creating the NTAP and PTAP to avoid design rule violations. To move
from polysilicon to M1, choose Create->Via and the via named ‘M1__PO’. Follow the layout
sketch that you have prepared in your homework and complete the design. An example layout is
shown in Fig 24.

Figure 24: An example layout

3.1.2 Running Design Rule Checks

Once the layout is completed, it has to be verified for design rule violations. This can be done by

• Click on the ‘Calibre’ tab and choose ‘Run DRC’

• In the pop up window, choose DK DRC (Design kit DRC)

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 • In the next window (Customization settings) keep the default settings and press ‘OK’

• Run DRC by clicking on the appropriate button

• Press ‘OK’ for the next few windows which pop up (if any) and wait for the DRC run to
finish

• A report window will appear showing all the DRC warning/errors along with passed rules

• Click on the ‘Show Unresolved’ option as depicted in Fig 25.

Figure 25: Running DRC and checking for violations

If there are any DRC violations, they will be displayed as shown in Fig 26. Right Click on
the error number and click on ‘Highlight’. The tool will zoom in automatically to the position
where the DRC violation occurs. Read the description of the DRC error and fix it. Make sure
you save your design before re-running DRC.

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 Figure 26: Running DRC and checking for violations

Once the DRC violations are fixed, you can add the input, output and power pins to your
design.

• Choose ‘M1 Pin’ layer and add connections to the appropriate places

• Create labels for your port names by using Create-> Label [L]

3.1.3 Running Layout Vs Schematic Checks

The next step is to check whether the layout done matches with the schematic.

• Choose Calibre-> Run LVS

• Keep the default option and Press OK for the next dialogue boxes which open up

• Start LVS by clicking on ‘Run LVS’

If the layout matches the schematic, the report window shows a success as shown in Fig 27. If
there are errors, click on the errors to examine the cause, fix them and re run LVS.

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 Figure 27: Running LVS and checking for violations

3.1.4 Extracting Parasitics

The next step is to extract the parasitics in your design. Parasitics are caused mainly because
of the capacitances and the resistances of the metal, poly and other layers used in designing the
layout. Since layouts are done manually, each designer would create a slightly different layout
for the same schematic and hence simulations have to be run to make sure that the design after
layout still meets the requirements. We will study the effects of these parasitics in this section.

• Click on Calibre-> Run Pex

• Keep the default settings in the customization Settings window and press ‘OK’

• Change the Extraction type to ‘R+C+CC’ and choose ‘No inductance’ in the Extraction
type setting

• Click on the Outputs button and choose Format to be ‘Calibreview’ as shown in Fig 28

• Click on ‘Run PEX’

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 Figure 28: Running Parasitics Extraction

At the end of the run a new window is displayed showing the values of parasitic capacitances
and resistors obtained from the layout. In the calibre view setup window, choose ‘Calibre view
type’ to be ‘Schematic’. Keep all other options unchanged. At the end of the run a new cell view
called ‘Calibre’ will be created. You can examine this in the Library manager.

3.1.5 Creating a config view for testbench

Now that we have a layout of the inverter, we will need to create a testbench to verify the oper-
ation of the layout and compare its performance with that of the schematic. To do this, open the
inverter testbench created in the first section of the lab when verifying the schematic. Instantiate
another inverter and a load. Connect both inverters to the same input supply. Fix the parameters
like ‘vdc’ to be 1.2V and the width and length to the values calculated for the balanced design.
‘Check and Save’ the design. Go to the Library manager and create a new ‘Cellview’ for the
inverter testbench cell. Choose view type to be ‘Config’ and Application as ‘Hierarchy Editor’
as shown in Fig 29 and click ‘OK’.

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 Figure 29: Creating a config view

In the ‘New Configuration’ window, click on ‘Use template’ and choose ‘Spectre’ as shown
in Fig. 30. Click ‘OK’. When starting Spectre, some default library bindings which we will use
for our simulations are loaded. In the Hierarchy Editor, click on tree view and choose one of the
inverters and bind to the layout. This is done by right clicking on one of the instances, choose
‘Instance view -> Calibre’, as shown in Fig. 31. Save the changes done in the Hierarchy Editor.

Figure 30: Creating a config view setup

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 Figure 31: Binding a Calibre view to an instance

Open the schematic of the inverter testbench and click on instance which you bound to the
‘Calibre’ view and descend by pressing [e]. Verify that there are parasitic resistance and capaci-
tances in the schematic. Return back by pressing [ctrl+e].

3.1.6 Layout simulations

Open up the Analog Design Environment as done in first section of the lab. Setup the simulation
exactly like described in first section. Choose the outputs of the instance bound to ‘Calibre’ view
and the schematic view. Run a simulation as described in the previous section and compare the
results. What do you find?

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 Table 1: Useful shortcuts
Command Description
Ctrl+D De-select everything
Esc De-select current operation
q Object properties
s Stretch border
m Move object
u Undo
U Redo
l Create label
v Create via
r Draw rectangle
p Draw path
e Move down one level in schematic
Shift+e Move down one level with schematic editing

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