DSA Project Report

To control the
speed of stepper motor using

light intensity on LDR.
DSA Project 2010
Sumit Vyas 200701008

Deepak Singh 200701013
Pankaj Srivastava 200701185
4/20/2010
DSA 2010 To control the speed of stepper motor using light intensity on LDR.
Contents
1. Problem Statement ……………………………………………………. 3
2. Functional Specification ……………………………………………… 3

Introduction ………………………………………………………… 4
Objective …………………………………………………………… 4
Approach …………………………………………………………… 4
3. Block Diagram ……………………………………………………….. 4
4. RTL Schematic ……………………………………………………… 5

Overall …………………………………………………………… 5
ADC ……………………………………………………………… 6
Stepper Motor ……………………………………………………. 7
5. Technology Schematic ……………………………………………… 9
6. Floor Plan …………………………………………………………… 10
7. Functional Simulation ……………………………………………… 10
8. Report ……………………………………………………............... 11
HDL Synthesis Report …………………………………………. 11
Timing Report …………………………………………………. 12
Mapping Report ………………………………………………... 12
Place and Route Report ………………………………………… 13
9. Experiment Setup and pics ……………………………….............. 13
10. Code ………………………………………………………………. 16
11. References ………………………………………………………… 25
2
Problem Statement
To control the speed of stepper motor using light intensity on LDR.
To interface LDR as an analog input to FPGA kit and display the output from LDR on
the 7 segment LED. It will also responsible for the speed of revolution of stepper motor
depending on the light intensity of the LDR.
Functional Specification
Introduction
The speed of stepper motor will be regulated by the light intensity on LDR. The ADC
chip 7891 will take output of analog sensor (LDR) as an input. Depending upon the
output of ADC the stepper motor will vary in speed. The components that are to be used:
LDR, Stepper Motor, ADC, and FPGA chip Spartan3.
Components used:
LDR - A photo resistor or Light Dependent Resistor is a component sensitive to

light. When light falls upon it, then resistance changes. Values of the resistance of
LDR may change over many orders of magnitude, the magnitude of resistance falling
as the light intensity increases. It is not uncommon for the values of resistance of an
LDR or photo resistor to be several mega ohms in darkness and then fall to few
hundred ohms in bright light.
Stepper Motor – The stepper motor is an electrical motor, which converts digital
electrical input into a rotator motion. Stepper motor is the one that revolves through a
3
fixed angle for each pulse applied to the logic sequence. By controlling the pulse rate
the speed of stepper motor can be controlled. Stepper motor is also called as a Single
Stack Variable Reluctance Motor. If the switching is carried out in a sequence, the
rotor will rotate with stepped motion.
The pulse rate given to stepper motor will depend on the ADC output, or indirectly on
Light Intensity.
Objective:
To regulate/change the speed of stepper motor depending upon the light intensity
at LDR. Also, to display the corresponding light intensity at 7 segment LED.
Approach:
We were required to change the speed of motor by light intensity of LDR. So, our first
task was to get digital output from LDR using ADC chip 7891 available on the board.
After making sure that the ADC interfacing is working properly, we shifted ourselves to
the next task at hand. We run the stepper motor as a separate module. After that we
integrated the modules to run the stepper motor depending upon the light intensity.
Block Diagram
4
LDR External Circuit
RTL Model
5
 ADC
6
 Stepper motor
7
8
Technology Schematic
9
Floor Plan
Functional Simulation
10
Reports
==========================================================
HDL Synthesis Report
Macro Statistics
# Adders/Sub tractors :4
32-bit adder :4
# Counters :5
19-bit up counter :1
32-bit up counter :4
# Registers :9
1-bit register :6
12-bit register :1
2-bit register :1
5-bit register :1
# Comparators : 14
12-bit comparator greatequal :4
12-bit comparator greater :3
12-bit comparator less :4
12-bit comparator lessequal :3
# Tristates :6
1-bit tristate buffer :6
=============================================================
Device Utilization Summary
Selected Device: 3s400pq208-4
Number of Slices: 148 out of 3584 4%

Number of Slice Flip Flops: 101 out of 7168 1%
Number of 4 input LUTs: 267 out of 7168 3%
Number of IOs: 49
Number of bonded IOBs: 49 out of 141 34%
IOB Flip Flops: 6
Number of GCLKs: 1 out of 8 12%
11
Timing Report
(a)Clock Information:
Clock Signal Clock buffer(FF name) Load

smc1/select_speed/speed NONE(smc1/fsm1/sequence_0) 6
clk BUFGP 86
a1/div_adc_17 NONE(a1/ps_1_FSM_FFd1) 15
(b) Timing Summary:

Speed Grade: -4
Minimum period: 12.689ns (Maximum Frequency: 78.808MHz)

Minimum input arrival time before clock: 8.972ns
Maximum output required time after clock: 13.155ns
Maximum combinational path delay: 7.266ns
Total memory usage is 138032 kilobytes
=============================================================
Mapping Report
Design Summary
 Number of errors: 0
 Number of warnings: 0
 Logic Utilization:
Number of Slice Flip Flops: 101 out of 7,168 1%
Number of 4 input LUTs: 108 out of 7,168 1%
 Logic Distribution:
Number of occupied Slices: 144 out of 3,584 4%
Number of Slices containing only related logic: 144 out of 144 100%
Number of Slices containing unrelated logic: 0 out of 144 0%
Total Number of 4 input LUTs: 264 out of 7,168 3%

Number used as logic: 108
Number used as a route-thru: 156
Number of bonded IOBs: 49 out of 141 34%
12
IOB Flip Flops: 6
Number of BUFGMUXs: 1 out of 8 12%
Peak Memory Usage: 131 MB

Total REAL time to MAP completion: 5 secs
Total CPU time to MAP completion: 4 secs
=============================================================
Place and Route Report

Device Utilization Summary:
Number of BUFGMUXs 1 out of 8 12%

Number of External IOBs 49 out of 141 34%
Number of LOCed IOBs 49 out of 49 100%
Number of Slices 144 out of 3584 4%

Number of SLICEMs 0 out of 1792 0%
Overall effort level (-ol): Standard

Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
Experiment
Kit Arrangement
13
1. Stepper motor rotating
2. Light Intensity at 7 segment LED
14
LDR resistance/ voltage drop
The Light Intensity is normal and signal applied is 5 Vpp Sine wave of freq. 100 KHz
The Light Intensity is almost zero.
15
Code
-----------------------------(1) Connector.v--------------------------------------
module
connector(clk,reset,ff,ch_adc,db,cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_
ad7891,start,direction, sequence,adc_data_out,y,seg_cs);
input clk,reset;
input ff;
input[2:0] ch_adc;
inout [11:0] db;
input start,direction;
output [3:0] sequence;
output [11:0] adc_data_out;
output cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891;
output [6:0] y;
output seg_cs;
reg [20:0] clk_prescalar;
always@(posedge clk)
clk_prescalar=clk_prescalar+1;
adc_controller
a1(smpclk,cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891,reset,clk,ch_a
dc,db,adc_data_out,y,seg_cs);
stepper_motor_controller smc1(clk, ff,start,direction,adc_data_out,sequence);
endmodule
//-----------------------------(2) adc_controller.v------------------------------------------------
module
adc_controller(smpclk,cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891,
reset,clk,ch_adc,db_7891,adc_data_out,y,seg_cs);
output smpclk,cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891;
output [11:0] adc_data_out;
output reg [6:0] y;

output seg_cs;
16
input clk, reset;

input [2:0] ch_adc;
inout [11:0] db_7891;
reg cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891,convst_ad7891_s;
wire sampling_clk,wr_s,rd_s;
`define reset_1 2'd0

`define write_cwr 2'd1
`define start_conv 2'd2
`define read_data 2'd3
reg [1:0] ps_1;

reg [1:0] ns_1;
wire [5:0] conc;
reg [18:0] div_adc;
reg [11:0] adcin,db_7891_s;
assign adc_data_out=adcin;
assign seg_cs = 1'b1;
always @ (negedge reset or posedge clk)

begin
if (!reset)
div_adc =0;
else
div_adc = div_adc + 1;
end
assign sampling_clk = div_adc[17];

assign smpclk = sampling_clk;
always @ (negedge reset or posedge sampling_clk)

begin
if (!reset)
ps_1 = `reset_1;
else
ps_1 = ns_1;
end
always @ (ps_1)
begin
case (ps_1)
`reset_1 : ns_1 = `write_cwr;
`write_cwr : begin
17
cs_ad7891 = 1'b0;
ns_1 = `start_conv; end
`start_conv : ns_1 = `read_data;
`read_data : begin
cs_ad7891 = 1'b0;
ns_1 = `reset_1; end
endcase
end
assign conc = {ch_adc,3'b0};

assign db_7891[5:0] = (wr_s == 1'b0) ? conc : 6'bZZZZZZ;
always @ (negedge reset or posedge sampling_clk)

begin
if (!reset)
convst_ad7891_s = 1'b0;
else
convst_ad7891_s = wr_s;
end
always @ (convst_ad7891_s)
convst_ad7891 = convst_ad7891_s;
always @ (negedge reset or negedge sampling_clk)

begin
if (!reset)
db_7891_s = 12'b0;
else if (!rd_s)
db_7891_s = db_7891;
end
always @ (db_7891_s)
adcin = db_7891_s;
always
mode_ad7891 = 1'b1;
assign wr_s = (ps_1 == `write_cwr) ? 1'b0 :1'b1;

assign rd_s = (ps_1 == `read_data) ? 1'b0 : 1'b1;
always @ (rd_s or wr_s)

begin
wr_ad7891 = wr_s;
rd_ad7891 = rd_s;
18
end
always @ (adcin) begin // 7 segment display
case (adcin[11:4])
8'b10111000 : y=7'b1110111;
8'b10111001 : y=7'b1111111;
8'b10111010 : y=7'b0111001;
8'b10111011 : y=7'b1011110;
8'b10111100 : y=7'b1111001;
8'b10111101 : y=7'b1110001;
8'b10111110 : y=7'b1111101;
8'b10111111 : y=7'b1110110;
8'b11000000 : y=7'b0000110;
8'b11000010 : y=7'b0001111;
8'b11000011 : y=7'b1110000;
8'b11000101 : y=7'b0111000;
8'b11000110 : y=7'b1011011;
8'b11001000 : y=7'b1001011;
8'b11001001 : y=7'b0111111;
8'b11001101 : y=7'b1110011;
8'b11001110 : y=7'b1100111;
8'b11010000 : y=7'b0111110;
8'b11010010 : y=7'b1100100;
8'b11010100 : y=7'b1101101;
default
y = 7'b0111111;
endcase
end
/* --- DAC code
always @ (dac_sel)
begin
case (dac_sel)
2'b00 : en = 4'b1000;
2'b01 : en = 4'b0100;
2'b10 : en = 4'b0010;
2'b11 : en = 4'b0001;
default : en = 4'b0000;
endcase
end
lowpass u1(.clk(div_adc[4]),.gateway_in(adcin),.gateway_out(dacout));
assign dac_out_s = bit_trunc[0] ? dacout[21:10] :
(bit_trunc[1] ? dacout[20:9] :
19
(bit_trunc[7] ? dacout[14:3]:
dacout[13:2])))))));
assign conc1 = {dac_out_s[11],~dac_out_s[10:0]};
assign dac_out = (dac_out_s[11] == 0) ? (conc1 + 1) : conc1;
*/
endmodule
//------------------------------------(3) Stepper_motor.v----------------------------------------------
module stepper_motor_controller(clk,ff,start,direction,adc_data_out,sequence);
input clk,ff; // ff to be used as fast forward

input start;
input direction;
input [11:0] adc_data_out;
output [3:0] sequence;
wire [1:0] flg;
clock_divider different_clock(clk,ff,adc_data_out,flg, f1, f2, f3, f4);
speed_decider select_speed(clk,flg,f1, f2, f3, f4, speed);
stepper_motor_fsm fsm1(speed, direction, start, sequence);
endmodule
//--------------------------(3a) clock divider-----------------------------
module clock_divider(clk,ff,adc_data_out, flg1,clk1, clk2, clk3, clk4);

input clk,ff;
input [11:0] adc_data_out;
output reg clk1;
output reg clk2;
output reg clk3;
output reg clk4;
integer i1 = 0, i2 = 0, i3 = 0, i4 = 0;
output [1:0] flg1;
reg [1:0]flg2;
assign flg1=flg2;
begin
20
if(adc_data_out>=12'b101000000001) // 1025 and above

begin
flg2=2'b11;
i1 = i1 + 1;
if(i1 == 5000) // max speed 800 rps
begin
clk1 = ~clk1;
i1 = 0;
end
end
if((adc_data_out>=12'b100010000001)&&( adc_data_out<=12'b101000000000) )
begin // between 257 and 1024
flg2=2'b10;
i2 = i2 + 1;
if(i2== 15000) // less speed than first 266.67 rps
begin
clk2 = ~clk2;
i2 = 0;
end
end
begin // between 3 and 256
flg2=2'b01;
if(!ff)
begin
i3 = i3 + 1;
if(i3== 150000) // slow speed if ff is not pressed 26.67 rps
begin
clk3 = ~clk3;
i3 = 0;
end
end
else
begin
i3 = i3 + 1;
if(i3== 5000) // ff speed 800 rps
begin
clk3 = ~clk3;
i3 = 0;
end
end
end
21
//clk4
begin //between 1 and 2
i4 = i4 + 1;
flg2=2'b00;
if(i4== 155000) // slowest speed 25.6 rps
begin
clk4 = ~clk4;
i4 = 0;
end
end
end // always block
endmodule
//--------------------------(3b) speed_decider.v-------------------------------------
module speed_decider (clk,flg,f1,f2,f3,f4,speed);
input clk,flg,f1,f2,f3,f4;
output reg speed;
// reg [1:0] flg2;
//assign flg2=flg;
begin
case (flg)
2'b00 : begin //slowest
speed =f4;
end
2'b01 : begin
speed =f3;
end
2'b10 : begin
speed =f2;
end
2'b11 : begin //fastest
speed =f1;
end
endcase
end
endmodule
22
//-------------------- Stepper Motor fsm----------------------------------
module stepper_motor_fsm(speed,d, start, sequence);

input speed;
input d;
input start;
output reg [4:0]sequence;
parameter [1:0] state1 = 1, state2 = 2, state3 = 3, state4 = 4;
reg [1:0] current = 1;
always@ (posedge speed)

begin
if(!start) begin sequence = 5'b10000; end
else
begin
case (current)
state1: begin
sequence = 5'b11100;
if(d)
current = state4;
else
current = state2;
end
state2: begin
if(d)
current = state1;
else
current = state3;
end
state3: begin
if(d)
current = state2;
else
current = state4;
end
state4: begin
if(d)
current = state3;
else
current = state1;
end
23
endcase
end
end
endmodule
//--------------------------connector.ucf-----------------------------------
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments

NET "adc_data_out[0]" LOC = "p161" ;
NET "ch_adc[0]" LOC = "p141" ;

NET "clk" LOC = "p76" ;
NET "db[0]" LOC = "p45" ;
NET "db[10]" LOC = "p68" ;
NET "db[11]" LOC = "p71" ;
NET "db[1]" LOC = "p46" ;
NET "db[2]" LOC = "p57" ;
NET "db[3]" LOC = "p58" ;
NET "db[4]" LOC = "p61" ;
NET "db[5]" LOC = "p62" ;
NET "db[6]" LOC = "p63" ;
NET "db[7]" LOC = "p64" ;
NET "db[8]" LOC = "p65" ;
NET "db[9]" LOC = "p67" ;
NET "direction" LOC = "p138" ;
NET "reset" LOC = "p143" ;
NET "ff" LOC = "p132" ;
NET "sequence[0]" LOC = "p43" ;
24

NET "start" LOC = "p137" ;
NET "mode_ad7891" LOC = "p72" ;
NET "rd_ad7891" LOC = "p51" ;
NET "seg_cs" LOC = "p180" ;
NET "wr_ad7891" LOC = "p52" ;
NET "y[0]" LOC = "p189" ;
NET "y[1]" LOC = "p190" ;
NET "y[2]" LOC = "p187" ;
NET "y[3]" LOC = "p185" ;
NET "y[4]" LOC = "p184" ;
NET "y[5]" LOC = "p183" ;
NET "y[6]" LOC = "p182" ;
NET "convst_ad7891" LOC = "p48" ;
NET "cs_ad7891" LOC = "p50" ;
#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PAC
References
1. Datasheet of ADC 7891.
2. Operational and User manual of Mechatronics Kit.
25

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To control the

speed of stepper motor using

Sumit Vyas 200701008

2. Functional Specification ……………………………………………… 3

3. Block Diagram ……………………………………………………….. 4

4. RTL Schematic ……………………………………………………… 5

5. Technology Schematic ……………………………………………… 9

6. Floor Plan …………………………………………………………… 10

7. Functional Simulation ……………………………………………… 10

9. Experiment Setup and pics ……………………………….............. 13

10. Code ………………………………………………………………. 16

11. References ………………………………………………………… 25

LDR - A photo resistor or Light Dependent Resistor is a component sensitive to

LDR External Circuit

Device Utilization Summary

Selected Device: 3s400pq208-4

Number of Slices: 148 out of 3584 4%

Clock Signal Clock buffer(FF name) Load

(b) Timing Summary:

Minimum period: 12.689ns (Maximum Frequency: 78.808MHz)

Total memory usage is 138032 kilobytes

Number of Slices containing unrelated logic: 0 out of 144 0%

Total Number of 4 input LUTs: 264 out of 7,168 3%

Number of bonded IOBs: 49 out of 141 34%

IOB Flip Flops: 6

Number of BUFGMUXs: 1 out of 8 12%

Peak Memory Usage: 131 MB

Place and Route Report

Number of BUFGMUXs 1 out of 8 12%

Number of Slices 144 out of 3584 4%

Overall effort level (-ol): Standard

1. Stepper motor rotating

2. Light Intensity at 7 segment LED

LDR resistance/ voltage drop

The Light Intensity is almost zero.

reg [20:0] clk_prescalar;

stepper_motor_controller smc1(clk, ff,start,direction,adc_data_out,sequence);

output reg [6:0] y;

input clk, reset;

`define reset_1 2'd0

reg [1:0] ps_1;

always @ (negedge reset or posedge clk)

assign sampling_clk = div_adc[17];

always @ (negedge reset or posedge sampling_clk)

`start_conv : ns_1 = `read_data;

assign conc = {ch_adc,3'b0};

always @ (negedge reset or posedge sampling_clk)

always @ (negedge reset or negedge sampling_clk)

assign wr_s = (ps_1 == `write_cwr) ? 1'b0 :1'b1;

always @ (rd_s or wr_s)

input clk,ff; // ff to be used as fast forward

//--------------------------(3a) clock divider-----------------------------

module clock_divider(clk,ff,adc_data_out, flg1,clk1, clk2, clk3, clk4);

if(adc_data_out>=12'b101000000001) // 1025 and above

module speed_decider (clk,flg,f1,f2,f3,f4,speed);

//-------------------- Stepper Motor fsm----------------------------------

module stepper_motor_fsm(speed,d, start, sequence);

always@ (posedge speed)

#PACE: Start of PACE I/O Pin Assignments

NET "ch_adc[0]" LOC = "p141" ;

NET "sequence[3]" LOC = "p39" ;

#PACE: Start of PACE Area Constraints