VLSI All Programs Assembly

TABLE OF CONTENT
1. Introduction to Hardware Descriptive Language & their software.

2. Write and simulate VHDL code for logic gates.
3. Implement Half Adder using VHDL.
4. Implement Full Adder using VHDL.
5. Implement Full Adder using two Half Adders.
6. Implement Half Subtractor and Full Subtractor using VHDL.
7. Implement Ripple Carry Adder usinf Full Adder in VHDL.
8. Implement 2x4 and 3x8 decoders using VHDL.
9. Implement 8x3 encoder using VHDL.
10. Implement 4x1 Multiplexer using VHDL.
11. Implement 4x2 Priority Encoder using VHDL.
12. Implement various Code Converters using VHDL.
ASSIGNMENT
1. Write a VHDL code for D , T and JK flip flop using behavioural modelling.
2. Write a VHDL code for 4 bit Johnson Counter
3. Write a VHDL code for MOD-16 up-counter.
4. Write a VHDL code for MOD-16 up-down counter.
1.Write a short note on Introduction to Hardware Descriptive
Languages and their softwares.
Hardware description language (HDL) is a specialized computer language used to program electronic
and digital logic circuits. The structure, operation and design of the circuits are programmable using
HDL. HDL includes a textual description consisting of operators, expressions, statements, inputs and
outputs. Instead of generating a computer executable file, the HDL compilers provide a gate map.
The gate map obtained is then downloaded to the programming device to check the operations of
the desired circuit. The language helps to describe any digital circuit in the form of structural,
behavioural and gate level.
The three common HDLs are Verilog, VHDL, and SystemC. The HDLs allow fast design and better
verification. In most of the industries, Verilog and VHDL are common. Verilog, one of the main
Hardware Description Language is used for designing all types of circuits. It consists of modules and
the language allows Behavioural, Dataflow and Structural Description. VHDL (Very High Speed
Integrated Circuit Hardware Description Language) is standardized by IEEE1164. The design is
composed of entities consisting of multiple architectures. SystemC is a language that consist a set of
C++classes and macros. It allows electronic system level and transaction modelling.
Need for HDLs

Complex digital circuit designs require more time for development, synthesis, simulation and
debugging. The arrival of HDLs has helped to solve this problem by allowing each module to be
worked by a separate team.
All the goals like power, throughput, latency (delay), test coverage, functionality and area
consumption required for a design can be known by using HDL. As a result, the designer can make
the necessary engineering tradeoffs and can develop the design in a better and efficient way.
HDL Structure & Design

Generally, HDL structure consist a textual description involving many inputs, outputs, signals
operators, components, multiple architectures, and comments. Concurrent and sequential way of
programming style is possible in HDL. Each and every HDL uses a different structure and design
method.
Different Types of HDLs

Different HDLs are available for describing analog circuits, digital circuits and PCBs.
HDLs for digital circuit design: Other than Verilog, VHDL and SystemC many HDLs are available for
digital circuits. Among them, `Advanced Boolean Expression Language (ABEL) is better for
programming PLDs (Programmable Logic Devices). Bluespec, a high level functional programming
HDL language is developed to handle chip design and automation systems. Bluespec System
Verilog(BSV) uses syntax similar to Verilog HDL. C-to-Verilog is generally a converter which helps to
convert C to Verilog language. Constructing Hardware in a Scala Embedded Language
(Chisel), MyHDL and HHDL are HDLs used to support advanced hardware design.
Compiler for Universal Programming Language (CUPL) is generally used for logic device
programming. Handel-C is used for programming FPGA’s. Hardware Join Java (HJJ) helps in
reconfigurable computing applications. Impulse C, subset of C supports parallel programming. Just-
Another Hardware Description Language (JHDL) uses an object oriented programming
approach. LavaHDL helps in specifying layout of circuits mainly. Lola HDL is basically used for
synchronous digital circuits. M, is another HDL from Mentor Graphics. PALASM is used as a HDL for
Programmable Array Logic (PAL) devices. Finally System Verilog is an extension to Verilog.
HDLs for analog circuit design: The HDLs used for analog circuits include Analog Hardware
Description Language (AHDL), Spectre High Level Description Language (SpectreHDL), Verilog for
Analog and Mixed Signal (Verilog – AMS), VHDL with analog and mixed signal extension (VHDL –
AMS) and finally HDL-A. AHDL is most commonly used as a HDL language for analog circuits.
SpectreHDL is a high level description language that uses functional description text files to model
the behaviour of the systems. Verilog-AMS is an industry standard modelling language that contains
continuous an event driven simulators for analog, digital and analog/digital circuits. VHDL-AMS is
good for verifying complex analog, mixed signal and RF (radio frequency) circuits. HDL-A is a
proprietary HDL for mixed and analog circuits.
HDL for Printed Circuit Design: PHDL (Printed Circuit Board HDL) is generally used for modeling text
based schematics for PCBs. It allows generating massive buses and re-uses device definitions easily.
Benefits of HDL
The major benefit of the language is fast design and better verification. The Top-down design and
hierarchical design method allows the design time; design cost and design errors to be reduced.
Another major advantage is related to complex designs, which can be managed and verified easily.
HDL provides the timing information and allows the design to be described in gate level and register
transfer level. Reusability of resources is one of the other advantages
.
1. Write and simulate the VHDL code for logic gates.
And Gate :
entity aand1_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end aand1_gate;
architecture Behavioral of aand1_gate is
begin
c <= a and b;
end Behavioral;
RTL Schematic
Test Bench WaveForm

OR GATE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or2_gate is
c : out STD_LOGIC);
end or2_gate;
architecture Behavioral of or2_gate is

begin
c <= a or b;
end Behavioral;
Test Bench WaveForm
RTL Schematic
NOT GATE
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not3_gate is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end not3_gate;
architecture Behavioral of not3_gate is
begin
b <= not a ;
end Behavioral;
RTL Schematic
Test Bench WaveForm

NAND GATE
library IEEE;
entity nnand3_gate is
c : out STD_LOGIC);
end nnand3_gate;
architecture Behavioral of nnand3_gate is
begin
c <= a nand b;
end Behavioral;
RTL Schematic
Test Bench WaveForm

NOR GATE:
library IEEE;
entity nor1_gate is
Port ( a ,b : in STD_LOGIC;
c : out STD_LOGIC);
end nor1_gate;
architecture Behavioral of nor1_gate is

begin
c <= a nor b;
end Behavioral;
RTL Schematic
.
Test Bench WaveForm
XOR GATE:
library IEEE;
entity xxor1_gate is
c : out STD_LOGIC);
end xxor1_gate;
architecture Behavioral of xxor1_gate is
begin
c <= a xor b;
end Behavioral;
RTL Schematic
Test Bench WaveForm
3. Write a program to implement Half adder using VHDL.

entity h_add is
c,s : out STD_LOGIC);
end h_add;
architecture Behavioral of h_add is
begin
s <= a xor b;
c <= a and b;
end Behavioral;
RTL Schematic
Test Bench WaveForm
2. Write a program to implement Full Adder using VHDL
library IEEE;
entity fa is
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
car : out STD_LOGIC);
end fa;
architecture Behavioral of fa is
begin
s<=a xor b xor c;
car<= (a and b) or (b and c) or (c and a);
end Behavioral;
RTL Schematic
Test Bench WaveForm
5.Implement Full Adder by using two half adders
entity full_adder1 is
Port ( x,y,z : in STD_LOGIC;
t,u : out STD_LOGIC);
end full_adder1;
architecture Behavioral of full_adder1 is

component half_adder is
port (a,b :in std_logic;
s,c : out std_logic);
end component;
component oor1_gate is
port (p,q : in std_logic;
r : out std_logic);
end component;
signal s1 ,s2,s3 : std_logic;
begin
HA1 : half_adder port map (x,y,s1,s2);
HA2 : half_adder port map (s1,z,t,s3);
OR1 : oor1_gate port map(s2,s3,u);
end Behavioral;
RTL Schematic
Test Bench WaveForm
6. Write a program to implement Half subtractor and Full subtractor

using VDHL
library IEEE;
entity hs_hs1 is
b : in STD_LOGIC;
d : out STD_LOGIC;
bor : out STD_LOGIC);
end hs_hs1;
architecture Behavioral of hs_hs1 is
begin
d<= a xor b;
bor<= a and not b;
end Behavioral;
RTL Schematic
Test Bench WaveForm

FULL SUBTRACTOR
library IEEE;
entity de is
b : in STD_LOGIC;
c : in STD_LOGIC;
d : out STD_LOGIC;
bor : out STD_LOGIC);
end de;
architecture Behavioral of de is
begin
d<= a xor b xor c;

bor<= (not a and b) or (b and c) or(c and not a);
end Behavioral;
RTL Schematic
Test Bench WaveForm
7. Write a program to implement Ripple Carry Adder using Full adder

in VHDL
library IEEE;
entity RCA is
Port ( a : in STD_LOGIC_vector(3 downto 0);
b : in STD_LOGIC_vector(3 downto 0);
ci : in STD_LOGIC;
sum : out STD_LOGIC_vector(3 downto 0);
carry : out STD_LOGIC);
end RCA;
architecture Behavioral of RCA is

component full_add
port (x:in STD_LOGIC;
y:in STD_LOGIC;
z:in STD_LOGIC;
s:out STD_LOGIC;
c:out STD_LOGIC);
end component;
signal s1,s2,s3: STD_LOGIC;
begin
FA1: full_add port map( A(0), B(0), ci, sum(0), s1);
FA2: full_add port map( A(1), B(1), s1, sum(1), s2);
FA3: full_add port map( A(2), B(2), s2, sum(2), s3);
FA4: full_add port map( A(3), B(3), s3, sum(3), carry);
end Behavioral;
RTL Schematic
Test Bench WaveForm

8. Write a program to implement 2x4 and 3x8 Decoder using VHDL(
Structural,Behavioral and Dataflow modelling)
2x4 Decoder
STRUCTURAL
library IEEE;
entity decoderTFstr is
Port ( s : in STD_LOGIC_vector(1 downto 0);
y : out STD_LOGIC_vector(3 downto 0));
end decoderTFstr;
architecture Behavioral of decoderTFstr is

component and1 is
port(a,b : in Std_logic;
c : out Std_logic);
end component;
component not2 is
port(a : in std_logic;
c : out std_logic);
end component;
signal A1,A2: std_logic;

begin
X1 : not2 port map(s(0),A2);
X2 : not2 port map(s(1),A1);
X3 : and1 port map(A1,A2,y(0));
X4 : and1 port map(A2,s(1),y(1));
X5 : and1 port map(s(1),A2,y(2));
X6 : and1 port map(s(0),s(1),y(3));
end Behavioral;
Structural Modelling (RTL)
BEHAVIORAL
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder1 is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0) );
end decoder1;
architecture bhv of decoder1 is
begin
process(a)
begin
if (a="00") then
b <= "0001";
elsif (a="01") then
b <= "0010";
elsif (a="10") then
b <= "0100";
else
b <= "1000";
end if;
end process;
end behavioral;
Behavioral Modelling (RTL)
DATAFLOW
library IEEE;
entity dec1 is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b: out STD_LOGIC_VECTOR (3 downto 0));
end dec1;
architecture Behavioral of dec1 is

begin
b(0)<=(not a(1) and not a(0));

b(1)<=(not a(1) and a(0));
b(2)<=( a(1) and not a(0));
b(3)<=( a(1) and a(0));
end Behavioral;
Data Flow Modelling(RTL)
Test Bench WaveForm

3x8 DECODER
STRUCTURAL
library IEEE;
entity TEstr is
b : out STD_LOGIC_vector(7 downto 0));
end TEstr;
architecture Behavioral of TEstr is

component and_gt is
port( a,b,c: in std_logic;
d : out std_logic);
end component;
begin
X1:and_gt port map(not a(2),not a(1),not a(0),b(0));
X2:and_gt port map(not a(2), not a(1),a(0),b(1));
X3:and_gt port map( not a(2), a(1),not a(0),b(2));
X4:and_gt port map( not a(2), a(1),a(0),b(3));
X5:and_gt port map( a(2), not a(1),not a(0),b(4));
X6:and_gt port map( a(2), not a(1),a(0),b(5));
X7:and_gt port map( a(2) ,a(1),not a(0),b(6));
X8:and_gt port map( a(2),a(1),a(0),b(7));
end Behavioral;

BEHAVIORAL
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder2 is
port( a : in STD_LOGIC_VECTOR(2 downto 0);
b : out STD_LOGIC_VECTOR(7 downto 0) );
end decoder2;
architecture behavioral of decoder2 is
begin
process(a)
begin
if (a="000") then
b <= "00000001";
elsif (a="001") then
b <= "00000010";
b <= "00000100";
b <= "00001000";
b <= "00010000";
b <= "00100000";
b <= "01000000";
b <= "10000000";
end if;
end process;
end behvioral;

DATAFLOW
library IEEE;
entity dec2 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
b: out STD_LOGIC_VECTOR (7 downto 0));
end dec2;
architecture Behavioral of dec2 is

begin
b(0)<=(not a(2) and not a(1) and not a(0));

b(1)<= (not a(2) and not a(1) and a(0));
b(2)<= (not a(2) and a(1) and not a(0));
b(3)<= (not a(2) and a(1) and a(0));
b(4)<= ( a(2) and not a(1) and not a(0));
b(5)<= (a(2) and not a(1) and a(0));
b(6)<= ( a(2) and a(1) and not a(0));
b(7)<= ( a(2) and a(1) and a(0));
end Behavioral;

Test Bench WaveForm
9. Implement 8x3 encoder using VHDL (Structural,Behavioral and

Dataflow modelling)
BEHAVIORAL
library IEEE;
entity ETe is
end ETe;
architecture Behavioral of ETe is

begin
b <= "000" when (a="10000000") else
"001" when (a="01000000") else
"010" when (a="00100000") else
"011" when (a="00010000") else
"100" when (a="00001000") else
"101" when (a="00000100") else
"110" when (a="00000010") else
"111";
end Behavioral;
DATAFLOW
library IEEE;
entity ETen is
end ETen;
architecture Behavioral of ETen is
begin
b(0) <= a(4) or a(5) or a(6) or a(7);
b(1) <= a(2) or a(3) or a(6) or a(7);
b(2) <= a(1) or a(3) or a(5) or a(7);
end Behavioral;
STRUCTURAL
entity enc8x3 is
Port ( p : out STD_LOGIC;
q : out STD_LOGIC;
r : out STD_logic;
s: in STD_LOGIC;
t: in STD_LOGIC;
u: in STD_LOGIC;
v: in STD_LOGIC;
w : in STD_LOGIC;
x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC);
end enc8x3;
architecture Behavioral of enc8x3 is

component or_gt is
port( a,b,c,d: in std_logic;
e:out std_logic);
end component;
begin
w_1:or_gt port map(t,v,x,z,p);
w_2:or_gt port map(u,v,y,z,q);
w_3:or_gt port map(w,x,y,z,p);
end behavioural;
Test Bench WaveForm
10. Write a program to implement 4x1 MUX using VHDL.
STRUCTURAL
library IEEE;
entity mux4x1 is
Port ( i0,i1,i2,i3 : in std logic;
s1 : in STD_LOGIC;
s0: in STD_LOGIC;
o: out std_logic);
end mux4x1;
architecture Behavioral of mux4x1 is

component and_gt is
port( a,b,c: in std_logic;
d:out std_logic);
end component;
component or_gt is
port( a1,b1,c1,e1: in std_logic;
d1:out std_logic);
end component;
signal sig1,sig2,sig3,sig4 : std_logic;
begin
X1:and_gt port map(i0,not s0,not s1,sig1);
X2:and_gt port map(i1,not s0, s1,sig2);
X3:and_gt port map(i2,s0,not s1,sig3);
X4:and_gt port map(i3,s0,s1,sig4);
X5:or_gt port map (sig1,sig2,sig3,sig4,s0);
end behavioral;
BEHAVIORAL
library IEEE;
entity mux is
Port ( I0,I1,I2,I3: in STD_LOGIC;
S0,S1 : in STD_LOGIC;
Y : out STD_LOGIC);
end mux;
architecture Behavioral of mux is
begin
process(I0,I1,I2,I3,S0,S1)
begin
if (S0='0'and S1='0')then
Y<= I0;
elsif (S0='0'and S1='1') then
Y<= I1;
elsif (S0='1'and S1='0') then
Y<= I2;
else
Y<= I3;
end if;
end process;
end Behavioral;
DATAFLOW
library IEEE;
entity mux41 is
Port ( s : in STD_LOGIC_VECTOR (1 downto 0);
i : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC);
end mux41;
architecture Behavioral of mux41 is

begin
y<= (not s(1) and not s(0) and i(0)) or (not s(1) and s(0) and i(1)) or (s(1) and not s(0) and i(2)) or (s(1)
and s(0) and i(3));
end Behavioral;
RTL Schematic
Test Bench WaveForm

11. Program to implement 4x2 Priority Encoder in VHDL.
library IEEE;
use IEEE.NUMERIC_STD.ALL;
entity priority_en is
Port ( a : in STD_ULOGIC_vector(3 downto 0);
e : in Std_logic;
end priority_en;
architecture Behavioral of priority_en is
begin
process (a,e)
begin
if (e ='1') then
if (std_match(a,"1---")) then
b <= "11";
elsif (std_match(a,"01--")) then
b <= "10";
elsif (std_match(a,"001-")) then
b <= "01";
elsif (std_match(a,"0001")) then
b <= "00";
end if;
else
b <= "00";
end if;
end process;
end Behavioral;
RTL Schematic
Test Bench WaveForm

12. Write programs to implement the following code converters in
VHDL.
A) Binary code to Gray code converter
library IEEE;
entity btg is
Port ( b : in STD_LOGIC_vector(3 downto 0);
g : out STD_LOGIC_vector(3 downto 0));
end gtb;
architecture Behavioral of btg is
begin
g(3)<= g(3);
g(2)<= g(3) xor g(2);
g(1)<= g(2) xor g(1);
g(0)<= g(1) xor g(0);
end Behavioral;
RTL Schematic
Test Bench WaveForm
B) Gray code to Binary code coverter
library IEEE;
entity gtb is
Port ( g : in STD_LOGIC_vector(3 downto 0);
end gtb;
architecture Behavioral of gtb_2 is
begin
b(3)<= g(3);
b(2)<= g(3) xor g(2);
b(1)<= g(3) xor g(2)xor g(1);
b(0)<= g(3) xor g(2)xor g(1) xor g(0);
end Behavioral;
RTL Schematic
C) BCD to 7segment code converter

library IEEE;
entity seven is
Port ( bcd : in STD_LOGIC_vector(3 downto 0);
seg7 : out STD_LOGIC_vector(6 downto 0));
end seven;
architecture Behavioral of seven is
begin
process(bcd)
begin
if(bcd="0000") then
seg7<="1111110";
elsif(bcd="0001") then
seg7<="0000110";
seg7<="1011011";
seg7<="1001111";
seg7<="0100111";
seg7<="1101101";
seg7<="1111101";
seg7<="1000110";
seg7<="1111111";
seg7<="1101111";
else seg7<="0000000";
end if;
end process;
end Behavioral;
RTL Schematic
Test Bench WaveForm

D) BCD to Excess-3 code converter
library IEEE;
entity xs3 is
Port ( bcd : in STD_LOGIC_vector(3 downto 0);
exst : out STD_LOGIC_vector(3 downto 0));
end xs3;
architecture Behavioral of xs3 is
begin
process(bcd)
begin
if(bcd="0000") then
exst<="0011";
exst<="0100";
exst<="0101";
exst<="0110";
exst<="0111";
exst<="1000";
exst<="1001";
exst<="1010";
exst<="1011";
exst<="1100";
end if;
end process;
end Behavioral;
RTL Schematic
ASSIGNMENT
1. Write a VHDL code for D , T and JK flip flop using behavioural modelling.
D Flip Flop –
library IEEE;
entity Dff is
Port ( clk,D : in STD_LOGIC;
Q,Qnot : out STD_LOGIC);
end Dff;
architecture Behavioral of Dff is
begin
process(clk,D)
begin
if clk='0' and clk'event then
Q <= D;
Qnot <= not D;
end if;
end process;
end Behavioral;
RTL Schematic
Test Bench WaveForm
JK Flip Flop –
library IEEE;
entity JKff is
Port ( J,K,clk : in STD_LOGIC;
end JKff;
architecture Behavioral of JKff is
begin
process(clk)
variable temp: std_logic;
begin
if clk='0' and clk'event then
if (J='0' and K='0') then
temp:= temp;
elsif (J='1' and K='1') then
temp:= not temp;
elsif (J='0' and K='1') then
temp:= '0';
else
temp:= '1';
end if;
end if;
Q <= temp;
Qnot <= not temp;
end process;
end Behavioral;
RTL Schematic
Test Bench WaveForm

T Flip Flop –
library IEEE;
entity Tff is
Port ( clk ,T : in STD_LOGIC;
end Tff;
architecture Behavioral of Tff is

signal temp : std_logic;
begin
process(clk)
begin
if clk ='1' and clk'event and T='1' then
temp <= not temp;
elsif T='0' then
temp <= temp;
end if;
end process;
Q <= temp;
Qnot <= not temp;
end Behavioral;
RTL Schematic
Test Bench WaveForm
2. Write a VHDL code for 4 bit Johnson Counter
library IEEE;
entity johnson_cntr is
Port ( clk,rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end johnson_cntr;
architecture Behavioral of johnson_cntr is
signal temp : std_logic_vector(3 downto 0) := "0000";
begin
process(clk,rst)
begin
if (rising_edge(clk)) then
if (rst='1') then
temp <= "0000";
else
temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= not temp(3);

end if;
end if;
end process;
Q <= temp;
end Behavioral;
RTL Schematic
Test Bench WaveForm

3. Write a VHDL code for MOD-16 up-counter.
library IEEE;
entity counter is
port( clk:in std_logic;
output:out std_logic_vector(3 downto 0)
);
end counter;
architecture Behavioral of counter is
component D_flipflop
port( clk:in std_logic;
D:in std_logic;
Q:out std_logic;
Qnot:out std_logic
);
end component;
signal temp:std_logic_vector(3 downto 0);
signal nottemp:std_logic_vector(3 downto 0) := "1111";
begin
F1: D_flipflop port map (clk,nottemp(0),temp(0),nottemp(0));
F2: D_flipflop port map (temp(0),nottemp(1),temp(1),nottemp(1));
output <= temp;
end Behavioral;
RTL Schematic
Test Bench WaveForm
4. Write a VHDL code for MOD-16 up-down counter.
library IEEE;
entity mod16_ud_counter is
port( clk,ud : in std_logic;
output : out std_logic_vector(3 downto 0));
end mod16_ud_counter;
architecture Mixed of mod16_ud_counter is
component JK_flipflop
port( J,K,clk : in std_logic;
Q,Qnot : out std_logic);
end component;
signal temp:std_logic_vector(3 downto 0);
signal nottemp:std_logic_vector(3 downto 0);
signal upordown:std_logic_vector(3 downto 0);
begin
updown: process(ud)
begin
if ud = '1' then
upordown <= temp;
else
upordown <= nottemp;
end if;
end process;
F1: JK_flipflop port map ('1','1',clk,temp(0),nottemp(0));
F2: JK_flipflop port map ('1','1',upordown(0),temp(1),nottemp(1));
output <= temp;
end Mixed;
RTL Schematic
Test Bench WaveForm

VLSI All Programs Assembly

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TABLE OF CONTENT

1. Introduction to Hardware Descriptive Language & their software.

Need for HDLs

HDL Structure & Design

Different Types of HDLs

architecture Behavioral of aand1_gate is

Test Bench WaveForm

architecture Behavioral of or2_gate is

Test Bench WaveForm

Test Bench WaveForm

architecture Behavioral of nnand3_gate is

Test Bench WaveForm

architecture Behavioral of nor1_gate is

architecture Behavioral of xxor1_gate is

3. Write a program to implement Half adder using VHDL.

2. Write a program to implement Full Adder using VHDL

Test Bench WaveForm

5.Implement Full Adder by using two half adders

architecture Behavioral of full_adder1 is

Test Bench WaveForm

6. Write a program to implement Half subtractor and Full subtractor

Test Bench WaveForm

d<= a xor b xor c;

7. Write a program to implement Ripple Carry Adder using Full adder

architecture Behavioral of RCA is

Test Bench WaveForm

architecture Behavioral of decoderTFstr is

signal A1,A2: std_logic;

architecture Behavioral of dec1 is

b(0)<=(not a(1) and not a(0));

Test Bench WaveForm

architecture Behavioral of TEstr is

Structural Modelling (RTL)

Behavioral Modelling (RTL)

architecture Behavioral of dec2 is

b(0)<=(not a(2) and not a(1) and not a(0));

Data Flow Modelling(RTL)

9. Implement 8x3 encoder using VHDL (Structural,Behavioral and

architecture Behavioral of ETe is

architecture Behavioral of ETen is

architecture Behavioral of enc8x3 is

10. Write a program to implement 4x1 MUX using VHDL.

architecture Behavioral of mux4x1 is

Structural Modelling (RTL)

Behavioral Modelling (RTL)

architecture Behavioral of mux41 is

Test Bench WaveForm

architecture Behavioral of priority_en is

Test Bench WaveForm

architecture Behavioral of btg is

B) Gray code to Binary code coverter

architecture Behavioral of gtb_2 is

C) BCD to 7segment code converter

architecture Behavioral of seven is

Test Bench WaveForm

architecture Behavioral of Dff is

Test Bench WaveForm

architecture Behavioral of Tff is

2. Write a VHDL code for 4 bit Johnson Counter

Port ( clk,rst : in STD_LOGIC;

Q : out STD_LOGIC_VECTOR(3 DOWNTO 0));

architecture Behavioral of johnson_cntr is

signal temp : std_logic_vector(3 downto 0) := "0000";

temp <= "0000";