َْ

ِ
ْ‫ ًِْ
َو رْ ُز‬
ِ ْ‫ب زد‬
 ‫َر‬
My Lord! Advance me in Knowledge and true
understanding

MICROPROCESSOR BASED SYSTEM

Lecture 5
Dr. Shahrul Naim Sidek
snaim@iiu.edu.my
Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 Memory System Design
(Chapter 8)

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

SECTION 8.5-8.7, 8.10

Introduction to address decoding

Although the memory space in the M68000 is said to be flat, it does not
mean that the physical implementation of memory is homogeneous
Different portions of memory are used for different purposes: RAM, ROM,
I/O devices.
Even if all the memory was of one type, we still have to implement it using
multiple ICs.
This means that for a given valid address, one and only one memory-
mapped component must be accessed
Address decoding is the process of generating chip select (CS*)
signals from the address bus for each device in the system

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Introduction to address decoding (cont)
The address bus lines are split into two sections
the N most significant bits are used to generate the CS* signals for the
different devices
the M least significant signals are passed to the devices as addresses to the
different memory cells or internal registers

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Introduction to address decoding: Example
Let’s assume a very simple microprocessor with 10 address lines (1KB
=512 Kwords memory) . Let’s assume we wish to implement all its
memory space and we use 128x8 memory chips
We will need 8
memory chips
(8x128=1024)
We will need 3
address lines to
select each one of
the 8 chips
Each chip will need
7 address lines to
address its internal
memory cells

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Introduction to address decoding: Methods
The previous example specified that all addressable memory space
was to be implemented but there are some situations where this
requirement is not necessary or affordable
If only a portion of the addressable space is going to be implemented
there are two basic address decoding strategies
Full address decoding
All the address lines are used to specify a memory location
Each physical memory location is identified by a unique address
Partial address decoding
Since not all the address space is implemented, only a subset of the
address lines are needed to point to the physical memory location
Each physical memory location is identified by several possible
addresses (using all combinations of the address lines that were not
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used) Microprocessor Based System (MCT 2219) SBAH Jul’07
Full Address Decoding
Full Address Decoding Strategies For M68000 µP
• All address lines that are not connected directly to a specific IC are used
to design address decoder
• Each addressable location within a memory / IO component responds
only to a single unique address
• May requires a large number of gates, LSI, MSI logic components for
address decoder.
• Example 1: Design an address decoder for interfacing 16KB
EPROM & 16KB RAM to M68000 µP.
1. Suitable memory IC are: 27C64 EPROM & 6264 RAM. Note: M68K
requires 2 ICs for each memory.
2. From 27C64 & 6264 pin out, A1-A13 (2^13) of µP go to memory ICs A0-
A12 (internally decoded). Address lines A14-A23 are not connected to
Rev 1.0
memory ICs, therefore will beBased
Microprocessor use for address
System decoding
(MCT 2219) circuit. SBAH Jul’07
 Full Address Decoding (cont)
Full Address Decoding
3. Draw suitable memory map with address boundaries. M68000 requires
EPROM to start at $00000. Note: since 2 ICs are used for each EPROM
& RAM, total size are 16KB (8Kword) for each.
$04000 $07FFF $FFFFF
EPROM (16K) RAM (16K)

$00000 $03FFF
4. Draw the address table:
Device 23 22 21 20 … 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
EPROM 0 0 0 0 0 0 X X X X X X X X X X X X X X
RAM 0 0 0 0 0 1 X X X X X X X X X X X X X X

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Full Address Decoding (cont)
Full Address Decoding
All address lines which go to memory IC are marked X. X can be logic ‘0’
or ‘1’. Other address lines are given appropriate logic for starting
address of the IC.
5. Draw logic circuit
A23
A22
A21
A20
A19
A18 /CS RAM ($04000 - $07FFF)
A17
A16
A15
/CS EPROM ($00000 - $03FFF)

/AS
A14

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Full Address Decoding (cont)
Example 2: Let’s assume the same microprocessor with 10 address
lines (1KB memory)
However, this time we wish to implement only 512 bytes of memory
We still must use 128-byte (2^7) memory chips
Physical memory must be placed on the upper half of the memory map
How to use decoder!

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Partial Address Decoding
Partial Address Decoding Strategies for M68000 µP
• Not all address lines are used to design address decoder
• Decoding circuit is simpler but memories / IO ICs may response to
different address range (called mirror image)
• Example 1: Design a partial address decoder for interfacing 8KB
EPROM & 8KB RAM to M68000 µP
1. If EPROM & RAM are the only devices in the system, the simplest
decoding circuit can be used only A14 to differentiate the 2 devices.

/CS RAM (A14=‘1’)

/CS EPROM (A14=‘0’)

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Partial Address Decoding
Partial Address Decoding Strategies for M68000 µP
2. From previous circuit, any address with A14=‘0’ will select EPROM and
any address with A14=‘1’ will select RAM. i.e. RAM & EPROM will have
mirror images. Start address is obtained by setting X to ‘0’ & end
address is obtained by setting X to ‘1’ in the previous address table:

Address Lines (A14 - A23) Mirror Images

23 22 21 20 … 16 15 14 From EPROM
0 0 0 0 … 0 0 0 $000000 - $003BFFF
0 0 0 0 … 0 1 0 $008000 - $00BFFF
0 0 0 0 … 1 0 0 $010000 - $013FFF
0 0 0 0 … 1 1 0 $018000 - $01BFFF
: : : :
1 1 1 1 .. 1 1 0 $FF8000 - $FFBFFF

0 if to select from EPROM

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07
 Partial Address Decoding
Example 2: Let’s assume the same microprocessor with 10 address
lines (1KB memory)
However, this time we wish to implement only 512 bytes of memory
We still must use 128-byte memory chips
Physical memory must be placed on the upper half of the memory map

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Design Available Memory
• Typical EPROM sizes Typical Static Ram Size Typical SIMM size
Part Size Add. Lines Part Size Add. Lines Part Size Add. Lines
2176 2KB 11 6116 2KB 11 41256 256KB 18
2732 4KB 12 6264 8KB 13 421000 1MBit 20
2764 8KB 13 62256 32KB 15 9400 4MB 22
27128 16KB 14
27256 32KB 15
27512 64KB 16

• Static RAM < EPROM < Dynamic RAM (Single Inline Memory Module SIMM or
Single Inline Pin Package SIPP)
• The larger RAM memory, the simple address decoder

FOR YOUR FURTHER UNDERSTANDING ON THE MATTER.

Read Examples in Chapter 8 of the text book.

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07

 Study Questions – Chapter 8
No. 3,5,6,8,9,10,11,12,15,24,28,30,31

Rev 1.0 Microprocessor Based System (MCT 2219) SBAH Jul’07